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https://github.com/espressif/esp-idf.git
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196 lines
9.1 KiB
C
196 lines
9.1 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_TIMG_STRUCT_H_
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#define _SOC_TIMG_STRUCT_H_
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typedef volatile struct {
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struct{
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union {
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struct {
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uint32_t reserved0: 10;
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uint32_t alarm_en: 1; /*When set alarm is enabled*/
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uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/
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uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/
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uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/
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uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/
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uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/
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uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
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};
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uint32_t val;
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} config;
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uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
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uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
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uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
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uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/
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uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/
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uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
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uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
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uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
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} hw_timer[2];
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union {
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struct {
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uint32_t reserved0: 14;
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uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/
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uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
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uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/
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uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/
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uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/
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uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
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uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
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uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
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uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/
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uint32_t en: 1; /*When set SWDT is enabled*/
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};
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uint32_t val;
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} wdt_config0;
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union {
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struct {
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uint32_t reserved0: 16;
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uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
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};
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uint32_t val;
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} wdt_config1;
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uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/
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uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/
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uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/
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uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/
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uint32_t wdt_feed; /*Write any value will feed SWDT*/
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uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/
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union {
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struct {
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uint32_t reserved0: 12;
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uint32_t start_cycling: 1;
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uint32_t clk_sel: 2;
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uint32_t rdy: 1;
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uint32_t max: 15;
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uint32_t start: 1;
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};
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uint32_t val;
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} rtc_cali_cfg;
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union {
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struct {
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uint32_t reserved0: 7;
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uint32_t value:25;
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};
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uint32_t val;
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} rtc_cali_cfg1;
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union {
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struct {
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uint32_t reserved0: 7;
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uint32_t rtc_only: 1;
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uint32_t cpst_en: 1;
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uint32_t lac_en: 1;
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uint32_t alarm_en: 1;
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uint32_t level_int_en: 1;
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uint32_t edge_int_en: 1;
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uint32_t divider: 16;
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uint32_t autoreload: 1;
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uint32_t increase: 1;
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uint32_t en: 1;
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};
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uint32_t val;
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} lactconfig;
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union {
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struct {
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uint32_t reserved0: 6;
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uint32_t step_len:26;
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};
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uint32_t val;
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} lactrtc;
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uint32_t lactlo; /**/
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uint32_t lacthi; /**/
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uint32_t lactupdate; /**/
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uint32_t lactalarmlo; /**/
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uint32_t lactalarmhi; /**/
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uint32_t lactloadlo; /**/
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uint32_t lactloadhi; /**/
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uint32_t lactload; /**/
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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uint32_t t1: 1; /*interrupt when timer1 alarm*/
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uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
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uint32_t lact: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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uint32_t t1: 1; /*interrupt when timer1 alarm*/
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uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
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uint32_t lact: 1;
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uint32_t reserved4:28;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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uint32_t t1: 1; /*interrupt when timer1 alarm*/
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uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
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uint32_t lact: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_st_timers;
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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uint32_t t1: 1; /*interrupt when timer1 alarm*/
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uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/
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uint32_t lact: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} int_clr_timers;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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union {
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struct {
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uint32_t date:28; /*Version of this regfile*/
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} timg_date;
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union {
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struct {
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uint32_t reserved0: 31;
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uint32_t en: 1; /*Force clock enable for this regfile*/
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};
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uint32_t val;
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} clk;
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} timg_dev_t;
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extern timg_dev_t TIMERG0;
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extern timg_dev_t TIMERG1;
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#endif /* _SOC_TIMG_STRUCT_H_ */
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