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383 lines
15 KiB
C
383 lines
15 KiB
C
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** SYSTIMER_CONF_REG register
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* Configure system timer clock
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*/
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#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
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/** SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
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* system timer force clock enable
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*/
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#define SYSTIMER_CLK_FO (BIT(0))
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#define SYSTIMER_CLK_FO_M (SYSTIMER_CLK_FO_V << SYSTIMER_CLK_FO_S)
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#define SYSTIMER_CLK_FO_V 0x00000001
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#define SYSTIMER_CLK_FO_S 0
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/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
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* register clock enable
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*/
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#define SYSTIMER_CLK_EN (BIT(31))
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#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
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#define SYSTIMER_CLK_EN_V 0x00000001
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#define SYSTIMER_CLK_EN_S 31
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/** SYSTIMER_LOAD_REG register
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* load value to system timer
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*/
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#define SYSTIMER_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x4)
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/** SYSTIMER_TIMER_LOAD : WO; bitpos: [31]; default: 0;
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* load value to system timer
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*/
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#define SYSTIMER_TIMER_LOAD (BIT(31))
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#define SYSTIMER_TIMER_LOAD_M (SYSTIMER_TIMER_LOAD_V << SYSTIMER_TIMER_LOAD_S)
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#define SYSTIMER_TIMER_LOAD_V 0x00000001
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#define SYSTIMER_TIMER_LOAD_S 31
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/** SYSTIMER_LOAD_HI_REG register
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* High 32-bit load to system timer
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*/
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#define SYSTIMER_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x8)
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/** SYSTIMER_TIMER_LOAD_HI : R/W; bitpos: [31:0]; default: 0;
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* High 32-bit load to system timer
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*/
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#define SYSTIMER_TIMER_LOAD_HI 0xFFFFFFFF
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#define SYSTIMER_TIMER_LOAD_HI_M (SYSTIMER_TIMER_LOAD_HI_V << SYSTIMER_TIMER_LOAD_HI_S)
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#define SYSTIMER_TIMER_LOAD_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_LOAD_HI_S 0
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/** SYSTIMER_LOAD_LO_REG register
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* Low 32-bit load to system timer
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*/
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#define SYSTIMER_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0xc)
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/** SYSTIMER_TIMER_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
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* Low 32-bit load to system timer
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*/
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#define SYSTIMER_TIMER_LOAD_LO 0xFFFFFFFF
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#define SYSTIMER_TIMER_LOAD_LO_M (SYSTIMER_TIMER_LOAD_LO_V << SYSTIMER_TIMER_LOAD_LO_S)
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#define SYSTIMER_TIMER_LOAD_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_LOAD_LO_S 0
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/** SYSTIMER_STEP_REG register
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* system timer accumulation step
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*/
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#define SYSTIMER_STEP_REG (DR_REG_SYSTIMER_BASE + 0x10)
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/** SYSTIMER_TIMER_XTAL_STEP : R/W; bitpos: [9:0]; default: 80;
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* system timer accumulation step when using XTAL
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*/
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#define SYSTIMER_TIMER_XTAL_STEP 0x000003FF
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#define SYSTIMER_TIMER_XTAL_STEP_M (SYSTIMER_TIMER_XTAL_STEP_V << SYSTIMER_TIMER_XTAL_STEP_S)
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#define SYSTIMER_TIMER_XTAL_STEP_V 0x000003FF
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#define SYSTIMER_TIMER_XTAL_STEP_S 0
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/** SYSTIMER_TIMER_PLL_STEP : R/W; bitpos: [19:10]; default: 1;
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* system timer accumulation step when using PLL
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*/
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#define SYSTIMER_TIMER_PLL_STEP 0x000003FF
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#define SYSTIMER_TIMER_PLL_STEP_M (SYSTIMER_TIMER_PLL_STEP_V << SYSTIMER_TIMER_PLL_STEP_S)
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#define SYSTIMER_TIMER_PLL_STEP_V 0x000003FF
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#define SYSTIMER_TIMER_PLL_STEP_S 10
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/** SYSTIMER_TARGET0_HI_REG register
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* System timer target0 high 32-bit
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*/
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#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
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/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [31:0]; default: 0;
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* System timer target0 high 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET0_HI 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
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#define SYSTIMER_TIMER_TARGET0_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET0_HI_S 0
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/** SYSTIMER_TARGET0_LO_REG register
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* System timer target0 low 32-bit
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*/
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#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
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/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
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* System timer target0 low 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
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#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET0_LO_S 0
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/** SYSTIMER_TARGET1_HI_REG register
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* System timer target1 high 32-bit
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*/
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#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
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/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [31:0]; default: 0;
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* System timer target1 high 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET1_HI 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
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#define SYSTIMER_TIMER_TARGET1_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET1_HI_S 0
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/** SYSTIMER_TARGET1_LO_REG register
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* System timer target1 low 32-bit
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*/
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#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
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/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
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* System timer target1 low 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
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#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET1_LO_S 0
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/** SYSTIMER_TARGET2_HI_REG register
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* System timer target2 high 32-bit
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*/
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#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
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/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [31:0]; default: 0;
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* System timer target2 high 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET2_HI 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
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#define SYSTIMER_TIMER_TARGET2_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET2_HI_S 0
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/** SYSTIMER_TARGET2_LO_REG register
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* System timer target2 low 32-bit
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*/
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#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
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/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
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* System timer target2 low 32-bit
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*/
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#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
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#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_TARGET2_LO_S 0
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/** SYSTIMER_TARGET0_CONF_REG register
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* Configure system timer target0 work mode
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*/
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#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x2c)
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/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [29:0]; default: 0;
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* System timer target0 alarm period
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*/
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#define SYSTIMER_TARGET0_PERIOD 0x3FFFFFFF
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#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
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#define SYSTIMER_TARGET0_PERIOD_V 0x3FFFFFFF
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#define SYSTIMER_TARGET0_PERIOD_S 0
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/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
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* Whether system timer target0 work in period mode
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*/
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#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
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#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
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#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001
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#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
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/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [31]; default: 0;
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* system timer target0 work enable
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*/
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#define SYSTIMER_TARGET0_WORK_EN (BIT(31))
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#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
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#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
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#define SYSTIMER_TARGET0_WORK_EN_S 31
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/** SYSTIMER_TARGET1_CONF_REG register
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* Configure system timer target1 work mode
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*/
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#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x30)
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/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [29:0]; default: 0;
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* System timer target1 alarm period
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*/
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#define SYSTIMER_TARGET1_PERIOD 0x3FFFFFFF
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#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
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#define SYSTIMER_TARGET1_PERIOD_V 0x3FFFFFFF
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#define SYSTIMER_TARGET1_PERIOD_S 0
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/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
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* Whether system timer target1 work in period mode
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*/
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#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
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#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
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#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001
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#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
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/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [31]; default: 0;
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* system timer target1 work enable
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*/
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#define SYSTIMER_TARGET1_WORK_EN (BIT(31))
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#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
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#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
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#define SYSTIMER_TARGET1_WORK_EN_S 31
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/** SYSTIMER_TARGET2_CONF_REG register
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* Configure system timer target2 work mode
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*/
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#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
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/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [29:0]; default: 0;
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* System timer target2 alarm period
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*/
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#define SYSTIMER_TARGET2_PERIOD 0x3FFFFFFF
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#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
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#define SYSTIMER_TARGET2_PERIOD_V 0x3FFFFFFF
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#define SYSTIMER_TARGET2_PERIOD_S 0
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/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
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* Whether system timer target2 work in period mode
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*/
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#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
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#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
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#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001
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#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
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/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [31]; default: 0;
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* system timer target2 work enable
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*/
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#define SYSTIMER_TARGET2_WORK_EN (BIT(31))
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#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
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#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
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#define SYSTIMER_TARGET2_WORK_EN_S 31
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/** SYSTIMER_UPDATE_REG register
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* Read out system timer value
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*/
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#define SYSTIMER_UPDATE_REG (DR_REG_SYSTIMER_BASE + 0x38)
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/** SYSTIMER_TIMER_VALUE_VALID : RO; bitpos: [30]; default: 0;
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* If it is valid to read out timer value from register
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*/
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#define SYSTIMER_TIMER_VALUE_VALID (BIT(30))
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#define SYSTIMER_TIMER_VALUE_VALID_M (SYSTIMER_TIMER_VALUE_VALID_V << SYSTIMER_TIMER_VALUE_VALID_S)
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#define SYSTIMER_TIMER_VALUE_VALID_V 0x00000001
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#define SYSTIMER_TIMER_VALUE_VALID_S 30
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/** SYSTIMER_TIMER_UPDATE : WO; bitpos: [31]; default: 0;
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* Update system timer value to register
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*/
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#define SYSTIMER_TIMER_UPDATE (BIT(31))
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#define SYSTIMER_TIMER_UPDATE_M (SYSTIMER_TIMER_UPDATE_V << SYSTIMER_TIMER_UPDATE_S)
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#define SYSTIMER_TIMER_UPDATE_V 0x00000001
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#define SYSTIMER_TIMER_UPDATE_S 31
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/** SYSTIMER_VALUE_HI_REG register
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* system timer high 32-bit
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*/
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#define SYSTIMER_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x3c)
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/** SYSTIMER_TIMER_VALUE_HI : RO; bitpos: [31:0]; default: 0;
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* system timer high 32-bit
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*/
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#define SYSTIMER_TIMER_VALUE_HI 0xFFFFFFFF
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#define SYSTIMER_TIMER_VALUE_HI_M (SYSTIMER_TIMER_VALUE_HI_V << SYSTIMER_TIMER_VALUE_HI_S)
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#define SYSTIMER_TIMER_VALUE_HI_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_VALUE_HI_S 0
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/** SYSTIMER_VALUE_LO_REG register
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* system timer low 32-bit
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*/
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#define SYSTIMER_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x40)
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/** SYSTIMER_TIMER_VALUE_LO : RO; bitpos: [31:0]; default: 0;
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* system timer low 32-bit
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*/
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#define SYSTIMER_TIMER_VALUE_LO 0xFFFFFFFF
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#define SYSTIMER_TIMER_VALUE_LO_M (SYSTIMER_TIMER_VALUE_LO_V << SYSTIMER_TIMER_VALUE_LO_S)
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#define SYSTIMER_TIMER_VALUE_LO_V 0xFFFFFFFF
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#define SYSTIMER_TIMER_VALUE_LO_S 0
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/** SYSTIMER_INT_ENA_REG register
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* system timer interrupt enable
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*/
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#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x44)
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/** SYSTIMER_SYSTIMER_INT0_ENA : R/W; bitpos: [0]; default: 0;
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* system timer target0 interrupt enable
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*/
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#define SYSTIMER_SYSTIMER_INT0_ENA (BIT(0))
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#define SYSTIMER_SYSTIMER_INT0_ENA_M (SYSTIMER_SYSTIMER_INT0_ENA_V << SYSTIMER_SYSTIMER_INT0_ENA_S)
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#define SYSTIMER_SYSTIMER_INT0_ENA_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT0_ENA_S 0
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/** SYSTIMER_SYSTIMER_INT1_ENA : R/W; bitpos: [1]; default: 0;
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* system timer target1 interrupt enable
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*/
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#define SYSTIMER_SYSTIMER_INT1_ENA (BIT(1))
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#define SYSTIMER_SYSTIMER_INT1_ENA_M (SYSTIMER_SYSTIMER_INT1_ENA_V << SYSTIMER_SYSTIMER_INT1_ENA_S)
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#define SYSTIMER_SYSTIMER_INT1_ENA_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT1_ENA_S 1
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/** SYSTIMER_SYSTIMER_INT2_ENA : R/W; bitpos: [2]; default: 0;
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* system timer target2 interrupt enable
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*/
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#define SYSTIMER_SYSTIMER_INT2_ENA (BIT(2))
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#define SYSTIMER_SYSTIMER_INT2_ENA_M (SYSTIMER_SYSTIMER_INT2_ENA_V << SYSTIMER_SYSTIMER_INT2_ENA_S)
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#define SYSTIMER_SYSTIMER_INT2_ENA_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT2_ENA_S 2
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/** SYSTIMER_INT_RAW_REG register
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* system timer interrupt raw
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*/
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#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x48)
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/** SYSTIMER_SYSTIMER_INT0_RAW : RO; bitpos: [0]; default: 0;
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* system timer target0 interrupt raw
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*/
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#define SYSTIMER_SYSTIMER_INT0_RAW (BIT(0))
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#define SYSTIMER_SYSTIMER_INT0_RAW_M (SYSTIMER_SYSTIMER_INT0_RAW_V << SYSTIMER_SYSTIMER_INT0_RAW_S)
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#define SYSTIMER_SYSTIMER_INT0_RAW_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT0_RAW_S 0
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/** SYSTIMER_SYSTIMER_INT1_RAW : RO; bitpos: [1]; default: 0;
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* system timer target1 interrupt raw
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*/
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#define SYSTIMER_SYSTIMER_INT1_RAW (BIT(1))
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#define SYSTIMER_SYSTIMER_INT1_RAW_M (SYSTIMER_SYSTIMER_INT1_RAW_V << SYSTIMER_SYSTIMER_INT1_RAW_S)
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#define SYSTIMER_SYSTIMER_INT1_RAW_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT1_RAW_S 1
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/** SYSTIMER_SYSTIMER_INT2_RAW : RO; bitpos: [2]; default: 0;
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* system timer target2 interrupt raw
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*/
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#define SYSTIMER_SYSTIMER_INT2_RAW (BIT(2))
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#define SYSTIMER_SYSTIMER_INT2_RAW_M (SYSTIMER_SYSTIMER_INT2_RAW_V << SYSTIMER_SYSTIMER_INT2_RAW_S)
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#define SYSTIMER_SYSTIMER_INT2_RAW_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT2_RAW_S 2
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/** SYSTIMER_INT_CLR_REG register
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* system timer interrupt clear
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*/
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#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x4c)
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/** SYSTIMER_SYSTIMER_INT0_CLR : WO; bitpos: [0]; default: 0;
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* system timer target0 interrupt clear
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*/
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#define SYSTIMER_SYSTIMER_INT0_CLR (BIT(0))
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#define SYSTIMER_SYSTIMER_INT0_CLR_M (SYSTIMER_SYSTIMER_INT0_CLR_V << SYSTIMER_SYSTIMER_INT0_CLR_S)
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#define SYSTIMER_SYSTIMER_INT0_CLR_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT0_CLR_S 0
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/** SYSTIMER_SYSTIMER_INT1_CLR : WO; bitpos: [1]; default: 0;
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* system timer target1 interrupt clear
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*/
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#define SYSTIMER_SYSTIMER_INT1_CLR (BIT(1))
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#define SYSTIMER_SYSTIMER_INT1_CLR_M (SYSTIMER_SYSTIMER_INT1_CLR_V << SYSTIMER_SYSTIMER_INT1_CLR_S)
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#define SYSTIMER_SYSTIMER_INT1_CLR_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT1_CLR_S 1
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/** SYSTIMER_SYSTIMER_INT2_CLR : WO; bitpos: [2]; default: 0;
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* system timer target2 interrupt clear
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*/
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#define SYSTIMER_SYSTIMER_INT2_CLR (BIT(2))
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#define SYSTIMER_SYSTIMER_INT2_CLR_M (SYSTIMER_SYSTIMER_INT2_CLR_V << SYSTIMER_SYSTIMER_INT2_CLR_S)
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#define SYSTIMER_SYSTIMER_INT2_CLR_V 0x00000001
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#define SYSTIMER_SYSTIMER_INT2_CLR_S 2
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/** SYSTIMER_DATE_REG register
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* system timer register version
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*/
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#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
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/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 25194848;
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* system timer register version
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*/
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#define SYSTIMER_DATE 0xFFFFFFFF
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#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
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#define SYSTIMER_DATE_V 0xFFFFFFFF
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#define SYSTIMER_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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