mirror of
https://github.com/espressif/esp-idf.git
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286 lines
8.2 KiB
C
286 lines
8.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include <assert.h>
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#include <string.h>
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#include <stdio.h>
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#include <sys/param.h> // For MIN/MAX(a, b)
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <soc/soc.h>
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#include <soc/soc_memory_layout.h>
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#include "soc/io_mux_reg.h"
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_cpu.h"
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#include "spi_flash_mmap.h"
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#include "esp_log.h"
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#include "esp_private/system_internal.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/esp_clk.h"
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#include "esp_private/esp_gpio_reserve.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#include "esp32/rom/spi_flash.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "soc/spi_mem_reg.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/opi_flash_private.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/cache.h"
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#endif
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#include "esp_rom_spiflash.h"
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#include "esp_flash_partitions.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/cache_utils.h"
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#include "esp_flash.h"
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#include "esp_attr.h"
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#include "bootloader_flash.h"
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#include "bootloader_flash_config.h"
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#include "esp_compiler.h"
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#include "esp_rom_efuse.h"
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#if CONFIG_SPIRAM
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#include "esp_private/esp_psram_io.h"
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#endif
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#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
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#include "hal/cache_hal.h"
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#endif
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/* bytes erased by SPIEraseBlock() ROM function */
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#define BLOCK_ERASE_SIZE 65536
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/* Limit number of bytes written/read in a single SPI operation,
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as these operations disable all higher priority tasks from running.
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*/
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#ifdef CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
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#define MAX_WRITE_CHUNK CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
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#else
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#define MAX_WRITE_CHUNK 8192
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#endif // CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE
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#define MAX_READ_CHUNK 16384
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static const char *TAG __attribute__((unused)) = "spi_flash";
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const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_default_ops = {
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.start = spi_flash_disable_interrupts_caches_and_other_cpu,
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.end = spi_flash_enable_interrupts_caches_and_other_cpu,
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};
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const DRAM_ATTR spi_flash_guard_funcs_t g_flash_guard_no_os_ops = {
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.start = spi_flash_disable_interrupts_caches_and_other_cpu_no_os,
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.end = spi_flash_enable_interrupts_caches_no_os,
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};
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static const spi_flash_guard_funcs_t *s_flash_guard_ops;
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void IRAM_ATTR spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs)
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{
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s_flash_guard_ops = funcs;
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}
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const spi_flash_guard_funcs_t *IRAM_ATTR spi_flash_guard_get(void)
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{
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return s_flash_guard_ops;
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}
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#ifdef CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS
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#define UNSAFE_WRITE_ADDRESS abort()
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#else
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#define UNSAFE_WRITE_ADDRESS return false
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#endif
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static __attribute__((unused)) bool is_safe_write_address(size_t addr, size_t size)
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{
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if (!esp_partition_main_flash_region_safe(addr, size)) {
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UNSAFE_WRITE_ADDRESS;
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}
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return true;
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}
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#if CONFIG_SPI_FLASH_ROM_IMPL
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#include "esp_heap_caps.h"
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void IRAM_ATTR *spi_flash_malloc_internal(size_t size)
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{
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return heap_caps_malloc(size, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
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}
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void IRAM_ATTR spi_flash_rom_impl_init(void)
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{
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spi_flash_guard_set(&g_flash_guard_default_ops);
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/* These two functions are in ROM only */
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extern void spi_flash_mmap_os_func_set(void *(*func1)(size_t size), void (*func2)(void *p));
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spi_flash_mmap_os_func_set(spi_flash_malloc_internal, heap_caps_free);
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extern esp_err_t spi_flash_mmap_page_num_init(uint32_t page_num);
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spi_flash_mmap_page_num_init(128);
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}
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#endif
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void IRAM_ATTR esp_mspi_pin_init(void)
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{
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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bool octal_mspi_required = bootloader_flash_is_octal_mode_enabled();
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#if CONFIG_SPIRAM_MODE_OCT
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octal_mspi_required |= true;
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#endif
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if (octal_mspi_required) {
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esp_rom_opiflash_pin_config();
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mspi_timing_set_pin_drive_strength();
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}
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//Set F4R4 board pin drive strength. TODO: IDF-3663
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#endif
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/* Reserve the GPIO pins */
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uint64_t reserve_pin_mask = 0;
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for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
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reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
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}
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esp_gpio_reserve_pins(reserve_pin_mask);
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}
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esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
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{
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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if (bootloader_flash_is_octal_mode_enabled()) {
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return esp_opiflash_init(rom_spiflash_legacy_data->chip.device_id);
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}
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#endif
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#if CONFIG_SPI_FLASH_HPM_ON
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return spi_flash_enable_high_performance_mode();
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#endif // CONFIG_SPI_FLASH_HPM_ON
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return ESP_OK;
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}
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void IRAM_ATTR spi_flash_set_rom_required_regs(void)
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{
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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if (bootloader_flash_is_octal_mode_enabled()) {
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//Disable the variable dummy mode when doing timing tuning
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CLEAR_PERI_REG_MASK(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY);
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/**
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* STR /DTR mode setting is done every time when `esp_rom_opiflash_exec_cmd` is called
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*
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* Add any registers that are not set in ROM SPI flash functions here in the future
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*/
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}
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#endif
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}
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#if CONFIG_SPIRAM_MODE_OCT
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// This function will only be called when Octal PSRAM enabled.
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void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
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{
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if (bootloader_flash_is_octal_mode_enabled()) {
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esp_opiflash_set_required_regs();
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SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 1, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
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} else {
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//Flash chip requires MSPI specifically, call this function to set them
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// Set back MSPI registers after Octal PSRAM initialization.
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SET_PERI_REG_BITS(SPI_MEM_CACHE_FCTRL_REG(1), SPI_MEM_CACHE_USR_CMD_4BYTE_V, 0, SPI_MEM_CACHE_USR_CMD_4BYTE_S);
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}
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}
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#endif
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static const uint8_t s_mspi_io_num_default[] = {
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SPI_CLK_GPIO_NUM,
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SPI_Q_GPIO_NUM,
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SPI_D_GPIO_NUM,
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SPI_CS0_GPIO_NUM,
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SPI_HD_GPIO_NUM,
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SPI_WP_GPIO_NUM,
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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SPI_DQS_GPIO_NUM,
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SPI_D4_GPIO_NUM,
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SPI_D5_GPIO_NUM,
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SPI_D6_GPIO_NUM,
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SPI_D7_GPIO_NUM
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#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
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};
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uint8_t esp_mspi_get_io(esp_mspi_io_t io)
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{
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#if CONFIG_SPIRAM
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if (io == ESP_MSPI_IO_CS1) {
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return esp_psram_io_get_cs_io();
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}
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#endif
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assert(io >= ESP_MSPI_IO_CLK);
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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assert(io <= ESP_MSPI_IO_D7);
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#else
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assert(io <= ESP_MSPI_IO_WP);
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#endif
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#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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uint8_t mspi_io = 0;
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uint32_t spiconfig = 0;
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if (io == ESP_MSPI_IO_WP) {
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/**
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* wp pad is a bit special:
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* 1. since 32's efuse does not have enough bits for wp pad, so wp pad config put in flash bin header
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* 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num
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*/
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#if CONFIG_IDF_TARGET_ESP32
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return bootloader_flash_get_wp_pin();
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#else
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spiconfig = esp_rom_efuse_get_flash_wp_gpio();
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return (spiconfig == 0x3f) ? s_mspi_io_num_default[io] : spiconfig & 0x3f;
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#endif
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}
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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spiconfig = (io < ESP_MSPI_IO_WP) ? esp_rom_efuse_get_flash_gpio_info() : esp_rom_efuse_get_opiconfig();
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#else
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spiconfig = esp_rom_efuse_get_flash_gpio_info();
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#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
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if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
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mspi_io = s_mspi_io_num_default[io];
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} else if (io < ESP_MSPI_IO_WP) {
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/**
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* [0 : 5] -- CLK
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* [6 :11] -- Q(D1)
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* [12:17] -- D(D0)
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* [18:23] -- CS
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* [24:29] -- HD(D3)
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*/
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mspi_io = (spiconfig >> io * 6) & 0x3f;
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}
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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else {
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/**
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* [0 : 5] -- DQS
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* [6 :11] -- D4
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* [12:17] -- D5
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* [18:23] -- D6
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* [24:29] -- D7
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*/
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mspi_io = (spiconfig >> (io - ESP_MSPI_IO_DQS) * 6) & 0x3f;
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}
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#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
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return mspi_io;
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#else // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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return s_mspi_io_num_default[io];
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#endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
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}
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