mirror of
https://github.com/espressif/esp-idf.git
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255 lines
8.2 KiB
C
255 lines
8.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for SPI Slave HD
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#include <string.h>
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "soc/spi_periph.h"
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#include "soc/lldesc.h"
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#include "soc/soc_caps.h"
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#include "soc/ext_mem_defs.h" //for SOC_NON_CACHEABLE_OFFSET
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#include "hal/spi_slave_hd_hal.h"
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#include "hal/assert.h"
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void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config)
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{
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spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id);
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hal->dev = hw;
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hal->dma_enabled = hal_config->dma_enabled;
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hal->append_mode = hal_config->append_mode;
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hal->tx_cur_desc = hal->dmadesc_tx;
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hal->rx_cur_desc = hal->dmadesc_rx;
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hal->tx_dma_head = hal->dmadesc_tx + hal->dma_desc_num -1;
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hal->rx_dma_head = hal->dmadesc_rx + hal->dma_desc_num -1;
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spi_ll_slave_hd_init(hw);
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spi_ll_set_addr_bitlen(hw, hal_config->address_bits);
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spi_ll_set_command_bitlen(hw, hal_config->command_bits);
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spi_ll_set_dummy(hw, hal_config->dummy_bits);
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spi_ll_set_rx_lsbfirst(hw, hal_config->rx_lsbfirst);
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spi_ll_set_tx_lsbfirst(hw, hal_config->tx_lsbfirst);
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spi_ll_slave_set_mode(hw, hal_config->mode, (hal_config->dma_enabled));
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spi_ll_disable_intr(hw, UINT32_MAX);
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spi_ll_clear_intr(hw, UINT32_MAX);
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if (!hal_config->append_mode) {
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spi_ll_set_intr(hw, SPI_LL_INTR_CMD7 | SPI_LL_INTR_CMD8);
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bool workaround_required = false;
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if (!spi_ll_get_intr(hw, SPI_LL_INTR_CMD7)) {
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hal->intr_not_triggered |= SPI_EV_RECV;
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workaround_required = true;
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}
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if (!spi_ll_get_intr(hw, SPI_LL_INTR_CMD8)) {
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hal->intr_not_triggered |= SPI_EV_SEND;
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workaround_required = true;
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}
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if (workaround_required) {
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//Workaround if the previous interrupts are not writable
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spi_ll_set_intr(hw, SPI_LL_INTR_TRANS_DONE);
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}
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} else {
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#if !SOC_GDMA_SUPPORTED
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spi_ll_enable_intr(hw, SPI_LL_INTR_CMD7 | SPI_LL_INTR_CMD8);
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#endif //SOC_GDMA_SUPPORTED
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}
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spi_ll_slave_hd_set_len_cond(hw, SPI_LL_TRANS_LEN_COND_WRBUF |
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SPI_LL_TRANS_LEN_COND_WRDMA |
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SPI_LL_TRANS_LEN_COND_RDBUF |
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SPI_LL_TRANS_LEN_COND_RDDMA);
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spi_ll_slave_set_seg_mode(hal->dev, true);
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}
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#if SOC_NON_CACHEABLE_OFFSET
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#include "hal/cache_ll.h"
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#define ADDR_DMA_2_CPU(addr) ((typeof(addr))CACHE_LL_L2MEM_NON_CACHE_ADDR(addr))
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#define ADDR_CPU_2_DMA(addr) ((typeof(addr))CACHE_LL_L2MEM_CACHE_ADDR(addr))
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#else
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#define ADDR_DMA_2_CPU(addr) (addr)
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#define ADDR_CPU_2_DMA(addr) (addr)
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#endif
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static int s_desc_get_received_len_addr(spi_dma_desc_t* head, spi_dma_desc_t** out_next, void **out_buff_head)
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{
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spi_dma_desc_t* desc_cpu = ADDR_DMA_2_CPU(head);
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int len = 0;
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if (out_buff_head) {
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*out_buff_head = desc_cpu->buffer;
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}
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while(head) {
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len += desc_cpu->dw0.length;
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bool eof = desc_cpu->dw0.suc_eof;
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desc_cpu = ADDR_DMA_2_CPU(desc_cpu->next);
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head = head->next;
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if (eof) break;
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}
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if (out_next) {
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*out_next = head;
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}
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return len;
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}
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void spi_slave_hd_hal_hw_prepare_rx(spi_slave_hd_hal_context_t *hal)
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{
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spi_ll_dma_rx_fifo_reset(hal->dev);
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spi_ll_infifo_full_clr(hal->dev);
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spi_ll_dma_rx_enable(hal->dev, 1);
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}
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void spi_slave_hd_hal_hw_prepare_tx(spi_slave_hd_hal_context_t *hal)
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{
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spi_ll_dma_tx_fifo_reset(hal->dev);
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spi_ll_outfifo_empty_clr(hal->dev);
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spi_ll_dma_tx_enable(hal->dev, 1);
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}
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void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal)
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{
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spi_ll_slave_reset(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7);
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spi_slave_hd_hal_hw_prepare_rx(hal);
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}
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void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal)
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{
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spi_ll_slave_reset(hal->dev);
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8);
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spi_slave_hd_hal_hw_prepare_tx(hal);
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}
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static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = 0;
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if (ev & SPI_EV_SEND) intr |= SPI_LL_INTR_CMD8;
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if (ev & SPI_EV_RECV) intr |= SPI_LL_INTR_CMD7;
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if (ev & SPI_EV_BUF_TX) intr |= SPI_LL_INTR_RDBUF;
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if (ev & SPI_EV_BUF_RX) intr |= SPI_LL_INTR_WRBUF;
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if (ev & SPI_EV_CMD9) intr |= SPI_LL_INTR_CMD9;
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if (ev & SPI_EV_CMDA) intr |= SPI_LL_INTR_CMDA;
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if (ev & SPI_EV_TRANS) intr |= SPI_LL_INTR_TRANS_DONE;
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return intr;
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}
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bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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if (spi_ll_get_intr(hal->dev, intr)) {
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spi_ll_clear_intr(hal->dev, intr);
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return true;
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}
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return false;
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}
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bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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//The trans_done interrupt is used for the workaround when some interrupt is not writable
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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// Workaround for these interrupts not writable
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uint32_t missing_intr = hal->intr_not_triggered & ev;
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if (missing_intr) {
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if ((missing_intr & SPI_EV_RECV) && spi_ll_get_intr(hal->dev, SPI_LL_INTR_CMD7)) {
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hal->intr_not_triggered &= ~SPI_EV_RECV;
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}
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if ((missing_intr & SPI_EV_SEND) && spi_ll_get_intr(hal->dev, SPI_LL_INTR_CMD8)) {
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hal->intr_not_triggered &= ~SPI_EV_SEND;
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}
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if (spi_ll_get_intr(hal->dev, SPI_LL_INTR_TRANS_DONE)) {
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spi_ll_disable_intr(hal->dev, SPI_LL_INTR_TRANS_DONE);
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}
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}
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if (spi_ll_get_intr(hal->dev, intr)) {
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spi_ll_disable_intr(hal->dev, intr);
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return true;
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}
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return false;
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}
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void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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spi_ll_enable_intr(hal->dev, intr);
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}
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void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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{
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spi_ll_intr_t intr = get_event_intr(hal, ev);
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// Workaround for these interrupts not writable
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if (hal->intr_not_triggered & ev & (SPI_EV_RECV | SPI_EV_SEND)) {
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intr |= SPI_LL_INTR_TRANS_DONE;
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}
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spi_ll_enable_intr(hal->dev, intr);
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}
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void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len)
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{
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spi_ll_read_buffer_byte(hal->dev, addr, out_data, len);
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}
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void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *data, size_t len)
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{
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spi_ll_write_buffer_byte(hal->dev, addr, data, len);
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}
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int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal)
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{
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return spi_ll_slave_hd_get_last_addr(hal->dev);
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}
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int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal)
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{
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//this is by -byte
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return spi_ll_slave_get_rx_byte_len(hal->dev);
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}
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int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal)
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{
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spi_dma_desc_t *desc = hal->dmadesc_rx->desc;
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return s_desc_get_received_len_addr(desc, NULL, NULL);
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}
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bool spi_slave_hd_hal_get_tx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans, void **real_buff_addr)
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{
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if ((uint32_t)hal->tx_dma_head->desc == hal->current_eof_addr) {
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return false;
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}
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//find used paired desc-trans by desc addr
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hal->tx_dma_head++;
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if (hal->tx_dma_head >= hal->dmadesc_tx + hal->dma_desc_num) {
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hal->tx_dma_head = hal->dmadesc_tx;
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}
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*out_trans = hal->tx_dma_head->arg;
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s_desc_get_received_len_addr(hal->tx_dma_head->desc, NULL, real_buff_addr);
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return true;
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}
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bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans, void **real_buff_addr, size_t *out_len)
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{
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if ((uint32_t)hal->rx_dma_head->desc == hal->current_eof_addr) {
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return false;
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}
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//find used paired desc-trans by desc addr
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hal->rx_dma_head++;
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if (hal->rx_dma_head >= hal->dmadesc_rx + hal->dma_desc_num) {
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hal->rx_dma_head = hal->dmadesc_rx;
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}
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*out_trans = hal->rx_dma_head->arg;
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*out_len = s_desc_get_received_len_addr(hal->rx_dma_head->desc, NULL, real_buff_addr);
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return true;
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}
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