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81 lines
3.2 KiB
C
81 lines
3.2 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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The cache has an interrupt that can be raised as soon as an access to a cached
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region (flash, psram) is done without the cache being enabled. We use that here
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to panic the CPU, which from a debugging perspective is better than grabbing bad
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data from the bus.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "freertos/FreeRTOS.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_attr.h"
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#include "soc/extmem_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/periph_defs.h"
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#include "sdkconfig.h"
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#include "esp32s2/dport_access.h"
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void esp_cache_err_int_init(void)
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{
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uint32_t core_id = xPortGetCoreID();
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ESP_INTR_DISABLE(ETS_MEMACCESS_ERR_INUM);
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// We do not register a handler for the interrupt because it is interrupt
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// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
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// a call to the panic handler for
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// this interrupt.
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intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
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// Enable invalid cache access interrupt when the cache is disabled.
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// The status bits are cleared first, in case we are restarting after
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// a cache error has triggered.
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DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_CLR_REG,
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EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
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EXTMEM_DCACHE_REJECT_INT_CLR |
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EXTMEM_DCACHE_WRITE_FLASH_INT_CLR |
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EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR |
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EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR |
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EXTMEM_ICACHE_REJECT_INT_CLR |
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EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR |
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EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR);
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DPORT_SET_PERI_REG_MASK(EXTMEM_CACHE_DBG_INT_ENA_REG,
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EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
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EXTMEM_DCACHE_REJECT_INT_ENA |
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EXTMEM_DCACHE_WRITE_FLASH_INT_ENA |
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EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA |
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EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA |
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EXTMEM_ICACHE_REJECT_INT_ENA |
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EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA |
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EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA |
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EXTMEM_CACHE_DBG_EN);
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ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
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}
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int IRAM_ATTR esp_cache_err_get_cpuid(void)
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{
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if (REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG) != 0 ||
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REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG) != 0) {
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return PRO_CPU_NUM;
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}
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return -1;
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}
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