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185 lines
7.3 KiB
C
185 lines
7.3 KiB
C
/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** MEM_MONITOR_LOG_SETTING_REG register
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* log config regsiter
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*/
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#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
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/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
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* enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
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*/
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#define MEM_MONITOR_LOG_ENA 0x00000007U
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#define MEM_MONITOR_LOG_ENA_M (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
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#define MEM_MONITOR_LOG_ENA_V 0x00000007U
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#define MEM_MONITOR_LOG_ENA_S 0
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/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
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* This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
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* HALFWORD monitor, 4'b1000: BYTE monitor.
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*/
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#define MEM_MONITOR_LOG_MODE 0x0000000FU
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#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
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#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
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#define MEM_MONITOR_LOG_MODE_S 3
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/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
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* Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
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*/
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#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(7))
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#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
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#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
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#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 7
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/** MEM_MONITOR_LOG_CHECK_DATA_REG register
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* check data regsiter
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*/
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#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
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/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
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* The special check data, when write this special data, it will trigger logging.
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*/
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#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
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#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_CHECK_DATA_S 0
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/** MEM_MONITOR_LOG_DATA_MASK_REG register
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* check data mask register
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*/
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#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
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/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
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* byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
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* mask second byte, and so on.
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*/
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#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
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#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
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#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
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#define MEM_MONITOR_LOG_DATA_MASK_S 0
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/** MEM_MONITOR_LOG_MIN_REG register
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* log boundary regsiter
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*/
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#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
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/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
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* the min address of log range
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*/
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#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
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#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MIN_S 0
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/** MEM_MONITOR_LOG_MAX_REG register
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* log boundary regsiter
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*/
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#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
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/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
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* the max address of log range
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*/
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#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
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#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MAX_S 0
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/** MEM_MONITOR_LOG_MEM_START_REG register
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* log message store range register
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*/
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#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
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/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
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* the start address of writing logging message
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*/
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#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
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#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MEM_START_S 0
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/** MEM_MONITOR_LOG_MEM_END_REG register
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* log message store range register
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*/
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#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
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/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
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* the end address of writing logging message
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*/
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#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
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#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MEM_END_S 0
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/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
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* current writing address.
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*/
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#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
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/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
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* means next writing address
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*/
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#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
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#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
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#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
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/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
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* writing address update
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*/
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#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
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/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
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* Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
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* MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
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*/
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#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
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#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
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#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
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#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
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/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
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* full flag status register
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*/
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#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
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/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
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* 1 means memory write loop at least one time at the range of MEM_START and MEM_END
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*/
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#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
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#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
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#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
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#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
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/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
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* Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
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*/
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#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
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#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
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#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
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#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
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/** MEM_MONITOR_CLOCK_GATE_REG register
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* clock gate force on register
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*/
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#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
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/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
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* Set 1 to force on the clk of mem_monitor register
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*/
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#define MEM_MONITOR_CLK_EN (BIT(0))
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#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
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#define MEM_MONITOR_CLK_EN_V 0x00000001U
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#define MEM_MONITOR_CLK_EN_S 0
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/** MEM_MONITOR_DATE_REG register
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* version register
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*/
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#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
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/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
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* version register
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*/
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#define MEM_MONITOR_DATE 0x0FFFFFFFU
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#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
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#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
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#define MEM_MONITOR_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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