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266 lines
9.2 KiB
C
266 lines
9.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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Tests for the spi sio mode
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*/
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#include <esp_types.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <malloc.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "unity.h"
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#include "driver/spi_master.h"
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#include "driver/spi_slave.h"
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#include "esp_heap_caps.h"
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#include "esp_log.h"
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#include "soc/spi_periph.h"
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#include "test_utils.h"
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#include "test/test_common_spi.h"
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#include "soc/gpio_periph.h"
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#include "hal/spi_ll.h"
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#if (TEST_SPI_PERIPH_NUM >= 2)
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//These will be only enabled on chips with 2 or more SPI peripherals
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/********************************************************************************
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* Test SIO
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********************************************************************************/
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#if CONFIG_IDF_TARGET_ESP32
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#define MASTER_DIN_SIGNAL HSPID_IN_IDX
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#else
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#define MASTER_DIN_SIGNAL FSPID_IN_IDX
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#endif
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static void inner_connect(spi_bus_config_t bus)
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{
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//Master MOSI(spid_out) output to `mosi_num`
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spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
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//Slave MOSI(spid_in) input to `mosi_num`
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spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in);
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//Master MOSI input(spid_in) to `miso_num`, due to SIO mode, we use Master's `spid_in` to receive data
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spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);
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//Slave MISO output(spiq_out)
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spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
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//Force this signal goes through gpio matrix
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GPIO.func_in_sel_cfg[MASTER_DIN_SIGNAL].sig_in_sel = 1;
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}
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TEST_CASE("SPI Single Board Test SIO", "[spi]")
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{
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//Master init
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spi_device_handle_t spi;
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_DISABLED));
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
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dev_cfg.clock_speed_hz = 4 * 1000 * 1000;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
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//Slave init
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bus_cfg.flags = 0;
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spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
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TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED));
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same_pin_func_sel(bus_cfg, dev_cfg, 0);
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inner_connect(bus_cfg);
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WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
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WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
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spi_transaction_t mst_trans;
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spi_slave_transaction_t slv_trans;
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spi_slave_transaction_t* ret;
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for (int i = 0; i < 8; i ++) {
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int tlen = i * 2 + 1;
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int rlen = 9 - i;
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ESP_LOGI("spi", "=========== TEST(%d) Master TX, Slave RX ==========", i);
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//Slave RX
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memset(&slv_trans, 0x0, sizeof(spi_slave_transaction_t));
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memset(slave_rx_buffer, 0x66, sizeof(slave_rx_buffer));
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slv_trans.length = tlen * 8;
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slv_trans.rx_buffer = slave_rx_buffer + tlen * 8;
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slv_trans, portMAX_DELAY));
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//Master TX
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memset(&mst_trans, 0x0, sizeof(spi_transaction_t));
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mst_trans.length = tlen * 8;
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mst_trans.tx_buffer = spitest_master_send;
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TEST_ESP_OK(spi_device_transmit(spi, &mst_trans));
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TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret, portMAX_DELAY));
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TEST_ASSERT(ret == &slv_trans);
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ESP_LOG_BUFFER_HEXDUMP("master tx", mst_trans.tx_buffer, tlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("slave rx", slv_trans.rx_buffer, tlen, ESP_LOG_INFO);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(mst_trans.tx_buffer, slv_trans.rx_buffer, tlen);
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ESP_LOGI("spi", "=========== TEST(%d) Master RX, Slave TX ==========", i);
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//Slave TX
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memset(&slv_trans, 0x0, sizeof(spi_slave_transaction_t));
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slv_trans.length = rlen * 8;
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slv_trans.tx_buffer = spitest_slave_send + rlen * 8;
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slv_trans, portMAX_DELAY));
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//Master RX
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memset(&mst_trans, 0x0, sizeof(spi_transaction_t));
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memset(master_rx_buffer, 0x66, sizeof(master_rx_buffer));
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mst_trans.rxlength = rlen * 8;
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mst_trans.rx_buffer = master_rx_buffer;
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TEST_ESP_OK(spi_device_transmit(spi, &mst_trans));
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TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret, portMAX_DELAY));
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TEST_ASSERT(ret == &slv_trans);
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ESP_LOG_BUFFER_HEXDUMP("slave tx", slv_trans.tx_buffer, rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("master rx", mst_trans.rx_buffer, rlen, ESP_LOG_INFO);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(slv_trans.tx_buffer, mst_trans.rx_buffer, rlen);
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}
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spi_slave_free(TEST_SLAVE_HOST);
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master_free_device_bus(spi);
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}
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#endif //#if (TEST_SPI_PERIPH_NUM >= 2)
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//TODO IDF-4455
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32S3, ESP32C2, ESP32H2)
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//These tests are ESP32 only due to lack of runners
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/********************************************************************************
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* Test SIO Master & Slave
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********************************************************************************/
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//if test_mosi is false, test on miso of slave, otherwise test on mosi of slave
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void test_sio_master_round(bool test_mosi)
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{
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spi_device_handle_t spi;
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WORD_ALIGNED_ATTR uint8_t rx_buffer[320];
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if (test_mosi) {
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ESP_LOGI(MASTER_TAG, "======== TEST MOSI ===========");
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} else {
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ESP_LOGI(MASTER_TAG, "======== TEST MISO ===========");
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}
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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if (!test_mosi) bus_cfg.mosi_io_num = bus_cfg.miso_io_num;
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bus_cfg.miso_io_num = -1;
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0));
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
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dev_cfg.clock_speed_hz = 1*1000*1000;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
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for (int i = 0; i < 8; i ++) {
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int tlen = i*2+1;
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int rlen = 9-i;
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spi_transaction_t t = {
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.length = tlen*8,
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.tx_buffer = spitest_master_send+i,
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.rxlength = rlen*8,
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.rx_buffer = rx_buffer+i,
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};
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memset(rx_buffer, 0x66, sizeof(rx_buffer));
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//get signal
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unity_wait_for_signal("slave ready");
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TEST_ESP_OK(spi_device_transmit(spi, &t));
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uint8_t* exp_ptr = spitest_slave_send+i;
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ESP_LOG_BUFFER_HEXDUMP("master tx", t.tx_buffer, tlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("master rx", t.rx_buffer, rlen, ESP_LOG_INFO);
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if (!test_mosi) {
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TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr+tlen, t.rx_buffer, rlen);
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}
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}
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master_free_device_bus(spi);
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}
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void test_sio_master(void)
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{
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test_sio_master_round(true);
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unity_send_signal("master ready");
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test_sio_master_round(false);
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}
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void test_sio_slave_round(bool test_mosi)
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{
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WORD_ALIGNED_ATTR uint8_t rx_buffer[320];
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if (test_mosi) {
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ESP_LOGI(SLAVE_TAG, "======== TEST MOSI ===========");
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} else {
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ESP_LOGI(SLAVE_TAG, "======== TEST MISO ===========");
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}
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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bus_cfg.mosi_io_num = spi_periph_signal[TEST_SLAVE_HOST].spid_iomux_pin;
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bus_cfg.miso_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiq_iomux_pin;
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bus_cfg.sclk_io_num = spi_periph_signal[TEST_SLAVE_HOST].spiclk_iomux_pin;
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spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
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slv_cfg.spics_io_num = spi_periph_signal[TEST_SLAVE_HOST].spics0_iomux_pin;
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TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, 0));
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for (int i = 0; i < 8; i++) {
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int tlen = 9-i;
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int rlen = i*2+1;
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spi_slave_transaction_t t = {
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.length = (tlen+rlen)*8,
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.tx_buffer = spitest_slave_send+i,
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.rx_buffer = rx_buffer,
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};
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TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &t, portMAX_DELAY));
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ESP_LOG_BUFFER_HEXDUMP("slave tx", t.tx_buffer, tlen+rlen, ESP_LOG_INFO);
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//send signal_idx
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unity_send_signal("slave ready");
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uint8_t *exp_ptr = spitest_master_send+i;
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spi_slave_transaction_t* ret_t;
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TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_t, portMAX_DELAY));
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ESP_LOG_BUFFER_HEXDUMP("exp tx", exp_ptr, tlen+rlen, ESP_LOG_INFO);
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ESP_LOG_BUFFER_HEXDUMP("slave rx", t.rx_buffer, tlen+rlen, ESP_LOG_INFO);
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if (test_mosi) {
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TEST_ASSERT_EQUAL_HEX8_ARRAY(exp_ptr, t.rx_buffer, rlen);
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}
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}
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spi_slave_free(TEST_SLAVE_HOST);
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}
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void test_sio_slave(void)
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{
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test_sio_slave_round(true);
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unity_wait_for_signal("master ready");
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test_sio_slave_round(false);
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}
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TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave);
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#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3, ESP32C2, ESP32H2)
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