Angus Gratton da27816314 Merge branch 'feat/add_efuse_cpu_freq_rating' into 'master' ...

efuse/add cpu freq rating

See merge request idf/esp-idf!1994

2018-03-29 05:59:52 +08:00

..

esp32

Merge branch 'feat/add_efuse_cpu_freq_rating' into 'master'

2018-03-29 05:59:52 +08:00

include/soc

Especially when internal memory fills up, some FreeRTOS structures (queues etc) get allocated in psram. These structures also contain a spinlock, which needs an atomic-compare-swap operation to work. The psram hardware, however, does not support this operation. As a workaround, this patch detects these spinlocks and will, instead of S32C1I, use equivalent C-code to simulate the behaviour, with an (internal) mux for atomicity.

2018-02-02 17:11:06 +08:00

test

soc: add source code of rtc_clk, rtc_pm

2017-04-11 15:45:54 +08:00

component.mk

Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.

2017-09-04 12:05:49 +08:00