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112 lines
4.1 KiB
C
112 lines
4.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/**
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* @file regi2c_saradc.h
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* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
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*
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* This file lists register fields of SAR, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* function in adc_ll.h.
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*/
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#define I2C_SAR_ADC 0x69
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#define I2C_SAR_ADC_HOSTID 0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
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#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
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#define ADC_SAR1_DREF_ADDR 0x2
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#define ADC_SAR1_DREF_ADDR_MSB 0x6
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#define ADC_SAR1_DREF_ADDR_LSB 0x4
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
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#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
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#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
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#define ADC_SAR2_DREF_ADDR 0x5
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#define ADC_SAR2_DREF_ADDR_MSB 0x6
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#define ADC_SAR2_DREF_ADDR_LSB 0x4
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#define I2C_SARADC_TSENS_DAC 0x6
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#define I2C_SARADC_TSENS_DAC_MSB 0x3
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#define I2C_SARADC_TSENS_DAC_LSB 0x0
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#define I2C_SARADC_DTEST 0x7
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#define I2C_SARADC_DTEST_MSB 0x1
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#define I2C_SARADC_DTEST_LSB 0x0
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#define I2C_SARADC_ENT_TSENS 0x7
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#define I2C_SARADC_ENT_TSENS_MSB 0x2
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#define I2C_SARADC_ENT_TSENS_LSB 0x2
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#define I2C_SARADC_ENT_SAR 0x7
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#define I2C_SARADC_ENT_SAR_MSB 0x3
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#define I2C_SARADC_ENT_SAR_LSB 0x3
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#define I2C_SARADC1_ENCAL_REF 0x7
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#define I2C_SARADC1_ENCAL_REF_MSB 0x4
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#define I2C_SARADC1_ENCAL_REF_LSB 0x4
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#define ADC_SAR1_ENCAL_GND_ADDR 0x7
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#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x5
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#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x5
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#define I2C_SARADC2_ENCAL_REF 0x7
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#define I2C_SARADC2_ENCAL_REF_MSB 0x6
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#define I2C_SARADC2_ENCAL_REF_LSB 0x6
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#define I2C_SAR2_ENCAL_GND 0x7
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#define I2C_SAR2_ENCAL_GND_MSB 0x7
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#define I2C_SAR2_ENCAL_GND_LSB 0x7
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#define POWER_GLITCH_XPD_VDET_PERIF 0x10
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#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0x0
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#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0x0
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#define POWER_GLITCH_XPD_VDET_VDDPST 0x10
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#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 0x1
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#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 0x1
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#define POWER_GLITCH_XPD_VDET_PLLBB 0x10
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#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 0x2
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#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 0x2
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#define POWER_GLITCH_XPD_VDET_PLL 0x10
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#define POWER_GLITCH_XPD_VDET_PLL_MSB 0x3
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#define POWER_GLITCH_XPD_VDET_PLL_LSB 0x3
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#define POWER_GLITCH_DREF_VDET_PERIF 0x11
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#define POWER_GLITCH_DREF_VDET_PERIF_MSB 0x2
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#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0x0
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#define POWER_GLITCH_DREF_VDET_VDDPST 0x11
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#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 0x6
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#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 0x4
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#define POWER_GLITCH_DREF_VDET_PLLBB 0x12
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#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 0x2
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#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0x0
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#define POWER_GLITCH_DREF_VDET_PLL 0x12
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#define POWER_GLITCH_DREF_VDET_PLL_MSB 0x6
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#define POWER_GLITCH_DREF_VDET_PLL_LSB 0x4
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