Allow to customize uart source_clk

This is for example needed when using an external crystal to select
UART_SCLK_XTAL, which fixes uart comm issue when using PM with light
sleep enabled.
This commit is contained in:
Bruno Binet
2022-06-22 15:37:06 +02:00
parent 51a50db0fd
commit d723fb7a5a
4 changed files with 7 additions and 3 deletions

View File

@ -22,6 +22,7 @@
.stop_bits = UART_STOP_BITS_1, \
.parity = UART_PARITY_DISABLE, \
.flow_control = ESP_MODEM_FLOW_CONTROL_NONE,\
.source_clk = UART_SCLK_APB, \
.baud_rate = 115200, \
.tx_io_num = 25, \
.rx_io_num = 26, \