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Allow to customize uart source_clk
This is for example needed when using an external crystal to select UART_SCLK_XTAL, which fixes uart comm issue when using PM with light sleep enabled.
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@ -22,6 +22,7 @@
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.stop_bits = UART_STOP_BITS_1, \
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.parity = UART_PARITY_DISABLE, \
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.flow_control = ESP_MODEM_FLOW_CONTROL_NONE,\
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.source_clk = UART_SCLK_APB, \
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.baud_rate = 115200, \
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.tx_io_num = 25, \
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.rx_io_num = 26, \
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