From 0362fcda3143d2095059d0bd3f98a27e343ddc1a Mon Sep 17 00:00:00 2001
From: Michael Miller <Makuna@hotmail.com>
Date: Mon, 24 May 2021 20:53:54 -0700
Subject: [PATCH] Esp8266 v3 updates (#472)

Fix to use standard IRAM_ATTR now supported between Esp8266 and ESP32
---
 src/internal/NeoEsp8266DmaMethod.h    |  4 ++--
 src/internal/NeoEsp8266UartMethod.cpp |  4 ++--
 src/internal/NeoEsp8266UartMethod.h   | 10 +++++-----
 src/internal/NeoEspBitBangMethod.cpp  |  4 ++--
 src/internal/NeoEspBitBangMethod.h    |  5 -----
 5 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/src/internal/NeoEsp8266DmaMethod.h b/src/internal/NeoEsp8266DmaMethod.h
index a68a2c1..f867ac8 100644
--- a/src/internal/NeoEsp8266DmaMethod.h
+++ b/src/internal/NeoEsp8266DmaMethod.h
@@ -404,7 +404,7 @@ public:
         I2SC |= I2STXS; // Start transmission
     }
 
-    void ICACHE_RAM_ATTR Update(bool)
+    void IRAM_ATTR Update(bool)
     {
         // wait for not actively sending data
         while (!IsReadyToUpdate())
@@ -455,7 +455,7 @@ private:
     // handle here is the RX_EOF_INT status, which indicate the DMA has sent a buffer whose
     // descriptor has the 'EOF' field set to 1.
     // in the case of this code, the second to last state descriptor
-    static void ICACHE_RAM_ATTR i2s_slc_isr(void)
+    static void IRAM_ATTR i2s_slc_isr(void)
     {
         ETS_SLC_INTR_DISABLE();
 
diff --git a/src/internal/NeoEsp8266UartMethod.cpp b/src/internal/NeoEsp8266UartMethod.cpp
index 5b6c4ad..66324b9 100644
--- a/src/internal/NeoEsp8266UartMethod.cpp
+++ b/src/internal/NeoEsp8266UartMethod.cpp
@@ -35,7 +35,7 @@ extern "C"
     #include <ets_sys.h>
 }
 
-const volatile uint8_t* ICACHE_RAM_ATTR NeoEsp8266UartContext::FillUartFifo(uint8_t uartNum,
+const volatile uint8_t* IRAM_ATTR NeoEsp8266UartContext::FillUartFifo(uint8_t uartNum,
     const volatile uint8_t* start,
     const volatile uint8_t* end)
 {
@@ -139,7 +139,7 @@ void NeoEsp8266UartInterruptContext::Detach(uint8_t uartNum)
     ETS_UART_INTR_ENABLE();
 }
 
-void ICACHE_RAM_ATTR NeoEsp8266UartInterruptContext::Isr(void* param)
+void IRAM_ATTR NeoEsp8266UartInterruptContext::Isr(void* param)
 {
     // make sure this is for us
     if (param == s_uartInteruptContext)
diff --git a/src/internal/NeoEsp8266UartMethod.h b/src/internal/NeoEsp8266UartMethod.h
index 2a5ee44..3d57d7c 100644
--- a/src/internal/NeoEsp8266UartMethod.h
+++ b/src/internal/NeoEsp8266UartMethod.h
@@ -37,17 +37,17 @@ class NeoEsp8266UartContext
 {
 public:
     // Gets the number of bytes waiting in the TX FIFO
-    static inline uint8_t ICACHE_RAM_ATTR GetTxFifoLength(uint8_t uartNum)
+    static inline uint8_t IRAM_ATTR GetTxFifoLength(uint8_t uartNum)
     {
         return (USS(uartNum) >> USTXC) & 0xff;
     }
     // Append a byte to the TX FIFO
-    static inline void ICACHE_RAM_ATTR Enqueue(uint8_t uartNum, uint8_t value)
+    static inline void IRAM_ATTR Enqueue(uint8_t uartNum, uint8_t value)
     {
         USF(uartNum) = value;
     }
 
-    static const volatile uint8_t* ICACHE_RAM_ATTR FillUartFifo(uint8_t uartNum,
+    static const volatile uint8_t* IRAM_ATTR FillUartFifo(uint8_t uartNum,
         const volatile uint8_t* start,
         const volatile uint8_t* end);
 };
@@ -79,7 +79,7 @@ private:
     volatile const uint8_t* _asyncBuffEnd;
     volatile static NeoEsp8266UartInterruptContext* s_uartInteruptContext[2]; 
 
-    static void ICACHE_RAM_ATTR Isr(void* param);
+    static void IRAM_ATTR Isr(void* param);
 };
 
 // this template feature class is used a base for all others and contains 
@@ -241,7 +241,7 @@ protected:
         free(_dataSending);
     }
 
-    void ICACHE_RAM_ATTR InitializeUart(uint32_t uartBaud, bool invert)
+    void IRAM_ATTR InitializeUart(uint32_t uartBaud, bool invert)
     {
         T_UARTFEATURE::Init(uartBaud, invert);
      
diff --git a/src/internal/NeoEspBitBangMethod.cpp b/src/internal/NeoEspBitBangMethod.cpp
index 1166d80..aad7943 100644
--- a/src/internal/NeoEspBitBangMethod.cpp
+++ b/src/internal/NeoEspBitBangMethod.cpp
@@ -35,7 +35,7 @@ static inline uint32_t getCycleCount(void)
     return ccount;
 }
 
-void ICACHE_RAM_ATTR NeoEspBitBangBase_send_pixels(uint8_t* pixels, uint8_t* end, uint8_t pin, uint32_t t0h, uint32_t t1h, uint32_t period)
+void IRAM_ATTR NeoEspBitBangBase_send_pixels(uint8_t* pixels, uint8_t* end, uint8_t pin, uint32_t t0h, uint32_t t1h, uint32_t period)
 {
     const uint32_t pinRegister = _BV(pin);
     uint8_t mask = 0x80;
@@ -93,7 +93,7 @@ void ICACHE_RAM_ATTR NeoEspBitBangBase_send_pixels(uint8_t* pixels, uint8_t* end
     }
 }
 
-void ICACHE_RAM_ATTR NeoEspBitBangBase_send_pixels_inv(uint8_t* pixels, uint8_t* end, uint8_t pin, uint32_t t0h, uint32_t t1h, uint32_t period)
+void IRAM_ATTR NeoEspBitBangBase_send_pixels_inv(uint8_t* pixels, uint8_t* end, uint8_t pin, uint32_t t0h, uint32_t t1h, uint32_t period)
 {
     const uint32_t pinRegister = _BV(pin);
     uint8_t mask = 0x80;
diff --git a/src/internal/NeoEspBitBangMethod.h b/src/internal/NeoEspBitBangMethod.h
index 6e24ffe..31e3811 100644
--- a/src/internal/NeoEspBitBangMethod.h
+++ b/src/internal/NeoEspBitBangMethod.h
@@ -32,11 +32,6 @@ License along with NeoPixel.  If not, see
 #include <eagle_soc.h>
 #endif
 
-// ESP32 doesn't define ICACHE_RAM_ATTR
-#ifndef ICACHE_RAM_ATTR
-#define ICACHE_RAM_ATTR IRAM_ATTR
-#endif
-
 #define CYCLES_LOOPTEST   (4) // adjustment due to loop exit test instruction cycles
 
 class NeoEspSpeedWs2811