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Add P4 exclusions for CORE3 (#853)

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* P4 Exclusion

* P4 Exclusion

* P4 Exclusions
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Troy authored and GitHub committed 2024-10-13 08:30:53 -07:00
1 parent a31d97c293
commit 2edd93ddbe
2 files changed
+5 -5
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src/internal/methods/ESP/NeoEspBitBangMethod.cpp
+2 -2
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@@ -36,7 +36,7 @@ static inline uint32_t getCycleCount(void)
{
uint32_t ccount;
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32H2)
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP32P4)
__asm__ __volatile__("csrr %0,0x7e2":"=r" (ccount));
//ccount = esp_cpu_get_ccount();
#else
@@ -114,7 +114,7 @@ bool IRAM_ATTR neoEspBitBangWriteSpacingPixels(const uint8_t* pixels,
volatile uint32_t* setRegister;
volatile uint32_t* clearRegister;
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32H2)
#if defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C6) || defined(CONFIG_IDF_TARGET_ESP32H2) || defined(CONFIG_IDF_TARGET_ESP32P4)
if (pin < 32)
{
setRegister = &GPIO.out_w1ts.val;