From 3dabc2ee829fe041a8c516b0c89b433e8066ee76 Mon Sep 17 00:00:00 2001 From: Michael Miller Date: Thu, 26 Dec 2024 20:04:36 -0500 Subject: [PATCH] STM32WLE5xx support (#867) --- src/internal/methods/NeoArmMethod.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/internal/methods/NeoArmMethod.h b/src/internal/methods/NeoArmMethod.h index 130aae4..2ea403b 100644 --- a/src/internal/methods/NeoArmMethod.h +++ b/src/internal/methods/NeoArmMethod.h @@ -560,7 +560,7 @@ typedef NeoArm400KbpsMethod NeoArmApa106Method; typedef NeoArmWs2805Method NeoArmWs2814Method; typedef NeoArmTm1814InvertedMethod NeoArmTm1914InvertedMethod; -#elif defined(ARDUINO_STM32_FEATHER) || defined(ARDUINO_ARCH_STM32L4) || defined(ARDUINO_ARCH_STM32F4) || defined(ARDUINO_ARCH_STM32F1)// FEATHER WICED (120MHz) +#elif defined(ARDUINO_ARCH_STM32) || defined(ARDUINO_STM32_FEATHER) || defined(ARDUINO_ARCH_STM32L4) || defined(ARDUINO_ARCH_STM32F4) || defined(ARDUINO_ARCH_STM32F1)// FEATHER WICED (120MHz) class NeoArmStm32SpeedProps800KbpsBase { @@ -705,7 +705,21 @@ public: volatile uint32_t* set = &(GPIO->BRR); volatile uint32_t* clr = &(GPIO->BSRR); +#elif defined(STM32WLE5xx) + const unsigned long GPIO_BASE_ADDR = 0x48000000UL; + const unsigned long GPIO_BASE_OFFSET = 0x00000400UL; + const uint32_t GPIO_NUMBER = 16; + + uint32_t pinMask = 1 << (pin % GPIO_NUMBER); + + GPIO_TypeDef* GPIO = reinterpret_cast(GPIO_BASE_ADDR + ((pin / GPIO_NUMBER) * GPIO_BASE_OFFSET)); + + volatile uint32_t* set = &(GPIO->BRR); + volatile uint32_t* clr = &(GPIO->BSRR); +#else +#error "SPECIFIC STM32 CHIP NOT ACCOUNTED FOR" #endif + for (;;) { if (p & bitMask)