forked from Makuna/NeoPixelBus
Uart0 support (#239)
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@@ -29,186 +29,114 @@ License along with NeoPixel. If not, see
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#include <utility>
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extern "C"
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{
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#include <eagle_soc.h>
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// #include <eagle_soc.h>
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#include <ets_sys.h>
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#include <uart.h>
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#include <uart_register.h>
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// #include <uart.h>
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// #include <uart_register.h>
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}
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#define UART1 1
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#define UART1_INV_MASK (0x3f << 19)
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volatile NeoEsp8266UartInterruptContext* NeoEsp8266UartInterruptContext::s_uartInteruptContext[] = { nullptr, nullptr };
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// Gets the number of bytes waiting in the TX FIFO of UART1
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static inline uint8_t getUartTxFifoLength()
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void NeoEsp8266UartInterruptContext::StartSending(uint8_t uartNum, uint8_t* start, uint8_t* end)
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{
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return (U1S >> USTXC) & 0xff;
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// send the pixels asynchronously
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_asyncBuff = start;
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_asyncBuffEnd = end;
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// enable the transmit interrupt
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USIE(uartNum) |= (1 << UIFE);
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}
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// Append a byte to the TX FIFO of UART1
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// You must ensure the TX FIFO isn't full
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static inline void enqueue(uint8_t byte)
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void NeoEsp8266UartInterruptContext::Attach(uint8_t uartNum)
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{
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U1F = byte;
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}
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static const uint8_t* esp8266_uart1_async_buf;
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static const uint8_t* esp8266_uart1_async_buf_end;
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NeoEsp8266Uart::NeoEsp8266Uart(uint16_t pixelCount, size_t elementSize)
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{
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_sizePixels = pixelCount * elementSize;
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_pixels = (uint8_t*)malloc(_sizePixels);
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memset(_pixels, 0x00, _sizePixels);
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}
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NeoEsp8266Uart::~NeoEsp8266Uart()
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{
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// Wait until the TX fifo is empty. This way we avoid broken frames
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// when destroying & creating a NeoPixelBus to change its length.
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while (getUartTxFifoLength() > 0)
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{
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yield();
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}
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free(_pixels);
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}
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void NeoEsp8266Uart::InitializeUart(uint32_t uartBaud)
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{
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// Configure the serial line with 1 start bit (0), 6 data bits and 1 stop bit (1)
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Serial1.begin(uartBaud, SERIAL_6N1, SERIAL_TX_ONLY);
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// Invert the TX voltage associated with logic level so:
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// - A logic level 0 will generate a Vcc signal
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// - A logic level 1 will generate a Gnd signal
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CLEAR_PERI_REG_MASK(UART_CONF0(UART1), UART1_INV_MASK);
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SET_PERI_REG_MASK(UART_CONF0(UART1), (BIT(22)));
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}
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void NeoEsp8266Uart::UpdateUart()
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{
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// Since the UART can finish sending queued bytes in the FIFO in
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// the background, instead of waiting for the FIFO to flush
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// we annotate the start time of the frame so we can calculate
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// when it will finish.
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_startTime = micros();
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// Then keep filling the FIFO until done
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const uint8_t* ptr = _pixels;
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const uint8_t* end = ptr + _sizePixels;
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while (ptr != end)
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{
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ptr = FillUartFifo(ptr, end);
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}
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}
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const uint8_t* ICACHE_RAM_ATTR NeoEsp8266Uart::FillUartFifo(const uint8_t* pixels, const uint8_t* end)
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{
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// Remember: UARTs send less significant bit (LSB) first so
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// pushing ABCDEF byte will generate a 0FEDCBA1 signal,
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// including a LOW(0) start & a HIGH(1) stop bits.
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// Also, we have configured UART to invert logic levels, so:
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const uint8_t _uartData[4] = {
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0b110111, // On wire: 1 000 100 0 [Neopixel reads 00]
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0b000111, // On wire: 1 000 111 0 [Neopixel reads 01]
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0b110100, // On wire: 1 110 100 0 [Neopixel reads 10]
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0b000100, // On wire: 1 110 111 0 [NeoPixel reads 11]
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};
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uint8_t avail = (UART_TX_FIFO_SIZE - getUartTxFifoLength()) / 4;
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if (end - pixels > avail)
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{
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end = pixels + avail;
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}
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while (pixels < end)
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{
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uint8_t subpix = *pixels++;
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enqueue(_uartData[(subpix >> 6) & 0x3]);
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enqueue(_uartData[(subpix >> 4) & 0x3]);
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enqueue(_uartData[(subpix >> 2) & 0x3]);
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enqueue(_uartData[ subpix & 0x3]);
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}
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return pixels;
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}
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NeoEsp8266AsyncUart::NeoEsp8266AsyncUart(uint16_t pixelCount, size_t elementSize)
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: NeoEsp8266Uart(pixelCount, elementSize)
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{
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_asyncPixels = (uint8_t*)malloc(_sizePixels);
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}
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NeoEsp8266AsyncUart::~NeoEsp8266AsyncUart()
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{
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// Remember: the UART interrupt can be sending data from _asyncPixels in the background
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while (esp8266_uart1_async_buf != esp8266_uart1_async_buf_end)
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{
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yield();
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}
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free(_asyncPixels);
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}
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void ICACHE_RAM_ATTR NeoEsp8266AsyncUart::InitializeUart(uint32_t uartBaud)
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{
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NeoEsp8266Uart::InitializeUart(uartBaud);
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// Disable all interrupts
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ETS_UART_INTR_DISABLE();
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// Clear the RX & TX FIFOS
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SET_PERI_REG_MASK(UART_CONF0(UART1), UART_RXFIFO_RST | UART_TXFIFO_RST);
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CLEAR_PERI_REG_MASK(UART_CONF0(UART1), UART_RXFIFO_RST | UART_TXFIFO_RST);
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const uint32_t fifoResetFlags = (1 << UCTXRST) | (1 << UCRXRST);
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USC0(uartNum) |= fifoResetFlags;
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USC0(uartNum) &= ~(fifoResetFlags);
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// Set the interrupt handler
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ETS_UART_INTR_ATTACH(IntrHandler, NULL);
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// attach the ISR if needed
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if (s_uartInteruptContext[0] == nullptr &&
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s_uartInteruptContext[1] == nullptr)
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{
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ETS_UART_INTR_ATTACH(Isr, s_uartInteruptContext);
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}
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// attach the context
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s_uartInteruptContext[uartNum] = this;
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// Set tx fifo trigger. 80 bytes gives us 200 microsecs to refill the FIFO
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WRITE_PERI_REG(UART_CONF1(UART1), 80 << UART_TXFIFO_EMPTY_THRHD_S);
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USC1(uartNum) = (80 << UCFET);
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// Disable RX & TX interrupts. It is enabled by uart.c in the SDK
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CLEAR_PERI_REG_MASK(UART_INT_ENA(UART1), UART_RXFIFO_FULL_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA);
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// Disable RX & TX interrupts. It maybe still enabled by uart.c in the SDK
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USIE(uartNum) &= ~((1 << UIFF) | (1 << UIFE));
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// Clear all pending interrupts in UART1
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WRITE_PERI_REG(UART_INT_CLR(UART1), 0xffff);
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USIC(uartNum) = 0xffff;
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// Reenable interrupts
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ETS_UART_INTR_ENABLE();
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}
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void NeoEsp8266AsyncUart::UpdateUart()
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void NeoEsp8266UartInterruptContext::Detach(uint8_t uartNum)
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{
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// Instruct ESP8266 hardware uart1 to send the pixels asynchronously
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esp8266_uart1_async_buf = _pixels;
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esp8266_uart1_async_buf_end = _pixels + _sizePixels;
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SET_PERI_REG_MASK(UART_INT_ENA(1), UART_TXFIFO_EMPTY_INT_ENA);
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// Disable interrupts
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ETS_UART_INTR_DISABLE();
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// Annotate when we started to send bytes, so we can calculate when we are ready to send again
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_startTime = micros();
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// Copy the pixels to the idle buffer and swap them
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memcpy(_asyncPixels, _pixels, _sizePixels);
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std::swap(_asyncPixels, _pixels);
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}
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void ICACHE_RAM_ATTR NeoEsp8266AsyncUart::IntrHandler(void* param)
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{
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// Interrupt handler is shared between UART0 & UART1
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if (READ_PERI_REG(UART_INT_ST(UART1))) //any UART1 stuff
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if (s_uartInteruptContext[uartNum] != nullptr)
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{
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// Fill the FIFO with new data
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esp8266_uart1_async_buf = FillUartFifo(esp8266_uart1_async_buf, esp8266_uart1_async_buf_end);
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// Disable TX interrupt when done
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if (esp8266_uart1_async_buf == esp8266_uart1_async_buf_end)
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// turn off uart
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USC1(uartNum) = 0;
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USIC(uartNum) = 0xffff;
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USIE(uartNum) = 0;
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s_uartInteruptContext[uartNum] = nullptr;
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if (s_uartInteruptContext[0] == nullptr &&
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s_uartInteruptContext[1] == nullptr)
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{
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CLEAR_PERI_REG_MASK(UART_INT_ENA(UART1), UART_TXFIFO_EMPTY_INT_ENA);
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// detach our ISR
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ETS_UART_INTR_ATTACH(NULL, NULL);
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// return so we don't enable interrupts since there is no ISR anymore
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return;
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}
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// Clear all interrupts flags (just in case)
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WRITE_PERI_REG(UART_INT_CLR(UART1), 0xffff);
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}
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if (READ_PERI_REG(UART_INT_ST(UART0)))
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// Reenable interrupts
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ETS_UART_INTR_ENABLE();
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}
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void ICACHE_RAM_ATTR NeoEsp8266UartInterruptContext::Isr(void* param)
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{
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// make sure this is for us
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if (param == s_uartInteruptContext)
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{
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// TODO: gdbstub uses the interrupt of UART0, but there is no way to call its
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// interrupt handler gdbstub_uart_hdlr since it's static.
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WRITE_PERI_REG(UART_INT_CLR(UART0), 0xffff);
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// Interrupt handler is shared between UART0 & UART1
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// so we need to test for both
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for (uint8_t uartNum = 0; uartNum < 2; uartNum++)
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{
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if (USIS(uartNum) && s_uartInteruptContext[uartNum] != nullptr)
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{
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// Fill the FIFO with new data
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s_uartInteruptContext[uartNum]->_asyncBuff = FillUartFifo(
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uartNum,
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s_uartInteruptContext[uartNum]->_asyncBuff,
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s_uartInteruptContext[uartNum]->_asyncBuffEnd);
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// Disable TX interrupt when done
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if (s_uartInteruptContext[uartNum]->_asyncBuff == s_uartInteruptContext[uartNum]->_asyncBuffEnd)
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{
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// clear the TX FIFO Empty
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USIE(uartNum) &= ~(1 << UIFE);
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}
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// Clear all interrupts flags (just in case)
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USIC(uartNum) = 0xffff;
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}
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}
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}
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}
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