 Michael Miller
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8a13d6f0f4
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Three four cadences (#827)
i2s x1, x8, x16 now use a 3 step cadence (33% & 66% pulse width) by default saving 25% memory in DMA buffer.
ESP32 & ESP32S2
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2024-08-25 19:59:32 -07:00 |
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4b96e0d666
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Esp32 s3 LCD Parallel (#824)
Co-authored-by: Colin Iuliano <colin@coliniuliano.ca>
Co-authored-by: Colin <cholin@gmail.com>
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2024-08-18 11:44:48 -07:00 |
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Michael Miller
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e40289f89c
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CONFIG_IDF_TARGET not a compile flag anymore (#799)
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2024-04-24 11:06:33 -07:00 |
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Michael Miller
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2e88d03c4e
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Hd108 (#798)
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2024-04-23 08:44:56 -07:00 |
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Michael Miller
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22746479f6
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Compiles with IDF5 (#789)
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2024-03-22 11:38:45 -07:00 |
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Michael Miller
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3417f1e5bf
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Tlc59711 (#783)
* 2Mhz max due to timing requirements with a clock based signal?!
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2024-03-16 11:21:56 -07:00 |
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Michael Miller
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7c6744da4f
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Rp2040 (#779)
Support x4 on each PIO
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2024-03-11 09:36:13 -07:00 |
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 nick-diel
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99f8bcf6f7
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Support for Adafruit Pixie (#749)
* Support for Adafruit Pixie
* Updated based on PR review to align with library style and added Pixie constructor to NeoPixelBugLg
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2023-12-13 16:33:42 -08:00 |
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Michael Miller
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66a6ae41d4
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Mbi6033 (#719)
* two wire protocol
* due to unique reset using clock pin, supports bit bang only methods.
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2023-06-19 10:01:55 -07:00 |
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Michael Miller
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c74febefef
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Method File Cleanup (#683)
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2023-04-09 10:02:49 -07:00 |
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