2 Commits

Include renames

Author	SHA1	Message	Date
Michael Miller	8a13d6f0f4	Three four cadences (#827) ... i2s x1, x8, x16 now use a 3 step cadence (33% & 66% pulse width) by default saving 25% memory in DMA buffer. ESP32 & ESP32S2	2024-08-25 19:59:32 -07:00
3 people	4b96e0d666	Esp32 s3 LCD Parallel (#824) ... Co-authored-by: Colin Iuliano <colin@coliniuliano.ca> Co-authored-by: Colin <cholin@gmail.com>	2024-08-18 11:44:48 -07:00