diff --git a/Processors/TFT_eSPI_STM32.h b/Processors/TFT_eSPI_STM32.h index 71557dc..b618fd6 100644 --- a/Processors/TFT_eSPI_STM32.h +++ b/Processors/TFT_eSPI_STM32.h @@ -414,21 +414,22 @@ #if defined (SSD1963_DRIVER) // Write 18 bit color to TFT (untested) - #define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \ - GPIOA->BSRR = D0_BSR_MASK(r) | D2_BSR_MASK(r) | D7_BSR_MASK(r); \ + uint8_t r6, g6, b6; + #define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \ + GPIOA->BSRR = D0_BSR_MASK(r6) | D2_BSR_MASK(r6) | D7_BSR_MASK(r6); \ WR_L; \ - GPIOC->BSRR = D1_BSR_MASK(r); \ - GPIOB->BSRR = D3_BSR_MASK(r) | D4_BSR_MASK(r) | D5_BSR_MASK(r) | D6_BSR_MASK(r); \ + GPIOC->BSRR = D1_BSR_MASK(r6); \ + GPIOB->BSRR = D3_BSR_MASK(r6) | D4_BSR_MASK(r6) | D5_BSR_MASK(r6) | D6_BSR_MASK(r6); \ WR_STB; \ - GPIOA->BSRR = D0_BSR_MASK(g) | D2_BSR_MASK(g) | D7_BSR_MASK(g); \ + GPIOA->BSRR = D0_BSR_MASK(g6) | D2_BSR_MASK(g6) | D7_BSR_MASK(g6); \ WR_L; \ - GPIOC->BSRR = D1_BSR_MASK(g); \ - GPIOB->BSRR = D3_BSR_MASK(g) | D4_BSR_MASK(g) | D5_BSR_MASK(g) | D6_BSR_MASK(g); \ + GPIOC->BSRR = D1_BSR_MASK(g6); \ + GPIOB->BSRR = D3_BSR_MASK(g6) | D4_BSR_MASK(g6) | D5_BSR_MASK(g6) | D6_BSR_MASK(g6); \ WR_STB; \ - GPIOA->BSRR = D0_BSR_MASK(b) | D2_BSR_MASK(b) | D7_BSR_MASK(b); \ + GPIOA->BSRR = D0_BSR_MASK(b6) | D2_BSR_MASK(b6) | D7_BSR_MASK(b6); \ WR_L; \ - GPIOC->BSRR = D1_BSR_MASK(b); \ - GPIOB->BSRR = D3_BSR_MASK(b) | D4_BSR_MASK(b) | D5_BSR_MASK(b) | D6_BSR_MASK(b); \ + GPIOC->BSRR = D1_BSR_MASK(b6); \ + GPIOB->BSRR = D3_BSR_MASK(b6) | D4_BSR_MASK(b6) | D5_BSR_MASK(b6) | D6_BSR_MASK(b6); \ WR_STB // Need to slow down strobe // 18 bit color write with swapped bytes @@ -556,21 +557,22 @@ #if defined (SSD1963_DRIVER) // Write 18 bit color to TFT (untested) - #define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \ - GPIOF->BSRR = D0_BSR_MASK(r) | D2_BSR_MASK(r) | D4_BSR_MASK(r) | D7_BSR_MASK(r); \ + uint8_t r6, g6, b6; + #define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \ + GPIOF->BSRR = D0_BSR_MASK(r6) | D2_BSR_MASK(r6) | D4_BSR_MASK(r6) | D7_BSR_MASK(r6); \ WR_L; \ - GPIOD->BSRR = D1_BSR_MASK(r); \ - GPIOE->BSRR = D3_BSR_MASK(r) | D5_BSR_MASK(r) | D6_BSR_MASK(r); \ + GPIOD->BSRR = D1_BSR_MASK(r6); \ + GPIOE->BSRR = D3_BSR_MASK(r6) | D5_BSR_MASK(r6) | D6_BSR_MASK(r6); \ WR_STB; \ - GPIOF->BSRR = D0_BSR_MASK(g) | D2_BSR_MASK(g) | D4_BSR_MASK(g) | D7_BSR_MASK(g); \ + GPIOF->BSRR = D0_BSR_MASK(g6) | D2_BSR_MASK(g6) | D4_BSR_MASK(g6) | D7_BSR_MASK(g6); \ WR_L; \ - GPIOD->BSRR = D1_BSR_MASK(g); \ - GPIOE->BSRR = D3_BSR_MASK(g) | D5_BSR_MASK(g) | D6_BSR_MASK(g); \ + GPIOD->BSRR = D1_BSR_MASK(g6); \ + GPIOE->BSRR = D3_BSR_MASK(g6) | D5_BSR_MASK(g6) | D6_BSR_MASK(g6); \ WR_STB; \ - GPIOF->BSRR = D0_BSR_MASK(b) | D2_BSR_MASK(b) | D4_BSR_MASK(b) | D7_BSR_MASK(b); \ + GPIOF->BSRR = D0_BSR_MASK(b6) | D2_BSR_MASK(b6) | D4_BSR_MASK(b6) | D7_BSR_MASK(b6); \ WR_L; \ - GPIOD->BSRR = D1_BSR_MASK(b); \ - GPIOE->BSRR = D3_BSR_MASK(b) | D5_BSR_MASK(b) | D6_BSR_MASK(b); \ + GPIOD->BSRR = D1_BSR_MASK(b6); \ + GPIOE->BSRR = D3_BSR_MASK(b6) | D5_BSR_MASK(b6) | D6_BSR_MASK(b6); \ WR_STB // Need to slow down strobe // 18 bit color write with swapped bytes @@ -729,10 +731,11 @@ #if defined (SSD1963_DRIVER) // Write 18 bit color to TFT (untested) - #define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \ - GPIOA->BSRR = (0x00FF0000 | (uint8_t)(r)); WR_L; WR_STB; \ - GPIOA->BSRR = (0x00FF0000 | (uint8_t)(g)); WR_L; WR_STB; \ - GPIOA->BSRR = (0x00FF0000 | (uint8_t)(b)); WR_L; WR_STB + uint8_t r6, g6, b6; + #define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \ + GPIOA->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \ + GPIOA->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \ + GPIOA->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB // 18 bit color write with swapped bytes #define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap) @@ -772,10 +775,11 @@ #if defined (SSD1963_DRIVER) // Write 18 bit color to TFT (untested) + uint8_t r, g, b; #define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \ - GPIOB->BSRR = (0x00FF0000 | (uint8_t)(r)); WR_L; WR_STB; \ - GPIOB->BSRR = (0x00FF0000 | (uint8_t)(g)); WR_L; WR_STB; \ - GPIOB->BSRR = (0x00FF0000 | (uint8_t)(b)); WR_L; WR_STB + GPIOB->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \ + GPIOB->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \ + GPIOB->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB // 18 bit color write with swapped bytes #define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap) @@ -885,36 +889,37 @@ #if defined (SSD1963_DRIVER) // Write 18 bit color to TFT (untested) - #define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \ - D0_PIN_PORT->BSRR = D8_BSR_MASK(r); \ - D1_PIN_PORT->BSRR = D9_BSR_MASK(r); \ - D2_PIN_PORT->BSRR = D10_BSR_MASK(r); \ - D3_PIN_PORT->BSRR = D11_BSR_MASK(r); \ + uint8_t r6, g6, b6; + #define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \ + D0_PIN_PORT->BSRR = D8_BSR_MASK(r6); \ + D1_PIN_PORT->BSRR = D9_BSR_MASK(r6); \ + D2_PIN_PORT->BSRR = D10_BSR_MASK(r6); \ + D3_PIN_PORT->BSRR = D11_BSR_MASK(r6); \ WR_L; \ - D4_PIN_PORT->BSRR = D12_BSR_MASK(r); \ - D5_PIN_PORT->BSRR = D13_BSR_MASK(r); \ - D6_PIN_PORT->BSRR = D14_BSR_MASK(r); \ - D7_PIN_PORT->BSRR = D15_BSR_MASK(r); \ + D4_PIN_PORT->BSRR = D12_BSR_MASK(r6); \ + D5_PIN_PORT->BSRR = D13_BSR_MASK(r6); \ + D6_PIN_PORT->BSRR = D14_BSR_MASK(r6); \ + D7_PIN_PORT->BSRR = D15_BSR_MASK(r6); \ WR_STB;\ - D0_PIN_PORT->BSRR = D8_BSR_MASK(g); \ - D1_PIN_PORT->BSRR = D9_BSR_MASK(g); \ - D2_PIN_PORT->BSRR = D10_BSR_MASK(g); \ - D3_PIN_PORT->BSRR = D11_BSR_MASK(g); \ + D0_PIN_PORT->BSRR = D8_BSR_MASK(g6); \ + D1_PIN_PORT->BSRR = D9_BSR_MASK(g6); \ + D2_PIN_PORT->BSRR = D10_BSR_MASK(g6); \ + D3_PIN_PORT->BSRR = D11_BSR_MASK(g6); \ WR_L; \ - D4_PIN_PORT->BSRR = D12_BSR_MASK(g); \ - D5_PIN_PORT->BSRR = D13_BSR_MASK(g); \ - D6_PIN_PORT->BSRR = D14_BSR_MASK(g); \ - D7_PIN_PORT->BSRR = D15_BSR_MASK(g); \ + D4_PIN_PORT->BSRR = D12_BSR_MASK(g6); \ + D5_PIN_PORT->BSRR = D13_BSR_MASK(g6); \ + D6_PIN_PORT->BSRR = D14_BSR_MASK(g6); \ + D7_PIN_PORT->BSRR = D15_BSR_MASK(g6); \ WR_STB;\ - D0_PIN_PORT->BSRR = D0_BSR_MASK(b); \ - D1_PIN_PORT->BSRR = D1_BSR_MASK(b); \ - D2_PIN_PORT->BSRR = D2_BSR_MASK(b); \ - D3_PIN_PORT->BSRR = D3_BSR_MASK(b); \ + D0_PIN_PORT->BSRR = D0_BSR_MASK(b6); \ + D1_PIN_PORT->BSRR = D1_BSR_MASK(b6); \ + D2_PIN_PORT->BSRR = D2_BSR_MASK(b6); \ + D3_PIN_PORT->BSRR = D3_BSR_MASK(b6); \ WR_L; \ - D4_PIN_PORT->BSRR = D4_BSR_MASK(b); \ - D5_PIN_PORT->BSRR = D5_BSR_MASK(b); \ - D6_PIN_PORT->BSRR = D6_BSR_MASK(b); \ - D7_PIN_PORT->BSRR = D7_BSR_MASK(b); \ + D4_PIN_PORT->BSRR = D4_BSR_MASK(b6); \ + D5_PIN_PORT->BSRR = D5_BSR_MASK(b6); \ + D6_PIN_PORT->BSRR = D6_BSR_MASK(b6); \ + D7_PIN_PORT->BSRR = D7_BSR_MASK(b6); \ WR_STB // 18 bit color write with swapped bytes