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Allow RP2040 SPI 0 or SPI 1 ports to be used

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Auto set of CGRAM offset for 135 x 240 ST7789 display
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Bodmer committed 2021-12-05 22:34:37 +00:00
1 parent 12f9ce8691
commit 5959550dd7
11 files changed
+160 -119
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Processors/TFT_eSPI_RP2040.c
+21 -21
View File
@@ -14,7 +14,7 @@
#else
// Community RP2040 board package by Earle Philhower
//SPIClass& spi = SPI; // will use board package default pins
SPIClassRP2040 spi = SPIClassRP2040(spi0, TFT_MISO, -1, TFT_SCLK, TFT_MOSI);
SPIClassRP2040 spi = SPIClassRP2040(SPI_X, TFT_MISO, -1, TFT_SCLK, TFT_MOSI);
#endif
#endif
@@ -201,17 +201,17 @@ void TFT_eSPI::pushBlock(uint16_t color, uint32_t len)
uint32_t br = b<<8 | r;
uint32_t gb = g<<8 | b;
// Must wait before changing to 16 bit
while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(spi0, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(SPI_X, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
while ( len > 1 ) {
while (!spi_is_writable(spi0)){}; spi_get_hw(spi0)->dr = rg;
while (!spi_is_writable(spi0)){}; spi_get_hw(spi0)->dr = br;
while (!spi_is_writable(spi0)){}; spi_get_hw(spi0)->dr = gb;
while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = rg;
while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = br;
while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = gb;
len -= 2;
}
// Must wait before changing back to 8 bit
while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(spi0, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(SPI_X, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
}
// Mop up the remaining pixels
@@ -250,8 +250,8 @@ void TFT_eSPI::pushPixels(const void* data_in, uint32_t len){
void TFT_eSPI::pushBlock(uint16_t color, uint32_t len){
while(len--)
{
while (!spi_is_writable(spi0)){};
spi_get_hw(spi0)->dr = (uint32_t)color;
while (!spi_is_writable(SPI_X)){};
spi_get_hw(SPI_X)->dr = (uint32_t)color;
}
}
@@ -264,8 +264,8 @@ void TFT_eSPI::pushPixels(const void* data_in, uint32_t len){
if (_swapBytes) {
while(len--)
{
while (!spi_is_writable(spi0)){};
spi_get_hw(spi0)->dr = (uint32_t)(*data++);
while (!spi_is_writable(SPI_X)){};
spi_get_hw(SPI_X)->dr = (uint32_t)(*data++);
}
}
else
@@ -274,8 +274,8 @@ void TFT_eSPI::pushPixels(const void* data_in, uint32_t len){
{
uint16_t color = *data++;
color = color >> 8 | color << 8;
while (!spi_is_writable(spi0)){};
spi_get_hw(spi0)->dr = (uint32_t)color;
while (!spi_is_writable(SPI_X)){};
spi_get_hw(SPI_X)->dr = (uint32_t)color;
}
}
}
@@ -303,8 +303,8 @@ bool TFT_eSPI::dmaBusy(void) {
if (!DMA_Enabled) return false;
if (dma_channel_is_busy(dma_tx_channel)) return true;
while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(spi0, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(SPI_X, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
return false;
}
@@ -315,8 +315,8 @@ bool TFT_eSPI::dmaBusy(void) {
void TFT_eSPI::dmaWait(void)
{
while (dma_channel_is_busy(dma_tx_channel));
while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(spi0, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {};
spi_set_format(SPI_X, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST);
}
/***************************************************************************************
@@ -330,7 +330,7 @@ void TFT_eSPI::pushPixelsDMA(uint16_t* image, uint32_t len)
dmaWait();
channel_config_set_bswap(&dma_tx_config, !_swapBytes);
dma_channel_configure(dma_tx_channel, &dma_tx_config, &spi_get_hw(spi0)->dr, (uint16_t*)image, len, true);
dma_channel_configure(dma_tx_channel, &dma_tx_config, &spi_get_hw(SPI_X)->dr, (uint16_t*)image, len, true);
}
/***************************************************************************************
@@ -378,7 +378,7 @@ void TFT_eSPI::pushImageDMA(int32_t x, int32_t y, int32_t w, int32_t h, uint16_t
setAddrWindow(x, y, dw, dh);
channel_config_set_bswap(&dma_tx_config, !_swapBytes);
dma_channel_configure(dma_tx_channel, &dma_tx_config, &spi_get_hw(spi0)->dr, (uint16_t*)buffer, len, true);
dma_channel_configure(dma_tx_channel, &dma_tx_config, &spi_get_hw(SPI_X)->dr, (uint16_t*)buffer, len, true);
}
@@ -396,7 +396,7 @@ bool TFT_eSPI::initDMA(bool ctrl_cs)
dma_tx_config = dma_channel_get_default_config(dma_tx_channel);
channel_config_set_transfer_data_size(&dma_tx_config, DMA_SIZE_16);
channel_config_set_dreq(&dma_tx_config, spi_get_index(spi0) ? DREQ_SPI1_TX : DREQ_SPI0_TX);
channel_config_set_dreq(&dma_tx_config, spi_get_index(SPI_X) ? DREQ_SPI1_TX : DREQ_SPI0_TX);
DMA_Enabled = true;
return true;
Processors/TFT_eSPI_RP2040.h
+31 -20
View File
@@ -17,9 +17,20 @@
// Include processor specific header
// None
// Use SPI0 as default if not defined
#ifndef TFT_SPI_PORT
#define TFT_SPI_PORT 0
#endif
#if (TFT_SPI_PORT == 0)
#define SPI_X spi0
#else
#define SPI_X spi1
#endif
// Processor specific code used by SPI bus transaction begin/end_tft_write functions
#define SET_BUS_WRITE_MODE spi_set_format(spi0, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST)
#define SET_BUS_READ_MODE // spi_set_format(spi0, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST)
#define SET_BUS_WRITE_MODE spi_set_format(SPI_X, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST)
#define SET_BUS_READ_MODE // spi_set_format(SPI_X, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST)
// Code to check if SPI or DMA is busy, used by SPI bus transaction startWrite and/or endWrite functions
#if !defined(TFT_PARALLEL_8_BIT) && !defined(SPI_18BIT_DRIVER)
@@ -31,9 +42,9 @@
#endif
// Wait for tx to end, flush rx FIFO, clear rx overrun
#define SPI_BUSY_CHECK while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {}; \
while (spi_is_readable(spi0)) (void)spi_get_hw(spi0)->dr; \
spi_get_hw(spi0)->icr = SPI_SSPICR_RORIC_BITS
#define SPI_BUSY_CHECK while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \
while (spi_is_readable(SPI_X)) (void)spi_get_hw(SPI_X)->dr; \
spi_get_hw(SPI_X)->icr = SPI_SSPICR_RORIC_BITS
// To be safe, SUPPORT_TRANSACTIONS is assumed mandatory
#if !defined (SUPPORT_TRANSACTIONS)
@@ -123,12 +134,12 @@
#if defined (SPI_18BIT_DRIVER) // SPI 18 bit colour
// Write 8 bits to TFT
#define tft_Write_8(C) spi_get_hw(spi0)->dr = (uint32_t)(C); \
while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {}; \
#define tft_Write_8(C) spi_get_hw(SPI_X)->dr = (uint32_t)(C); \
while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \
//#define tft_Write_8(C) spi.transfer(C);
#define tft_Write_8N(B) while (!spi_is_writable(spi0)){}; \
spi_get_hw(spi0)->dr = (uint8_t)(B)
#define tft_Write_8N(B) while (!spi_is_writable(SPI_X)){}; \
spi_get_hw(SPI_X)->dr = (uint8_t)(B)
// Convert 16 bit colour to 18 bit and write in 3 bytes
#define tft_Write_16(C) tft_Write_8N(((C) & 0xF800)>>8); \
@@ -191,25 +202,25 @@
#else
// This swaps to 8 bit mode, then back to 16 bit mode
#define tft_Write_8(C) while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {}; \
spi_set_format(spi0, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST); \
spi_get_hw(spi0)->dr = (uint32_t)(C); \
while (spi_get_hw(spi0)->sr & SPI_SSPSR_BSY_BITS) {}; \
spi_set_format(spi0, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST)
#define tft_Write_8(C) while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \
spi_set_format(SPI_X, 8, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST); \
spi_get_hw(SPI_X)->dr = (uint32_t)(C); \
while (spi_get_hw(SPI_X)->sr & SPI_SSPSR_BSY_BITS) {}; \
spi_set_format(SPI_X, 16, (spi_cpol_t)0, (spi_cpha_t)0, SPI_MSB_FIRST)
// Note: the following macros do not wait for the end of transmission
#define tft_Write_16(C) while (!spi_is_writable(spi0)){}; spi_get_hw(spi0)->dr = (uint32_t)(C)
#define tft_Write_16(C) while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = (uint32_t)(C)
#define tft_Write_16N(C) while (!spi_is_writable(spi0)){}; spi_get_hw(spi0)->dr = (uint32_t)(C)
#define tft_Write_16N(C) while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = (uint32_t)(C)
#define tft_Write_16S(C) while (!spi_is_writable(spi0)){}; spi_get_hw(spi0)->dr = (uint32_t)(C)<<8 | (C)>>8
#define tft_Write_16S(C) while (!spi_is_writable(SPI_X)){}; spi_get_hw(SPI_X)->dr = (uint32_t)(C)<<8 | (C)>>8
#define tft_Write_32(C) spi_get_hw(spi0)->dr = (uint32_t)((C)>>16); spi_get_hw(spi0)->dr = (uint32_t)(C)
#define tft_Write_32(C) spi_get_hw(SPI_X)->dr = (uint32_t)((C)>>16); spi_get_hw(SPI_X)->dr = (uint32_t)(C)
#define tft_Write_32C(C,D) spi_get_hw(spi0)->dr = (uint32_t)(C); spi_get_hw(spi0)->dr = (uint32_t)(D)
#define tft_Write_32C(C,D) spi_get_hw(SPI_X)->dr = (uint32_t)(C); spi_get_hw(SPI_X)->dr = (uint32_t)(D)
#define tft_Write_32D(C) spi_get_hw(spi0)->dr = (uint32_t)(C); spi_get_hw(spi0)->dr = (uint32_t)(C)
#define tft_Write_32D(C) spi_get_hw(SPI_X)->dr = (uint32_t)(C); spi_get_hw(SPI_X)->dr = (uint32_t)(C)
#endif // RPI_DISPLAY_TYPE
#endif