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Add 16 bit parallel for RP2040 processor

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Correct legacy comments
Add ESP32 S3 parallel setup 70d
Add setups 105-107 for RP2040 with 16 bit display
Add file conversion notes to PNG array example
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Bodmer committed 2022-05-16 19:58:05 +01:00
1 parent 84238dde70
commit 7bf48bb179
24 files changed
+11937 -7175
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Processors/TFT_eSPI_RP2040.c
+16 -7
View File
@@ -28,9 +28,12 @@
// SPI PIO code for 16 bit colour transmit
#include "pio_SPI.pio.h"
#endif
#else
#elif defined (TFT_PARALLEL_8_BIT)
// SPI PIO code for 8 bit parallel interface (16 bit colour)
#include "pio_8bit_parallel.pio.h"
#else // must be TFT_PARALLEL_16_BIT
// SPI PIO code for 16 bit parallel interface (16 bit colour)
#include "pio_16bit_parallel.pio.h"
#endif
// Board package specific differences
@@ -189,7 +192,7 @@ void pioinit(uint32_t clock_freq) {
pio_instr_set_dc = pio_encode_set((pio_src_dest)0, 1);
pio_instr_clr_dc = pio_encode_set((pio_src_dest)0, 0);
}
#else
#else // 8 or 16 bit parallel
void pioinit(uint16_t clock_div, uint16_t fract_div) {
// Find a free SM on one of the PIO's
@@ -212,21 +215,27 @@ void pioinit(uint16_t clock_div, uint16_t fract_div) {
}
}
*/
#if defined (TFT_PARALLEL_8_BIT)
uint8_t bits = 8;
#else // must be TFT_PARALLEL_16_BIT
uint8_t bits = 16;
#endif
// Load the PIO program
program_offset = pio_add_program(tft_pio, &tft_io_program);
// Associate pins with the PIO
pio_gpio_init(tft_pio, TFT_DC);
pio_gpio_init(tft_pio, TFT_WR);
for (int i = 0; i < 8; i++) {
for (int i = 0; i < bits; i++) {
pio_gpio_init(tft_pio, TFT_D0 + i);
}
// Configure the pins to be outputs
pio_sm_set_consecutive_pindirs(tft_pio, pio_sm, TFT_DC, 1, true);
pio_sm_set_consecutive_pindirs(tft_pio, pio_sm, TFT_WR, 1, true);
pio_sm_set_consecutive_pindirs(tft_pio, pio_sm, TFT_D0, 8, true);
pio_sm_set_consecutive_pindirs(tft_pio, pio_sm, TFT_D0, bits, true);
// Configure the state machine
pio_sm_config c = tft_io_program_get_default_config(program_offset);
@@ -234,8 +243,8 @@ void pioinit(uint16_t clock_div, uint16_t fract_div) {
sm_config_set_set_pins(&c, TFT_DC, 1);
// Define the single side-set pin
sm_config_set_sideset_pins(&c, TFT_WR);
// Define the 8 consecutive pins that are used for data output
sm_config_set_out_pins(&c, TFT_D0, 8);
// Define the consecutive pins that are used for data output
sm_config_set_out_pins(&c, TFT_D0, bits);
// Set clock divider and fractional divider
sm_config_set_clkdiv_int_frac(&c, clock_div, fract_div);
// Make a single 8 words FIFO from the 4 words TX and RX FIFOs
Processors/TFT_eSPI_RP2040.h
+35 -15
View File
@@ -30,7 +30,7 @@
// Include processor specific header
// None
#if defined (TFT_PARALLEL_8_BIT) || defined (RP2040_PIO_SPI)
#if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT) || defined (RP2040_PIO_SPI)
#define RP2040_PIO_INTERFACE
#define RP2040_PIO_PUSHBLOCK
#endif
@@ -80,18 +80,33 @@
#endif
#else
// ILI9481 needs a slower cycle time
// Byte rate = (CPU clock/(4 * divider))
#ifdef ILI9481_DRIVER
#define DIV_UNITS 1
#define DIV_FRACT 160
#else
#define DIV_UNITS 1
#define DIV_FRACT 0
// Different controllers have different minimum write cycle periods, so the PIO clock is changed accordingly
// The PIO clock is a division of the CPU clock so scales when the processor is overclocked
// PIO write frequency = (CPU clock/(4 * DIV_UNITS))
#if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT) || defined (RP2040_PIO_SPI)
#if defined (TFT_PARALLEL_16_BIT)
// Different display drivers have different minimum write cycle times
#if defined (HX8357C_DRIVER) || defined (SSD1963_DRIVER)
#define DIV_UNITS 1 // 32ns write cycle time SSD1963, HX8357C (maybe HX8357D?)
#elif defined (ILI9486_DRIVER) || defined (HX8357B_DRIVER) || defined (HX8357D_DRIVER)
#define DIV_UNITS 2 // 64ns write cycle time ILI9486, HX8357D, HX8357B
#else // ILI9481 needs a slower cycle time
#define DIV_UNITS 3 // 96ns write cycle time
#endif
#define DIV_FRACT 0
#else // 8 bit parallel mode
#ifdef ILI9481_DRIVER
#define DIV_UNITS 1
#define DIV_FRACT 160 // Note: Fractional values done with clock period dithering
#else
#define DIV_UNITS 1
#define DIV_FRACT 0
#endif
#endif
#endif
// Initialise TFT data bus
#if defined (TFT_PARALLEL_8_BIT)
#if defined (TFT_PARALLEL_8_BIT) || defined (TFT_PARALLEL_16_BIT)
#define INIT_TFT_DATA_BUS pioinit(DIV_UNITS, DIV_FRACT);
#elif defined (RP2040_PIO_SPI)
#define INIT_TFT_DATA_BUS pioinit(SPI_FREQUENCY);
@@ -184,7 +199,7 @@
////////////////////////////////////////////////////////////////////////////////////////
// Define the WR (TFT Write) pin drive code
////////////////////////////////////////////////////////////////////////////////////////
#if !defined (TFT_PARALLEL_8_BIT) // SPI
#if !defined (TFT_PARALLEL_8_BIT) && !defined (TFT_PARALLEL_16_BIT) // SPI
#ifdef TFT_WR
#define WR_L digitalWrite(TFT_WR, LOW)
#define WR_H digitalWrite(TFT_WR, HIGH)
@@ -384,13 +399,18 @@
#define tft_Write_32D(C) WAIT_FOR_FIFO_FREE(2); TX_FIFO = (((C)<<8) | ((C)>>8)); tft_Write_8L(C)
#else
// This writes 8 bits, then switches back to 16 bit mode automatically
// Have already waited for pio stalled (last data write complete) when DC switched to command mode
// The wait for stall allows DC to be changed immediately afterwards
#else // PIO interface, SPI or parallel
// This writes 8 bits, then switches back to 16 bit mode automatically
// Have already waited for pio stalled (last data write complete) when DC switched to command mode
// The wait for stall allows DC to be changed immediately afterwards
#if defined (TFT_PARALLEL_8_BIT) || defined (RP2040_PIO_SPI)
#define tft_Write_8(C) tft_pio->sm[pio_sm].instr = pio_instr_jmp8; \
TX_FIFO = (C); \
WAIT_FOR_STALL
#else // For 16 bit parallel 16 bits are always sent
#define tft_Write_8(C) TX_FIFO = (C); \
WAIT_FOR_STALL
#endif
// Note: the following macros do not wait for the end of transmission
Processors/pio_16bit_parallel.pio
+76
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@@ -0,0 +1,76 @@
// Raspberry Pi Pico PIO program to output data to a TFT
// controller via a 16 bit 8080 style data path.
// Original sourced from:
// https://github.com/zapta/pio_tft
// Side set: 1 output pin, TFT_WR. Active low.
// Data set: 16 consecutive output pins, TFT_D0 .. TFT_D15
.program tft_io
.side_set 1 opt ; The TFT_WR output.
// The C++ code switches between the different SM routines
// by waiting for the SM to be idle and setting its PC.
// The default SM routine is a 16 bit transfer
// Do a block fill of N+1 pixels.
public block_fill:
// Fetch colour value.
pull side 1
// Move colour to x.
mov x, osr
// Fetch pixel count N (sends N+1 pixels).
pull
// Move pixel count to y.
mov y, osr
next:
// Copy colour value into osr, colour in LS 16 bits.
mov osr, x side 1
// Output colour 16 bits, unwanted top 16 bits shifted through.
out pins, 32 side 0 [1]
// Decrement pixel count and loop.
jmp y--, next side 1
.wrap_target
// Transmit an 8 bit value (LS 8 bits of 32 bits).
public start_8:
// Transmit a 16 bit value (LS 16 bits of 32 bits).
public start_tx:
// Fetch the next 32 bit value from the TX FIFO and set TFT_WR high.
pull side 1
// Write the 16 bits and set WR low. This also
// shifts the unused top 16 bits through.
out pins, 32 side 0 [1]
// Set WR high and jump back to start.
jmp start_tx side 1
// Transmit a set window command sequence.
public set_addr_window:
// Loop count in x (to send caset, paset and ramwr commands).
set x, 2 side 1
pull_cmd:
// Set TFT_DC low.
set pins, 0
// Fetch caset, paset or ramwr.
pull
// Output LS byte (caset, paset or ramwr), discarding top 16 bits, set TFT_WR low.
out pins, 32 side 0
// Jump to end if 3rd cmd byte ramwr sent (x == 0)
jmp !x, end_set_addr
// pull next start and end coordinates, TFT_WR high.
pull side 1
// Set TFT_DC high.
set pins, 1
send_xy:
// Output byte, TFT_WR low.
out pins, 8 side 0 [1]
// Loop until 4 bytes sent, TFT_WR high.
jmp !osre, send_xy side 1 [1]
end_set_addr: // Jump here since delay needed before DC change
// Loop back for next command and write last command.
jmp x--, pull_cmd side 1
// Set DC high.
set pins, 1
// Auto-wrap back to start_tx.
.wrap
Processors/pio_16bit_parallel.pio.h
+62
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@@ -0,0 +1,62 @@
// -------------------------------------------------- //
// This file is autogenerated by pioasm; do not edit! //
// -------------------------------------------------- //
#pragma once
#if !PICO_NO_HARDWARE
#include "hardware/pio.h"
#endif
// ------ //
// tft_io //
// ------ //
#define tft_io_wrap_target 7
#define tft_io_wrap 20
#define tft_io_offset_block_fill 0u
#define tft_io_offset_start_8 7u
#define tft_io_offset_start_tx 7u
#define tft_io_offset_set_addr_window 10u
static const uint16_t tft_io_program_instructions[] = {
0x98a0, // 0: pull block side 1
0xa027, // 1: mov x, osr
0x80a0, // 2: pull block
0xa047, // 3: mov y, osr
0xb8e1, // 4: mov osr, x side 1
0x7100, // 5: out pins, 32 side 0 [1]
0x1884, // 6: jmp y--, 4 side 1
// .wrap_target
0x98a0, // 7: pull block side 1
0x7100, // 8: out pins, 32 side 0 [1]
0x1807, // 9: jmp 7 side 1
0xf822, // 10: set x, 2 side 1
0xe000, // 11: set pins, 0
0x80a0, // 12: pull block
0x7000, // 13: out pins, 32 side 0
0x0033, // 14: jmp !x, 19
0x98a0, // 15: pull block side 1
0xe001, // 16: set pins, 1
0x7108, // 17: out pins, 8 side 0 [1]
0x19f1, // 18: jmp !osre, 17 side 1 [1]
0x184b, // 19: jmp x--, 11 side 1
0xe001, // 20: set pins, 1
// .wrap
};
#if !PICO_NO_HARDWARE
static const struct pio_program tft_io_program = {
.instructions = tft_io_program_instructions,
.length = 21,
.origin = -1,
};
static inline pio_sm_config tft_io_program_get_default_config(uint offset) {
pio_sm_config c = pio_get_default_sm_config();
sm_config_set_wrap(&c, offset + tft_io_wrap_target, offset + tft_io_wrap);
sm_config_set_sideset(&c, 2, true, false);
return c;
}
#endif