Fix #2297

The SSD1963 requires 18 bit colour in 3 bytes when an 8 bit parallel interface is used.

Added new PIO parallel code

Processors/TFT_eSPI_RP2040.c

@@ -29,10 +29,15 @@
       #include "pio_SPI.pio.h"
     #endif
   #elif defined (TFT_PARALLEL_8_BIT)
-    // SPI PIO code for 8 bit parallel interface (16 bit colour)
-    #include "pio_8bit_parallel.pio.h"
+    #if defined (SSD1963_DRIVER)
+      // PIO code for 8 bit parallel interface (18 bit colour)
+      #include "pio_8bit_parallel_18bpp.pio.h"
+    #else
+      // PIO code for 8 bit parallel interface (16 bit colour)
+      #include "pio_8bit_parallel.pio.h"
+    #endif
   #else // must be TFT_PARALLEL_16_BIT
-    // SPI PIO code for 16 bit parallel interface (16 bit colour)
+    // PIO code for 16 bit parallel interface (16 bit colour)
     #include "pio_16bit_parallel.pio.h"
   #endif
 
@@ -279,7 +284,7 @@ void pioinit(uint16_t clock_div, uint16_t fract_div) {
 // PIO handles pixel block fill writes
 void TFT_eSPI::pushBlock(uint16_t color, uint32_t len)
 {
-#if  defined (SPI_18BIT_DRIVER)
+#if  defined (SPI_18BIT_DRIVER) || (defined (SSD1963_DRIVER) && defined (TFT_PARALLEL_8_BIT))
   uint32_t col = ((color & 0xF800)<<8) | ((color & 0x07E0)<<5) | ((color & 0x001F)<<3);
   if (len) {
     WAIT_FOR_STALL;
@@ -327,7 +332,7 @@ void TFT_eSPI::pushBlock(uint16_t color, uint32_t len){
 ** Description:             Write a sequence of pixels
 ***************************************************************************************/
 void TFT_eSPI::pushPixels(const void* data_in, uint32_t len){
-#if  defined (SPI_18BIT_DRIVER)
+#if  defined (SPI_18BIT_DRIVER) || (defined (SSD1963_DRIVER) && defined (TFT_PARALLEL_8_BIT))
   uint16_t *data = (uint16_t*)data_in;
   if (_swapBytes) {
     while ( len-- ) {

Processors/TFT_eSPI_RP2040.h

@@ -408,7 +408,7 @@
   // Temporary - to be deleted
   #define GPIO_DIR_MASK 0
 
-  #if  defined (SPI_18BIT_DRIVER) // SPI 18 bit colour
+  #if  defined (SPI_18BIT_DRIVER)  || defined (SSD1963_DRIVER) // 18 bit colour (3 bytes)
       // This writes 8 bits, then switches back to 16 bit mode automatically
       // Have already waited for pio stalled (last data write complete) when DC switched to command mode
       // The wait for stall allows DC to be changed immediately afterwards

Processors/pio_8bit_parallel_18bpp.pio.h

@@ -0,0 +1,73 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------ //
+// tft_io //
+// ------ //
+
+#define tft_io_wrap_target 11
+#define tft_io_wrap 31
+
+#define tft_io_offset_block_fill 0u
+#define tft_io_offset_start_tx 11u
+#define tft_io_offset_start_8 18u
+#define tft_io_offset_set_addr_window 21u
+
+static const uint16_t tft_io_program_instructions[] = {
+    0x98a0, //  0: pull   block           side 1     
+    0xa027, //  1: mov    x, osr                     
+    0x80a0, //  2: pull   block                      
+    0xa047, //  3: mov    y, osr                     
+    0xb8e1, //  4: mov    osr, x          side 1     
+    0x7110, //  5: out    pins, 16        side 0 [1] 
+    0xb942, //  6: nop                    side 1 [1] 
+    0x7108, //  7: out    pins, 8         side 0 [1] 
+    0xb942, //  8: nop                    side 1 [1] 
+    0x7108, //  9: out    pins, 8         side 0 [1] 
+    0x1884, // 10: jmp    y--, 4          side 1     
+            //     .wrap_target
+    0x98a0, // 11: pull   block           side 1     
+    0x7110, // 12: out    pins, 16        side 0 [1] 
+    0xb942, // 13: nop                    side 1 [1] 
+    0x7108, // 14: out    pins, 8         side 0 [1] 
+    0xb942, // 15: nop                    side 1 [1] 
+    0x7108, // 16: out    pins, 8         side 0 [1] 
+    0x180b, // 17: jmp    11              side 1     
+    0x98a0, // 18: pull   block           side 1     
+    0x7100, // 19: out    pins, 32        side 0 [1] 
+    0x180b, // 20: jmp    11              side 1     
+    0xf822, // 21: set    x, 2            side 1     
+    0xe000, // 22: set    pins, 0                    
+    0x80a0, // 23: pull   block                      
+    0x7000, // 24: out    pins, 32        side 0     
+    0x003e, // 25: jmp    !x, 30                     
+    0x98a0, // 26: pull   block           side 1     
+    0xe001, // 27: set    pins, 1                    
+    0x7108, // 28: out    pins, 8         side 0 [1] 
+    0x19fc, // 29: jmp    !osre, 28       side 1 [1] 
+    0x1856, // 30: jmp    x--, 22         side 1     
+    0xe001, // 31: set    pins, 1                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program tft_io_program = {
+    .instructions = tft_io_program_instructions,
+    .length = 32,
+    .origin = -1,
+};
+
+static inline pio_sm_config tft_io_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + tft_io_wrap_target, offset + tft_io_wrap);
+    sm_config_set_sideset(&c, 2, true, false);
+    return c;
+}
+#endif