T display s3 (#2317)
* Added T-DISPLAY-S3 i8080 support for more than 33 data pins (#2296) * Modified the ESP32-S3 I8080 interface's support for data pins above 33 pins. * Added T-DISPLAY-S3 support * Update Setup206_LilyGo_T_Display_S3.h * Eliminate need for TFT_DATA_PIN_OFFSET_EN in setup file * Update TFT_eSPI_ESP32_S3.h * Update User_Setup_Select.h * Add new init sequence for LilyGo T Display S3 Co-authored-by: Micky <513673326@qq.com>
This commit is contained in:
BodmerandMicky authored and 
GitHub committed
1 parent
d37f202b94
commit
f33836faac
4 files changed
+201
-32
No files matched your search
@@ -351,31 +351,51 @@ SPI3_HOST = 2
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
#if defined (TFT_PARALLEL_8_BIT)
|
||||
|
||||
#if (TFT_D0 >= 32) // If D0 is a high GPIO assume all other data bits are high GPIO
|
||||
#define MASK_OFFSET 32
|
||||
#define GPIO_CLR_REG GPIO.out1_w1tc.val
|
||||
#define GPIO_SET_REG GPIO.out1_w1ts.val
|
||||
#else
|
||||
#define MASK_OFFSET 0
|
||||
#define GPIO_CLR_REG GPIO.out_w1tc
|
||||
#define GPIO_SET_REG GPIO.out_w1ts
|
||||
#endif
|
||||
|
||||
// Create a bit set lookup table for data bus - wastes 1kbyte of RAM but speeds things up dramatically
|
||||
// can then use e.g. GPIO.out_w1ts = set_mask(0xFF); to set data bus to 0xFF
|
||||
#define PARALLEL_INIT_TFT_DATA_BUS \
|
||||
for (int32_t c = 0; c<256; c++) \
|
||||
{ \
|
||||
xset_mask[c] = 0; \
|
||||
if ( c & 0x01 ) xset_mask[c] |= (1 << TFT_D0); \
|
||||
if ( c & 0x02 ) xset_mask[c] |= (1 << TFT_D1); \
|
||||
if ( c & 0x04 ) xset_mask[c] |= (1 << TFT_D2); \
|
||||
if ( c & 0x08 ) xset_mask[c] |= (1 << TFT_D3); \
|
||||
if ( c & 0x10 ) xset_mask[c] |= (1 << TFT_D4); \
|
||||
if ( c & 0x20 ) xset_mask[c] |= (1 << TFT_D5); \
|
||||
if ( c & 0x40 ) xset_mask[c] |= (1 << TFT_D6); \
|
||||
if ( c & 0x80 ) xset_mask[c] |= (1 << TFT_D7); \
|
||||
xset_mask[c] = 0; \
|
||||
if ( c & 0x01 ) xset_mask[c] |= (1 << (TFT_D0-MASK_OFFSET)); \
|
||||
if ( c & 0x02 ) xset_mask[c] |= (1 << (TFT_D1-MASK_OFFSET)); \
|
||||
if ( c & 0x04 ) xset_mask[c] |= (1 << (TFT_D2-MASK_OFFSET)); \
|
||||
if ( c & 0x08 ) xset_mask[c] |= (1 << (TFT_D3-MASK_OFFSET)); \
|
||||
if ( c & 0x10 ) xset_mask[c] |= (1 << (TFT_D4-MASK_OFFSET)); \
|
||||
if ( c & 0x20 ) xset_mask[c] |= (1 << (TFT_D5-MASK_OFFSET)); \
|
||||
if ( c & 0x40 ) xset_mask[c] |= (1 << (TFT_D6-MASK_OFFSET)); \
|
||||
if ( c & 0x80 ) xset_mask[c] |= (1 << (TFT_D7-MASK_OFFSET)); \
|
||||
} \
|
||||
|
||||
// Mask for the 8 data bits to set pin directions
|
||||
#define GPIO_DIR_MASK ((1 << TFT_D0) | (1 << TFT_D1) | (1 << TFT_D2) | (1 << TFT_D3) | (1 << TFT_D4) | (1 << TFT_D5) | (1 << TFT_D6) | (1 << TFT_D7))
|
||||
#define GPIO_DIR_MASK ((1 << (TFT_D0-MASK_OFFSET)) | (1 << (TFT_D1-MASK_OFFSET)) | (1 << (TFT_D2-MASK_OFFSET)) | (1 << (TFT_D3-MASK_OFFSET)) | (1 << (TFT_D4-MASK_OFFSET)) | (1 << (TFT_D5-MASK_OFFSET)) | (1 << (TFT_D6-MASK_OFFSET)) | (1 << (TFT_D7-MASK_OFFSET)))
|
||||
|
||||
#if (TFT_WR >= 32)
|
||||
// Data bits and the write line are cleared sequentially
|
||||
#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK); WR_L
|
||||
#if (TFT_D0 >= 32)
|
||||
// Data bits and the write line are cleared to 0 in one step (1.25x faster)
|
||||
#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << (TFT_WR-32)))
|
||||
#elif (TFT_D0 >= 0)
|
||||
// Data bits and the write line are cleared sequentially
|
||||
#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK); WR_L
|
||||
#endif
|
||||
#elif (TFT_WR >= 0)
|
||||
// Data bits and the write line are cleared to 0 in one step (1.25x faster)
|
||||
#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << TFT_WR))
|
||||
#if (TFT_D0 >= 32)
|
||||
// Data bits and the write line are cleared sequentially
|
||||
#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK); WR_L
|
||||
#elif (TFT_D0 >= 0)
|
||||
// Data bits and the write line are cleared to 0 in one step (1.25x faster)
|
||||
#define GPIO_OUT_CLR_MASK (GPIO_DIR_MASK | (1 << TFT_WR))
|
||||
#endif
|
||||
#else
|
||||
#define GPIO_OUT_CLR_MASK
|
||||
#endif
|
||||
@@ -389,7 +409,7 @@ SPI3_HOST = 2
|
||||
//*/
|
||||
|
||||
// Write 8 bits to TFT
|
||||
#define tft_Write_8(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t)(C)); WR_H
|
||||
#define tft_Write_8(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t)(C)); WR_H
|
||||
|
||||
#if defined (SSD1963_DRIVER)
|
||||
|
||||
@@ -409,33 +429,33 @@ SPI3_HOST = 2
|
||||
#define tft_Write_16S(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H
|
||||
#else
|
||||
// Write 16 bits to TFT
|
||||
#define tft_Write_16(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H
|
||||
#define tft_Write_16(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H
|
||||
|
||||
// 16 bit write with swapped bytes
|
||||
#define tft_Write_16S(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H
|
||||
#define tft_Write_16S(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
// Write 32 bits to TFT
|
||||
#define tft_Write_32(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 24)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 16)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H
|
||||
#define tft_Write_32(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 24)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 16)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H
|
||||
|
||||
// Write two concatenated 16 bit values to TFT
|
||||
#define tft_Write_32C(C,D) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((D) >> 8)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((D) >> 0)); WR_H
|
||||
#define tft_Write_32C(C,D) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((D) >> 8)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((D) >> 0)); WR_H
|
||||
|
||||
// Write 16 bit value twice to TFT - used by drawPixel()
|
||||
#define tft_Write_32D(C) GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO.out_w1tc = GPIO_OUT_CLR_MASK; GPIO.out_w1ts = set_mask((uint8_t) ((C) >> 0)); WR_H
|
||||
#define tft_Write_32D(C) GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 8)); WR_H; \
|
||||
GPIO_CLR_REG = GPIO_OUT_CLR_MASK; GPIO_SET_REG = set_mask((uint8_t) ((C) >> 0)); WR_H
|
||||
|
||||
// Read pin
|
||||
#ifdef TFT_RD
|
||||
|
||||
Reference in new issue
Block a user