arduino-esp32/tools/sdk/esp32s2/lib/libesp_system.a

!<arch>
/               1589215762  0     0     0       626       `
fffffffff
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<01>r
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panic_print_charpanic_print_strpanic_print_hexpanic_print_decg_panic_abortpanic_abortesp_reset_reason_set_hintesp_reset_reason_get_hintesp_panic_handleresp_register_shutdown_handleresp_unregister_shutdown_handleresp_restart_noos_digesp_restartesp_get_free_heap_sizeesp_get_minimum_free_heap_sizeesp_get_idf_versionesp_system_abortpanicHandlerxt_unhandled_exceptionpanic_restart_xt_panicxt_highint4ld_include_panic_highint_hdlesp_reset_reasonesp_reset_reason_set_hintesp_reset_reason_get_hint//                                              116       `
system_api.c.obj/
panic_handler.c.obj/
panic_handler_asm.S.obj/
dport_panic_highint_hdl.S.obj/
reset_reason.c.obj/

panic.c.obj/    1589215748  501   20    100644  88260     `
ELF



^
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Setting breakpoint at 0x and returning...

ELF file SHA256: Rebooting...
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_default_types.h_stdint.hstddef.hlock.h_types.hreent.hstdlib.hesp_err.hesp_system.hhal.hcore.h	ets_sys.h
soc_memory_layout.hpanic_internal.huart.h
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.symtab.strtab.shstrtab.rela.literal.esp_register_shutdown_handler.rela.literal.esp_unregister_shutdown_handler.rela.iram1.28.literal.rela.iram1.29.literal.rela.literal.esp_get_free_heap_size.rela.literal.esp_get_minimum_free_heap_size.rela.literal.esp_get_idf_version.rela.literal.esp_system_abort.text.data.bss.rela.text.esp_register_shutdown_handler.rela.text.esp_unregister_shutdown_handler.rela.iram1.28.rela.iram1.29.rela.text.esp_get_free_heap_size.rela.text.esp_get_minimum_free_heap_size.rodata.esp_get_idf_version.str1.4.rela.text.esp_get_idf_version.rela.text.esp_system_abort.bss.shutdown_handlers.rela.debug_frame.rela.debug_info.debug_abbrev.rela.debug_loc.rela.debug_aranges.rela.debug_ranges.rela.debug_line.debug_str.comment.xtensa.info.rela.xt.lit.rela.xt.prop 
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<00><><EFBFBD><EFBFBD><EFBFBD> <00><00>(8\`x<00><00>Unknown reasonMemory protection faultUnknownException was unhandled.IllegalInstruction6A<08>I<><13>C<EFBFBD>s<>"fX<18><13>fh<18><03><13>fx<08><00><00>c<00><00>#<08>3<EFBFBD>"<14><><0C><><11><00><><EFBFBD><08>c<02>"f<08><00>C<08><13>"fxM<78><00><00>ʁ<00>C<EFBFBD><00>#<00><00>C<EFBFBD><00>",y<>9<10><><11><00><><EFBFBD><08>#<23>
<00><00>#<23><00>3<EFBFBD>#<23><00><><04><00>C<EFBFBD><00>S<EFBFBD><12>c)s<1D>Re-enable cpu cache.
6<><00><00><00>ځ<00><00><00><00><00><00><00>*<2A>"<14><><EFBFBD><EFBFBD>(A<00><04><00><00><04><00><00><04><00><00><03>
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<01><00><1D>0x:0x6A<00><00><00><00><02><00><00><00><00><00><03><00><1D>Memory dump at 0x:  6A<00>|<7C> <20>*(<28><00><><EFBFBD><00>9P<39><00><00><00><02><00><00><00><00><00> <00>"<00><00>10<> <20><00><00> <00>"
<01><00><00><03><00><00> <00>"<22><00><1D>Icache sync parameter configuration error, the error address and size is 0x(0x)
Icache preload parameter configuration error, the error address and size is 0xIcache reject error occurred while accessing the address 0x (invalid mmu entry)
Dcache sync parameter configuration error, the error address and size is 0xDcache preload parameter configuration error, the error address and size is 0xWrite back error occurred while dcache tries to write back to flash
Dcache reject error occurred while accessing the address 0xMMU entry fault error occurred while accessing the address 0x6A!<00> X!<00> H<06>@(<28> <20><10><00>O<><00><>F!<00><00><02>,a<00> xa<00> h<06><00><00><00><07><00><00><00><00><00><06><00><00><00><00>a<00> xa<00> h<06><00><00><00><07><00><00><00><00>`<60> <20><00><00><00><00>F
a<00> h<06><00><00><00><06><00><00><00> <00><08>h<08><00><00><00><00><00> <20>!'<27>F)<00>2!'!'V<>C!'<27><02>%!'<27><02>1F>!<00> h!<00> (<02><00><00><00><06><00><00><00><00> <20> <20><00><00><00><00><00>.!<00> h!<00> (<02><00><00><00><06><00><00><00><00><00><02><00><00><00><00><00><00><00><00>!<00> (<02><00><00><00><02><00>!<00> (<02>b<08><00><00><00><00><00>F
!<00> (<02><00><00><00><02><00>!<00> (<02>b<08><00><00><00><00><00>3<1C>7"<02>|<7C><1D>WriteReadInstruction fetch operation at address 0x not permitted.
6a<00><00>-
<EFBFBD>ы<EFBFBD><EFBFBD><EFBFBD><04><00><00>!̨<>(1<>"<22><00><00><00><00><00><00><00><00><00><00><00><11><00><00><00><00><1D>Core  register dump:: 0x   was running in ISR context:
EPC1    : 0x  EPC2    : 0x  EPC3    : 0x  EPC4    : 0xPC      PS      A0      A1      A2      A3      A4      A5      A6      A7      A8      A9      A10     A11     A12     A13     A14     A15     SAR     EXCCAUSEEXCVADDRLBEG    LEND    LCOUNT  <00><00><00><00><00><00><00><00><00><00><00>

 
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Backtrace: |<-CORRUPTED |<-CONTINUES6a898B9!(2)1<><00><00><00>ֺ! <20>! <20> <20>!<21><><EFBFBD><EFBFBD><00>8!!*#<23>'8
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ֺ<00><00><><10><00><> <20>!<02><><EFBFBD><EFBFBD><00><00>(<28>X<EFBFBD>1<EFBFBD><16><><EFBFBD><EFBFBD><EFBFBD><00><00>F(1<>r<EFBFBD><00><00><1D>6A<00><00><00><18><03><02><00><00><00><00><00><03><02><00><1D>6A<0B><02><00><00><00><00><1D>Debug exception reason: SingleStep HwBreakpoint Stack canary watchpoint triggered () Watchpoint 0 triggered BREAK instr BREAKN instr DebugIntr 6A <20><03><00><00>b<08><00><00>b<08><00><00>'b:<3A>b.
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/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_system/port/esp32s2/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/machine/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/sys/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/lib/gcc/xtensa-esp32s2-elf/8.2.0/include/Users/ficeto/.espressif/tools/xtensa-esp32s2-elf/esp-2020r1-8.2.0/xtensa-esp32s2-elf/xtensa-esp32s2-elf/sys-include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_system/include/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_rom/include/esp32s2/rom/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/soc/soc/esp32s2/include/soc/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/soc/soc/esp32s2/../include/socreset_reason.c
_default_types.h_stdint.hlock.h_types.hstddef.hreent.hstdlib.hesp_system.hets_sys.hrtc.hrtc_io_struct.hrtc_cntl_struct.hsens_struct.hrtc_io_periph.h	assert.h

	

	
	
	


	
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