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stddef.h_default_types.hlock.h_types.hreent.hstdlib.h_stdint.hstdio.hesp_err.hets_sys.hhal.hcore.h	xtensa_perfmon_masks.h
xtensa_perfmon_apis.h
xtensa_perfmon_access.h
esp_log.h

	

	

	
	
	
	
	
	
	
	
	

	
	
	
	
	
	
	
	
	
	
	
	

	
	
	

		

	
	
	
	
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_stdint.hhal.hcore.hxtensa_perfmon_masks.hxtensa_perfmon_masks.cXthal_extra_sizeXthal_have_windowedXthal_intlevel_maskXthal_excm_levelXthal_dtlb_arf_waysXthal_debug_configuredXthal_num_aregs_log2Xthal_have_spanning_wayXthal_dcache_waysXthal_dataram_paddrXthal_have_mul16Xthal_num_ccompareselectXthal_tram_pendinglong long unsigned intGNU C99 8.2.0 -mlongcalls -ggdb -Og -std=gnu99 -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fstack-protectorXthal_num_instramXthal_dcache_linesizeXthal_build_unique_idXthal_icache_setwidthXthal_inttype_maskXthal_release_minorlong long intsigned charxtensa_perfmon_masksXthal_hw_release_nameXthal_datarom_paddrXthal_dcache_sizeXthal_mmu_ca_bitsXthal_instrom_paddrXthal_dtlb_way_bitsXthal_mmu_max_pte_page_sizeXthal_icache_linesizeXthal_num_intlevelsXthal_dataram_sizeXthal_cpregs_save_nw_fnxtensa_perfmon_select_tableXthal_tram_enabledxtensa_perfmon_select_tXthal_intlevelxtensa_perfmon_select_mask_allXthal_dcache_linewidthxtensa_perfmon_masks_tXthal_cp_id_XCHAL_CP4_IDENTXthal_rev_no__uint32_tXthal_itlb_way_bitsXthal_dtlb_waysXthal_num_dataromXthal_num_dbreakXthal_cp_maxXthal_have_speculationXthal_xlmi_paddrXthal_have_nsaunsigned intXthal_mmu_asid_bitsXthal_cp_id_XCHAL_CP1_IDENTXthal_num_ibreakXthal_itlb_waysXthal_num_aregs/Users/ficeto/Desktop/ESP32/ESP32S2/esp32-arduino-lib-builder/buildshort unsigned intXthal_cp_mask_XCHAL_CP0_IDENTXthal_cp_id_XCHAL_CP5_IDENTXthal_have_threadptrXthal_cp_id_XCHAL_CP6_IDENTXthal_datarom_sizeXthal_have_highlevel_interruptsXthal_cp_mask_XCHAL_CP2_IDENT/Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/perfmon/xtensa_perfmon_masks.cXthal_intlevel_andbelow_maskXthal_mpu_bgmapXthal_cp_mask_XCHAL_CP7_IDENTXthal_inttypeXthal_have_fpXthal_num_dataramXthal_have_densityXthal_xlmi_vaddrXthal_num_xlmiXthal_have_tlbsXthal_cp_mask_XCHAL_CP6_IDENTXthal_hw_release_majorXthal_tram_syncXthal_release_internalXthal_icache_linewidthXthal_mmu_asid_kernelXthal_icache_line_lockableXthal_hw_release_minorxtensa_perfmon_selectXthal_dcache_line_lockableXthal_have_nmiXthal_all_extra_alignXthal_instram_vaddrXthal_cpregs_save_fnXthal_cpregs_alignXthal_instram_sizeXthal_extra_alignXthal_mmu_sr_bitsXthal_instrom_vaddrXthal_hw_release_internalXthal_icache_waysXthal_have_mimic_cacheattrXthal_num_writebuffer_entriesunsigned charXthal_cpregs_restore_nw_fnXthal_have_exceptionsXthal_have_pifshort intXthal_have_identity_mapXthal_mmu_ringsXthal_cp_id_XCHAL_CP3_IDENTXthal_cpregs_restore_fnXthal_num_coprocessorsXthal_icache_sizeXthal_num_interruptsXthal_cp_mask_XCHAL_CP4_IDENTXthal_have_priduint32_tXthal_cp_numXthal_have_clampsXthal_cp_namesXthal_memory_ordercharXthal_dcache_is_writebackXthal_xlmi_sizeXthal_have_xlt_cacheattrXthal_cpregs_sizeXthal_instram_paddrXthal_instrom_sizeXthal_cp_id_XCHAL_CP0_IDENTXthal_mmu_ring_bitsXthal_have_ccountXthal_cp_id_XCHAL_CP2_IDENTXthal_have_booleansXthal_dataram_vaddrmaskxthal_MPU_entryXthal_xea_versionXthal_itlb_arf_waysXthal_mmu_min_pte_page_sizeXthal_release_nameXthal_have_minmaxXthal_release_majorXthal_have_mac16Xthal_have_sextXthal_hw_configid0Xthal_hw_configid1Xthal_cp_maskXthal_timer_interruptXthal_data
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