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IDF master 3e370c4296

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* Fix build compilation due to changes in the HW_TIMER's structs

* Fix compilation warnings and errors with USB

* Update USBCDC.cpp

* Update CMakeLists.txt

* Update HWCDC.cpp
This commit is contained in:
Me No Dev
2021-10-01 17:52:29 +03:00
committed by GitHub
parent 381e88ec75
commit 00214d5c2a
1475 changed files with 88153 additions and 49503 deletions
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2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/apb_ctrl_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div: 10;

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/apb_saradc_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;

4
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/assist_debug_reg.h
View File

@ -652,7 +652,7 @@ extern "C" {
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
#define ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094)
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094)
/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF
@ -660,7 +660,7 @@ extern "C" {
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
#define ASSIST_DEBUG_C0RE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098)
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098)
/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))

38
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_reg.h
View File

@ -141,12 +141,12 @@ extern "C" {
#define EFUSE_DIS_ICACHE_M (BIT(8))
#define EFUSE_DIS_ICACHE_V 0x1
#define EFUSE_DIS_ICACHE_S 8
/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Set this bit to disable boot from RTC RAM.*/
#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1
#define EFUSE_DIS_RTC_RAM_BOOT_S 7
/* EFUSE_RPT4_RESERVED5 : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED5 (BIT(7))
#define EFUSE_RPT4_RESERVED5_M (BIT(7))
#define EFUSE_RPT4_RESERVED5_V 0x1
#define EFUSE_RPT4_RESERVED5_S 7
/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
/*description: Set this bit to disable reading from BlOCK4-10.*/
#define EFUSE_RD_DIS 0x0000007F
@ -516,12 +516,12 @@ extern "C" {
#define EFUSE_DIS_ICACHE_M (BIT(8))
#define EFUSE_DIS_ICACHE_V 0x1
#define EFUSE_DIS_ICACHE_S 8
/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The value of DIS_RTC_RAM_BOOT.*/
#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_M (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_V 0x1
#define EFUSE_DIS_RTC_RAM_BOOT_S 7
/* EFUSE_RPT4_RESERVED5 : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED5 (BIT(7))
#define EFUSE_RPT4_RESERVED5_M (BIT(7))
#define EFUSE_RPT4_RESERVED5_V 0x1
#define EFUSE_RPT4_RESERVED5_S 7
/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
/*description: The value of RD_DIS.*/
#define EFUSE_RD_DIS 0x0000007F
@ -1486,12 +1486,12 @@ extern "C" {
#define EFUSE_DIS_ICACHE_ERR_M (BIT(8))
#define EFUSE_DIS_ICACHE_ERR_V 0x1
#define EFUSE_DIS_ICACHE_ERR_S 8
/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/
#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (BIT(7))
#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x1
#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7
/* EFUSE_RPT4_RESERVED5_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: Reserved..*/
#define EFUSE_RPT4_RESERVED5_ERR (BIT(7))
#define EFUSE_RPT4_RESERVED5_ERR_M (BIT(7))
#define EFUSE_RPT4_RESERVED5_ERR_V 0x1
#define EFUSE_RPT4_RESERVED5_ERR_S 7
/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
/*description: If any bit in RD_DIS is 1 then it indicates a programming error.*/
#define EFUSE_RD_DIS_ERR 0x0000007F
@ -1691,7 +1691,7 @@ extern "C" {
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x1
#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0
#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18C)
/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */
/*description: Reserved.*/
#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF

10
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/efuse_struct.h
View File

@ -17,12 +17,12 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/
union {
struct {
uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/
uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/
uint32_t rpt4_reserved5: 1; /*Reserved*/
uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/
uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/
uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/
@ -106,7 +106,7 @@ typedef volatile struct {
union {
struct {
uint32_t rd_dis: 7; /*The value of RD_DIS.*/
uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/
uint32_t rpt4_reserved5: 1; /*Reserved*/
uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/
uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/
uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/
@ -274,7 +274,7 @@ typedef volatile struct {
union {
struct {
uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/
uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/
uint32_t rpt4_reserved5_err: 1; /*Reserved.*/
uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/
uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/
uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/
@ -342,7 +342,6 @@ typedef volatile struct {
};
uint32_t val;
} rd_repeat_err3;
uint32_t reserved_18c;
union {
struct {
uint32_t rpt4_reserved4_err:24; /*Reserved.*/
@ -350,6 +349,7 @@ typedef volatile struct {
};
uint32_t val;
} rd_repeat_err4;
uint32_t reserved_190;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gdma_struct.h
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@ -19,7 +19,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gdma_dev_s {
struct {
union {
struct {

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gpio_sd_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;

41
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gpio_sig_map.h
View File

@ -53,26 +53,26 @@
#define GPIO_WLAN_PRIO_IDX 18
#define GPIO_BT_ACTIVE_IDX 19
#define GPIO_WLAN_ACTIVE_IDX 19
#define BB_DIAG0_IDX 20
#define BB_DIAG1_IDX 21
#define BB_DIAG2_IDX 22
#define BB_DIAG3_IDX 23
#define BB_DIAG4_IDX 24
#define BB_DIAG5_IDX 25
#define BB_DIAG6_IDX 26
#define BB_DIAG7_IDX 27
#define BB_DIAG8_IDX 28
#define BB_DIAG9_IDX 29
#define BB_DIAG10_IDX 30
#define BB_DIAG11_IDX 31
#define BB_DIAG12_IDX 32
#define BB_DIAG13_IDX 33
#define BB_DIAG14_IDX 34
#define BB_DIAG15_IDX 35
#define BB_DIAG16_IDX 36
#define BB_DIAG17_IDX 37
#define BB_DIAG18_IDX 38
#define BB_DIAG19_IDX 39
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_OUT_IDX 36
#define USB_JTAG_TMS_OUT_IDX 37
#define USB_JTAG_TDI_OUT_IDX 38
#define USB_JTAG_TDO_OUT_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
@ -179,6 +179,7 @@
#define CLK_OUT_OUT2_IDX 124
#define CLK_OUT_OUT3_IDX 125
#define SPICS1_OUT_IDX 126
#define USB_JTAG_TRST_OUT_IDX 127
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2006130
#endif /* _SOC_GPIO_SIG_MAP_H_ */

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/gpio_struct.h
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@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
union {
struct {

1
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/hwcrypto_reg.h
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@ -133,6 +133,7 @@
#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58)
#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c)
#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60)
#define HMAC_INVALIDATE_JTAG BIT(0)
#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64)
#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/i2c_struct.h
View File

@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period : 9;

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/i2s_struct.h
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@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;

3
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/io_mux_reg.h
View File

@ -124,9 +124,6 @@
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U0RXD_GPIO_NUM 20
#define U0TXD_GPIO_NUM 21
#define SPI_HD_GPIO_NUM 12
#define SPI_WP_GPIO_NUM 13
#define SPI_CS0_GPIO_NUM 14

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/ledc_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {

6
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/periph_defs.h
View File

@ -76,7 +76,7 @@ typedef enum {
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_TWAI_INTR_SOURCE, /**< interrupt of can, level*/
ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
@ -102,8 +102,8 @@ typedef enum {
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_DMA_APBPERI_PMS_INTR_SOURCE,
ETS_CORE0_IRAM0_PMS_INTR_SOURCE,

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/reset_reasons.h
View File

@ -52,6 +52,8 @@ typedef enum {
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
} soc_reset_reason_t;

8
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rmt_struct.h
View File

@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /**/
union {
struct {
@ -291,11 +291,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[48];
};
rmt_item32_t data32[48];
} chan[4];
} rmt_mem_t;

3
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc.h
View File

@ -206,7 +206,8 @@ typedef enum {
typedef enum {
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
RTC_CAL_32K_XTAL = 2, //!< External 32 kHz XTAL
RTC_CAL_INTERNAL_OSC = 3 //!< Internal 150 kHz oscillator
} rtc_cal_sel_t;
/**

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc_cntl_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/rtc_i2c_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/

5
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/sensitive_struct.h
View File

@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct sensitive_dev_s {
union {
struct {
uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/
@ -959,8 +959,7 @@ typedef volatile struct {
union {
struct {
uint32_t reg_clk_en : 1; /*clk_en*/
uint32_t reserved1 : 31;
uint32_t reservedNone : None; /*SENSITIVE_CLOCK_GATE_REG_REG*/
uint32_t reserved1 : 31; /*SENSITIVE_CLOCK_GATE_REG_REG*/
};
uint32_t val;
} clock_gate;

50
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc.h
View File

@ -268,57 +268,13 @@
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fcebf10
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage
* 0 1 extern level Panic
* 1 1 extern level WMAC
* 2 1 extern level
* 3 1 extern level
* 4 1 extern level WBB
* 5 1 extern level BT/BLE Controller
* 6 1 timer FreeRTOS Tick(L1)
* 7 1 software
* 8 1 extern level BT/BLE BB(RX/TX)
* 9 1 extern level
* 10 1 extern edge
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved
* 15 3 timer FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level TG1_WDT
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved
* 28 4 extern edge Reserved
* 29 3 software Reserved
* 30 4 extern edge Reserved
* 31 5 extern level
*************************************************************************************************************
*/
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 1
//#define ETS_BT_HOST_INUM 1
#define ETS_WBB_INUM 4
#define ETS_SYSTICK_INUM 9
#define ETS_TG0_T1_INUM 10 /* use edge interrupt */
#define ETS_CPU_INTR0_INUM 12 /* used as freertos soft intr */
#define ETS_FRC1_INUM 22
//CPU0 Interrupt number reserved in riscv/vector.S, not touch this.
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM 26
#define ETS_DPORT_INUM 28
//CPU0 Max valid interrupt number
#define ETS_MAX_INUM 31

42
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/soc_caps.h
View File

@ -6,6 +6,7 @@
#pragma once
#define SOC_CPU_CORES_NUM 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
@ -14,7 +15,9 @@
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define SOC_TEMP_SENSOR_SUPPORTED 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_XT_WDT_SUPPORTED 1
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_SUPPORTS_SECURE_DL_MODE 1
@ -32,19 +35,31 @@
#define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
#define SOC_ADC_ARBITER_SUPPORTED 1
#define SOC_ADC_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (16)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_MAX_BITWIDTH (12)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
//F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
#define SOC_ADC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
@ -94,6 +109,11 @@
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_AUTO_ENABLE (1) /*!< The dedicated GPIO peripheral is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
@ -108,11 +128,10 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_CODEC (1)
#define SOC_I2S_SUPPORTS_TDM (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
@ -239,7 +258,6 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C3 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/spi_mem_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/spi_struct.h
View File

@ -19,7 +19,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct spi_dev_s {
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/

30
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/syscon_struct.h
View File

@ -17,26 +17,26 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t apb_ctrl_pre_div_cnt: 10;
uint32_t apb_ctrl_clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t apb_ctrl_rst_tick_cnt: 1;
uint32_t reserved13: 19;
uint32_t pre_div_cnt: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick_cnt: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
} sysclk_conf;
union {
struct {
uint32_t apb_ctrl_xtal_tick_num: 8;
uint32_t apb_ctrl_ck8m_tick_num: 8;
uint32_t apb_ctrl_tick_enable: 1;
uint32_t reserved17: 15;
uint32_t xtal_tick_num: 8;
uint32_t ck8m_tick_num: 8;
uint32_t tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} apb_ctrl_tick_conf;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
@ -53,7 +53,7 @@ typedef volatile struct {
uint32_t reserved11: 21;
};
uint32_t val;
} apb_ctrl_clk_out_en;
} clk_out_en;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
@ -161,7 +161,7 @@ typedef volatile struct {
uint32_t reserved1: 31;
};
uint32_t val;
} apb_ctrl_sdio_ctrl;
} sdio_ctrl;
union {
struct {
uint32_t redcy_sig0: 31;
@ -472,7 +472,7 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /*Version control*/
uint32_t date; /*Version control*/
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/system_struct.h
View File

@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct system_dev_s {
union {
struct {
uint32_t reserved0 : 6; /*reserved*/

10
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/systimer_struct.h
View File

@ -88,6 +88,7 @@ typedef union {
* update timer_unit0
*/
uint32_t timer_unit_update: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} systimer_unit_op_reg_t;
@ -102,6 +103,7 @@ typedef struct {
* timer unit load high 32 bit
*/
uint32_t timer_unit_load_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@ -126,6 +128,7 @@ typedef struct {
* timer target high 32 bit
*/
uint32_t timer_target_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@ -172,6 +175,7 @@ typedef struct {
* timer read value high 20bit
*/
uint32_t timer_unit_value_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@ -195,6 +199,7 @@ typedef union {
* timer comp load value
*/
uint32_t timer_comp_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp_load_reg_t;
@ -208,6 +213,7 @@ typedef union {
* timer unit load value
*/
uint32_t timer_unit_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_unit_load_reg_t;
@ -230,6 +236,7 @@ typedef union {
* interupt2 enable
*/
uint32_t target2_int_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@ -251,6 +258,7 @@ typedef union {
* interupt2 raw
*/
uint32_t target2_int_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@ -272,6 +280,7 @@ typedef union {
* interupt2 clear
*/
uint32_t target2_int_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;
@ -293,6 +302,7 @@ typedef union {
* reg_target2_int_st
*/
uint32_t target2_int_st: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_st_reg_t;

883
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/timer_group_reg.h
View File

@ -1,24 +1,17 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_REG_H_
#define _SOC_TIMG_REG_H_
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
@ -29,413 +22,559 @@ extern "C" {
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
#define TIMG_WDT_RESET_LENGTH_100_NS 0
#define TIMG_WDT_RESET_LENGTH_200_NS 1
#define TIMG_WDT_RESET_LENGTH_300_NS 2
#define TIMG_WDT_RESET_LENGTH_400_NS 3
#define TIMG_WDT_RESET_LENGTH_500_NS 4
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (BIT(31))
#define TIMG_T0_EN_V 0x1
#define TIMG_T0_EN_S 31
/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (BIT(30))
#define TIMG_T0_INCREASE_V 0x1
#define TIMG_T0_INCREASE_S 30
/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (BIT(29))
#define TIMG_T0_AUTORELOAD_V 0x1
#define TIMG_T0_AUTORELOAD_S 29
/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
/*description: */
#define TIMG_T0_DIVIDER 0x0000FFFF
#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
#define TIMG_T0_DIVIDER_V 0xFFFF
#define TIMG_T0_DIVIDER_S 13
/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (BIT(12))
#define TIMG_T0_DIVCNT_RST_V 0x1
#define TIMG_T0_DIVCNT_RST_S 12
/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (BIT(10))
#define TIMG_T0_ALARM_EN_V 0x1
#define TIMG_T0_ALARM_EN_S 10
/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
/*description: */
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (BIT(9))
#define TIMG_T0_USE_XTAL_V 0x1
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
#define TIMG_T0_USE_XTAL (BIT(9))
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
#define TIMG_T0_USE_XTAL_V 0x00000001U
#define TIMG_T0_USE_XTAL_S 9
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
#define TIMG_T0_ALARM_EN (BIT(10))
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
#define TIMG_T0_ALARM_EN_V 0x00000001U
#define TIMG_T0_ALARM_EN_S 10
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* When set, Timer 0 's clock divider counter will be reset.
*/
#define TIMG_T0_DIVCNT_RST (BIT(12))
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
#define TIMG_T0_DIVCNT_RST_S 12
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Timer 0 clock (T0_clk) prescaler value.
*/
#define TIMG_T0_DIVIDER 0x0000FFFFU
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
#define TIMG_T0_DIVIDER_S 13
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* When set, timer 0 auto-reload at alarm is enabled.
*/
#define TIMG_T0_AUTORELOAD (BIT(29))
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
#define TIMG_T0_AUTORELOAD_V 0x00000001U
#define TIMG_T0_AUTORELOAD_S 29
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
* When set, the timer 0 time-base counter will increment every clock tick. When
* cleared, the timer 0 time-base counter will decrement.
*/
#define TIMG_T0_INCREASE (BIT(30))
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
#define TIMG_T0_INCREASE_V 0x00000001U
#define TIMG_T0_INCREASE_S 30
/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
* When set, the timer 0 time-base counter is enabled.
*/
#define TIMG_T0_EN (BIT(31))
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
#define TIMG_T0_EN_V 0x00000001U
#define TIMG_T0_EN_S 31
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004)
/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LO 0xFFFFFFFF
#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
#define TIMG_T0_LO_V 0xFFFFFFFF
/** TIMG_T0LO_REG register
* Timer 0 current value, low 32 bits
*/
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
* of timer 0 can be read here.
*/
#define TIMG_T0_LO 0xFFFFFFFFU
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
#define TIMG_T0_LO_V 0xFFFFFFFFU
#define TIMG_T0_LO_S 0
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008)
/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_HI 0x003FFFFF
#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
#define TIMG_T0_HI_V 0x3FFFFF
/** TIMG_T0HI_REG register
* Timer $x current value, high 22 bits
*/
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
#define TIMG_T0_HI 0x003FFFFFU
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
#define TIMG_T0_HI_V 0x003FFFFFU
#define TIMG_T0_HI_S 0
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c)
/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (BIT(31))
#define TIMG_T0_UPDATE_V 0x1
/** TIMG_T0UPDATE_REG register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
#define TIMG_T0_UPDATE (BIT(31))
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
#define TIMG_T0_UPDATE_V 0x00000001U
#define TIMG_T0_UPDATE_S 31
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010)
/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_ALARM_LO 0xFFFFFFFF
#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF
/** TIMG_T0ALARMLO_REG register
* Timer $x alarm value, low 32 bits
*/
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T0_ALARM_LO_S 0
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014)
/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_ALARM_HI 0x003FFFFF
#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
#define TIMG_T0_ALARM_HI_V 0x3FFFFF
/** TIMG_T0ALARMHI_REG register
* Timer $x alarm value, high bits
*/
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
#define TIMG_T0_ALARM_HI 0x003FFFFFU
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
#define TIMG_T0_ALARM_HI_S 0
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018)
/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD_LO 0xFFFFFFFF
#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF
/** TIMG_T0LOADLO_REG register
* Timer $x reload value, low 32 bits
*/
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_LO_S 0
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c)
/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
/*description: */
#define TIMG_T0_LOAD_HI 0x003FFFFF
#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
#define TIMG_T0_LOAD_HI_V 0x3FFFFF
/** TIMG_T0LOADHI_REG register
* Timer $x reload value, high 22 bits
*/
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
#define TIMG_T0_LOAD_HI 0x003FFFFFU
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
#define TIMG_T0_LOAD_HI_S 0
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020)
/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_T0_LOAD 0xFFFFFFFF
#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
#define TIMG_T0_LOAD_V 0xFFFFFFFF
/** TIMG_T0LOAD_REG register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
#define TIMG_T0_LOAD 0xFFFFFFFFU
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048)
/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (BIT(31))
#define TIMG_WDT_EN_V 0x1
#define TIMG_WDT_EN_S 31
/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG0 0x00000003
#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
#define TIMG_WDT_STG0_V 0x3
#define TIMG_WDT_STG0_S 29
/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG1 0x00000003
#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
#define TIMG_WDT_STG1_V 0x3
#define TIMG_WDT_STG1_S 27
/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG2 0x00000003
#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
#define TIMG_WDT_STG2_V 0x3
#define TIMG_WDT_STG2_S 25
/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
/*description: */
#define TIMG_WDT_STG3 0x00000003
#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
#define TIMG_WDT_STG3_V 0x3
#define TIMG_WDT_STG3_S 23
/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_V 0x1
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (BIT(21))
#define TIMG_WDT_USE_XTAL_V 0x1
#define TIMG_WDT_USE_XTAL_S 21
/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007
#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
/*description: */
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007
#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_V 0x1
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
/*description: */
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_V 0x1
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_APPCPU_RESET_EN_S 12
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
#define TIMG_WDT_PROCPU_RESET_EN_S 13
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
#define TIMG_WDT_USE_XTAL (BIT(21))
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
#define TIMG_WDT_USE_XTAL_V 0x00000001U
#define TIMG_WDT_USE_XTAL_S 21
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
#define TIMG_WDT_CONF_UPDATE_EN_S 22
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG3 0x00000003U
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
#define TIMG_WDT_STG3_V 0x00000003U
#define TIMG_WDT_STG3_S 23
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG2 0x00000003U
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
#define TIMG_WDT_STG2_V 0x00000003U
#define TIMG_WDT_STG2_S 25
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG1 0x00000003U
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
#define TIMG_WDT_STG1_V 0x00000003U
#define TIMG_WDT_STG1_S 27
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
#define TIMG_WDT_STG0 0x00000003U
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
#define TIMG_WDT_STG0_V 0x00000003U
#define TIMG_WDT_STG0_S 29
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
#define TIMG_WDT_EN (BIT(31))
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
#define TIMG_WDT_EN_V 0x00000001U
#define TIMG_WDT_EN_S 31
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c)
/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
/*description: */
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF
#define TIMG_WDT_CLK_PRESCALE_S 16
/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (BIT(0))
#define TIMG_WDT_DIVCNT_RST_V 0x1
/** TIMG_WDTCONFIG1_REG register
* Watchdog timer prescaler register
*/
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
#define TIMG_WDT_DIVCNT_RST (BIT(0))
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
#define TIMG_WDT_DIVCNT_RST_S 0
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
#define TIMG_WDT_CLK_PRESCALE_S 16
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050)
/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
/*description: */
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG2_REG register
* Watchdog timer stage 0 timeout value
*/
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG0_HOLD_S 0
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054)
/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
/*description: */
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG3_REG register
* Watchdog timer stage 1 timeout value
*/
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG1_HOLD_S 0
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058)
/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG4_REG register
* Watchdog timer stage 2 timeout value
*/
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG2_HOLD_S 0
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c)
/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
/*description: */
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF
/** TIMG_WDTCONFIG5_REG register
* Watchdog timer stage 3 timeout value
*/
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define TIMG_WDT_STG3_HOLD_S 0
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060)
/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define TIMG_WDT_FEED 0xFFFFFFFF
#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
#define TIMG_WDT_FEED_V 0xFFFFFFFF
/** TIMG_WDTFEED_REG register
* Write to feed the watchdog timer
*/
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
#define TIMG_WDT_FEED 0xFFFFFFFFU
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
#define TIMG_WDT_FEED_S 0
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064)
/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
/*description: */
#define TIMG_WDT_WKEY 0xFFFFFFFF
#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
#define TIMG_WDT_WKEY_V 0xFFFFFFFF
/** TIMG_WDTWPROTECT_REG register
* Watchdog write protect register
*/
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
#define TIMG_WDT_WKEY 0xFFFFFFFFU
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
#define TIMG_WDT_WKEY_S 0
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
/*description: */
#define TIMG_RTC_CALI_MAX 0x00007FFF
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7FFF
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
/*description: */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
/*description: */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
/*description: */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
/** TIMG_RTCCALICFG_REG register
* RTC calibration configure register
*/
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
#define TIMG_RTC_CALI_START_CYCLING_S 12
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
#define TIMG_RTC_CALI_CLK_SEL_S 13
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
#define TIMG_RTC_CALI_RDY_V 0x00000001U
#define TIMG_RTC_CALI_RDY_S 15
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
#define TIMG_RTC_CALI_MAX 0x00007FFFU
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
#define TIMG_RTC_CALI_MAX_S 16
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
#define TIMG_RTC_CALI_START_V 0x00000001U
#define TIMG_RTC_CALI_START_S 31
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
/*description: */
#define TIMG_RTC_CALI_VALUE 0x01FFFFFF
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1
/** TIMG_RTCCALICFG1_REG register
* RTC calibration configure1 register
*/
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
#define TIMG_RTC_CALI_VALUE_S 7
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070)
/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (BIT(1))
#define TIMG_WDT_INT_ENA_V 0x1
#define TIMG_WDT_INT_ENA_S 1
/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (BIT(0))
#define TIMG_T0_INT_ENA_V 0x1
/** TIMG_INT_ENA_TIMERS_REG register
* Interrupt enable bits
*/
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ENA (BIT(0))
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ENA (BIT(1))
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
#define TIMG_WDT_INT_ENA_V 0x00000001U
#define TIMG_WDT_INT_ENA_S 1
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074)
/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (BIT(1))
#define TIMG_WDT_INT_RAW_V 0x1
#define TIMG_WDT_INT_RAW_S 1
/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (BIT(0))
#define TIMG_T0_INT_RAW_V 0x1
/** TIMG_INT_RAW_TIMERS_REG register
* Raw interrupt status
*/
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_RAW (BIT(0))
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_RAW (BIT(1))
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
#define TIMG_WDT_INT_RAW_V 0x00000001U
#define TIMG_WDT_INT_RAW_S 1
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078)
/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (BIT(1))
#define TIMG_WDT_INT_ST_V 0x1
#define TIMG_WDT_INT_ST_S 1
/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (BIT(0))
#define TIMG_T0_INT_ST_V 0x1
/** TIMG_INT_ST_TIMERS_REG register
* Masked interrupt status
*/
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_ST (BIT(0))
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_ST (BIT(1))
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
#define TIMG_WDT_INT_ST_V 0x00000001U
#define TIMG_WDT_INT_ST_S 1
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c)
/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */
/*description: */
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (BIT(1))
#define TIMG_WDT_INT_CLR_V 0x1
#define TIMG_WDT_INT_CLR_S 1
/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */
/*description: */
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (BIT(0))
#define TIMG_T0_INT_CLR_V 0x1
/** TIMG_INT_CLR_TIMERS_REG register
* Interrupt clear bits
*/
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
#define TIMG_T0_INT_CLR (BIT(0))
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
#define TIMG_WDT_INT_CLR (BIT(1))
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
#define TIMG_WDT_INT_CLR_V 0x00000001U
#define TIMG_WDT_INT_CLR_S 1
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080)
/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
/*description: timeout if cali value counts over threshold*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
/*description: Cycles that release calibration timeout reset*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
/*description: timeout indicator*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_V 0x1
/** TIMG_RTCCALICFG2_REG register
* Timer group calibration register
*/
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
#define TIMG_RTC_CALI_TIMEOUT_S 0
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8)
/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */
/*description: */
#define TIMG_NTIMERS_DATE 0x0FFFFFFF
#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
#define TIMG_NTIMERS_DATE_V 0xFFFFFFF
#define TIMG_NTIMERS_DATE_S 0
/** TIMG_NTIMERS_DATE_REG register
* Timer version control register
*/
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
#define TIMG_NTIMGS_DATE_S 0
#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc)
/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (BIT(31))
#define TIMG_CLK_EN_V 0x1
#define TIMG_CLK_EN_S 31
/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */
/*description: */
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */
/*description: */
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1
/** TIMG_REGCLK_REG register
* Timer group clock gate register
*/
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
#define TIMG_CLK_EN (BIT(31))
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
#define TIMG_CLK_EN_V 0x00000001U
#define TIMG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif
#endif /*_SOC_TIMG_REG_H_ */

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tools/sdk/esp32c3/include/soc/esp32c3/include/soc/timer_group_struct.h
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@ -1,222 +1,561 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_TIMG_STRUCT_H_
#define _SOC_TIMG_STRUCT_H_
/**
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
/** Group: T0 Control and configuration registers */
/** Type of txconfig register
* Timer x configuration register
*/
typedef union {
struct {
union {
struct {
uint32_t reserved0: 9;
uint32_t use_xtal: 1;
uint32_t alarm_en: 1;
uint32_t reserved11: 1;
uint32_t divcnt_rst: 1;
uint32_t divider: 16;
uint32_t autoreload: 1;
uint32_t increase: 1;
uint32_t enable: 1;
};
uint32_t val;
} config;
uint32_t cnt_low; /**/
union {
struct {
uint32_t hi: 22;
uint32_t reserved22:10;
};
uint32_t val;
} cnt_high;
union {
struct {
uint32_t reserved0: 31;
uint32_t update: 1;
};
uint32_t val;
} update;
uint32_t alarm_low; /**/
union {
struct {
uint32_t alarm_hi: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} alarm_high;
uint32_t load_low; /**/
union {
struct {
uint32_t load_hi: 22;
uint32_t reserved22:10;
};
uint32_t val;
} load_high;
uint32_t reload; /**/
} hw_timer[1];
uint32_t reserved_24;
uint32_t reserved_28;
uint32_t reserved_2c;
uint32_t reserved_30;
uint32_t reserved_34;
uint32_t reserved_38;
uint32_t reserved_3c;
uint32_t reserved_40;
uint32_t reserved_44;
union {
struct {
uint32_t reserved0: 12;
uint32_t appcpu_reset_en: 1;
uint32_t procpu_reset_en: 1;
uint32_t flashboot_mod_en: 1;
uint32_t sys_reset_length: 3;
uint32_t cpu_reset_length: 3;
uint32_t use_xtal: 1;
uint32_t conf_update_en: 1;
uint32_t stg3: 2;
uint32_t stg2: 2;
uint32_t stg1: 2;
uint32_t stg0: 2;
uint32_t en: 1;
};
uint32_t val;
} wdt_config0;
union {
struct {
uint32_t divcnt_rst: 1;
uint32_t reserved1: 15;
uint32_t clk_prescale: 16;
};
uint32_t val;
} wdt_config1;
uint32_t wdt_config2; /**/
uint32_t wdt_config3; /**/
uint32_t wdt_config4; /**/
uint32_t wdt_config5; /**/
uint32_t wdt_feed; /**/
uint32_t wdt_wprotect; /**/
union {
struct {
uint32_t reserved0: 12;
uint32_t start_cycling: 1;
uint32_t clk_sel: 2;
uint32_t rdy: 1;
uint32_t max: 15;
uint32_t start: 1;
};
uint32_t val;
} rtc_cali_cfg;
union {
struct {
uint32_t cycling_data_vld: 1;
uint32_t reserved1: 6;
uint32_t value: 25;
};
uint32_t val;
} rtc_cali_cfg1;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t t0: 1;
uint32_t wdt: 1;
uint32_t reserved2: 30;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t timeout: 1; /*timeout indicator*/
uint32_t reserved1: 2;
uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/
uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/
};
uint32_t val;
} rtc_cali_cfg2;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;
uint32_t reserved_b8;
uint32_t reserved_bc;
uint32_t reserved_c0;
uint32_t reserved_c4;
uint32_t reserved_c8;
uint32_t reserved_cc;
uint32_t reserved_d0;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
uint32_t reserved_f0;
uint32_t reserved_f4;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} timg_date;
union {
struct {
uint32_t reserved0: 29;
uint32_t wdt_clk_is_active: 1;
uint32_t timer_clk_is_active: 1;
uint32_t en: 1;
};
uint32_t val;
} clk;
uint32_t reserved_0:9;
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
* clock of timer group.
*/
uint32_t tx_use_xtal:1;
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
* When set, the alarm is enabled. This bit is automatically cleared once an
* alarm occurs.
*/
uint32_t tx_alarm_en:1;
uint32_t reserved_11:1;
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
* When set, Timer x 's clock divider counter will be reset.
*/
uint32_t tx_divcnt_rst:1;
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
* Timer x clock (Tx_clk) prescaler value.
*/
uint32_t tx_divider:16;
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
* When set, timer x auto-reload at alarm is enabled.
*/
uint32_t tx_autoreload:1;
/** tx_increase : R/W; bitpos: [30]; default: 1;
* When set, the timer x time-base counter will increment every clock tick. When
* cleared, the timer x time-base counter will decrement.
*/
uint32_t tx_increase:1;
/** tx_en : R/W; bitpos: [31]; default: 0;
* When set, the timer x time-base counter is enabled.
*/
uint32_t tx_en:1;
};
uint32_t val;
} timg_txconfig_reg_t;
/** Type of txlo register
* Timer x current value, low 32 bits
*/
typedef union {
struct {
/** tx_lo : RO; bitpos: [31:0]; default: 0;
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
* of timer x can be read here.
*/
uint32_t tx_lo:32;
};
uint32_t val;
} timg_txlo_reg_t;
/** Type of txhi register
* Timer $x current value, high 22 bits
*/
typedef union {
struct {
/** tx_hi : RO; bitpos: [21:0]; default: 0;
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
* of timer $x can be read here.
*/
uint32_t tx_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txhi_reg_t;
/** Type of txupdate register
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
*/
uint32_t tx_update:1;
};
uint32_t val;
} timg_txupdate_reg_t;
/** Type of txalarmlo register
* Timer $x alarm value, low 32 bits
*/
typedef union {
struct {
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
* Timer $x alarm trigger time-base counter value, low 32 bits.
*/
uint32_t tx_alarm_lo:32;
};
uint32_t val;
} timg_txalarmlo_reg_t;
/** Type of txalarmhi register
* Timer $x alarm value, high bits
*/
typedef union {
struct {
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
* Timer $x alarm trigger time-base counter value, high 22 bits.
*/
uint32_t tx_alarm_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txalarmhi_reg_t;
/** Type of txloadlo register
* Timer $x reload value, low 32 bits
*/
typedef union {
struct {
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
* Low 32 bits of the value that a reload will load onto timer $x time-base
* Counter.
*/
uint32_t tx_load_lo:32;
};
uint32_t val;
} timg_txloadlo_reg_t;
/** Type of txloadhi register
* Timer $x reload value, high 22 bits
*/
typedef union {
struct {
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
* High 22 bits of the value that a reload will load onto timer $x time-base
* counter.
*/
uint32_t tx_load_hi:22;
uint32_t reserved_22:10;
};
uint32_t val;
} timg_txloadhi_reg_t;
/** Type of txload register
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
*/
typedef union {
struct {
/** tx_load : WT; bitpos: [31:0]; default: 0;
*
* Write any value to trigger a timer $x time-base counter reload.
*/
uint32_t tx_load:32;
};
uint32_t val;
} timg_txload_reg_t;
/** Group: WDT Control and configuration registers */
/** Type of wdtconfig0 register
* Watchdog timer configuration register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
* WDT reset CPU enable.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
* When set, Flash boot protection is enabled.
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
* choose WDT clock:0-apb_clk; 1-xtal_clk.
*/
uint32_t wdt_use_xtal:1;
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
* update the WDT configuration registers
*/
uint32_t wdt_conf_update_en:1;
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg3:2;
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg2:2;
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg1:2;
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
*/
uint32_t wdt_stg0:2;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* When set, MWDT is enabled.
*/
uint32_t wdt_en:1;
};
uint32_t val;
} timg_wdtconfig0_reg_t;
/** Type of wdtconfig1 register
* Watchdog timer prescaler register
*/
typedef union {
struct {
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
* When set, WDT 's clock divider counter will be reset.
*/
uint32_t wdt_divcnt_rst:1;
uint32_t reserved_1:15;
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
* TIMG_WDT_CLK_PRESCALE.
*/
uint32_t wdt_clk_prescale:16;
};
uint32_t val;
} timg_wdtconfig1_reg_t;
/** Type of wdtconfig2 register
* Watchdog timer stage 0 timeout value
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
* Stage 0 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} timg_wdtconfig2_reg_t;
/** Type of wdtconfig3 register
* Watchdog timer stage 1 timeout value
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
* Stage 1 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} timg_wdtconfig3_reg_t;
/** Type of wdtconfig4 register
* Watchdog timer stage 2 timeout value
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 2 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} timg_wdtconfig4_reg_t;
/** Type of wdtconfig5 register
* Watchdog timer stage 3 timeout value
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
* Stage 3 timeout value, in MWDT clock cycles.
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} timg_wdtconfig5_reg_t;
/** Type of wdtfeed register
* Write to feed the watchdog timer
*/
typedef union {
struct {
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
* Write any value to feed the MWDT. (WO)
*/
uint32_t wdt_feed:32;
};
uint32_t val;
} timg_wdtfeed_reg_t;
/** Type of wdtwprotect register
* Watchdog write protect register
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
* If the register contains a different value than its reset value, write
* protection is enabled.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} timg_wdtwprotect_reg_t;
/** Group: RTC CALI Control and configuration registers */
/** Type of rtccalicfg register
* RTC calibration configure register
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
* Reserved
*/
uint32_t rtc_cali_start_cycling:1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel:2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
* Reserved
*/
uint32_t rtc_cali_rdy:1;
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
* Reserved
*/
uint32_t rtc_cali_max:15;
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
* Reserved
*/
uint32_t rtc_cali_start:1;
};
uint32_t val;
} timg_rtccalicfg_reg_t;
/** Type of rtccalicfg1 register
* RTC calibration configure1 register
*/
typedef union {
struct {
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t rtc_cali_cycling_data_vld:1;
uint32_t reserved_1:6;
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
* Reserved
*/
uint32_t rtc_cali_value:25;
};
uint32_t val;
} timg_rtccalicfg1_reg_t;
/** Type of rtccalicfg2 register
* Timer group calibration register
*/
typedef union {
struct {
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
* RTC calibration timeout indicator
*/
uint32_t rtc_cali_timeout:1;
uint32_t reserved_1:2;
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
* Cycles that release calibration timeout reset
*/
uint32_t rtc_cali_timeout_rst_cnt:4;
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
* Threshold value for the RTC calibration timer. If the calibration timer's value
* exceeds this threshold, a timeout is triggered.
*/
uint32_t rtc_cali_timeout_thres:25;
};
uint32_t val;
} timg_rtccalicfg2_reg_t;
/** Group: Interrupt registers */
/** Type of int_ena_timers register
* Interrupt enable bits
*/
typedef union {
struct {
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_ena:1;
/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_ena_timers_reg_t;
/** Type of int_raw_timers register
* Raw interrupt status
*/
typedef union {
struct {
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_raw:1;
/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_raw_timers_reg_t;
/** Type of int_st_timers register
* Masked interrupt status
*/
typedef union {
struct {
/** t0_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_st:1;
/** wdt_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_st_timers_reg_t;
/** Type of int_clr_timers register
* Interrupt clear bits
*/
typedef union {
struct {
/** t0_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the TIMG_T$x_INT interrupt.
*/
uint32_t t0_int_clr:1;
/** wdt_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the TIMG_WDT_INT interrupt.
*/
uint32_t wdt_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} timg_int_clr_timers_reg_t;
/** Group: Version register */
/** Type of ntimers_date register
* Timer version control register
*/
typedef union {
struct {
/** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409;
* Timer version control register
*/
uint32_t ntimgs_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} timg_ntimers_date_reg_t;
/** Group: Clock configuration registers */
/** Type of regclk register
* Timer group clock gate register
*/
typedef union {
struct {
uint32_t reserved_0:29;
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
* enable WDT's clock
*/
uint32_t wdt_clk_is_active:1;
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
* enable Timer $x's clock
*/
uint32_t timer_clk_is_active:1;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
* Registers can not be read or written to by software.
*/
uint32_t clk_en:1;
};
uint32_t val;
} timg_regclk_reg_t;
typedef struct {
volatile timg_txconfig_reg_t config;
volatile timg_txlo_reg_t lo;
volatile timg_txhi_reg_t hi;
volatile timg_txupdate_reg_t update;
volatile timg_txalarmlo_reg_t alarmlo;
volatile timg_txalarmhi_reg_t alarmhi;
volatile timg_txloadlo_reg_t loadlo;
volatile timg_txloadhi_reg_t loadhi;
volatile timg_txload_reg_t load;
} timg_hwtimer_reg_t;
typedef struct {
volatile timg_hwtimer_reg_t hw_timer[1];
uint32_t reserved_024[9];
volatile timg_wdtconfig0_reg_t wdtconfig0;
volatile timg_wdtconfig1_reg_t wdtconfig1;
volatile timg_wdtconfig2_reg_t wdtconfig2;
volatile timg_wdtconfig3_reg_t wdtconfig3;
volatile timg_wdtconfig4_reg_t wdtconfig4;
volatile timg_wdtconfig5_reg_t wdtconfig5;
volatile timg_wdtfeed_reg_t wdtfeed;
volatile timg_wdtwprotect_reg_t wdtwprotect;
volatile timg_rtccalicfg_reg_t rtccalicfg;
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
volatile timg_int_ena_timers_reg_t int_ena_timers;
volatile timg_int_raw_timers_reg_t int_raw_timers;
volatile timg_int_st_timers_reg_t int_st_timers;
volatile timg_int_clr_timers_reg_t int_clr_timers;
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
uint32_t reserved_084[29];
volatile timg_ntimers_date_reg_t ntimers_date;
volatile timg_regclk_reg_t regclk;
} timg_dev_t;
extern timg_dev_t TIMERG0;
extern timg_dev_t TIMERG1;
#ifndef __cplusplus
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SOC_TIMG_STRUCT_H_ */

88
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/twai_struct.h
View File

@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@ -61,97 +61,99 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
uint32_t reserved1: 1; /* Internal Reserved */
uint32_t reserved13: 1; /* Internal Reserved */
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@ -159,45 +161,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");

44
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/uart_pins.h Normal file
View File

@ -0,0 +1,44 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 20
#define U0TXD_GPIO_NUM 21
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/uart_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte; /*a*/

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/uhci_struct.h
View File

@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/

2
tools/sdk/esp32c3/include/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
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@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct usb_serial_jtag_dev_s {
union {
struct {
uint32_t rdwr_byte : 32; /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */

2
tools/sdk/esp32c3/include/soc/include/soc/adc_periph.h
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@ -18,7 +18,7 @@
#include "soc/soc_caps.h"
#include "soc/syscon_struct.h"
#if SOC_ADC_SUPPORT_RTC_CTRL
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_reg.h"
#include "soc/sens_struct.h"
#endif

27
tools/sdk/esp32c3/include/soc/include/soc/i2s_periph.h
View File

@ -1,4 +1,4 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,16 +27,21 @@ extern "C" {
Stores a bunch of per-I2S-peripheral data.
*/
typedef struct {
const uint8_t o_bck_in_sig;
const uint8_t o_ws_in_sig;
const uint8_t o_bck_out_sig;
const uint8_t o_ws_out_sig;
const uint8_t o_data_out_sig;
const uint8_t i_bck_in_sig;
const uint8_t i_ws_in_sig;
const uint8_t i_bck_out_sig;
const uint8_t i_ws_out_sig;
const uint8_t i_data_in_sig;
const uint8_t mck_out_sig;
const uint8_t m_tx_bck_sig;
const uint8_t m_rx_bck_sig;
const uint8_t m_tx_ws_sig;
const uint8_t m_rx_ws_sig;
const uint8_t s_tx_bck_sig;
const uint8_t s_rx_bck_sig;
const uint8_t s_tx_ws_sig;
const uint8_t s_rx_ws_sig;
const uint8_t data_out_sig;
const uint8_t data_in_sig;
const uint8_t irq;
const periph_module_t module;
} i2s_signal_conn_t;

14
tools/sdk/esp32c3/include/soc/include/soc/lcd_periph.h
View File

@ -21,6 +21,7 @@
extern "C" {
#endif
#if SOC_LCDCAM_SUPPORTED
typedef struct {
struct {
const periph_module_t module;
@ -41,6 +42,19 @@ typedef struct {
} panels[SOC_LCD_RGB_PANELS];
} lcd_signal_conn_t;
#endif // SOC_LCDCAM_SUPPORTED
#if SOC_I2S_LCD_I80_VARIANT
typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_LCD_I80_BUS_WIDTH];
const int wr_sig;
} buses[SOC_LCD_I80_BUSES];
} lcd_signal_conn_t;
#endif // SOC_I2S_LCD_I80_VARIANT
extern const lcd_signal_conn_t lcd_periph_signals;
#ifdef __cplusplus

4
tools/sdk/esp32c3/include/soc/include/soc/mcpwm_periph.h
View File

@ -34,13 +34,13 @@ typedef struct {
} operators[SOC_MCPWM_OPERATORS_PER_GROUP];
struct {
const uint32_t fault_sig;
} detectors[SOC_MCPWM_FAULT_DETECTORS_PER_GROUP];
} gpio_faults[SOC_MCPWM_GPIO_FAULTS_PER_GROUP];
struct {
const uint32_t cap_sig;
} captures[SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER];
struct {
const uint32_t sync_sig;
} ext_syncers[SOC_MCPWM_EXT_SYNCERS_PER_GROUP];
} gpio_synchros[SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP];
} groups[SOC_MCPWM_GROUPS];
} mcpwm_signal_conn_t;

16
tools/sdk/esp32c3/include/soc/include/soc/pcnt_periph.h
View File

@ -1,4 +1,4 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -27,12 +27,14 @@ extern "C" {
typedef struct {
struct {
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} channels[SOC_PCNT_UNIT_CHANNEL_NUM];
} units[SOC_PCNT_UNIT_NUM];
const uint32_t irq;
const periph_module_t module;
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} channels[SOC_PCNT_CHANNELS_PER_UNIT];
} units[SOC_PCNT_UNITS_PER_GROUP];
const uint32_t irq;
const periph_module_t module;
} groups[SOC_PCNT_GROUPS];
} pcnt_signal_conn_t;
extern const pcnt_signal_conn_t pcnt_periph_signals;

2
tools/sdk/esp32c3/include/soc/include/soc/rtc_io_periph.h
View File

@ -27,7 +27,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#if SOC_ADC_SUPPORT_RTC_CTRL
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_struct.h"
#endif

3
tools/sdk/esp32c3/include/soc/include/soc/sdio_slave_periph.h
View File

@ -15,9 +15,12 @@
#pragma once
#include <stdint.h>
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#ifdef SOC_SDIO_SLAVE_SUPPORTED
#include "soc/slc_reg.h"
#include "soc/slc_struct.h"
#endif
#include "soc/host_reg.h"
#include "soc/host_struct.h"
#include "soc/hinf_reg.h"

17
tools/sdk/esp32c3/include/soc/include/soc/spi_periph.h
View File

@ -30,8 +30,7 @@
#endif
#ifdef __cplusplus
extern "C"
{
extern "C" {
#endif
#if CONFIG_IDF_TARGET_ESP32S2
@ -41,8 +40,6 @@ extern "C"
#define SPI_FWRITE_QIO 0
#endif
/*
Stores a bunch of per-spi-peripheral data.
*/
@ -53,10 +50,22 @@ typedef struct {
const uint8_t spiq_out;
const uint8_t spiwp_out;
const uint8_t spihd_out;
#if SOC_SPI_SUPPORT_OCT
const uint8_t spid4_out;
const uint8_t spid5_out;
const uint8_t spid6_out;
const uint8_t spid7_out;
#endif // SOC_SPI_SUPPORT_OCT
const uint8_t spid_in; //GPIO mux input signals
const uint8_t spiq_in;
const uint8_t spiwp_in;
const uint8_t spihd_in;
#if SOC_SPI_SUPPORT_OCT
const uint8_t spid4_in;
const uint8_t spid5_in;
const uint8_t spid6_in;
const uint8_t spid7_in;
#endif // SOC_SPI_SUPPORT_OCT
const uint8_t spics_out[3]; // /CS GPIO output mux signals
const uint8_t spics_in;
const uint8_t spidqs_out;

32
tools/sdk/esp32c3/include/soc/include/soc/uart_periph.h
View File

@ -18,16 +18,40 @@
#include "soc/uart_struct.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "soc/uart_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_TX_PIN_IDX (0)
#define SOC_UART_RX_PIN_IDX (1)
#define SOC_UART_RTS_PIN_IDX (2)
#define SOC_UART_CTS_PIN_IDX (3)
/**
* @brief Macro that can be used to retrieve the signal of a certain pin for a
* certain UART.
*/
#define UART_PERIPH_SIGNAL(IDX, PIN) (uart_periph_signal[(IDX)].pins[(PIN)].signal)
typedef struct {
const uint8_t tx_sig;
const uint8_t rx_sig;
const uint8_t rts_sig;
const uint8_t cts_sig;
/* Default GPIO number for this UART pin in the IOMUX.
* This value can be -1 if there is no default GPIO for a pin.
* For example, ESP32-C3 doesn't have any default GPIO for
* U0CTS and U0RTS. */
int32_t default_gpio : 15;
/* Func which should be assigned to the GPIO to be used as UART */
int32_t iomux_func : 4;
/* Marks if the current UART pin is input (or not) */
uint32_t input : 1;
/* Signal in the GPIO signal map. */
uint32_t signal : 12;
} uart_periph_sig_t;
typedef struct {
const uart_periph_sig_t pins[SOC_UART_PINS_COUNT];
const uint8_t irq;
const periph_module_t module;
} uart_signal_conn_t;

35
tools/sdk/esp32c3/include/soc/include/soc/usb_phy_periph.h Normal file
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
Stores a bunch of USB-peripheral data.
*/
typedef struct {
const uint8_t extphy_vp_in;
const uint8_t extphy_vm_in;
const uint8_t extphy_rcv_in;
const uint8_t extphy_oen_out;
const uint8_t extphy_vpo_out;
const uint8_t extphy_vmo_out;
const uint8_t extphy_suspend_in;
const uint8_t extphy_speed_in;
const periph_module_t module;
} usb_phy_signal_conn_t;
extern const usb_phy_signal_conn_t usb_phy_periph_signal;
#ifdef __cplusplus
}
#endif