diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c index 78fc5c8e..ac70c532 100644 --- a/cores/esp32/esp32-hal-cpu.c +++ b/cores/esp32/esp32-hal-cpu.c @@ -30,7 +30,6 @@ #ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ #if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 #include "esp32/rom/rtc.h" -const uint32_t MHZ = 1000000; #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/rtc.h" #else diff --git a/platform.txt b/platform.txt index 88510ff2..8dffa1b2 100644 --- a/platform.txt +++ b/platform.txt @@ -22,8 +22,8 @@ compiler.prefix=xtensa-{build.mcu}-elf- # # ESP32 Support Start # -compiler.cpreprocessor.flags.esp32=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.3-dev-1197-g8bc19ba89-dirty" -DESP_PLATFORM "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/src/esp32" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/hal/esp32/include" "-I{compiler.sdk.path}/include/hal/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32/include" "-I{compiler.sdk.path}/include/esp32/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/soc/soc/esp32" "-I{compiler.sdk.path}/include/soc/soc/esp32/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/bt/include" "-I{compiler.sdk.path}/include/bt/common/osi/include" "-I{compiler.sdk.path}/include/bt/host/bluedroid/api/include/api" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/unity/unity/extras/fixture/src" "-I{compiler.sdk.path}/include/cmock/CMock/src" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/esp-face/face_detection/include" "-I{compiler.sdk.path}/include/esp-face/face_recognition/include" "-I{compiler.sdk.path}/include/esp-face/object_detection/include" "-I{compiler.sdk.path}/include/esp-face/image_util/include" "-I{compiler.sdk.path}/include/esp-face/pose_estimation/include" "-I{compiler.sdk.path}/include/esp-face/lib/include" "-I{compiler.sdk.path}/include/esp32-camera/driver/include" "-I{compiler.sdk.path}/include/esp32-camera/conversions/include" "-I{compiler.sdk.path}/include/fb_gfx/include" -compiler.c.elf.libs.esp32=-lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lbt -lcbor -lunity -lcmock -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lspiffs -lulp -lwifi_provisioning -lesp-face -lesp32-camera -lfb_gfx -lasio -lcbor -lcmock -lunity -lcoap -lesp_gdbstub -lesp_hid -lesp_local_ctrl -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lesp-face -lpe -lfd -lfr -ldetection_cat_face -ldetection -ldl -lesp32-camera -lfb_gfx -lbt -lbtdm_app -lesp_adc_cal -lmdns -lconsole -lfatfs -lwear_levelling -lopenssl -lspiffs -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxt_hal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc +compiler.cpreprocessor.flags.esp32=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.3-dev-1472-g0b71a0a46-dirty" -DESP_PLATFORM "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/soc/src/esp32" "-I{compiler.sdk.path}/include/hal/esp32/include" "-I{compiler.sdk.path}/include/hal/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32/include" "-I{compiler.sdk.path}/include/esp32/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/esp_pm/include" "-I{compiler.sdk.path}/include/soc/soc/esp32" "-I{compiler.sdk.path}/include/soc/soc/esp32/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/bt/include" "-I{compiler.sdk.path}/include/bt/common/osi/include" "-I{compiler.sdk.path}/include/bt/host/bluedroid/api/include/api" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/unity/unity/extras/fixture/src" "-I{compiler.sdk.path}/include/cmock/CMock/src" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/esp-face/face_detection/include" "-I{compiler.sdk.path}/include/esp-face/face_recognition/include" "-I{compiler.sdk.path}/include/esp-face/object_detection/include" "-I{compiler.sdk.path}/include/esp-face/image_util/include" "-I{compiler.sdk.path}/include/esp-face/pose_estimation/include" "-I{compiler.sdk.path}/include/esp-face/lib/include" "-I{compiler.sdk.path}/include/esp32-camera/driver/include" "-I{compiler.sdk.path}/include/esp32-camera/conversions/include" "-I{compiler.sdk.path}/include/fb_gfx/include" +compiler.c.elf.libs.esp32=-lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lbt -lcbor -lunity -lcmock -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lspiffs -lulp -lwifi_provisioning -lesp-face -lesp32-camera -lfb_gfx -lasio -lcbor -lcmock -lunity -lcoap -lesp_gdbstub -lesp_hid -lesp_local_ctrl -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lesp-face -lpe -lfd -lfr -ldetection_cat_face -ldetection -ldl -lesp32-camera -lfb_gfx -lbt -lbtdm_app -lesp_adc_cal -lmdns -lconsole -lfatfs -lwear_levelling -lopenssl -lspiffs -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxt_hal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc compiler.c.flags.esp32=-mlongcalls -Wno-frame-address -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -O2 -fstack-protector -std=gnu99 -Wno-old-style-declaration -MMD -c compiler.cpp.flags.esp32=-mlongcalls -Wno-frame-address -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -O2 -fstack-protector -std=gnu++11 -fexceptions -fno-rtti -MMD -c compiler.S.flags.esp32=-ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -O2 -fstack-protector -x assembler-with-cpp -MMD -c @@ -37,8 +37,8 @@ build.extra_flags.esp32=-DARDUINO_SERIAL_PORT=0 # # ESP32S2 Support Start # -compiler.cpreprocessor.flags.esp32s2=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.3-dev-1197-g8bc19ba89-dirty" -DESP_PLATFORM "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/src/esp32s2" "-I{compiler.sdk.path}/include/soc/src/esp32s2/include" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/hal/esp32s2/include" "-I{compiler.sdk.path}/include/hal/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32s2/include" "-I{compiler.sdk.path}/include/esp32s2/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32s2/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32s2/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/soc/soc/esp32s2" "-I{compiler.sdk.path}/include/soc/soc/esp32s2/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32s2/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/unity/unity/extras/fixture/src" "-I{compiler.sdk.path}/include/cmock/CMock/src" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/esp_https_server/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32s2" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/freertos/include/freertos" "-I{compiler.sdk.path}/include/tinyusb/tinyusb/src" "-I{compiler.sdk.path}/include/tinyusb/additions/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/esp-face/face_detection/include" "-I{compiler.sdk.path}/include/esp-face/face_recognition/include" "-I{compiler.sdk.path}/include/esp-face/object_detection/include" "-I{compiler.sdk.path}/include/esp-face/image_util/include" "-I{compiler.sdk.path}/include/esp-face/pose_estimation/include" "-I{compiler.sdk.path}/include/esp-face/lib/include" "-I{compiler.sdk.path}/include/fb_gfx/include" -compiler.c.elf.libs.esp32s2=-lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lcbor -lunity -lcmock -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lperfmon -lspiffs -lulp -lwifi_provisioning -lesp-face -lfb_gfx -lasio -lcbor -lcmock -lunity -lcoap -lesp_gdbstub -lesp_hid -lesp_local_ctrl -lesp_https_server -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lperfmon -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lesp-face -lpe -lfd -lfr -ldetection_cat_face -ldetection -ldl -lfb_gfx -lesp_adc_cal -lmdns -lconsole -lfatfs -lwear_levelling -lopenssl -lspiffs -ltinyusb -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxt_hal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc +compiler.cpreprocessor.flags.esp32s2=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.3-dev-1472-g0b71a0a46-dirty" -DESP_PLATFORM "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/soc/src/esp32s2" "-I{compiler.sdk.path}/include/soc/src/esp32s2/include" "-I{compiler.sdk.path}/include/hal/esp32s2/include" "-I{compiler.sdk.path}/include/hal/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32s2/include" "-I{compiler.sdk.path}/include/esp32s2/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32s2/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32s2/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/esp_pm/include" "-I{compiler.sdk.path}/include/soc/soc/esp32s2" "-I{compiler.sdk.path}/include/soc/soc/esp32s2/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32s2/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/unity/unity/extras/fixture/src" "-I{compiler.sdk.path}/include/cmock/CMock/src" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/esp_https_server/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32s2" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/freertos/include/freertos" "-I{compiler.sdk.path}/include/tinyusb/tinyusb/src" "-I{compiler.sdk.path}/include/tinyusb/additions/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/esp-face/face_detection/include" "-I{compiler.sdk.path}/include/esp-face/face_recognition/include" "-I{compiler.sdk.path}/include/esp-face/object_detection/include" "-I{compiler.sdk.path}/include/esp-face/image_util/include" "-I{compiler.sdk.path}/include/esp-face/pose_estimation/include" "-I{compiler.sdk.path}/include/esp-face/lib/include" "-I{compiler.sdk.path}/include/fb_gfx/include" +compiler.c.elf.libs.esp32s2=-lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lcbor -lunity -lcmock -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lperfmon -lspiffs -lulp -lwifi_provisioning -lesp-face -lfb_gfx -lasio -lcbor -lcmock -lunity -lcoap -lesp_gdbstub -lesp_hid -lesp_local_ctrl -lesp_https_server -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lperfmon -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lesp-face -lpe -lfd -lfr -ldetection_cat_face -ldetection -ldl -lfb_gfx -lesp_adc_cal -lmdns -lconsole -lfatfs -lwear_levelling -lopenssl -lspiffs -ltinyusb -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lesp_pm -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lhal -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lsdmmc -lesp_serial_slave_link -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxt_hal -lesp32s2 -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc compiler.c.flags.esp32s2=-mlongcalls -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -O2 -fstack-protector -std=gnu99 -Wno-old-style-declaration -MMD -c compiler.cpp.flags.esp32s2=-mlongcalls -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -O2 -fstack-protector -std=gnu++11 -fexceptions -fno-rtti -MMD -c compiler.S.flags.esp32s2=-ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -O2 -fstack-protector -x assembler-with-cpp -MMD -c diff --git a/tools/esptool.py b/tools/esptool.py index 2eecc7e8..9a908433 100755 --- a/tools/esptool.py +++ b/tools/esptool.py @@ -60,6 +60,13 @@ except ImportError: print("The installed version (%s) of pyserial appears to be too old for esptool.py (Python interpreter %s). " "Check the README for installation instructions." % (sys.VERSION, sys.executable)) raise +except Exception: + if sys.platform == "darwin": + # swallow the exception, this is a known issue in pyserial+macOS Big Sur preview ref https://github.com/espressif/esptool/issues/540 + list_ports = None + else: + raise + __version__ = "3.0-dev" @@ -96,7 +103,7 @@ def check_supported_function(func, check_func): bootloader function to check if it's supported. This is used to capture the multidimensional differences in - functionality between the ESP8266 & ESP32/32S2 ROM loaders, and the + functionality between the ESP8266 & ESP32/32S2/32S3 ROM loaders, and the software stub that runs on both. Not possible to do this cleanly via inheritance alone. """ @@ -115,7 +122,7 @@ def stub_function_only(func): def stub_and_esp32_function_only(func): - """ Attribute for a function only supported by software stubs or ESP32/32S2 ROM """ + """ Attribute for a function only supported by software stubs or ESP32/32S2/32S3 ROM """ return check_supported_function(func, lambda o: o.IS_STUB or isinstance(o, ESP32ROM)) @@ -201,7 +208,7 @@ class ESPLoader(object): ESP_FLASH_DEFL_END = 0x12 ESP_SPI_FLASH_MD5 = 0x13 - # Commands supported by ESP32-S2 ROM bootloader only + # Commands supported by ESP32-S2/S3 ROM bootloader only ESP_GET_SECURITY_INFO = 0x14 # Some commands supported by stub only @@ -233,8 +240,9 @@ class ESPLoader(object): # Flash sector size, minimum unit of erase. FLASH_SECTOR_SIZE = 0x1000 - UART_DATE_REG_ADDR = 0x60000078 # used to differentiate ESP8266 vs ESP32* - UART_DATE_REG2_ADDR = 0x3f400074 # used to differentiate ESP32-S2 vs other models + UART_DATE_REG_ADDR = 0x60000078 + + CHIP_DETECT_MAGIC_REG_ADDR = 0x40001000 # This ROM address has a different value on each chip model UART_CLKDIV_MASK = 0xFFFFF @@ -302,11 +310,10 @@ class ESPLoader(object): try: print('Detecting chip type...', end='') sys.stdout.flush() - date_reg = detect_port.read_reg(ESPLoader.UART_DATE_REG_ADDR) - date_reg2 = detect_port.read_reg(ESPLoader.UART_DATE_REG2_ADDR) + chip_magic_value = detect_port.read_reg(ESPLoader.CHIP_DETECT_MAGIC_REG_ADDR) - for cls in [ESP8266ROM, ESP32ROM, ESP32S2ROM]: - if date_reg == cls.DATE_REG_VALUE and (cls.DATE_REG2_VALUE is None or date_reg2 == cls.DATE_REG2_VALUE): + for cls in [ESP8266ROM, ESP32ROM, ESP32S2ROM, ESP32S3BETA2ROM]: + if chip_magic_value == cls.CHIP_DETECT_MAGIC_VALUE: # don't connect a second time inst = cls(detect_port._port, baud, trace_enabled=trace_enabled) inst._post_connect() @@ -317,7 +324,7 @@ class ESPLoader(object): "autodetection will not work. Need to manually specify the chip.") finally: print('') # end line - raise FatalError("Unexpected UART datecode value 0x%08x. Failed to autodetect chip type." % (date_reg)) + raise FatalError("Unexpected CHIP magic value 0x%08x. Failed to autodetect chip type." % (chip_magic_value)) """ Read a SLIP packet from the serial port """ def read(self): @@ -524,17 +531,16 @@ class ESPLoader(object): if not detecting: try: # check the date code registers match what we expect to see - date_reg = self.read_reg(self.UART_DATE_REG_ADDR) - date_reg2 = self.read_reg(self.UART_DATE_REG2_ADDR) - if date_reg != self.DATE_REG_VALUE or (self.DATE_REG2_VALUE is not None and date_reg2 != self.DATE_REG2_VALUE): + chip_magic_value = self.read_reg(ESPLoader.CHIP_DETECT_MAGIC_REG_ADDR) + if chip_magic_value != self.CHIP_DETECT_MAGIC_VALUE: actually = None - for cls in [ESP8266ROM, ESP32ROM, ESP32S2ROM]: - if date_reg == cls.DATE_REG_VALUE and (cls.DATE_REG2_VALUE is None or date_reg2 == cls.DATE_REG2_VALUE): + for cls in [ESP8266ROM, ESP32ROM, ESP32S2ROM, ESP32S3BETA2ROM]: + if chip_magic_value == cls.CHIP_DETECT_MAGIC_VALUE: actually = cls break if actually is None: - print(("WARNING: This chip doesn't appear to be a %s (date codes 0x%08x:0x%08x). " + - "Probably it is unsupported by this version of esptool.") % (self.CHIP_NAME, date_reg, date_reg2)) + print(("WARNING: This chip doesn't appear to be a %s (chip magic value 0x%08x). " + + "Probably it is unsupported by this version of esptool.") % (self.CHIP_NAME, chip_magic_value)) else: raise FatalError("This chip is %s not %s. Wrong --chip argument?" % (actually.CHIP_NAME, self.CHIP_NAME)) except UnsupportedCommandError: @@ -635,7 +641,7 @@ class ESPLoader(object): timeout = timeout_per_mb(ERASE_REGION_TIMEOUT_PER_MB, size) # ROM performs the erase up front params = struct.pack('II", mac1, mac0)[2:] + try: + return tuple(ord(b) for b in bitstring) + except TypeError: # Python 3, bitstring elements are already bytes + return tuple(bitstring) + + class ESP32StubLoader(ESP32ROM): """ Access class for ESP32 stub loader, runs on top of ROM. """ @@ -1705,7 +1773,7 @@ ESP32ROM.STUB_CLASS = ESP32StubLoader class ESP32S2StubLoader(ESP32S2ROM): """ Access class for ESP32-S2 stub loader, runs on top of ROM. - (Basically the same as ESP2StubLoader, but different base class. + (Basically the same as ESP32StubLoader, but different base class. Can possibly be made into a mixin.) """ FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c @@ -1726,6 +1794,26 @@ class ESP32S2StubLoader(ESP32S2ROM): ESP32S2ROM.STUB_CLASS = ESP32S2StubLoader +class ESP32S3BETA2StubLoader(ESP32S3BETA2ROM): + """ Access class for ESP32S3 stub loader, runs on top of ROM. + + (Basically the same as ESP32StubLoader, but different base class. + Can possibly be made into a mixin.) + """ + FLASH_WRITE_SIZE = 0x4000 # matches MAX_WRITE_BLOCK in stub_loader.c + STATUS_BYTES_LENGTH = 2 # same as ESP8266, different to ESP32 ROM + IS_STUB = True + + def __init__(self, rom_loader): + self.secure_download_mode = rom_loader.secure_download_mode + self._port = rom_loader._port + self._trace_enabled = rom_loader._trace_enabled + self.flush_input() # resets _slip_reader + + +ESP32S3BETA2ROM.STUB_CLASS = ESP32S3BETA2StubLoader + + class ESPBOOTLOADER(object): """ These are constants related to software ESP bootloader, working with 'v2' image files """ @@ -1750,6 +1838,8 @@ def LoadFirmwareImage(chip, filename): return ESP32FirmwareImage(f) elif chip == "esp32s2": return ESP32S2FirmwareImage(f) + elif chip == "esp32s3beta2": + return ESP32S3BETA2FirmwareImage(f) else: # Otherwise, ESP8266 so look at magic to determine the image type magic = ord(f.read(1)) f.seek(0) @@ -2283,7 +2373,7 @@ class ESP32FirmwareImage(BaseFirmwareImage): chip_id = fields[4] if chip_id != self.ROM_LOADER.IMAGE_CHIP_ID: print(("Unexpected chip id in image. Expected %d but value was %d. " + - "Is this image for a different chip model?") % (self.ROM_LOADER.IMAGE_CHIP_ID, chip_id)) + "Is this image for a different chip model?") % (self.ROM_LOADER.IMAGE_CHIP_ID, chip_id)) # reserved fields in the middle should all be zero if any(f for f in fields[6:-1] if f != 0): @@ -2325,6 +2415,14 @@ class ESP32S2FirmwareImage(ESP32FirmwareImage): ESP32S2ROM.BOOTLOADER_IMAGE = ESP32S2FirmwareImage +class ESP32S3BETA2FirmwareImage(ESP32FirmwareImage): + """ ESP32S3 Firmware Image almost exactly the same as ESP32FirmwareImage """ + ROM_LOADER = ESP32S3BETA2ROM + + +ESP32S3BETA2ROM.BOOTLOADER_IMAGE = ESP32S3BETA2FirmwareImage + + class ELFFile(object): SEC_TYPE_PROGBITS = 0x01 SEC_TYPE_STRTAB = 0x03 @@ -2888,6 +2986,11 @@ def elf2image(args): if args.secure_pad_v2: image.secure_pad = '2' image.min_rev = 0 + elif args.chip == 'esp32s3beta2': + image = ESP32S3BETA2FirmwareImage() + if args.secure_pad_v2: + image.secure_pad = '2' + image.min_rev = 0 elif args.version == '1': # ESP8266 image = ESP8266ROMFirmwareImage() else: @@ -3052,7 +3155,7 @@ def main(custom_commandline=None): parser.add_argument('--chip', '-c', help='Target chip type', type=lambda c: c.lower().replace('-', ''), # support ESP32-S2, etc. - choices=['auto', 'esp8266', 'esp32', 'esp32s2'], + choices=['auto', 'esp8266', 'esp32', 'esp32s2', 'esp32s3beta2'], default=os.environ.get('ESPTOOL_CHIP', 'auto')) parser.add_argument( @@ -3309,6 +3412,9 @@ def main(custom_commandline=None): initial_baud = args.baud if args.port is None: + if list_ports is None: + raise FatalError("Listing all serial ports is currently not available on this operating system version. " + "Specify the port when running esptool.py") ser_list = sorted(ports.device for ports in list_ports.comports()) print("Found %d serial ports" % len(ser_list)) else: @@ -3325,6 +3431,7 @@ def main(custom_commandline=None): 'esp8266': ESP8266ROM, 'esp32': ESP32ROM, 'esp32s2': ESP32S2ROM, + 'esp32s3beta2': ESP32S3BETA2ROM, }[args.chip] esp = chip_class(each_port, initial_baud, args.trace) esp.connect(args.before, args.connect_attempts) @@ -3600,73 +3707,105 @@ RR0zr38KpBPT0CuujNa9/rr3Puq141476bXTXtv02rbb1j14dKd/4Dc6Pf27G/Tp5Tcf/6k/+op2dE0e rjvjrfmNm36jM+wdv7HnNzqmSYcg73uSpgdn3mvbXruKV+wS/Tfu4r9aCvxRKfFHpcgflTJ/VApd1b7mj1ZtbNPtwAnuPCp+El8lcXd88518EgR0O22VjrtwpZts9vpWcjyJVGLMp/8HHp1i9w==\ """))) ESP32ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b""" -eNqNWntX3cYR/ypCxrziNLuSrrSibg2YXMD2qYHEGKf09Egrqc6pywFyXa4J/u7deWlXukrSPwTSajU7Mzvzm8feXzcX7XKxuRvVm1dLZdylrpZd9uJqqW3wADf9Q5VdLdvaPTQwzb/J9+F2zd1X7uqullZFMAJU\ -E/euKwfDW+5PFkWLq2XplmoT95i7a+ZXUwq+mtFXRrv/+YCCYwVoO3aMIe4rGFOOZKu8OKqOO2DBjRZuKtDIgA5wqgcES5qmGzeqAqlNxKJ3JhTVcQ7fNyOmHDOOA5hp1PrFMb3FmdX/M3O8OlxaRf1ORKM9wcsI\ -Ry2oy4p4NZFUlrThF2ZJkas6UHA54rBMPtKNH0FVX3xZFcVRfHSjCUgTqyiirZkSR6k94rcVZt08ty9l5Vlpm0BxdsxWORJoyNX0mnxpf2+U/9oqtmggIBdOzKKReSM3Sczy5S/BakES4yVpK3pbzUTB5oD2AWbB\ -f52diSEWbMi1iYGnlLzK2vSM1IlErVh6vOfmav3UjafBzim+B7GQQjA43PfUvWmSwZtzO9jlS5h18ZnY3kthvDww8auXJ/FQuaUKFKfMHt+ZQLe4bBY+7+3J3TEN4zdl1pMSW661KDVitwZ1VrwvZf4TwUWIDGVw\ -34NByVtsQjuuk+3Ah1mTJVuyQdN3shovZ6lov7TbTlsSs5bHeqo2ueQvnAGUdQhVyYm4lKeLhm6DnWN6ZQEcH/GEwssm95UmG8PxSixYmEBYqYPppiCU1RUBIPi+Us5bW0Mv4UWr8eVi1WdC+7kOdVheLeZCbTh+\ -PfxqQew3AcuGHGExQBvW3tCBT7+F2MCQ4f7UGBIus9PUsrelYLCX4FQ//XB6dbXPUjIFsJpey+bQDeS8BehQ66QCdNXkKUPoCJHAP3UGMqYAbHUSsd2xH4XxxtjdmKzPZts/bsGHu/E2/NvKQFXOmca4aIagjg5y\ -Q0Gxq14cr6P8MD8mTQC6KMdq0zJ7DQGbCcDSs/QX2A3EnIQU0Yr6NZljlXgzh3EtUKFJG20SeFfiLVDcZhTQKryLwvHkZ/G6Nd4TIN2t4leoyEo9YTAbB2SAAIFnJXABZAwHMJRKiYTHMAHks/sS0pIwJOOI3jbI\ -IbhfFe+k6vk+R86kPN6+ZII2RHpksEynAs4z4qGPdKADpqB4vxL2S5jW0ibA+6ZmjdQTGpE5li08HdLGb4WmYTrF79BpeE62OmdVJpJkVzK1JPCwxD/rOmYfqjm4ATdd9luZjdxfhg+PhBVq5qy+MX9i+wcI64ch\ -IoK87iFfWyMeGs3GG2RbA9cM4O3MR4oa3ef0paNoGw7cskNBQAkpdXbHT67Z/VZYSMcfvoopnF5YShyrIADUwdeAx1XF+N9ObCCMl0FqUMs3T8U8v2XzyIc5j1IITva3N9ibh2U5rJ3gABUEDpNGvN+Mmytfm98z\ -rk/htn8MH27Ch0X4sAwfYC/+xajZqN7tYK2P7IBrlU9twzRXV90JaQgDo6n9BqDjZ8+urj8AoYOOp0xaw5kvJFDenvo7CGez905HhqzJ5mmgvZznTzioz4Bvg41GJh/OPvC8fD2YjEre+4XUrhngpS4iA71ZioEX\ -kFBJDKvbqRjmZla3NNiXELNzDIsPt4w+dbBVNdDUaJpRK4hyA9JFgYMEYtez8bIP8cNhQQjcZDSpQd2cLqbFMgXE7ZpoyhYo2r1rkHD+ickkoQbhzZZXXbMSwy84uWopi6oCw1b5JyJT1/DiV7bAglN+cJT8+6vF\ -T6AQ+OK1gOI7Lj0REh6pgoYpkGHYsvse1j7fANoF6UYl70kXVUn+LrlI3XibFYwo7TRGlMUURoQp0TPQFJqh+uMYgHPsi7fH+yeUE3Ef4JGyR1UDLmdMAx6U7yJgdZC9GBVXE5UZ2J4ZhIi9Qek4zk2RJQLi/sEZ\ -4mZAIQvaF5JpCAuBGFJUMpHaVzePH3nplrHmUlLMvU87GJ1MwkFKO9SgO2vp7g39A5OeMRlA1JLEWVJ0U5QPuWh22WPYG4rsgGHuE831pyR9YORxhfDEyY76rYABXyGIBDn4MDAADiav4yKRCvU12bvVEVuL4u8R\ -ado1hqV2n5y163aejPsode9cbrZpyaHQIqyPEmp2UAesrxiho29RnnOyaKWHHSRnv6exzzW3OavXpLopXG3KCfUICAekE9qmuiL3sdkeVL8QPm0S1vERtcQgUVXsZtOwQhglftboV7xkMIhww5qCrLvSIaChmzYT\ -3NdNiNI76RrBYgd23STfDMSCdDW/W5E2FXH6UQgz6cE+yHzA6Z3GSZs4qO/OrhYfzjaodFdQRNrinijodi7cyafpHd9gf+gQCNwcRh3cJMdxvyik6tnJGXtXb55s4To5OMMKY5Ri6IkUA6SBiE5WTLEJ0hRKR36f\ -LRfgSoSImxtAjSOCal2EKz8FkxhmPOB44Cs2nc6E1ARKgxs2OH43UDKaKfYBCuYuJ6aUui//1gEKJXOSBi0rv4+6QrKMWxk8goU6xMJk/l5W3ICb7ohJECh17/0yFeLlPPaKLEfM2JzvHTO4xD0TqxAU5xQ6FBRp\ -A/5LT7IekJwL1HFs44najhZW+QGtutPRphA3b2X61QIZYpCBRA/SKGgTDXXJ7QGQQ1JJcHK9stx7ebl+FA7/py8o+jRIak5w/KGuElGUDqcpmqKL9WBQy6Am5lQ2DHf9xHTM6J+Del4RKA9FPuYOMerjjmZ13dyX\ -/+j/xcX6Fljr3VQ9viCYw61sQsY2qMmH3FryFNjGElVzAIaU3MHf9AbgIvIdtTq7IFNAxJtRduL87pCbcNy0wgTPBEEbLqjmje5WsrddCNl3nDxCblpxauDgfBO4vw0q177rdsEwgtCVBcsoKm2M/ufKSjtU5Rp9\ -Ij28e/H2Y85/ae17SDIy3tJ0uDzLcTEpR7kqh5sIOaJjFNtAd4Ixsge42Y/hZs9/GO0VpJUgk8p/DEgoza+IxH+lZRMTzxXeQIes1n0K0ZfTUzSUaLrUiJRoCNkpbHQkbCdHtP8Dt6oNRHtoh4s1YedX4FZ9Jju0\ -+cfAcgEc6+zZMcQKvcPaDI2d1qpkLTTgZeJXu1kQCAFKtdBgrzCEY7AjA4U2a6s/NAfgX998WSe6JVhH+hV1kf/dd5URgVqPQI7cItyxHHuM1/B3+QGIxwccUyBFLLnHHAaRUj1Qw4nyAfF1SBzNuCVTUUcBLsz8\ -DbWucRyPUNTRDrXz+u7NTKIi9+thrtZ7cBPJq9zLoyheshVn/ZSCQylWfOow6oXhKA7RuMTGPGLJSznpy6gn0gN2Io44VBi3AkqTybi54H4ldv4OcV/BsPPnQQ1gaU7PPBsWom0mSM1I10Li0BnwPbANCxl2jU02\ -PKLRDEgjfHSkr3vrnA9AdeNQVvhOqo6YKzk5wZCsb9iuCvqcY2tWA0/bwewpXiZ9KvXF4zFuCYf9Q4nUZspFMP4+CeCC2JeV5hFvFjZ80CPOlzEH9myfWvFdi0t/ZeFyMjw50cEUv/Ub0ODRV2/5HFmgw4fhK4VI\ -+RlubmgZvaKI/KL0esTyppVXJWdI5uj58R7nkFkgKzbLq699g7zrjzMeyABL8/Pre1z4mjnrHqCPcUP1s1VHBbGjOWsBBUDFDj7X8jElqMBUPkXXRUdYjUcMEOlr0knv6+b4anH+s4cSLE/aPcJBk8qrHglJITdy\ -+l1CJuEAzEixYCi1aFVwkGbsVJaqxmZ4QeZjR0XAsqNkf/8IHag7lLCxRCtrPFwUaMEbmc8cMZK37NBd75+b91xL4DRIh1G7qDHUWv9+vusdBA8k2lEYahJk7q08Zvj4y5yL43aYVJFrA1ohYoNBQ0iyfKJSm7FO\ -1miP0QE05yztuHiEz1z5fAgFAVSNGmEPa8hoPSIUBnTGxWX/oK1kue8MJ51jSMDNSvngrud4oqRohmI2GLyBFTm49nHdxC036cH8G+O/rCUypAdhmURsYmSo64imoQkzg5aPONvZre81YD3c/kHdBQf4TYgFeJqh\ -DuWgL6PFIA5rbp6BRZRyuBMeTJQJhPq2/YccCa31By2b3OTnLhreGxiFxAp2tq3bdxOngPQlyG0zkZtlxY7DxIbp/FXfdMcTwfdwIli8whPBYqvYA2nVSUHeQKYmukk5CPZ6uhcruodgS0vfMToo7ykqlwNV/Rmb\ -NV84stKZ911FLt1iL0NhDynf2uDvK5ARKyt09F3Jh0gxVgu8wPa+86ejVq99YhCTk0MGnUr/m3upfFxipSK35L2WK/imP3NZrOrRYnCtzQYsdyupGGkVnQbPneGt5OA1HUZWcOBruO8JMwGZwW0o947oGJsfsQMX\ -eYrYp6vIePFwTbTcUgEHvRo8oZTffASHe6I2DEL6KR/nCd8WdbaNPwDSz2F/tgxhclVwsifdIskEm3ybARkMD84hmpxYpNZWwc6DhlacXM6JL490F28IA3QO5pjsA5VGLNNs/0g2aDi0G/1d+L7cvuTmPYb4rfiC\ -wbXqs5jzCbzSfxVqbyYSHP12PDj/VeBnK+FOVdmGi7z6I1A8XJ2A9317ga1L5+dcvmE7rJV2d//jLjHHPj5ynwwxidNNC8YsZ+uYrxU+cVLob+kj9fLwbcsVmMZEeSOmLTKjsnDlTFdtP5F10U9jIdxBKkdrxv3Z\ -8Kb/hRSxhrO/9cnIyrlxI7/cEtHywaexZ2V4JLD5LMJfEP7zl0V1B78j1KrIZolSeebetNeLuy/9oM7KxA021aIKfnDI3fZNfhMSSnM1m2XZ1/8BHuaCug==\ +eNqNWntz2zYS/yo063fTG4CkSNDTTiTXle2kd7XTVnE6urkjQbLpTOqxHfWsuMl99sO+CJBS2/uDNgmCi93F7m8f0O8Hq3a9OjiJ6oPlWhl3qeW6y54v19oGD3DTP1TZct3W7qGBaf5NPoPbHXdfuatbrq2KYASo\ +Ju5dVw6GD92fLIpWy3XplmoT95i7a+JXUwq+mtBXRrv/+YCCYwVoO3aMIe4rGFOOZKu8OKqOO2DBjRZuKtDIgA5wqgcES5qmGzeqAqlNxKJ3JhTVcQ7fNyOmHDOOA5hp1O7igt7izOr/mTleHS6ton4notGe4GWE\ +oxbUZUW8mkgqS9rwC7OkyFUdKLgccVgmb+nGj6CqFx82RXEUP7rRBKSJVRTR1mwTR6kp8dsKs26e25ey8qy0TaA4O2arHAk05Gr7mnxpf2+U/9oqtmggIBdOzKKReSM3Sczy5V+D1YIkxkvSVvS2moiCzSntA8yC\ +/zq7FkMs2JBrEwNPKXmVtek1qROJWrH0eOrmar3nxtNg5xTfg1hIIRgc7nvq3jTJ4M0rO9jlG5i1+I3YnqYwXp6a+MXXl/FQuaUKFKfMlO9MoFtcNgufp1O5u6Bh/KbMelJiy7UWpUbo1k7HFW9KKTqeDJGhDO57\ +MCh5i01ox3VyFPgwa7JkSx7MLAESjBe4VLRx2u2rLYlry2P9Rza54S8cl2UdYlZyOXapYAE0/cpzI4uJSvG+AA+Y8+TMS94yVlZwz9aI64euYhF06uBTpAcmCTQBFpT6SATgjXYEWj2Hj0I/Cm3qNtRruVz1ZIbj\ +t8OvVsR0EzBqyDlWA+WwIodOffUFxAuGEfenxh28ya5Syx6YghHfgKP99P3Vcjkj6KevnfO0jCnGnDmF5bwD6GG7JDj6bkL/RVUhSoHP6gxkTAHs6iRiW2TfCmOQsScxWaTNjn44hA9P4iP4d5iBqpyDjbHSDIEe\ +neaOAmVXPb/YRflhfkyaqNi8HLcNY2fVEN6ZAEM9V1/BhiAUJaSOVnZAk01WiTd6GNeCILplPsTjEm934kqjIFfhXRSOJ7+IJ+4w62CT3SamhYqs1GcMcOMgDcggkK0EQoAM7CVymhAbJN4FTADh7EzCXBKGaRzR\ +RwY5zGDX4+NUfTnjaJoc3ZQXbCNowF+ANg1os5Kdnoy5fEZM9OEPlMBzFe9Wwu4I01raAnjf1KySeotKZI5lE0+HtPFboWmYTvEndBqek23O2YysJMmJpG+Jf4fmw8+6jhmeao54wE2X/VG6I/c34YMDpQYxfwqo\ +8Td2AECufhjCJMjrHvKdHeKh0Wy6QQo28M3cY9u1Dx81Os/V146ibTiayw4FUSak1NljP7lm59tgIR1/+CKmGLuwlE2iH7C71sHXgMRVxbDfbtlAGC+DfKGWb/a8lZJ55MNESCm0WfvHG+zNw7Ic1v6VebwLN+9t\ ++HAXPqzCh3X4ABr9mcGvUb3zwHpv2Y12Kp+1hhmsrrpLklMjqtVejei/2bPl7RsgdNrxlK17eu1rBJS5Eeo/QlSavHYbZNjK84L11NC6OH+Lu/rk9j7YLmTy6RpZmu8FM3Hbpu9J75oRWuodsrG7tdhoAYmSxCG7\ +NQ65j6p7GuxLg8krDG1P9wwgNqglMKVw+1Uj7UbQHzd/z5dntLxw9G8IqcxGbcZsPMVPZwWhasNiNqj5q9V2MU0B4bggvUpUULSVtyDx/B2T0aE64c2hV6W89IwsONdqKR+qmFMErvwdkalrQPnf2RwLTjtB/Pyb\ +5eonUAx88VJw7kcuMVPvv5C04hoFJQ/WdN8AC6/2YQnQBBS9yWtSCXABnlyijThN1qBJMFz0fRam7Lb4/8SXTUjBbMMC2tdWUGgim/kMA5imLfwzx8Zc1z7/7mJ2SdxyMwByRsCUGnA44+/hQflWApYI2fNRhbWl\ +PANDNYOQMB3Uj+NkFFki4O0fnM4OAgpZ0MMQIxIWAjGksmQitS9xPr7lpVtGpRvJKafvjjEamYSDknb4QnfW0t239A8SzAmTAQQtSZw1RTNFCZCLXjc92n1LkRzQzn2iuQht2t5/b+MKgYyzG/VHAQK+QrjRFDDx\ +8z4QnELUVC/jAlCj2KO9pBVekktYHXF6iclDKyACi4HFtztyM5MC8/izcW+l7h3RzQZUBjpoIHj9dOkjbLNh4jNB4Fdk4MB52E1yJnwV+xzziBN6/d/tKNyYLSqy+UaXKqGtqityJZtNoQyGkIkQ2xf0EfXGIDtV\ +7HLbcYeCSs3yNfoFLxkMIh5ZUg+k2pUOEW97/HXc1zaE9eMUUiDYc7DtJvl8IBYk0fnDhrSpiNOPQlBKT2cg8ykHO42TDnBQP1wvV2+u96mGhyCgbfFIFCBWoI0hg/J1+sA32Cs6Axp3Z1GHNxdxvy6k6Nnl9XyY\ +q2i7e3oNGRtAl/QxgGOwJrJT4LSl4rzr/nzRe/IaF+LuABrOCaV1EuY7QCrzoQEG23ZPBvcoinXd3JusUg8DRaHjlQVdyEBOEK7UY/mP7mdJIYhnNJD8Mep4ss3vZfAcVNkhrCXz16yUfB9uunMcFHzpXvuVKoS+\ +edybEDbQQn7A6vHe8YNLPDKxCvFtThFAQYE1EKH0JOsBybmgFidhpWzeaGGVn9Kqxx2pnrj5TqYvV8gQAwRkdxDhoO0zVCeX9iCH7g2F1h0u97q3ovNw+Ne+FkC/lbYM1kPJWFeJKEqH0xRN0cVuMKhlUBNzKhtG\ +rn5iOpboJCjEYUI2nnDBWRrq40HsGPYs9buii0VzCICx2lZLrwitcCvbkLF9atoht0iFtrHESH4KhpQ8wN/0Drw+8r2qOluQKQBwQbCoMAW+O6Nwjm2mihM5E8RfuKASN/rtRpZ2AtH3geMO1A4VR3kHgQfA/X1Q\ +dPZ9sgW1dLp27rVe8dVh23CjFlwcU4Fq9Evppj5KwfOC82Ba+9FQT8gG9fZIjputcpSbciwot3WMVowcBDuyB7jZn8LNnn8/2ivIG0Emlf8QkFCaXxGJR2m3xMRzhTcJAWmt+4SgL4a3kVEQMahtioESbSG7AiKR\ +cJ6ckwnQ/Fte1kDQhg43GRSbBzVqfyM7tPkvgeUCPtbZswtIbPQz1mZo7LRQJQuhAa8Tv9TdikAIUKrl9miFAWNGEA82Cklyq980p+Bin3/YJdIlGEj6CXWRL5d9p/iBIzJjkKO2CvcM0Cd/AX/Wb4B0fMpRAtK9\ +knvFYSFdqif3J5W4Ls4OSaAZt1MqqibgwmzeUAsax/FMRJ0fc8dSOi8TCX7cQYa5Wk/hJjr1QUfEURQW2YyzfkrBERPbGeos6oXhnBMibomddgSTs/DorgkQOxFPHOjrknHUZDJsFhwIsWuH5NZg2PlXYRpAzcie\ +d4YpRNtMkJrDTouZpgHfA9uwkCzX2B/DIxdNLjrGR0f6trfO+QBU989kBdkdIFQ3/kRCqa2dpqBHObZmNXCzzzEDitdJnw598His6CATq5vuTEK12eYjGIB3A7wg/mWp+Q5vVluIP7xaxxzZsxk3AVpc+xNLl/vT\ +YTxGSHwWDzvQ4FlWb/lUyWJ3DuNXCqHyN7i5o2X0hiZyOMgTRTaYBcurEg8wnEbPv/x2SmO6txuEWOBTGtsbbvREVliaX14+4uq3zF73BN2NOyqGrToviCcEuZJT8JIcr+XDR2zyVINmhJO/I9TWxYxT9HbN/oev\ +exN/E0TXakZSde0doaJJ3/SCkGru5GA7qQCEcJLU6ckODLUU0ffkxR5pt+vAmQr2VspJBdg7zNKn5+gybEcf0KYanxYWKN5+5rO+jss2NISud8eDR64AcNp7GAfKiFUoe/BeYXoDeSWCRBuAQpMgV9/JY4aP7+fc\ +iWuH+RN5MeBSi7qOKfRYPvWoub0zKJIq5r8MaqxhuQc9K1funk3gRUyYWOKNinYjwlvAYVxc9gc6RZZr11qP12XcT/lgred49FuFnKvqQMwG4zSwImfOPoSbeI9b6Vh+1P7LWmJAehrWPcQmxoC6jmgadimZQctn\ +kdXkwXcIGtyjvyikngDsQ6/HMwd1xudxkOvAIR3EW82NMLCGUs5gwuODMqn4/GPyTzm82elPRA64G8/NXUVNswNKo8BLW+zZ/bjlyI4+BultJtKzxNhV27JtGNC5QY7Hd6/h+K54gcd3xWExBZnVZUHeUteMVqQq\ +Dnq9th7Flh4huNLSD+SfnUAIQGsup5/6ETsrTxxJ6dD6oaIQ0GIPQmH/Jz/cFzQBGbGUwuLzxCdAFXsGIFij9xb+HNPqnVvO2Uv6EKwUqpdK/8rdSz7XsFJiW0o28N7QsRG1bv6zqUSLobQ2+7DcvWRdpFL0Gzwh\ +hreScdd0bFjB6azhxiXMBDgBp6VMO6IDZ37E1lnkKWKDraIKDk/BRMUtlWvggXiWKL8mCE7hRGdWdDbhXr6wblFtR/gLHv0V7M+hIZSvCk7uOs03nPk1+RG3ncHw4LQB+t6VlZaUYRdCQysub+bBTyjsl1x+MSxL\ +7wx4t5jzzaCl24idmqMf5tQEF0QwWoUTyqMbbhbQhMN4wdmjaAED8PdbgEw/5wCg/7751uir8eD8U79IwjE1oYrTr/PyrwDzm80JeN93GdjshmdQ/S+1xDr75Jt7XfRjCsrLLChSTsQxcSh8aFfoe+lHSgbwbcvl\ +l8YkeT8m2cyoJtw4i1VHn8m66LOxEO4gjaM14/5M98D/3IlYw9lf8MnItvPeRn6GJaLlg09jz8pQVwfPIvw54L/er6oH+FGgVkU2SZwSM/emvV09fOgHdVbmbrCpVlXw60Humh/wm5BQmqvJJMs+/Q8JS3S9\ """))) ESP32S2ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b""" -eNqNW+t21EYSfpXxgG8Ykm5JI7VYNh4DmZiwm8UOcRyO98RSSzLksF7bmRibwLuv6qYuaWQ2P4Q1rb5UVdflq+rmz81lfbPcfDwpN09ujGsfA8/pyY316ge98I/C75zcNPVu2yc0p3vwZ639ULRPc3LjzQRaYMqo\ -/dbkveat9p9k0r7mSfu0S9VR25K2z0yvBgNnNNDZ9m/am6QlBaZvZ3COqC+gzSzb6Yxip5w2QEXbmrVdYY4E5gFibW/CnLrZqm3taHg9me++NvNd4rClFsZUA0JaAtpVHbyZ+0f79BV7Fn+lZ39FeB62q8Jf/qMe\ -J4TUIBkvnJQ0k/HEeFiPmUJiSiXLfEBYHr2ll9CCUj26XeWgnfFT2xoBE1MD+wi7sMoFPHOitxZi237tFuRFIKWulLz8kKx8wFCfqvE1+bHh3Rk12rD+wgTyYMdkIvu8JqREU2YufQbaCWy4wEZd0NdiJtJ1T2kT\ -oBf8tcmBKFzGClu6KRAUkwF5Hx+QLHFSLxo9nbd9rV1v22O1bYbfgSecQTX2Nz1uv1RR78uh723xMfQ6+oPInsfQnj910++fvZj2JZsbJTXYDVi+qXZFkZWcE/17Ppe3fZicx4DN82yiy6UVuU7QglsxVxmvnb4h\ -t6A9QK7eO6PPeX+dVuIy2lZ2y5LMWY0d6n3Lqwt8wgP7Zdvt9DmR7bmtm9VHxzyiVYC81C4peiH2FOZFLfdq53i+PAOKv+MOWeBN3gtLOobtBbEXiEBXUqruLiNvagtydGD4xrSmWjv6CB9qix+Xqwaj9edcyzA/\ -WS5ktn77eX/UksivFMmODGHZczUsvaH12kR86y7rg+cfLoHFbatPZUJ+u9Uu2Cxpxi2yyuF0Pg56xNDS3Nu2wXydJ/NAk4xZvViOOnwUET3IYcpRyox8s2Lng/F6/nj4fTEMeQ9BpECbi/oWr+dEOrR3U/ql+4l8\ -GyMhu+zenLcouoG/48mYUO9o2wsOsKUKaU5FlF685RDkeuF0vqNWo8GVhKNIBjdbGBxt8IcS2UEiYE0h6OFC5/1gtsr7Vn/ZogKaWmYrjPxTUepmyiGydt26S/ABW9ui02JjyB7sTUHBqTN4YAPkhXIFcnMw9G3w\ -0xN4Awvw6NnbQc38QftvQd4LJAXOHFXSrQcdNWmwOv3gFtV373fo28k7oqV8JwT2FtHJFeuxgR2pw/52jX4hFqQo6EZ083B0zAejK940NxawibzH0SqraFb825bTDj7wWk0yPlVYGDmdSZiAsBJNwGfBZmB71Se0\ -6z8LMUJzXDixnCKRN9O5n5qtCeXU6lvBjhcUoifv+JElt47mNUC84itQfdqnrMjO7/JN0G6VwMUniNX8dT/UvqcUHmDDWrrONfegivEG6z7gBKbL+J2o+LJKIuBiFsi4MrSbK3EqDS1rsMMKwI+e9WGg7Ln3l8qw\ -9xDMHSevYs+4DIQYH0NEefPjq5OTPfaZyE1rYL4RM3/eLpJypEbcdZ82ClUhor8+WwWuQLxNgJIY8G8ZTfqOq7dN/vGUlSzZfr0FAx9Pt+HPVgKK0cKunjpfUD7UFIi2VAowF5BVstoV/JbyLiC1GDCUV7QIsED5\ -i1ioLIZU/hN3HMQXUSwpJXZbsjiJc4KdrOBMSwbuEwXNogBfmmg0A0K/5yYr8KHkJdFoWF3rZiSsmvuMgAc+D/1ms+L/LHGGFLLFE2f70AH48nuSBEU6d8MWu+0Q8ABmK6YPYvNkTyJBvr99LC5kpnx3Ye6Bud+d\ -ooTs+Vj/eH/IO+38Fe+y89Jm/I8EcdbWaEcgjllz16b2gd5BwMzkWF4982zLifJSClrrmRr/IHQWx7RCwopj+X5KicWRJ5dbKKhSqtHgAyAe3uVHcFyukqQyjAH1q1BHHrH/HOAjY9D+/NhmvNfCf6t/XOgfS/3j\ -Rv9geIXOaK0YZNmlmCAi/6eol09Z/Zhr58ogBtyF5Bfg+yl6RnBWuK8H/USw4ndb/ARgevYzmw64kzRWaCfl/nY8fJBttc60FlKRpI8HSMPivuqJZMx/Jw9j2T1IqCGNuLgRjcoo4tJQ78acInB2ya5OgNXsEP3s\ -x0t22KXajBLmRCHZyToliE1zAe55ojRS8Vyu+I2P04/PM7LjKmHBoFK9Wo6z5TKIBSXNKeUiRrnnwOHiPU+TaPHBly2FdFfM4ojlWROmLhoVxNP3NE1Ztly6inUs42oD2E767cnyDQgERrwUkPQTV7fiYF04b009\ -IXJ513wLJBxuwBIgCUAf0c8kEohpYGcF8nLaNqYi8YITV0vhcsw6CzNmnSrYov1BQ+nvLt401e6/9vdeAMIjlPWJVjXRfP+J+ENHrr9tU2mHO6UEEssP+CWUMN18vjuo9YwUilpON6V1C5YdFt8c663rufF5r9y1\ -Oj0WPUyifthE1VMlwRPKmgAvnRpTqhrMCYVVXK0yKh8udHJccc58LCAVdqhOhMrkgpuN+UMJtnISf8wLAbdu1sHcv0nXTnbYTHO9v5Qpvby5ZBvfbq6lr/nAb3ly3VFAsnvbzZlyHmXWgusCk5siVFQeVMPGoJFr\ -lGshDPKVSqa6oAC8RS+nWSSlupdkfR59S4ehIM9p6jXSt6beEzD44F6/ary2BZ9fcHZZ5Gx2XRLT7JyukYFBO7AGf+Ep2GujdXCZy5jxtDr3T9gndqlvNYI3waOUuiDMT87xtTL/p8whKUo9Mm8a8K/ABe/vKHvw\ -9zxfnas3fiV93+NSw+DE4NU0AMZttqleqlJyBOhz/uaucLBHnq1pDolhUA+93sOT85ElYS6I2UOWcI1iRBWLeIWViKQG3cFf+mQOJVeAKT7SxeMJ2bTjpBD2HpcZSeBAXXPeico+4iVVY2m/YqIjZtdoTSrqEdJp\ -7N5DGPggPgSnskN5q52N1yUQrQCYoDlOT5eUOGE4T/qKxgKZ7svw/44oCki7DsCniMaBTLECcC55mxougPJqpTh5nDmXqiwnStLpLMycl+MrjrVrFJ2P4HGlApAapFOC7f1m3OmMVSDtvt7C13IP6CzZZ2AOvoVt\ -6KwOTpa3BxtQNOd02WcfaA7bLPQJn0wQX/FLJDKwF80E+lr7dtotDY45fXew6MNq6zfKA0zmVA0FwHgeKnS4BeRYScDwXQzCiX+MS00GJ5j2FFPE4i2ikVMq+kBuDj7IZqulm7zpl3Tqen210UP+L1sDMaGqhqig\ -J10Amh9YohGpcYGqf5b9gMOiViq+ZhtMrydN1/MPaUTRNxsCz7n6bdINDA0LngSzadMcqYUwrV9MVQTQtIAZ5hXRgitcq6Gey8u24gqO5iAPKLbFht2UC5IvEUelJdpnvarBk7B2yZ2GtoJIOZC+oLtnWfC/jbw3\ -PTHyOuhKTBhr+wy+6b5s9ki4VIXwLke44pJj1Fso7gTUSAeDRnFPflr8mQQf1Z8u7q38HBRDPiVBdP9Q1W9ZqIG9LVQAt9kRNEBRGAtnNXiKvRH34uicpoBU08WL4DKN2eDsJJEpabMIEJVY0r6Cf+MLYGgSTpzK\ -5IiSRIQdM3GlF3woJQdHmOm4YBN4vgbFEWdnK2nMY0CnV5yMQZJWpHxk5sHNuvRaVTe7k68jKrg19SLIu+CnQQz01cpKDyibRngk4QD20ZM3vuJkkNb/4AjpYoE17pPAvKyP8pKv8gI7liGxjdIK3+0Dm5SzWgEW\ -x9qhbLDcwW+kv2h12NBp+58MYrC47qalbOq6pGTQcE1owKcfFDXGqok6x+PkQL0u+RS7kdJXx0Z0pgdeCgWHSEEIQcXAq0N4QlpypOV9OPMkcsA1OCPLIiGCeb9AwgKj7k0UKLi4pigBEBLyAKQDY3ZxSwUlOW6C\ -QnOFER3UpEp3bjdofjwSjj/jCWT6b70txe9qCi4M0vGekJaS+8pzERBu3s0RhEY572kMh06vJODN6S0Ih/cQqixucMIBcR+6t8+S7MGWcvSAc2Zfk7RyiZIzFTE50QXKMPTj+0R1SANfpouockiuO2Yh5Bor9d2J\ -4qk7O7KnN7ThLv0W5feGrV9k5aJwPoqCdYz9pF7s0oGHRAFmXH9HI/hGDpgWJOrFkxAcnGYK7edMD+Vw1bgrAHygBaBFHtJFsSmVsAxwZkvvucDhxnwUKxuevpHV7suSX0s2M+0DdB+P5AeprkwPBWGUBZv0AaKu\ -6U3UQ3/pZ5rBMXLY56AteGowI4y4t0J7Z2w4bRGyUucOb6YMQ+BAAQs99a3SJb4/ZUt1Z8Dy8nXYmtqF6A/hKVjKf5h+c0aKBOLJQOPjC8TfQ7tLDymnQ9dTy9ecqxR49vj371j78f6A4p0M9xsmo1EXGPKifNu8\ -hK/vTs6ZJECEkAHl5jNrfZbT1SRQ4CrleAyy8be8Nmj2TNW2Mj6wxnMiSVtELml38iHm5N7J2bLjUiDwAVJ38Ts6I7lWqR9GN6hDNwgd/PoZ142g4oBASy7CFLMVzEvFWw5lZa0Qrli34fsjNn1+hmdbIjGffkJl\ -a1SsQ0FupMHVNKwCXhRuBbF96GCYH0F63UENbH3N5rmK6mz66yr0gtETNTrToyUSPgML77JSweJAOuAEUn9Mi3Ft8u8dQrseGvPaGbXk9i3z3UvtCb5BVTrBA7mp+F5M8ic76F05hGDGmJ1Sschj6rgcyYIjMjO8\ -yGN/G3ZYcI1ZsV3hzTVYXq6wlfgSs7eCSOrkNllKKYyML+/Ky6CqhHlZWU6Y4pIVj6m3rj5j4IsmX3850wRuVpzxJWMwmBtdAYYOjFMN4xF4SglrGVkQaiZWaPf6V2TAo9V4TJmEWyU1nWtuclVC0p0EAcMm3c0C\ -z1hX649Gjn9pJIjCp5OweRb35/XqBtr0++4cCs+Bf4Zz4Ow3PAfOtrJTvET2DlixP4zHjqIzCxFlrMJ4xHiY0MCHSSkEXXHN0oRrKSZd07ZhuMYJXq7By7h4dnFVkMuvsSxlsPSabq1302zSuQKlyXkQs2A1OK7z\ -VqRH+GwNRiFzfFOmsNJS8slNzofKjRQNHOXohkWMbQAGrFuVU45RvIRLNIW71IkUKa/Ha2vwVXKHUu4OF1jV5CNF6As+Hhw+Jg2ArcpcXTMGdzibhFk9F1iBRLwVI/Kuwq0bPK/mexbGdidk4mjy9gWgy+xooKYo\ -Oqg+uq2ETiDAjSNSa2w4kodlqnSLz5dAJRuOXVRaYDDqs3evOcHvUqMj7oM3XQFzNtMA0MLVCWnMt18vbkUbt6ZHDFSr9W/UwX9KIBATozvKpTYdU/WroQPfirhWlvv6iQptnUMkWxjOhO8C4CBHGYYFLK5FlFj6\ -9B11oFOp7rq3FPS6UMpFOid5AaBkH4XLEyitTEE8vIEaf6K6K36tOSm0iL83pqpC+qV7Vmb7nqyLl3GmMnGDYDlTO1Rh+i23Zog07P2IzzXVWt0alVzqFtbS3tBpIKV/crf5cIL/j+DX35fFFfxvAmuyODezNE3a\ -L/X58uq2a8xmcLl9syqWxeC/HTTV7iZ/6U2URpExyef/AWm6JiM=\ +eNqNW/9X3DYS/1d2nQBLSO8kr9eW095jSdp9pOn1Ak0pzeNdsWUb0pdysN3Akkv+99N8s2SvSe8HB68sjUaj+fKZkfLfnVW9Xu08G5U7Z2tl3KPgOT9baxv8oBf+Udi9s3VT77s+vjk9gD9j96FwT3O2tmoELUAy\ +dt+avNM8cf8kI/eaJ+5xU9Wxa0ndMwtng4EzGmi0+5t2iDhWgLyjYAxxX0CbWjlyKlhOGTXAhWvNXFegkQAdYFZ3CObUTVeuteXhzWi+/0bN92mFjlsYU/UYcQy4WQ28qccnh/QVexb/T8/ujPA8dbPCX/4TPEYY\ +qUEyVlZSEiVlaeF+Pl4UMlMGssx7jOXxJb34FpTqyf3mChzFT641hkVECvYRdmFzFfDMid9amHX93BbkhWelrgJ52T5beW9BXa6G5+RH+3ejgtGK9RcIyIMdk5Hs81hYiSNeXPoCtBOWYfwy6oK+FjORrnlOmwC9\ +4K9OjkThMlbY0kTA0JQMyNrpEckSiVrR6Gju+mq95dqnwbYpfoc1IYWgsbvpU/elijtfjm1ni0+h18kHYns+hfb8uYm+f/Ey6ko2V4HUYDdg+qbaF0UO5JyEv+dzeTsE4jwGbJ6piS6XWuQ6Qgt2Yq54p3IR86zr\ +BPLgvbX7nLfYhHpcxruB6bIwc9bkTs8crN/4NcMDe6fd1tqclmC5rR1k41Me4bjMy9A9xS/7JhVMgKpfeG5kMhEpvmdgAQvunPiV1+wWC3hnhcT5Q1Ox6GvKYCjSA60EmuAWlPpEBOCLdgRqvYBBoR2FanUVyjU/\ +W7Vkuu1X3VErYroKGDVkH6uOcFiQfaNGzUBrBI1LYD49551AG3c/yiT4kSvqQ+oVuOHcRmyE064bDANGEdMjmyQG3wkqKdnpYP90gGY452zze7jkRkmALds3Y3WworF3lKEWWUO7UXA4LIOVm8D/dxbCAcP0gp9O\ +JMztz/eCqZkSu2wTC6VmgnFN+6AqQdlY0vli5rl2s149vAHEw6Q7bVEBg2Ox4EgUr4k4ukF053lXYLKTXdG7Og2CIwStguJKa5+wDBAeChnNA0xwF1zsCN5ASy06ZTeomT9x/xbkdUBs4IdhkaDeaJfMCOpIvBmX\ +cMvqL+sAPa3IY5rNtnJgU47Plqx/7ktV1n6/20a7IM3rcNCOaOlwbMt7oytekhkKt8Tes3hzqWgO/FuXURv8ea4mGSblJ8aVzrwthb0LI1ZRJPKmlHiFmi0F1+zUp2AnB/vbkd30K9exYJOwPewp9ora4J6yIjyB\ +Kptt7p3RkZecAA+xgAcdwXSTEOgq+GGQvGPqKtw40KnpNusxhGtmStm9uPiybiHuYf4pXmBkQfVBLhuaVpnAXoJA9qKLxmQ7rL0JjPQA4exp8npqGR6BBKen4E3e/vT67OyA8DetBmJ86yq+dZOkHBsR/jymXUId\ +iEkJbb6JH4F5nQAnU4ChZTxi0cYDe2SfRaxdye6bCQx8Fu3Cn0kCWuHQT0cvryktaQoEPQESnwvWKVnnCn5LCw/NLXIQeDiNOGcE4pwKl0Wfy3/ijoP4YNGgeBIrNZmOBBrBL1rgHiBFmwXYKPYIoYkHsxB0YGa0\ +EatLng/NhXW1bgaCmnrMKLQfsEFTmw0vpglJIYds57SsQ+gAi7IHkojEYf6ELXrXILqAjLGInkzVNwfi0ndP88MWmX+FoQVEWMh2z4YTBZ+/noY/3h/zJhu75A02VtqU/YmymvGYNgN0WKuH9hMVvsVTR96hkUN5\ +/cKyGSeBd3oAQzT2ie8sDmmDhQ2f8n1E0P7EUtxGyMhxuAxGg/lDWHvIheC4PEhTSj8GFL5WJH3ym2k3/1IK98IObcT7UPiX4Y/r8Mcq/LEOfzBkQj80Lnp5binWh1nTc9TKgx+8SVISUHo5ADZZCrr7lQsLMfrH\ +5gzKJOkWwYHNGP+UUM3TvvCOxH6ct7QsWl38DHB39ovbhYyI2PTrAOuktACZqRtt3O+SCYq31ugpPh6xUSTI+mIrGIFJwPxPiq6aHYsEKVKo67UoZNZVSDsdcqjgn24oWLUAa3aMPvrjDTt7K84endM1LHfEtDU0\ +Sybj/lYSeJgB4glqTil7zHIDLn6MPn6bkVuoeKEV8vp6NbxQk0kinvrUmaHwFWz14j0vuQ4FC18mXpi26jNywkC8JuBdBFBKpe+JTFmSrZia9TbDQUsw+O/Ort6SLhTxK4FOP3PFaurZBJstGp4oo1Bos+Y74ON4\ +G+YBcQCWiX8huUADWG9eB74n7Vp8ofrrAS1vfAyRiNuavuLBEu9QT2sRmwavRzB9SjCdthRdQOFolwMWROhvFCh4/VcQmeVY7f/r8OAlIEtChJ+Ihornh9+gZ6goUrmGIPcx55ToYMUCv/iqp5nP93vloYHakpPC\ +jrROYM5+vc6wnZhO3Jl3KmSD6/H5Jf7QSVCCFa0VzhqPg00wpgzKNmeEAnC2KkycizBxrji5PhU0DWpRJ8Jlcs3NSn2QyGikVAM/1EtB4WbW4vGvpWsrO2wmWu9vhKSVN5Ps4tv6VvqqO37Lk9uWA5LdZUsz5fwN\ +smMBlmDSEcLa54w3xBduxNexqHBg3D6KPQeAp15FGSCpDNS3lhlekd5aPWq1uiYbc7Q+g/TH+O8BAZGmefKoW3EeP4LPLzm9hTUggTaFavZKwBpTardS8KvZi8VsVLMA+dabSX5uvyHD9bm3SCnsWgZO1sZeaJyY\ +rbqu8Utlk7zYZASpJx66t9GleKBkwt8BmPdpdcZvpGQH7CR7Zw6vIw93d9nEOllWGSSF6A3wecvRpxqaBlHnMXlJ0JZwPocIBqYEWmZgSTiHGdDMQm8sJSZ9hfwAXLJN5lC0BZiFmUdbfh6RiRtOZkEDcJqBvW8C\ +N49oiHfZBu2lnjDfMa9YhSpV2AHuaezBNgx8Mj0GN7O3oDxuqDZSsuPnxZZC6fwcIGB6y2g5UDfuGR0Kkd8H1AVkHgDDvBnGVZvtN+TlmoZLpTzbJYMkTZkqVeUZVHKXd9QFyeYPTLex3bBhksbmA6WGQAemLMSY\ +Uo/uF9xtibhp+/UevpYHwGfJ3gNLCBNsg8XER2er+6NtKr0DBW2zO6KhKy6VZLIzMH665JdYRKCvm1EDW6wuo47A0ndH3eRA2+3SzVezg2Org40ipwo0am8ARrzitAzn5FwYoKJLaIsL6Hx+7mvoZUoZdVheAtCS\ +2269C/KeImyfeWQEXFdt0O3IDsDtHcsrJsRWYDHpIvsRu8cL8ploZentqGl7fpDGBVZhtiUTOJU68zaGgAUTwVRfNSfBRFhzWESBpw95gd3KK+IFZ7gNhiLaWdC2YnkpXEHuYbHDmS3JBUlUiuA6l30MZ1V4Wuam\ +3GtI+MTKkfQFDbrIvIdt5L3piJHngTVItgdjdXeBb9svOx0WbtoEnOIeUlhyYTPuTDRtBdRIB4Uq/0h+avyZMLmkT27aIQeL1/Ip8aL7Iai5y0QN7G2R+y86g0zCQPUZq3o1uIKDAe8BlUVE7mtw7wuyIGJrm9Od\ +REjSZpG/LrF2vkRofg3sjvyhU5mccAgCUyBfeM3njXhwVHDeZDz6xNM3qNwYvXGycfIMsOiSsz9I6IuUz9EsIGeD7lx5QnTydUKlwKZeBMcs/DQIdP62MdMTSvYR9tfij+9oMte45OyT5r8zhGvRmU27LPBatgbX\ +km+u5YQyLMdsE6iEbTeB7cnE4e4vTsPAt81CB6eR/hrqAn8hTf/EGAXr9yYqPTyrA0dVqFuK9zZdBwwpHdBq5W7k0L0u+aS7aVGfrCS+CAcuhYljZEICTO1jnEQeZCRHRv7w55/EC/gFo2TO9tyo/vL8C4T769hP\ +f31LkoW5KwAsOSL74gMVu+R4C8IsQBqTg45U6d79NhHH0+LpZzyITP8d7knxn4AElywxcrV8peS48lxEg55ofQIxT46UGsUx0QbLt+r8HiTDGwi1IdM7QYF4Dt3dsyJjaEunCmlmfydR5RIRZ0F05JwWOMOQju+j\ +oEPq16Xa6Cnn52HHzIdXpaXsPArW1J5N6fM17bbBWKaKEzZ9kZVpBciCNQxMpIzdlovEN6IAMz4WQAvYlwOsBYl68Q8fFky4KDSei3DoMzlMXoJ7BS0AFbKQGYpBBRW3Hnp0/F4Jzm3UR7Gv3rkam+yhTNkeJkVd\ +8G2nA9g/DWvmfUGowHZVuodwKlrHHVSXfiYKjhLWJJpDjtchsgpIwpDHG8y3pjbGTeT8BoKQOV5HjEDgoAOcX1PfB8rE16v81TECcJK5yt7Uxgd+iEzeVP7gBagL0iSQTwYqP71GYN03vPSEEhmEa7V8zbkigYeb\ +/3jF6o9n2sHayXL5to5ugosMeVFeNq/g67uzK2YJUpgCvIv6zGqf5XRzCTQY6pY11/yUvee5QeVnXvI640NxjWUz8HT1mkEU71ig9lyMFGGD1DHjz728dcohKHf+60rke81XYRoEDxaQKGetDZQXEG3RdZktbN+6\ +hH9PACQ3AagVs1Z8a0SnLy7wrE0kZVDdVAtvMcFU24IR8ZIDaE36aBCe2fSuxVzlIKybe5BZc7mzC990+tsmxoIBI4a1Uo7tJZhQCqvarFIgN2wXVoVQ1TG5Ra0iZ94Csdu+5Y4vqCXXl520lXN0QmlwNJlAkRTy\ +c3K0mK2P9tCVcrzAmnh2TrUfi6WN1UAiG5NJ4a2doUwXzKOadZde4T02PJbkkFvGXJt13qn+HKQ42o8sH8q2IEXHbKssR8xuyXrFrGuzVfmjdazv1F/OF2E1G573hqv5QN5yvd4YDEoN57WQXpQSwzK63YG2h5VX\ +OXLW/mZcjfenpv6WSk1nqztcWJCsJkF0sENZOHjButp6OnAETSNBGjYd+c3TuD9vBorY6fftgRieRf8CZ9HZ73gWnU2yc7xD9g4LBz8OFPNSX/9HgyCZBjE7ZuRLof9uVApDS66UKX/NRaXj0DiwsDjmi4N4LxfP\ +PJYFufca60sKS6rpZKsls8OHWJgN517MhMro3NBqkR6BsTGMwsXxzRuXnXCLHFAgsuKaJpYCDJ01KRYxtkHk12ZTTjmG7NJswebdhPkS6a/Fq2rwVbKEUq4RF1ie5NMR6AsuClwvpgcApMo8uHEMljMbeaoAIPBU\ +JuYrNiLvyl/hMVy7wYRKtzUfcTR5jKdCxeynnpqi6KCMaCYJnSxA7oGwrNH+WgBMU6UTPpcClWw4TlEFgZGnzd69Ce9kyLneSz7cY8SWNd4naEZyeRP5aOUpSGO+i4Q/wsBJdHJMp0/F7OvgVsKMcKBzyVfDtVA9\ +G1L/Vd+rT+KALVDaWXiNqXWVXCjr0cN3KVtDntKPGMMXlXI5G20hPZfdjGQE4Pps7G9zmLZu1l5bgBGfqJSKX2vOBTUi7+2Il5X+xQ0utftI5sXbQZEQbhAmZ8G+VJh1yzUeYg17f8WHo8Fc7RyVXPaWpaWdoZFn\ +pSurnacj/P8Fv/25Kpbwvwy0yqa5mqVp4r7UV6vlfduYzXTqGqtiVfT+O0JT7e/wlw6hNI6VSj7/D3TrM/g=\ +"""))) +ESP32S3BETA2ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b""" +eNqNWntz2zYS/yoy6/iV9IYgKRL05aaS68p2cm3s1FWcnmZaECTb3uQ8tqqcFTf57od9ESClpvcHbRIEF4t9/PYB/bG/atar/eNRtb9Yx9pdMVw/L9bKBg90ww8me7pY2+orN8cP51P4t7NYt8ZdrZsQj2AESCbu\ +XVv2hg/cn2zkbsvMXW6pJnEjubvG4Wrw4Zg+1Mr9z3tEHCtA3lHQmrg3MBavHLk42E4VtcCFGy3cVKCRAR1gVvUIljRN1W604+EaX/18He7T8Qxf1gN2HBtubQ138e78nN7iTPP/zOyvC9ezUaeA0YYqYIfCTgNS\ +srKriujFloTgV+UNIktVINdywF6Z/Eo3fgQlPP+wuQ9H8aMbTWArUQw6BY1s7gWuCfHbCLNunlNHaTwrTR1IzQ7ZKgcb6nO1fU2+lL/XcfB1zLYMBOTCidloYNjITRLx/vKvwVhhJ9rvpDH01oxFwPqE9ACz4L/K\ +rsT+CrbfSkfAU0r+ZG16ReJEolYMPJq4uUo9ceNpoLmY72FbSCEY7Os9dW/qpPfmte1p+QZmzd8T25MUxssTHb34+iLqC7eMA8GBQmB5a74Siw5EnYXPk4ncnQNx/gYggKmJOVdK5DpihwaJVrK8SHrch4UyuO+Q\ +oGRF69Caq+QwcGOWZ8n23JtZAh5ov224QH3KadeWvAse6z6yyQ1/4bgsqxCwkouhYwULoAMYz40sJlLF+wL8YMaTM7/zhoHSwD3bJK4fOoxF3KmCT5EeGCbQBHCI449EAN4oR6BRM/go9KbQsm5DuZaLVUemP37b\ +/2pFTNcBo5pcZNUTDgty6NqNhIyMIcX9qVCPN9llatkbUzDoG3C6H7+/XCymhP5E4wkRQRHoUye2nPWA3rZL20c/Tui/CCxELPBflcFOUwC+KhmxRbKfhWFI2+OI7NJmh9cH8OFxdAj/DjIQmHO2Hm7e0Q5bgz7W\ +h/8Ju2tNIlh3d7lhO3MM1wilAbwr9KwRvE6FUTNk9FvQFCJVQhKqRDWKjNUk3htgXAnAsA02KvDGxNtkm2yNgQbvRhvWUfGSpgYlsrm3m2I18S5D38BEEMgFzGNBFiCjBS8SWp52dg4TYF92KgEwCaM3jqhDjfYM\ +WYuJjtL4+ZTjbHJ4U5534eBLkKIGKRpR+njI4ogjkJiw+4AZAkDBfSfsnyDyhkQP7+uKtVdtkYfMsWztaZ82fis0NdMpPkOn5jnZ5pzNgEs7OZZkLvHv0Gz4WVUR41XFgRC4af8kbfBZ5k34AOz9F/Y3gaDJ3p7B\ +Aw9PHvBfvrNDq9eKjXWr3aO0Opi78pGkAkWoy6/dErbm8C66CQJOSKm1R34yfb+FhXT44YuIgu7cUm6JSM4YVQVfAygbwy7RbFEdjJdBAlHJN0+8fZJh5P3MKI7RWu2fq9YbhuV9WPtXhvEuVNuv4cNd+LAKH9bh\ +w/k5qxYAGpPAbHJ9zq6zYzzChcmsMu0F7VAhglVegOiw2bPF7Vtg+aTlKVu1eeWrBNxtLdR/gNA0fsNIhRZfsIRqWhfnb3FRn+feB4pCJh+vkKXZk2AmKmzyO0lcMRpLxUPWdbcW6ywgYZIwZLeGIYD0exrsqoTx\ +a4xsj/cMGjYoKzCvcJqqkDau14hhPvEFGi0vHEGdmDMblR6y8Rg9nhYEozVvs0bJX662b1MXEI0LkqvktzGp8hZ2PHvHZFQoTnhz4EUpLz0jc064GkqKDHOKYJW/IzJVBfH0I7t2wbknbD//ZrH6EQQDX7wUbPuB\ +I0zqPde0vEZBuYPV7TfAwus9WAIkAWVv8oZEAlyAD5doI06SFUgSDBe9njdTbguGY19BIQW9DQU4Tgv+jEWZzzBoKVLhX2G9S91fnU8vgFtqB3yEbwtwUsxY4S72PQQ94QSmV2NtKdDAPnUP/Se9CnLzSywi4ix4\ +cKLaDyhkQfNCbEdYEO79RpFCFVY4rf4WsUYT5Lw7ZjRCD1H4AMlazsOQKPLwustSiUN+OKe3DgrLMb8FvbeUDSwWFJ9wHNyDx59dYzy77NIG0Nu/CAUdp4rr1Np2fn0bGQQ4TnMEUDYAG74qOFmUjNyHhpMK/r6M\ +ioTMH42sA4+X5C1WjZ4IFbKpumWKaGjNjtxMeVPt0RfDxgu4oG25iwHeCz6DRoTXjxc+7NYbJjoVsH1Ntg/Mh90mZ92Xkc8zDznVVx+3A3Sdb5GSzTa6WAlFQMiSwctsNoFiGeIoom9X9gN2ZpSpxuyNutvuIH0I\ +XLBW3ByywSBCVUniAZMyKgRDJGu2cF+ZEPGP0h2qetoGQmPytLctSKjz5cZuU9lONwrxKj2Zwp5POA4qnLSPg2p5tVi9vdrjMh9KSls8EAUII2hmyKB8nS75BjtKp0Dj7nTU4s151K2LvnhxNesnMMrunrgFG9/q\ +AHYh9pOREoyCeVq0888v6qJhifnV3R2kp2cE4CrpJ0FILfWBA8YhLTPh+FhUPRPPAIaXPYmta6fTsqALOckJ5uP4ofyu/UXSDOo8oKXkD6OWJ9v8XgbPQKYtYmAye8PSyffgpj3DQUcbG63tG7+SQZycRZ0tYaoV\ +8mNzvnf84BIPTMxgWT2jKBFD1dXbQulJVj2SM6pLiD/oQYgWBwvH+QmtetSSDoibVzJ9sUKGGCkgA4QoCP2hvji5+od9qM5iaN3+cm86czoLh//TVQrowNK/wTopGcoqEUGpcFpMU1SxGwwqGVTEXJz1Q1w3MR3u\ +6HlQmMOEbDjhnOMUymNJs9AKTeq1oop5fQDIsdxWYK8ItlCVTcjYHjX4kFukQmosMeyfgCElS/ib3oH7j3xTq8rmZAqIYGNKSpybnVLsx36U4WRPB8EaLijPtdqAzfkxFE1LjkFQWZiM23MWPEGLewghaqjNqaho\ +m5mXuuGrxf7iTxsrHVHhqtWFNF8fpBw651yZ1n7QlA3YoA4f7GO+dR/l5j7mlP86Rg0jB+GP6ACV/SlU9uz7ga4wxwC3z68DErHiV0TiQTqkEfFs8CbhBJkzg65O3kYjhrhBzVUMl2gI2SUoeiRsJ2ekf5p/y2tq\ +CN3QDRdrQtPIpKP7nuzQ5r8Flgv4WGXPziHJUUcszdDYaS0ja6EBrxO/2t2KQAhQqlHcZWnbKXWPwEAh3WrU2/oE/Ovph12iC6mbTj+hLHLI2biffMtWzQDkqK1ChQH05C/gz/otkI5OOK2A1LbkjnIYXsr40f1J\ +JbqLp0MvTA97LIbKDbgw3dfUqMZxPD+Jz464oyntmLGEQO4zw1ylJnAzOvERR7YTU3BkG866KQXHTex0xKejbjOcfELoLbEfj0hyKqd7CbU6OrhOxA178rpgENWZDOs5R0Hs4yG5NVh1/o8wGaDOZMc7WxVCbSYw\ +zTGngSSh1eB4YBgWsuYKm2Z4PKMYjQbg6EjfdqY56yHq3qmsINoBQlUdnFs0bCr9JlTQtRyactxzs6eYB0XrpEuKPngwjumsE+ug9lTitN7mIBh9dwOwIP5lqdkOKwu7AegPr9eRNGKmktfj2p94d7k/QMbDhtjn\ +8qCBGs+9OsunUjceTzh4pRAn38PNHS2jNiSRw6GfCLLGEl5elZTcxfrs+T8nNKY6u0F8BT6ly73hRo9khaX+7eUDrn7L7LWP0P64owLKxmcF8QTnAZhxJJSUg+M1fFCJXSDT61a4/bcE2aqYcqLerNn/8HVn4m+D\ +0Gqm5Attc0fZpE7fdhsh0dzJ2XdiFktXjGkpkZKdxZJ00B2laevzUmoSgD8V7LCUkwq2t5iuT87Qa9iU/kCzqn1aiA4S72U+68PebsO20HYeuf/ApQBOew/jQBnhCrcfvLeY3kBe2bLpdbhQJ8jVK3nM8PH3GXfr\ +mn7+RI4M0GRR3BFFHwClrkHVDKolKbDgBMBwj6hf98Fnru49hdweCj6FGIfl32h3RJALUIyLi4qgm2S5iJW20EbfPeUTuI7jwS8a8sCleIs1xmlgRY6ofQgH4EFNK6lAKv9xJZEgPQlrIOIUI0FVjWga1tfMo+Vz\ +y2Z87xsGNarp80UVd682sO8eDp7rEBPwmCI+xdO8UzrfA1tV3ETDn47IgY0OOtkSyRd8zKOpH+O43uf+PTeFY2q27VNqZThUmPH1lpM++hjEYTMRB4sAz5S2qBLjPLfU8dTvDZz6FS/w1K84KCaw2fiiYArlkMLM\ +58i+VEw5SHZyfRDDe4BgTDwtyZlbgRw78z5YYpLf7Kw48urF6gO2g7G2PjQHewI5sGMstrA8PRbBkqQsHzLUeOx37c9Drdr5NzFt5FRQ0zSjfuM2KB+NWKnJLWUCeK+puUONntWmVC2G3ErvwXL3gXrZZC2eN8Nb\ +ScsrOmg0cMqruQMKMwFzwL0oHR/R8TU/grDGI08RejxgC1Dm4RGaiLahms40fAopv00IjvBEbJbFZsamb5kWxXaIPwnCaqQ+0ITRpuAksFV8wxlinR9K/zqhYwtoWBkrDayUnQktr7i4mQW/ybDPuUYT7GYjU1Bl\ +m2T6N/hWrFYfXs8Y0Bsh/jScUB4CcZ3KhINozqBsulznagvOqb9zfMAyapgGqe82vOGPboWEm1MAIn6Ri78C0+nmBLzvOhBsbf1Wd/eLLzHKLjfnhhj9IoPSNgsmLafniEmFj/wx/uok/Ug6w7cNl2YKc+i9iAxI\ +D+rFjfPb+PALWRe9NRLCLWR5tGbUnQPv+19OEWs4+0s+Wdl2RlzLL7pka3nv08iz0pfV/rMR/qDwp99XZgk/K1RxUaRFGReJe9PcrpYfZFDHY5W7wdqszOD3h9Z8tc9vQkJxUpTjMvn0P3ZbiIQ=\ """))) diff --git a/tools/gen_esp32part.py b/tools/gen_esp32part.py index fdb5009e..3406478c 100755 --- a/tools/gen_esp32part.py +++ b/tools/gen_esp32part.py @@ -166,8 +166,8 @@ class PartitionTable(list): for p in self: if p.type == ptype and p.subtype == subtype: - return p - return None + yield p + return def find_by_name(self, name): for p in self: diff --git a/tools/platformio-build-esp32.py b/tools/platformio-build-esp32.py index 9562b145..877f18f3 100644 --- a/tools/platformio-build-esp32.py +++ b/tools/platformio-build-esp32.py @@ -118,8 +118,8 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "lwip", "lwip", "src", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "lwip", "port", "esp32", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "lwip", "port", "esp32", "include", "arch"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "src", "esp32"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "src", "esp32"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "hal", "esp32", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "hal", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_rom", "include"), @@ -136,6 +136,7 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espcoredump", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_timer", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_ipc", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_pm", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "soc", "esp32"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "soc", "esp32", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "soc", "include"), @@ -229,7 +230,7 @@ env.Append( ], LIBS=[ - "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lbt", "-lcbor", "-lunity", "-lcmock", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lspiffs", "-lulp", "-lwifi_provisioning", "-lesp-face", "-lesp32-camera", "-lfb_gfx", "-lasio", "-lcbor", "-lcmock", "-lunity", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_local_ctrl", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lesp-face", "-lpe", "-lfd", "-lfr", "-ldetection_cat_face", "-ldetection", "-ldl", "-lesp32-camera", "-lfb_gfx", "-lbt", "-lbtdm_app", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lwear_levelling", "-lopenssl", "-lspiffs", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxt_hal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" + "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lbt", "-lcbor", "-lunity", "-lcmock", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lspiffs", "-lulp", "-lwifi_provisioning", "-lesp-face", "-lesp32-camera", "-lfb_gfx", "-lasio", "-lcbor", "-lcmock", "-lunity", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_local_ctrl", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lesp-face", "-lpe", "-lfd", "-lfr", "-ldetection_cat_face", "-ldetection", "-ldl", "-lesp32-camera", "-lfb_gfx", "-lbt", "-lbtdm_app", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lwear_levelling", "-lopenssl", "-lspiffs", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxt_hal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" ], CPPDEFINES=[ @@ -238,7 +239,7 @@ env.Append( "UNITY_INCLUDE_CONFIG_H", "WITH_POSIX", "_GNU_SOURCE", - ("IDF_VER", '\\"v4.3-dev-1197-g8bc19ba89-dirty\\"'), + ("IDF_VER", '\\"v4.3-dev-1472-g0b71a0a46-dirty\\"'), "ESP_PLATFORM", "ARDUINO_ARCH_ESP32", "ESP32", diff --git a/tools/platformio-build-esp32s2.py b/tools/platformio-build-esp32s2.py index d4879303..f62fc09e 100644 --- a/tools/platformio-build-esp32s2.py +++ b/tools/platformio-build-esp32s2.py @@ -112,9 +112,9 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "lwip", "lwip", "src", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "lwip", "port", "esp32", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "lwip", "port", "esp32", "include", "arch"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "src", "esp32s2"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "src", "esp32s2", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "hal", "esp32s2", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "hal", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_rom", "include"), @@ -131,6 +131,7 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espcoredump", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_timer", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_ipc", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_pm", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "soc", "esp32s2"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "soc", "esp32s2", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "soc", "include"), @@ -223,7 +224,7 @@ env.Append( ], LIBS=[ - "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lcbor", "-lunity", "-lcmock", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lperfmon", "-lspiffs", "-lulp", "-lwifi_provisioning", "-lesp-face", "-lfb_gfx", "-lasio", "-lcbor", "-lcmock", "-lunity", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_local_ctrl", "-lesp_https_server", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lperfmon", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lesp-face", "-lpe", "-lfd", "-lfr", "-ldetection_cat_face", "-ldetection", "-ldl", "-lfb_gfx", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lwear_levelling", "-lopenssl", "-lspiffs", "-ltinyusb", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxt_hal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" + "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lcbor", "-lunity", "-lcmock", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lperfmon", "-lspiffs", "-lulp", "-lwifi_provisioning", "-lesp-face", "-lfb_gfx", "-lasio", "-lcbor", "-lcmock", "-lunity", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_local_ctrl", "-lesp_https_server", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lperfmon", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lesp-face", "-lpe", "-lfd", "-lfr", "-ldetection_cat_face", "-ldetection", "-ldl", "-lfb_gfx", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lwear_levelling", "-lopenssl", "-lspiffs", "-ltinyusb", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lesp_pm", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lhal", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lsdmmc", "-lesp_serial_slave_link", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxt_hal", "-lesp32s2", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" ], CPPDEFINES=[ @@ -232,7 +233,7 @@ env.Append( "UNITY_INCLUDE_CONFIG_H", "WITH_POSIX", "_GNU_SOURCE", - ("IDF_VER", '\\"v4.3-dev-1197-g8bc19ba89-dirty\\"'), + ("IDF_VER", '\\"v4.3-dev-1472-g0b71a0a46-dirty\\"'), "ESP_PLATFORM", "ARDUINO_ARCH_ESP32", "ESP32", diff --git a/tools/sdk/esp32/bin/bootloader_dio_40m.bin b/tools/sdk/esp32/bin/bootloader_dio_40m.bin index 17f7ebba..f3566bf3 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dio_40m.bin and b/tools/sdk/esp32/bin/bootloader_dio_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_dio_80m.bin b/tools/sdk/esp32/bin/bootloader_dio_80m.bin index 35769905..dac47a10 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dio_80m.bin and b/tools/sdk/esp32/bin/bootloader_dio_80m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_dout_40m.bin b/tools/sdk/esp32/bin/bootloader_dout_40m.bin index 17f7ebba..f3566bf3 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dout_40m.bin and b/tools/sdk/esp32/bin/bootloader_dout_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_dout_80m.bin b/tools/sdk/esp32/bin/bootloader_dout_80m.bin index 35769905..dac47a10 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dout_80m.bin and b/tools/sdk/esp32/bin/bootloader_dout_80m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qio_40m.bin b/tools/sdk/esp32/bin/bootloader_qio_40m.bin index 17f7ebba..f3566bf3 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qio_40m.bin and b/tools/sdk/esp32/bin/bootloader_qio_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qio_80m.bin b/tools/sdk/esp32/bin/bootloader_qio_80m.bin index 35769905..dac47a10 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qio_80m.bin and b/tools/sdk/esp32/bin/bootloader_qio_80m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qout_40m.bin b/tools/sdk/esp32/bin/bootloader_qout_40m.bin index 17f7ebba..f3566bf3 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qout_40m.bin and b/tools/sdk/esp32/bin/bootloader_qout_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qout_80m.bin b/tools/sdk/esp32/bin/bootloader_qout_80m.bin index 35769905..dac47a10 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qout_80m.bin and b/tools/sdk/esp32/bin/bootloader_qout_80m.bin differ diff --git a/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h b/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h index e444271e..baf36702 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h +++ b/tools/sdk/esp32/include/bootloader_support/include/bootloader_common.h @@ -21,6 +21,8 @@ #include "esp32/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" #endif #ifdef __cplusplus @@ -167,6 +169,13 @@ esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t */ uint8_t bootloader_common_get_chip_revision(void); +/** + * @brief Get chip package + * + * @return Chip package number + */ +uint32_t bootloader_common_get_chip_ver_pkg(void); + /** * @brief Query reset reason * diff --git a/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash.h b/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash.h new file mode 100644 index 00000000..5b745965 --- /dev/null +++ b/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash.h @@ -0,0 +1,30 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include /* including in bootloader for error values */ +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_CACHE_SUPPORT_WRAP +/** + * @brief Set the burst mode setting command for specified wrap mode. + * + * @param mode The specified warp mode. + * @return always ESP_OK + */ +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); +#endif + diff --git a/tools/sdk/esp32/include/bootloader_support/include/esp_flash_encrypt.h b/tools/sdk/esp32/include/bootloader_support/include/esp_flash_encrypt.h index fc1b3729..ef3b8027 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/esp_flash_encrypt.h +++ b/tools/sdk/esp32/include/bootloader_support/include/esp_flash_encrypt.h @@ -49,7 +49,7 @@ typedef enum { */ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_enabled(void) { - uint32_t flash_crypt_cnt; + uint32_t flash_crypt_cnt = 0; #if CONFIG_IDF_TARGET_ESP32 flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); #elif CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_a2dp_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_a2dp_api.h index 903b17c3..e300d322 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_a2dp_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_a2dp_api.h @@ -77,7 +77,7 @@ typedef enum { /// A2DP media control commands typedef enum { - ESP_A2D_MEDIA_CTRL_NONE = 0, /*!< dummy command */ + ESP_A2D_MEDIA_CTRL_NONE = 0, /*!< Not for application use, use inside stack only. */ ESP_A2D_MEDIA_CTRL_CHECK_SRC_RDY, /*!< check whether AVDTP is connected, only used in A2DP source */ ESP_A2D_MEDIA_CTRL_START, /*!< command to set up media transmission channel */ ESP_A2D_MEDIA_CTRL_STOP, /*!< command to stop media transmission */ @@ -194,7 +194,8 @@ esp_err_t esp_a2d_sink_register_data_callback(esp_a2d_sink_data_cb_t callback); /** * * @brief Initialize the bluetooth A2DP sink module. This function should be called - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully. Note: A2DP can work independently. + * If you want to use AVRC together, you should initiate AVRC first. * * @return * - ESP_OK: if the initialization request is sent successfully @@ -265,7 +266,8 @@ esp_err_t esp_a2d_media_ctrl(esp_a2d_media_ctrl_t ctrl); /** * * @brief Initialize the bluetooth A2DP source module. This function should be called - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully. Note: A2DP can work independently. + * If you want to use AVRC together, you should initiate AVRC first. * * @return * - ESP_OK: if the initialization request is sent successfully diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_avrc_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_avrc_api.h index e75eb637..2f4f1eee 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_avrc_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_avrc_api.h @@ -414,7 +414,8 @@ esp_err_t esp_avrc_ct_register_callback(esp_avrc_ct_cb_t callback); /** * * @brief Initialize the bluetooth AVRCP controller module, This function should be called - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully. Note: AVRC cannot work independently, + * AVRC should be used along with A2DP and AVRC should be initialized before A2DP. * * @return * - ESP_OK: success @@ -427,7 +428,8 @@ esp_err_t esp_avrc_ct_init(void); /** * * @brief De-initialize AVRCP controller module. This function should be called after - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully. Note: AVRC cannot work independently, + * AVRC should be used along with A2DP and AVRC should be deinitialized before A2DP. * * @return * - ESP_OK: success @@ -543,7 +545,8 @@ esp_err_t esp_avrc_tg_register_callback(esp_avrc_tg_cb_t callback); /** * * @brief Initialize the bluetooth AVRCP target module, This function should be called - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully. Note: AVRC cannot work independently, + * AVRC should be used along with A2DP and AVRC should be initialized before A2DP. * * @return * - ESP_OK: success @@ -556,7 +559,8 @@ esp_err_t esp_avrc_tg_init(void); /** * * @brief De-initialize AVRCP target module. This function should be called after - * after esp_bluedroid_enable() completes successfully + * after esp_bluedroid_enable() completes successfully. Note: AVRC cannot work independently, + * AVRC should be used along with A2DP and AVRC should be deinitialized before A2DP. * * @return * - ESP_OK: success diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h index 4ecc64a3..66fffb7d 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h @@ -221,6 +221,7 @@ typedef enum { ESP_BT_GAP_SET_AFH_CHANNELS_EVT, /*!< set AFH channels event */ ESP_BT_GAP_READ_REMOTE_NAME_EVT, /*!< read Remote Name event */ ESP_BT_GAP_MODE_CHG_EVT, + ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT, /*!< remove bond device complete event */ ESP_BT_GAP_EVT_MAX, } esp_bt_gap_cb_event_t; @@ -355,6 +356,14 @@ typedef union { esp_bt_pm_mode_t mode; /*!< PM mode*/ } mode_chg; /*!< mode change event parameter struct */ + /** + * @brief ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT + */ + struct bt_remove_bond_dev_cmpl_evt_param { + esp_bd_addr_t bda; /*!< remote bluetooth device address*/ + esp_bt_status_t status; /*!< Indicate the remove bond device operation success status */ + }remove_bond_dev_cmpl; /*!< Event parameter of ESP_BT_GAP_REMOVE_BOND_DEV_COMPLETE_EVT */ + } esp_bt_gap_cb_param_t; /** diff --git a/tools/sdk/esp32/include/config/sdkconfig.h b/tools/sdk/esp32/include/config/sdkconfig.h index 858300ae..216a2f70 100644 --- a/tools/sdk/esp32/include/config/sdkconfig.h +++ b/tools/sdk/esp32/include/config/sdkconfig.h @@ -23,7 +23,6 @@ #define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 #define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 -#define CONFIG_ESPTOOLPY_WITH_STUB 1 #define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 #define CONFIG_ESPTOOLPY_FLASHMODE "dio" #define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1 @@ -219,6 +218,7 @@ #define CONFIG_ESP_NETIF_TCPIP_LWIP 1 #define CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER 1 #define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1 +#define CONFIG_ESP_TIMER_RTC_USE 1 #define CONFIG_ESP_TIMER_TASK_STACK_SIZE 4096 #define CONFIG_ESP_TIMER_IMPL_TG0_LAC 1 #define CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE 1 @@ -240,7 +240,7 @@ #define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE 1 #define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20 #define CONFIG_ESP32_PHY_MAX_TX_POWER 20 -#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1 +#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1 #define CONFIG_FATFS_CODEPAGE_850 1 #define CONFIG_FATFS_CODEPAGE 850 #define CONFIG_FATFS_LFN_STACK 1 @@ -461,6 +461,7 @@ #define CONFIG_MFN56_1X 1 #define CONFIG_HD_NANO1 1 #define CONFIG_HP_NANO1 1 +#define CONFIG_OV7670_SUPPORT 1 #define CONFIG_OV2640_SUPPORT 1 #define CONFIG_OV3660_SUPPORT 1 #define CONFIG_OV5640_SUPPORT 1 @@ -497,6 +498,7 @@ #define CONFIG_ESP32S2_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT #define CONFIG_ESP32_APPTRACE_DEST_NONE CONFIG_APPTRACE_DEST_NONE #define CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE CONFIG_ESP_COREDUMP_ENABLE_TO_NONE #define CONFIG_ESP32_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT #define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN #define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT @@ -579,5 +581,5 @@ #define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED #define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS -#define CONFIG_ARDUINO_IDF_COMMIT "8bc19ba89" -#define CONFIG_ARDUINO_IDF_BRANCH "master" +#define CONFIG_ARDUINO_IDF_COMMIT "" +#define CONFIG_ARDUINO_IDF_BRANCH "release/v4.2" diff --git a/tools/sdk/esp32/include/driver/include/driver/twai.h b/tools/sdk/esp32/include/driver/include/driver/twai.h index 383a9956..ef240a38 100644 --- a/tools/sdk/esp32/include/driver/include/driver/twai.h +++ b/tools/sdk/esp32/include/driver/include/driver/twai.h @@ -40,10 +40,11 @@ extern "C" { * configured. The other members of the general configuration structure are * assigned default values. */ -#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ - .clkout_io = TWAI_IO_UNUSED, .bus_off_io = TWAI_IO_UNUSED, \ - .tx_queue_len = 5, .rx_queue_len = 5, \ - .alerts_enabled = TWAI_ALERT_NONE, .clkout_divider = 0, } +#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ + .clkout_io = TWAI_IO_UNUSED, .bus_off_io = TWAI_IO_UNUSED, \ + .tx_queue_len = 5, .rx_queue_len = 5, \ + .alerts_enabled = TWAI_ALERT_NONE, .clkout_divider = 0, \ + .intr_flags = ESP_INTR_FLAG_LEVEL1} /** * @brief Alert flags @@ -70,7 +71,7 @@ extern "C" { #define TWAI_ALERT_BUS_OFF 0x1000 /**< Alert(4096): Bus-off condition occurred. TWAI controller can no longer influence bus */ #define TWAI_ALERT_ALL 0x1FFF /**< Bit mask to enable all alerts during configuration */ #define TWAI_ALERT_NONE 0x0000 /**< Bit mask to disable all alerts during configuration */ -#define TWAI_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur */ +#define TWAI_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur. Note that logging from the ISR is disabled if CONFIG_TWAI_ISR_IN_IRAM is enabled (see docs). */ /** @endcond */ @@ -103,6 +104,7 @@ typedef struct { uint32_t rx_queue_len; /**< Number of messages RX queue can hold */ uint32_t alerts_enabled; /**< Bit field of alerts to enable (see documentation) */ uint32_t clkout_divider; /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */ + int intr_flags; /**< Interrupt flags to set the priority of the driver's ISR. Note that to use the ESP_INTR_FLAG_IRAM, the CONFIG_TWAI_ISR_IN_IRAM option should be enabled first. */ } twai_general_config_t; /** diff --git a/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h b/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h index 3afd9a48..71fcc6df 100644 --- a/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h +++ b/tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 8c9f6537b47cc5b26a1a5896158c612a +// md5_digest_table f552d73ac112985991efa6734a60c8d9 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. diff --git a/tools/sdk/esp32/include/efuse/include/esp32s3/esp_efuse.h b/tools/sdk/esp32/include/efuse/include/esp32s3/esp_efuse.h new file mode 100644 index 00000000..c33eca5b --- /dev/null +++ b/tools/sdk/esp32/include/efuse/include/esp32s3/esp_efuse.h @@ -0,0 +1,69 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32S3 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/efuse/include/esp_efuse.h b/tools/sdk/esp32/include/efuse/include/esp_efuse.h index ab792a49..84d03c5a 100644 --- a/tools/sdk/esp32/include/efuse/include/esp_efuse.h +++ b/tools/sdk/esp32/include/efuse/include/esp_efuse.h @@ -27,6 +27,8 @@ extern "C" { #include "esp32/esp_efuse.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/esp_efuse.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/esp_efuse.h" #endif #define ESP_ERR_EFUSE 0x1600 /*!< Base error code for efuse api. */ diff --git a/tools/sdk/esp32/include/esp-tls/esp_tls.h b/tools/sdk/esp32/include/esp-tls/esp_tls.h index 10941700..752c18e1 100644 --- a/tools/sdk/esp32/include/esp-tls/esp_tls.h +++ b/tools/sdk/esp32/include/esp-tls/esp_tls.h @@ -205,6 +205,7 @@ typedef struct esp_tls_cfg { /*!< Function pointer to esp_crt_bundle_attach. Enables the use of certification bundle for server verification, must be enabled in menuconfig */ + void *ds_data; /*!< Pointer for digital signature peripheral context */ } esp_tls_cfg_t; #ifdef CONFIG_ESP_TLS_SERVER diff --git a/tools/sdk/esp32/include/esp32-camera/driver/include/sensor.h b/tools/sdk/esp32/include/esp32-camera/driver/include/sensor.h index 3ea7e2ce..b899118a 100755 --- a/tools/sdk/esp32/include/esp32-camera/driver/include/sensor.h +++ b/tools/sdk/esp32/include/esp32-camera/driver/include/sensor.h @@ -16,6 +16,7 @@ #define OV2640_PID (0x26) #define OV3660_PID (0x36) #define OV5640_PID (0x56) +#define OV7670_PID (0x76) typedef enum { PIXFORMAT_RGB565, // 2BPP/RGB565 diff --git a/tools/sdk/esp32/include/esp_eth/include/esp_eth_mac.h b/tools/sdk/esp32/include/esp_eth/include/esp_eth_mac.h index f12c66ae..a9052eee 100644 --- a/tools/sdk/esp32/include/esp_eth/include/esp_eth_mac.h +++ b/tools/sdk/esp32/include/esp_eth/include/esp_eth_mac.h @@ -298,8 +298,8 @@ typedef struct { uint32_t sw_reset_timeout_ms; /*!< Software reset timeout value (Unit: ms) */ uint32_t rx_task_stack_size; /*!< Stack size of the receive task */ uint32_t rx_task_prio; /*!< Priority of the receive task */ - int smi_mdc_gpio_num; /*!< SMI MDC GPIO number */ - int smi_mdio_gpio_num; /*!< SMI MDIO GPIO number */ + int smi_mdc_gpio_num; /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */ + int smi_mdio_gpio_num; /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */ uint32_t flags; /*!< Flags that specify extra capability for mac driver */ } eth_mac_config_t; diff --git a/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h index a942426a..a6da8573 100644 --- a/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h @@ -537,7 +537,7 @@ int esp_http_client_read_response(esp_http_client_handle_t client, char *buffer, * - ESP_FAIL If failed to read response * - ESP_ERR_INVALID_ARG If the client is NULL */ -int esp_http_client_flush_response(esp_http_client_handle_t client, int *len); +esp_err_t esp_http_client_flush_response(esp_http_client_handle_t client, int *len); /** * @brief Get URL from client diff --git a/tools/sdk/esp32/include/esp32/include/esp32/pm.h b/tools/sdk/esp32/include/esp_pm/include/esp32/pm.h similarity index 100% rename from tools/sdk/esp32/include/esp32/include/esp32/pm.h rename to tools/sdk/esp32/include/esp_pm/include/esp32/pm.h diff --git a/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/pm.h b/tools/sdk/esp32/include/esp_pm/include/esp32s2/pm.h similarity index 100% rename from tools/sdk/esp32s2/include/esp32s2/include/esp32s2/pm.h rename to tools/sdk/esp32/include/esp_pm/include/esp32s2/pm.h diff --git a/tools/sdk/esp32/include/esp_pm/include/esp32s3/pm.h b/tools/sdk/esp32/include/esp_pm/include/esp32s3/pm.h new file mode 100644 index 00000000..0b29c66a --- /dev/null +++ b/tools/sdk/esp32/include/esp_pm/include/esp32s3/pm.h @@ -0,0 +1,42 @@ +// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once +#include +#include +#include "esp_err.h" + +#include "soc/rtc.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Power management config for ESP32 + * + * Pass a pointer to this structure as an argument to esp_pm_configure function. + */ +typedef struct { + int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */ + int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */ + bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */ +} esp_pm_config_esp32s3_t; + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_common/include/esp_pm.h b/tools/sdk/esp32/include/esp_pm/include/esp_pm.h similarity index 99% rename from tools/sdk/esp32/include/esp_common/include/esp_pm.h rename to tools/sdk/esp32/include/esp_pm/include/esp_pm.h index 15af6a4a..d15a904b 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_pm.h +++ b/tools/sdk/esp32/include/esp_pm/include/esp_pm.h @@ -21,6 +21,8 @@ #include "esp32/pm.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/pm.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/pm.h" #endif #ifdef __cplusplus @@ -175,8 +177,6 @@ esp_err_t esp_pm_lock_delete(esp_pm_lock_handle_t handle); */ esp_err_t esp_pm_dump_locks(FILE* stream); - - #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_private/pm_impl.h b/tools/sdk/esp32/include/esp_pm/include/esp_private/pm_impl.h similarity index 98% rename from tools/sdk/esp32s2/include/esp_common/include/esp_private/pm_impl.h rename to tools/sdk/esp32/include/esp_pm/include/esp_private/pm_impl.h index 71d41bd7..122190f2 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_private/pm_impl.h +++ b/tools/sdk/esp32/include/esp_pm/include/esp_private/pm_impl.h @@ -26,6 +26,9 @@ #include "esp_timer.h" #include "sdkconfig.h" +#ifdef __cplusplus +extern "C" { +#endif /** * This is an enum of possible power modes supported by the implementation @@ -151,3 +154,7 @@ static inline pm_time_t IRAM_ATTR pm_get_time(void) return esp_timer_get_time(); } #endif // WITH_PROFILING + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_private/pm_trace.h b/tools/sdk/esp32/include/esp_pm/include/esp_private/pm_trace.h similarity index 95% rename from tools/sdk/esp32s2/include/esp_common/include/esp_private/pm_trace.h rename to tools/sdk/esp32/include/esp_pm/include/esp_private/pm_trace.h index 24e67190..7bc35c15 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_private/pm_trace.h +++ b/tools/sdk/esp32/include/esp_pm/include/esp_private/pm_trace.h @@ -16,6 +16,10 @@ #include "sdkconfig.h" +#ifdef __cplusplus +extern "C" { +#endif + typedef enum { ESP_PM_TRACE_IDLE, ESP_PM_TRACE_TICK, @@ -43,3 +47,7 @@ void esp_pm_trace_exit(esp_pm_trace_event_t event, int core_id); #define ESP_PM_TRACE_EXIT(type, core_id) do { (void) core_id; } while(0) #endif // CONFIG_PM_TRACE + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h index 1ec326ca..259e7bab 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h @@ -81,11 +81,11 @@ typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; * * This function is used to verify the bootloader before burning its public key hash into Efuse. * Also, it is used to verify the app on loading the image on boot and on OTA. - * + * * @param sig The signature block flashed aligned 4096 bytes from the firmware. * @param image_digest The SHA-256 Digest of the firmware to be verified * @param trusted_key_digest The SHA-256 Digest of the public key (ets_rsa_pubkey_t) of a single signature block. - * @param verified_digest RSA-PSS signature of image_digest. Pass an uninitialised array. + * @param verified_digest RSA-PSS signature of image_digest. Pass an uninitialised array. * * @return SBV2_SUCCESS if signature is valid * SBV2_FAILED for failures. @@ -94,16 +94,16 @@ secure_boot_v2_status_t ets_secure_boot_verify_signature(const ets_secure_boot_s /** @brief This function verifies the 1st stage bootloader. Implemented in the ROM. * Reboots post verification. It reads the Efuse key for verification of the public key. - * + * * This function is not used in the current workflow. - * + * */ void ets_secure_boot_verify_boot_bootloader(void); /** @brief Confirms if the secure boot V2 has been enabled. Implemented in the ROM. - * + * * In ESP32-ECO3 - It checks the value of ABS_DONE_1 in EFuse. - * + * * @return true if is Secure boot v2 has been enabled * False if Secure boot v2 has not been enabled. */ @@ -111,4 +111,8 @@ bool ets_use_secure_boot_v2(void); #endif /* CONFIG_ESP32_REV_MIN_3 */ +#ifdef __cplusplus +} +#endif + #endif /* _ROM_SECURE_BOOT_H_ */ \ No newline at end of file diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/sha.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/sha.h index 323749ef..f43c19d1 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/sha.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/sha.h @@ -24,6 +24,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -44,7 +45,7 @@ enum SHA_TYPE { SHA_INVALID = -1, }; -/* Do not use these function in multi core mode due to +/* Do not use these function in multi core mode due to * inside they have no safe implementation (without DPORT workaround). */ void ets_sha_init(SHA_CTX *ctx); diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/spi_flash.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/spi_flash.h index b78a6130..c71b8100 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/spi_flash.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/spi_flash.h @@ -121,6 +121,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) //Extra dummy for flash read #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/opi_flash.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/opi_flash.h index bb209f67..c985810b 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/opi_flash.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/opi_flash.h @@ -40,6 +40,7 @@ typedef struct { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_OP_MODE_RDCMD_DOUT 0x3B #define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/spi_flash.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/spi_flash.h index 1eee20a5..2cf63166 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/spi_flash.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/spi_flash.h @@ -119,6 +119,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_ID_GD25LQ32C 0xC86016 diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h index 432c65ef..1df00a1d 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h @@ -21,8 +21,6 @@ extern "C" { #endif -#define AES_BLOCK_SIZE (16) - enum AES_TYPE { AES_ENC, AES_DEC, diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/opi_flash.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/opi_flash.h new file mode 100644 index 00000000..be7fcb06 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/opi_flash.h @@ -0,0 +1,300 @@ +/* + * copyright (c) Espressif System 2019 + * + */ + +#ifndef _ROM_OPI_FLASH_H_ +#define _ROM_OPI_FLASH_H_ +#include +#include +#include +#include "spi_flash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint16_t cmd; /*!< Command value */ + uint16_t cmdBitLen; /*!< Command byte length*/ + uint32_t *addr; /*!< Point to address value*/ + uint32_t addrBitLen; /*!< Address byte length*/ + uint32_t *txData; /*!< Point to send data buffer*/ + uint32_t txDataBitLen; /*!< Send data byte length.*/ + uint32_t *rxData; /*!< Point to recevie data buffer*/ + uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/ + uint32_t dummyBitLen; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +// Definition of MX25UM25645G Octa Flash +// SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +// FLASH commands +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +// Definitions for GigaDevice GD25LX256E Flash +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +// spi user mode command config + +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission + */ +void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ +void esp_rom_opiflash_pin_config(void); + +// set SPI read/write mode +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ +void esp_rom_opiflash_mode_reset(int spi_num); + +#if 0 +// MX25UM25645G opi flash interface +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase flash operation + */ +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash ID(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash id + */ +uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash status register(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash status value + */ +uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief wait opi flash status register to be idle + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of configure register + * @return value of config register2 + */ +uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr); + +/** + * @brief to write the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of config register + * @param val the value to write + */ +void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val); + +/** + * @brief to erase flash sector(for MX25UM25645G) + * @param spi_num spi port + * @param address the sector address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase flash block(for MX25UM25645G) + * @param spi_num spi port + * @param address the block address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase a flash area define by start address and length(for MX25UM25645G) + * @param spi_num spi port + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @param mode flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read data from opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len); + +/** + * @brief to write data to opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len); + +/** + * @brief to set opi flash operation mode(for MX25UM25645G) + * @param spi_num spi port + * @param cur_mode current operation mode + * @param target the target operation mode to be set + */ +void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h index 15adc528..a5a1ecb6 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h @@ -16,8 +16,7 @@ #include #include -#include "ets_sys.h" -#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h index fb060c15..44d447e9 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h @@ -111,6 +111,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_ID_GD25LQ32C 0xC86016 diff --git a/tools/sdk/esp32/include/esp_system/include/esp_async_memcpy.h b/tools/sdk/esp32/include/esp_system/include/esp_async_memcpy.h new file mode 100644 index 00000000..67194e44 --- /dev/null +++ b/tools/sdk/esp32/include/esp_system/include/esp_async_memcpy.h @@ -0,0 +1,115 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "esp_err.h" + +/** + * @brief Type of async memcpy handle + * + */ +typedef struct async_memcpy_context_t *async_memcpy_t; + +/** + * @brief Type of async memcpy event object + * + */ +typedef struct { + void *data; /*!< Event data */ +} async_memcpy_event_t; + +/** + * @brief Type of async memcpy interrupt callback function + * + * @param mcp_hdl Handle of async memcpy + * @param event Event object, which contains related data, reserved for future + * @param cb_args User defined arguments, passed from esp_async_memcpy function + * @return Whether a high priority task is woken up by the callback function + * + * @note User can call OS primitives (semaphore, mutex, etc) in the callback function. + * Keep in mind, if any OS primitive wakes high priority task up, the callback should return true. + */ +typedef bool (*async_memcpy_isr_cb_t)(async_memcpy_t mcp_hdl, async_memcpy_event_t *event, void *cb_args); + +/** + * @brief Type of async memcpy configuration + * + */ +typedef struct { + uint32_t backlog; /*!< Maximum number of streams that can be handled simultaneously */ + uint32_t flags; /*!< Extra flags to control async memcpy feature */ +} async_memcpy_config_t; + +/** + * @brief Default configuration for async memcpy + * + */ +#define ASYNC_MEMCPY_DEFAULT_CONFIG() \ + { \ + .backlog = 8, \ + .flags = 0, \ + } + +/** + * @brief Install async memcpy driver + * + * @param[in] config Configuration of async memcpy + * @param[out] asmcp Handle of async memcpy that returned from this API. If driver installation is failed, asmcp would be assigned to NULL. + * @return + * - ESP_OK: Install async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Install async memcpy driver failed because of invalid argument + * - ESP_ERR_NO_MEM: Install async memcpy driver failed because out of memory + * - ESP_FAIL: Install async memcpy driver failed because of other error + */ +esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_t *asmcp); + +/** + * @brief Uninstall async memcpy driver + * + * @param[in] asmcp Handle of async memcpy driver that returned from esp_async_memcpy_install + * @return + * - ESP_OK: Uninstall async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Uninstall async memcpy driver failed because of invalid argument + * - ESP_FAIL: Uninstall async memcpy driver failed because of other error + */ +esp_err_t esp_async_memcpy_uninstall(async_memcpy_t asmcp); + +/** + * @brief Send an asynchronous memory copy request + * + * @param[in] asmcp Handle of async memcpy driver that returned from esp_async_memcpy_install + * @param[in] dst Destination address (copy to) + * @param[in] src Source address (copy from) + * @param[in] n Number of bytes to copy + * @param[in] cb_isr Callback function, which got invoked in interrupt context. Set to NULL can bypass the callback. + * @param[in] cb_args User defined argument to be passed to the callback function + * @return + * - ESP_OK: Send memory copy request successfully + * - ESP_ERR_INVALID_ARG: Send memory copy request failed because of invalid argument + * - ESP_FAIL: Send memory copy request failed because of other error + * + * @note The callback function is invoked in interrupt context, never do blocking jobs in the callback. + */ +esp_err_t esp_async_memcpy(async_memcpy_t asmcp, void *dst, void *src, size_t n, async_memcpy_isr_cb_t cb_isr, void *cb_args); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp32/include/esp_intr_alloc.h b/tools/sdk/esp32/include/esp_system/include/esp_intr_alloc.h similarity index 94% rename from tools/sdk/esp32/include/esp32/include/esp_intr_alloc.h rename to tools/sdk/esp32/include/esp_system/include/esp_intr_alloc.h index 67aca5b7..ace95cbb 100644 --- a/tools/sdk/esp32/include/esp32/include/esp_intr_alloc.h +++ b/tools/sdk/esp32/include/esp_system/include/esp_intr_alloc.h @@ -18,7 +18,6 @@ #include #include #include "esp_err.h" -#include "freertos/xtensa_api.h" #ifdef __cplusplus extern "C" { @@ -68,9 +67,9 @@ extern "C" { * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources, * pass these pseudo-sources to the functions. */ -#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 ///< Xtensa timer 0 interrupt source -#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 ///< Xtensa timer 1 interrupt source -#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 ///< Xtensa timer 2 interrupt source +#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 ///< Platform timer 0 interrupt source +#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 ///< Platform timer 1 interrupt source +#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 ///< Platform timer 2 interrupt source #define ETS_INTERNAL_SW0_INTR_SOURCE -4 ///< Software int source 1 #define ETS_INTERNAL_SW1_INTR_SOURCE -5 ///< Software int source 2 #define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 ///< Int source for profiling @@ -82,10 +81,10 @@ extern "C" { #define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE) /** Enable interrupt by interrupt number */ -#define ESP_INTR_ENABLE(inum) xt_ints_on((1< #include "esp_rom_sys.h" #include "sdkconfig.h" +#include "freertos/xtensa_api.h" #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS #include "soc/soc_memory_layout.h" #endif -//#include "xtensa_context.h" - /*----------------------------------------------------------- * Port specific definitions. * diff --git a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_api.h b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_api.h index 19630ce5..bdfd7151 100644 --- a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_api.h +++ b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_api.h @@ -1,130 +1,2 @@ -/******************************************************************************* -Copyright (c) 2006-2015 Cadence Design Systems Inc. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be included -in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -******************************************************************************/ - -/****************************************************************************** - Xtensa-specific API for RTOS ports. -******************************************************************************/ - -#ifndef __XTENSA_API_H__ -#define __XTENSA_API_H__ - -#include - -#include "xtensa_context.h" - - -/* Typedef for C-callable interrupt handler function */ -typedef void (*xt_handler)(void *); - -/* Typedef for C-callable exception handler function */ -typedef void (*xt_exc_handler)(XtExcFrame *); - - -/* -------------------------------------------------------------------------------- - Call this function to set a handler for the specified exception. The handler - will be installed on the core that calls this function. - - n - Exception number (type) - f - Handler function address, NULL to uninstall handler. - - The handler will be passed a pointer to the exception frame, which is created - on the stack of the thread that caused the exception. - - If the handler returns, the thread context will be restored and the faulting - instruction will be retried. Any values in the exception frame that are - modified by the handler will be restored as part of the context. For details - of the exception frame structure see xtensa_context.h. -------------------------------------------------------------------------------- -*/ -extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f); - - -/* -------------------------------------------------------------------------------- - Call this function to set a handler for the specified interrupt. The handler - will be installed on the core that calls this function. - - n - Interrupt number. - f - Handler function address, NULL to uninstall handler. - arg - Argument to be passed to handler. -------------------------------------------------------------------------------- -*/ -extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg); - - -/* -------------------------------------------------------------------------------- - Call this function to enable the specified interrupts on the core that runs - this code. - - mask - Bit mask of interrupts to be enabled. -------------------------------------------------------------------------------- -*/ -extern void xt_ints_on(unsigned int mask); - - -/* -------------------------------------------------------------------------------- - Call this function to disable the specified interrupts on the core that runs - this code. - - mask - Bit mask of interrupts to be disabled. -------------------------------------------------------------------------------- -*/ -extern void xt_ints_off(unsigned int mask); - - -/* -------------------------------------------------------------------------------- - Call this function to set the specified (s/w) interrupt. -------------------------------------------------------------------------------- -*/ -static inline void xt_set_intset(unsigned int arg) -{ - xthal_set_intset(arg); -} - - -/* -------------------------------------------------------------------------------- - Call this function to clear the specified (s/w or edge-triggered) - interrupt. -------------------------------------------------------------------------------- -*/ -static inline void xt_set_intclear(unsigned int arg) -{ - xthal_set_intclear(arg); -} - -/* -------------------------------------------------------------------------------- - Call this function to get handler's argument for the specified interrupt. - - n - Interrupt number. -------------------------------------------------------------------------------- -*/ -extern void * xt_get_interrupt_handler_arg(int n); - -#endif /* __XTENSA_API_H__ */ - +/* This header file has been moved, please include in future */ +#include diff --git a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_context.h b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_context.h index 120676da..1d0f4e58 100644 --- a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_context.h +++ b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/xtensa_context.h @@ -1,387 +1,2 @@ -/******************************************************************************* -Copyright (c) 2006-2015 Cadence Design Systems Inc. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be included -in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. --------------------------------------------------------------------------------- - - XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES - -This header contains definitions and macros for use primarily by Xtensa -RTOS assembly coded source files. It includes and uses the Xtensa hardware -abstraction layer (HAL) to deal with config specifics. It may also be -included in C source files. - -!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !! - -NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. - -*******************************************************************************/ - -#ifndef XTENSA_CONTEXT_H -#define XTENSA_CONTEXT_H - -#ifdef __ASSEMBLER__ -#include -#endif - -#include -#include -#include -#include - - -/* Align a value up to nearest n-byte boundary, where n is a power of 2. */ -#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) - - -/* -------------------------------------------------------------------------------- - Macros that help define structures for both C and assembler. -------------------------------------------------------------------------------- -*/ - -#ifdef STRUCT_BEGIN -#undef STRUCT_BEGIN -#undef STRUCT_FIELD -#undef STRUCT_AFIELD -#undef STRUCT_END -#endif - -#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) - -#define STRUCT_BEGIN .pushsection .text; .struct 0 -#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size -#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) -#define STRUCT_END(sname) sname##Size:; .popsection - -#else - -#define STRUCT_BEGIN typedef struct { -#define STRUCT_FIELD(ctype,size,asname,name) ctype name; -#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; -#define STRUCT_END(sname) } sname; - -#endif //_ASMLANGUAGE || __ASSEMBLER__ - - -/* -------------------------------------------------------------------------------- - INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT - - A stack frame of this structure is allocated for any interrupt or exception. - It goes on the current stack. If the RTOS has a system stack for handling - interrupts, every thread stack must allow space for just one interrupt stack - frame, then nested interrupt stack frames go on the system stack. - - The frame includes basic registers (explicit) and "extra" registers introduced - by user TIE or the use of the MAC16 option in the user's Xtensa config. - The frame size is minimized by omitting regs not applicable to user's config. - - For Windowed ABI, this stack frame includes the interruptee's base save area, - another base save area to manage gcc nested functions, and a little temporary - space to help manage the spilling of the register windows. -------------------------------------------------------------------------------- -*/ - -STRUCT_BEGIN -STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ -STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ -STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ -STRUCT_FIELD (long, 4, XT_STK_A0, a0) -STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ -STRUCT_FIELD (long, 4, XT_STK_A2, a2) -STRUCT_FIELD (long, 4, XT_STK_A3, a3) -STRUCT_FIELD (long, 4, XT_STK_A4, a4) -STRUCT_FIELD (long, 4, XT_STK_A5, a5) -STRUCT_FIELD (long, 4, XT_STK_A6, a6) -STRUCT_FIELD (long, 4, XT_STK_A7, a7) -STRUCT_FIELD (long, 4, XT_STK_A8, a8) -STRUCT_FIELD (long, 4, XT_STK_A9, a9) -STRUCT_FIELD (long, 4, XT_STK_A10, a10) -STRUCT_FIELD (long, 4, XT_STK_A11, a11) -STRUCT_FIELD (long, 4, XT_STK_A12, a12) -STRUCT_FIELD (long, 4, XT_STK_A13, a13) -STRUCT_FIELD (long, 4, XT_STK_A14, a14) -STRUCT_FIELD (long, 4, XT_STK_A15, a15) -STRUCT_FIELD (long, 4, XT_STK_SAR, sar) -STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) -STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) -#if XCHAL_HAVE_LOOPS -STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) -STRUCT_FIELD (long, 4, XT_STK_LEND, lend) -STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) -#endif -#ifndef __XTENSA_CALL0_ABI__ -/* Temporary space for saving stuff during window spill */ -STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) -STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) -STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) -#endif -#ifdef XT_USE_SWPRI -/* Storage for virtual priority mask */ -STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) -#endif -#ifdef XT_USE_OVLY -/* Storage for overlay state */ -STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) -#endif -STRUCT_END(XtExcFrame) - -#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) -#define XT_STK_NEXT1 XtExcFrameSize -#else -#define XT_STK_NEXT1 sizeof(XtExcFrame) -#endif - -/* Allocate extra storage if needed */ -#if XCHAL_EXTRA_SA_SIZE != 0 - -#if XCHAL_EXTRA_SA_ALIGN <= 16 -#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) -#else -/* If need more alignment than stack, add space for dynamic alignment */ -#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) -#endif -#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) - -#else - -#define XT_STK_NEXT2 XT_STK_NEXT1 - -#endif - -/* -------------------------------------------------------------------------------- - This is the frame size. Add space for 4 registers (interruptee's base save - area) and some space for gcc nested functions if any. -------------------------------------------------------------------------------- -*/ -#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) - - -/* -------------------------------------------------------------------------------- - SOLICITED STACK FRAME FOR A THREAD - - A stack frame of this structure is allocated whenever a thread enters the - RTOS kernel intentionally (and synchronously) to submit to thread scheduling. - It goes on the current thread's stack. - - The solicited frame only includes registers that are required to be preserved - by the callee according to the compiler's ABI conventions, some space to save - the return address for returning to the caller, and the caller's PS register. - - For Windowed ABI, this stack frame includes the caller's base save area. - - Note on XT_SOL_EXIT field: - It is necessary to distinguish a solicited from an interrupt stack frame. - This field corresponds to XT_STK_EXIT in the interrupt stack frame and is - always at the same offset (0). It can be written with a code (usually 0) - to distinguish a solicted frame from an interrupt frame. An RTOS port may - opt to ignore this field if it has another way of distinguishing frames. -------------------------------------------------------------------------------- -*/ - -STRUCT_BEGIN -#ifdef __XTENSA_CALL0_ABI__ -STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) -STRUCT_FIELD (long, 4, XT_SOL_PC, pc) -STRUCT_FIELD (long, 4, XT_SOL_PS, ps) -STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) -STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ -STRUCT_FIELD (long, 4, XT_SOL_A13, a13) -STRUCT_FIELD (long, 4, XT_SOL_A14, a14) -STRUCT_FIELD (long, 4, XT_SOL_A15, a15) -#else -STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) -STRUCT_FIELD (long, 4, XT_SOL_PC, pc) -STRUCT_FIELD (long, 4, XT_SOL_PS, ps) -STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) -STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ -STRUCT_FIELD (long, 4, XT_SOL_A1, a1) -STRUCT_FIELD (long, 4, XT_SOL_A2, a2) -STRUCT_FIELD (long, 4, XT_SOL_A3, a3) -#endif -STRUCT_END(XtSolFrame) - -/* Size of solicited stack frame */ -#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) - - -/* -------------------------------------------------------------------------------- - CO-PROCESSOR STATE SAVE AREA FOR A THREAD - - The RTOS must provide an area per thread to save the state of co-processors - when that thread does not have control. Co-processors are context-switched - lazily (on demand) only when a new thread uses a co-processor instruction, - otherwise a thread retains ownership of the co-processor even when it loses - control of the processor. An Xtensa co-processor exception is triggered when - any co-processor instruction is executed by a thread that is not the owner, - and the context switch of that co-processor is then peformed by the handler. - Ownership represents which thread's state is currently in the co-processor. - - Co-processors may not be used by interrupt or exception handlers. If an - co-processor instruction is executed by an interrupt or exception handler, - the co-processor exception handler will trigger a kernel panic and freeze. - This restriction is introduced to reduce the overhead of saving and restoring - co-processor state (which can be quite large) and in particular remove that - overhead from interrupt handlers. - - The co-processor state save area may be in any convenient per-thread location - such as in the thread control block or above the thread stack area. It need - not be in the interrupt stack frame since interrupts don't use co-processors. - - Along with the save area for each co-processor, two bitmasks with flags per - co-processor (laid out as in the CPENABLE reg) help manage context-switching - co-processors as efficiently as possible: - - XT_CPENABLE - The contents of a non-running thread's CPENABLE register. - It represents the co-processors owned (and whose state is still needed) - by the thread. When a thread is preempted, its CPENABLE is saved here. - When a thread solicits a context-swtich, its CPENABLE is cleared - the - compiler has saved the (caller-saved) co-proc state if it needs to. - When a non-running thread loses ownership of a CP, its bit is cleared. - When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. - Avoids co-processor exceptions when no change of ownership is needed. - - XT_CPSTORED - A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether the state of each co-processor is saved in the state - save area. When a thread enters the kernel, only the state of co-procs - still enabled in CPENABLE is saved. When the co-processor exception - handler assigns ownership of a co-processor to a thread, it restores - the saved state only if this bit is set, and clears this bit. - - XT_CP_CS_ST - A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether callee-saved state is saved in the state save area. - Callee-saved state is saved by itself on a solicited context switch, - and restored when needed by the coprocessor exception handler. - Unsolicited switches will cause the entire coprocessor to be saved - when necessary. - - XT_CP_ASA - Pointer to the aligned save area. Allows it to be aligned more than - the overall save area (which might only be stack-aligned or TCB-aligned). - Especially relevant for Xtensa cores configured with a very large data - path that requires alignment greater than 16 bytes (ABI stack alignment). -------------------------------------------------------------------------------- -*/ - -#if XCHAL_CP_NUM > 0 - -/* Offsets of each coprocessor save area within the 'aligned save area': */ -#define XT_CP0_SA 0 -#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) -#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) -#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) -#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) -#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) -#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) -#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) -#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) - -/* Offsets within the overall save area: */ -#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ -#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ -#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ -#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ -/* Overall size allows for dynamic alignment: */ -#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) -#else -#define XT_CP_SIZE 0 -#endif - - -/* - Macro to get the current core ID. Only uses the reg given as an argument. - Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0) - and 0xABAB on the APP CPU (1). We can distinguish between the two by checking - bit 13: it's 1 on the APP and 0 on the PRO processor. -*/ -#ifdef __ASSEMBLER__ - .macro getcoreid reg - rsr.prid \reg - extui \reg,\reg,13,1 - .endm -#endif - -/* Note: These are different to xCoreID used in ESP-IDF FreeRTOS, most places use - 0 and 1 which are determined by checking bit 13 (see previous comment) -*/ -#define CORE_ID_REGVAL_PRO 0xCDCD -#define CORE_ID_REGVAL_APP 0xABAB - -/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */ -#define CORE_ID_PRO CORE_ID_REGVAL_PRO - -/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */ -#define CORE_ID_APP CORE_ID_REGVAL_APP - -/* -------------------------------------------------------------------------------- - MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN - - Convenient where the frame size requirements are the same for both ABIs. - ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). - ENTRY0, RET0 are for frameless functions (no locals, no calls). - - where size = size of stack frame in bytes (must be >0 and aligned to 16). - For framed functions the frame is created and the return address saved at - base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). - For frameless functions, there is no frame and return address remains in a0. - Note: Because CPP macros expand to a single line, macros requiring multi-line - expansions are implemented as assembler macros. -------------------------------------------------------------------------------- -*/ - -#ifdef __ASSEMBLER__ -#ifdef __XTENSA_CALL0_ABI__ - /* Call0 */ - #define ENTRY(sz) entry1 sz - .macro entry1 size=0x10 - addi sp, sp, -\size - s32i a0, sp, 0 - .endm - #define ENTRY0 - #define RET(sz) ret1 sz - .macro ret1 size=0x10 - l32i a0, sp, 0 - addi sp, sp, \size - ret - .endm - #define RET0 ret -#else - /* Windowed */ - #define ENTRY(sz) entry sp, sz - #define ENTRY0 entry sp, 0x10 - #define RET(sz) retw - #define RET0 retw -#endif -#endif - - - - - -#endif /* XTENSA_CONTEXT_H */ - +/* This header file has been moved, please include in future */ +#include \ No newline at end of file diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/i2s_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/i2s_ll.h index 5b7d93be..0b2af70e 100644 --- a/tools/sdk/esp32/include/hal/esp32/include/hal/i2s_ll.h +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/i2s_ll.h @@ -390,61 +390,6 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) hw->rx_eof_num = val / 4; } -/** - * @brief Get I2S tx pdm fp - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to get tx pdm fp - */ -static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) -{ - *val = hw->pdm_freq_conf.tx_pdm_fp; -} - -/** - * @brief Get I2S tx pdm fs - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to get tx pdm fs - */ -static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) -{ - *val = hw->pdm_freq_conf.tx_pdm_fs; -} - -/** - * @brief Set I2S tx pdm fp - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set tx pdm fp - */ -static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) -{ - hw->pdm_freq_conf.tx_pdm_fp = val; -} - -/** - * @brief Set I2S tx pdm fs - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set tx pdm fs - */ -static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) -{ - hw->pdm_freq_conf.tx_pdm_fs = val; -} - -/** - * @brief Get I2S rx sinc dsr 16 en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to get rx sinc dsr 16 en - */ -static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) -{ - *val = hw->pdm_conf.rx_sinc_dsr_16_en; -} - /** * @brief Set I2S clkm div num * @@ -533,17 +478,6 @@ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) hw->sample_rate_conf.rx_bits_mod = val; } -/** - * @brief Set I2S rx sinc dsr 16 en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set rx sinc dsr 16 en - */ -static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) -{ - hw->pdm_conf.rx_sinc_dsr_16_en = val; -} - /** * @brief Set I2S dscr en * @@ -577,50 +511,6 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) hw->conf2.camera_en = val; } -/** - * @brief Set I2S pcm2pdm conv en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set pcm2pdm conv en - */ -static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val) -{ - hw->pdm_conf.pcm2pdm_conv_en = val; -} - -/** - * @brief Set I2S pdm2pcm conv en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set pdm2pcm conv en - */ -static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) -{ - hw->pdm_conf.pdm2pcm_conv_en = val; -} - -/** - * @brief Set I2S rx pdm en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set rx pdm en - */ -static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) -{ - hw->pdm_conf.rx_pdm_en = val; -} - -/** - * @brief Set I2S tx pdm en - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set tx pdm en - */ -static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) -{ - hw->pdm_conf.tx_pdm_en = val; -} - /** * @brief Set I2S tx fifo mod force en * @@ -753,17 +643,6 @@ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) hw->conf.rx_mono = val; } -/** - * @brief Set I2S tx sinc osr2 - * - * @param hw Peripheral I2S hardware instance address. - * @param val value to set tx sinc osr2 - */ -static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) -{ - hw->pdm_conf.tx_sinc_osr2 = val; -} - /** * @brief Set I2S sig loopback * @@ -863,35 +742,6 @@ static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw) hw->conf.rx_msb_shift = 0; } -/** - * @brief Configure I2S TX pdm - * - * @param sample_rate The sample rate to be set. - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_tx_pdm_cfg(i2s_dev_t *hw, uint32_t sample_rate) -{ - uint32_t fp = 96; - uint32_t fs = sample_rate / 1000 * 10; - hw->pdm_freq_conf.tx_pdm_fp = fp; - hw->pdm_freq_conf.tx_pdm_fs = fs; - hw->pdm_conf.tx_sinc_osr2 = fp/fs; - hw->pdm_conf.pcm2pdm_conv_en = 1; - hw->pdm_conf.tx_pdm_en = 1; -} - -/** - * @brief Configure I2S TX pdm - * - * @param hw Peripheral I2S hardware instance address. - */ -static inline void i2s_ll_rx_pdm_cfg(i2s_dev_t *hw) -{ - hw->pdm_conf.rx_sinc_dsr_16_en = 0; - hw->pdm_conf.pdm2pcm_conv_en = 1; - hw->pdm_conf.rx_pdm_en = 1; -} - /** * @brief Enable I2S build in ADC mode * @@ -919,6 +769,82 @@ static inline void i2s_ll_build_in_dac_ena(i2s_dev_t *hw) hw->conf.tx_short_sync = 0; } + +/** + * @brief Enable I2S RX PDM mode + * + * @param hw Peripheral I2S hardware instance address. + * @param pdm_en Set true to enable rx PDM mode + */ +static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool pdm_en) +{ + hw->pdm_conf.rx_pdm_en = pdm_en; +} + +/** + * @brief Enable I2S tx pdm mode + * + * @param hw Peripheral I2S hardware instance address. + * @param pdm_en Set true to enable tx PDM mode + */ +static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool pdm_en) +{ + hw->pdm_conf.tx_pdm_en = pdm_en; +} + +/** + * @brief Configure I2S tx PDM filter module group0 + * + * @param hw Peripheral I2S hardware instance address. + * @param fp The fp value of TX PDM filter module group0. + * @param fs The fs value of TX PDM filter module group0. + */ +static inline void i2s_ll_tx_pdm_cfg(i2s_dev_t *hw, uint32_t fp, uint32_t fs) +{ + hw->pdm_freq_conf.tx_pdm_fp = fp; + hw->pdm_freq_conf.tx_pdm_fs = fs; + hw->pdm_conf.tx_sinc_osr2 = fp/fs; + hw->pdm_conf.pcm2pdm_conv_en = 1; + hw->pdm_conf.tx_pdm_en = 1; +} + +/** + * @brief Configure I2S rx PDM + * + * @param hw Peripheral I2S hardware instance address. + * @param dsr Down-sampling rate value of rx PDM + */ +static inline void i2s_ll_rx_pdm_cfg(i2s_dev_t *hw, uint32_t dsr) +{ + hw->pdm_conf.rx_sinc_dsr_16_en = dsr; + hw->pdm_conf.pdm2pcm_conv_en = 1; + hw->pdm_conf.rx_pdm_en = 1; +} + +/** + * @brief Get I2S tx PDM configuration + * + * @param hw Peripheral I2S hardware instance address. + * @param fp Pointer to store tx PDM fp configuration + * @param fs Pointer to store tx PDM fs configuration + */ +static inline void i2s_ll_get_tx_pdm(i2s_dev_t *hw, uint32_t *fp, uint32_t *fs) +{ + *fp = hw->pdm_freq_conf.tx_pdm_fp; + *fs = hw->pdm_freq_conf.tx_pdm_fs; +} + +/** + * @brief Get I2S rx PDM configuration + * + * @param hw Peripheral I2S hardware instance address. + * @param dsr Pointer to stoe the rx PDM down-sample rate configuration + */ +static inline void i2s_ll_get_rx_pdm(i2s_dev_t *hw, uint32_t *dsr) +{ + *dsr = hw->pdm_conf.rx_sinc_dsr_16_en; +} + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/interrupt_controller_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/interrupt_controller_ll.h new file mode 100644 index 00000000..3c3d5981 --- /dev/null +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/interrupt_controller_ll.h @@ -0,0 +1,105 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "soc/soc.h" +#include "xtensa/xtensa_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be enabled + */ +static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask) +{ + xt_ints_on(mask); +} + +/** + * @brief disable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be disabled + */ +static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask) +{ + xt_ints_off(mask); +} + +/** + * @brief checks if given interrupt number has a valid handler + * + * @param intr interrupt number ranged from 0 to 31 + * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1 + * @return true for valid handler, false otherwise + */ +static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu) +{ + return xt_int_has_handler(intr, cpu); +} + +/** + * @brief sets interrupt handler and optional argument of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * @param handler handler invoked when an interrupt occurs + * @param arg optional argument to pass to the handler + */ +static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg) +{ + xt_set_interrupt_handler(intr, (xt_handler)handler, arg); +} + +/** + * @brief Gets argument passed to handler of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * + * @return argument used by handler of passed interrupt number + */ +static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr) +{ + return xt_get_interrupt_handler_arg(intr); +} + +/** + * @brief Disables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + * @return oldmask where to store old interrupts state + */ +static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask) +{ + return xt_int_disable_mask(newmask); +} + +/** + * @brief Enables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + */ +static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask) +{ + xt_int_enable_mask(newmask); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/sha_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/sha_ll.h new file mode 100644 index 00000000..65cfa785 --- /dev/null +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/sha_ll.h @@ -0,0 +1,156 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "hal/sha_types.h" +#include "soc/hwcrypto_reg.h" +#include "soc/dport_access.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SHA_LL_TYPE_OFFSET 0x10 + +/** + * @brief Returns the LOAD_REG register address for the given sha type + * + * @param sha_type The SHA algorithm type + * @return uint32_t the LOAD_REG register address + */ +inline static uint32_t SHA_LOAD_REG(esp_sha_type sha_type) +{ + return SHA_1_LOAD_REG + sha_type * SHA_LL_TYPE_OFFSET; +} + +/** + * @brief Returns the BUSY register address for the given sha type + * + * @param sha_type The SHA algorithm type + * @return uint32_t the BUSY register address + */ +inline static uint32_t SHA_BUSY_REG(esp_sha_type sha_type) +{ + return SHA_1_BUSY_REG + sha_type * SHA_LL_TYPE_OFFSET; +} + +/** + * @brief Returns the START register address for the given sha type + * + * @param sha_type The SHA algorithm type + * @return uint32_t the START register address + */ +inline static uint32_t SHA_START_REG(esp_sha_type sha_type) +{ + return SHA_1_START_REG + sha_type * SHA_LL_TYPE_OFFSET; +} + +/** + * @brief Returns the CONTINUE register address for the given sha type + * + * @param sha_type The SHA algorithm type + * @return uint32_t the CONTINUE register address + */ +inline static uint32_t SHA_CONTINUE_REG(esp_sha_type sha_type) +{ + return SHA_1_CONTINUE_REG + sha_type * SHA_LL_TYPE_OFFSET; +} + +/** + * @brief Start a new SHA block conversion (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_block(esp_sha_type sha_type) +{ + DPORT_REG_WRITE(SHA_START_REG(sha_type), 1); +} + +/** + * @brief Continue a SHA block conversion (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_block(esp_sha_type sha_type) +{ + DPORT_REG_WRITE(SHA_CONTINUE_REG(sha_type), 1); +} + +/** + * @brief Load the current hash digest to digest register + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_load(esp_sha_type sha_type) +{ + DPORT_REG_WRITE(SHA_LOAD_REG(sha_type), 1); +} + +/** + * @brief Checks if the SHA engine is currently busy hashing a block + * + * @return true SHA engine busy + * @return false SHA engine idle + */ +static inline bool sha_ll_busy(void) +{ + return (DPORT_REG_READ(SHA_1_BUSY_REG) || DPORT_REG_READ(SHA_256_BUSY_REG) + || DPORT_REG_READ(SHA_384_BUSY_REG) || DPORT_REG_READ(SHA_512_BUSY_REG)); +} + +/** + * @brief Write a text (message) block to the SHA engine + * + * @param input_text Input buffer to be written to the SHA engine + * @param block_word_len Number of words in block + */ +static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) +{ + uint32_t *reg_addr_buf = NULL; + uint32_t *data_words = NULL; + reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE); + data_words = (uint32_t *)input_text; + for (int i = 0; i < block_word_len; i++) { + reg_addr_buf[i] = __builtin_bswap32(data_words[i]); + } +} + +/** + * @brief Read the message digest from the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Buffer that message digest will be written to + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE); + if (sha_type == SHA2_384 || sha_type == SHA2_512) { + /* for these ciphers using 64-bit states, swap each pair of words */ + DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU. + for (int i = 0; i < digest_word_len; i += 2) { + digest_state_words[i + 1] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i]); + digest_state_words[i] = DPORT_SEQUENCE_REG_READ((uint32_t)®_addr_buf[i + 1]); + } + DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level + } else { + esp_dport_access_read_buffer(digest_state_words, (uint32_t)®_addr_buf[0], digest_word_len); + } +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/spi_flash_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/spi_flash_ll.h index 0b4db159..656425e8 100644 --- a/tools/sdk/esp32/include/hal/esp32/include/hal/spi_flash_ll.h +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/spi_flash_ll.h @@ -224,7 +224,7 @@ static inline void spi_flash_ll_user_start(spi_dev_t *dev) */ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev) { - return dev->ext2.st != 0; + return dev->ext2.st == 0; } /*------------------------------------------------------------------------------ @@ -390,4 +390,4 @@ static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n) #ifdef __cplusplus } -#endif \ No newline at end of file +#endif diff --git a/tools/sdk/esp32/include/hal/esp32/include/hal/spi_ll.h b/tools/sdk/esp32/include/hal/esp32/include/hal/spi_ll.h index 73b8b01a..dd2b1d46 100644 --- a/tools/sdk/esp32/include/hal/esp32/include/hal/spi_ll.h +++ b/tools/sdk/esp32/include/hal/esp32/include/hal/spi_ll.h @@ -34,7 +34,7 @@ extern "C" { #endif /// Registers to reset during initialization. Don't use in app. -#define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST) +#define SPI_LL_DMA_FIFO_RST_MASK (SPI_AHBM_RST | SPI_AHBM_FIFO_RST) /// Interrupt not used. Don't use in app. #define SPI_LL_UNUSED_INT_MASK (SPI_INT_EN | SPI_SLV_WR_STA_DONE | SPI_SLV_RD_STA_DONE | SPI_SLV_WR_BUF_DONE | SPI_SLV_RD_BUF_DONE) /// Swap the bit order to its correct place to send @@ -49,6 +49,9 @@ extern "C" { */ typedef uint32_t spi_ll_clock_val_t; +//On ESP32-S2 and earlier chips, DMA registers are part of SPI registers. So set the registers of SPI peripheral to control DMA. +typedef spi_dev_t spi_dma_dev_t; + /** IO modes supported by the master. */ typedef enum { SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases @@ -58,11 +61,6 @@ typedef enum { SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases } spi_ll_io_mode_t; -/// Interrupt type for different working pattern -typedef enum { - SPI_LL_INT_TYPE_NORMAL = 0, ///< Typical pattern, only wait for trans done -} spi_ll_slave_intr_type; - /*------------------------------------------------------------------------------ * Control @@ -74,11 +72,6 @@ typedef enum { */ static inline void spi_ll_master_init(spi_dev_t *hw) { - //Reset DMA - hw->dma_conf.val |= SPI_LL_RST_MASK; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~SPI_LL_RST_MASK; //Reset timing hw->ctrl2.val = 0; @@ -105,10 +98,6 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) hw->user.doutdin = 1; //we only support full duplex hw->user.sio = 0; hw->slave.slave_mode = 1; - hw->dma_conf.val |= SPI_LL_RST_MASK; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~SPI_LL_RST_MASK; hw->slave.sync_reset = 1; hw->slave.sync_reset = 0; //use all 64 bytes of the buffer @@ -119,84 +108,6 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK; } -/** - * Reset TX and RX DMAs. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_reset_dma(spi_dev_t *hw) -{ - //Reset DMA peripheral - hw->dma_conf.val |= SPI_LL_RST_MASK; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~SPI_LL_RST_MASK; - hw->dma_conf.out_data_burst_en = 1; - hw->dma_conf.indscr_burst_en = 1; - hw->dma_conf.outdscr_burst_en = 1; -} - -/** - * Start RX DMA. - * - * @param hw Beginning address of the peripheral registers. - * @param addr Address of the beginning DMA descriptor. - */ -static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr) -{ - hw->dma_in_link.addr = (int) addr & 0xFFFFF; - hw->dma_in_link.start = 1; -} - -/** - * Start TX DMA. - * - * @param hw Beginning address of the peripheral registers. - * @param addr Address of the beginning DMA descriptor. - */ -static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr) -{ - hw->dma_out_link.addr = (int) addr & 0xFFFFF; - hw->dma_out_link.start = 1; -} - -/** - * Write to SPI buffer. - * - * @param hw Beginning address of the peripheral registers. - * @param buffer_to_send Data address to copy to the buffer. - * @param bitlen Length to copy, in bits. - */ -static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) -{ - for (int x = 0; x < bitlen; x += 32) { - //Use memcpy to get around alignment issues for txdata - uint32_t word; - memcpy(&word, &buffer_to_send[x / 8], 4); - hw->data_buf[(x / 32)] = word; - } -} - -/** - * Read from SPI buffer. - * - * @param hw Beginning address of the peripheral registers. - * @param buffer_to_rcv Address to copy buffer data to. - * @param bitlen Length to copy, in bits. - */ -static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) -{ - for (int x = 0; x < bitlen; x += 32) { - //Do a memcpy to get around possible alignment issues in rx_buffer - uint32_t word = hw->data_buf[x / 32]; - int len = bitlen - x; - if (len > 32) { - len = 32; - } - memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); - } -} - /** * Check whether user-defined transaction is done. * @@ -232,48 +143,110 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) } /** - * Disable the trans_done interrupt. + * Reset SPI CPU FIFO * * @param hw Beginning address of the peripheral registers. */ -static inline void spi_ll_disable_int(spi_dev_t *hw) +static inline void spi_ll_cpu_fifo_reset(spi_dev_t *hw) { - hw->slave.trans_inten = 0; + //This is not used in esp32 } /** - * Clear the trans_done interrupt. + * Reset SPI DMA FIFO * * @param hw Beginning address of the peripheral registers. */ -static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +static inline void spi_ll_dma_fifo_reset(spi_dev_t *hw) { - hw->slave.trans_done = 0; + hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK; + hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK; } /** - * Set the trans_done interrupt. - * + * Clear in fifo full error + * * @param hw Beginning address of the peripheral registers. */ -static inline void spi_ll_set_int_stat(spi_dev_t *hw) +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - hw->slave.trans_done = 1; + //This is not used in esp32 } /** - * Enable the trans_done interrupt. - * + * Clear out fifo empty error + * * @param hw Beginning address of the peripheral registers. */ -static inline void spi_ll_enable_int(spi_dev_t *hw) +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - hw->slave.trans_inten = 1; + //This is not used in esp32 } -static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type) +/*------------------------------------------------------------------------------ + * SPI configuration for DMA + *----------------------------------------------------------------------------*/ + +/** + * Enable/Disable RX DMA (Peripherals->DMA->RAM) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) { - hw->slave.trans_inten = 1; + //This is not used in esp32 +} + +/** + * Enable/Disable TX DMA (RAM->DMA->Peripherals) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) +{ + //This is not used in esp32 +} + +/*------------------------------------------------------------------------------ + * Buffer + *----------------------------------------------------------------------------*/ +/** + * Write to SPI buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_send Data address to copy to the buffer. + * @param bitlen Length to copy, in bits. + */ +static inline void spi_ll_write_buffer(spi_dev_t *hw, const uint8_t *buffer_to_send, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Use memcpy to get around alignment issues for txdata + uint32_t word; + memcpy(&word, &buffer_to_send[x / 8], 4); + hw->data_buf[(x / 32)] = word; + } +} + +/** + * Read from SPI buffer. + * + * @param hw Beginning address of the peripheral registers. + * @param buffer_to_rcv Address to copy buffer data to. + * @param bitlen Length to copy, in bits. + */ +static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, size_t bitlen) +{ + for (int x = 0; x < bitlen; x += 32) { + //Do a memcpy to get around possible alignment issues in rx_buffer + uint32_t word = hw->data_buf[x / 32]; + int len = bitlen - x; + if (len > 32) { + len = 32; + } + memcpy(&buffer_to_rcv[x / 8], &word, (len + 7) / 8); + } } /*------------------------------------------------------------------------------ @@ -291,7 +264,7 @@ static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_ if (pos_cs) { hw->pin.master_cs_pol |= (1 << cs); } else { - hw->pin.master_cs_pol &= (1 << cs); + hw->pin.master_cs_pol &= ~(1 << cs); } } @@ -485,7 +458,7 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) * @param hw Beginning address of the peripheral registers. * @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``). */ -static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val) +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) { hw->clock.val = *(uint32_t *)val; } @@ -615,7 +588,7 @@ static inline void spi_ll_master_set_cksel(spi_dev_t *hw, int cs, uint32_t cksel if (cksel) { hw->pin.master_ck_sel |= (1 << cs); } else { - hw->pin.master_ck_sel &= (1 << cs); + hw->pin.master_ck_sel &= ~(1 << cs); } } @@ -875,6 +848,167 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) return hw->slv_rd_bit.slv_rdata_bit; } +/*------------------------------------------------------------------------------ + * Interrupts + *----------------------------------------------------------------------------*/ +/** + * Disable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_disable_int(spi_dev_t *hw) +{ + hw->slave.trans_inten = 0; +} + +/** + * Clear the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +{ + hw->slave.trans_done = 0; +} + +/** + * Set the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_int_stat(spi_dev_t *hw) +{ + hw->slave.trans_done = 1; +} + +/** + * Enable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_enable_int(spi_dev_t *hw) +{ + hw->slave.trans_inten = 1; +} + +/*------------------------------------------------------------------------------ + * DMA: + * RX DMA (Peripherals->DMA->RAM) + * TX DMA (RAM->DMA->Peripherals) + *----------------------------------------------------------------------------*/ +/** + * Reset RX DMA which stores the data received from a peripheral into RAM. + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + */ +static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in) +{ + //Reset RX DMA peripheral + dma_in->dma_conf.in_rst = 1; + dma_in->dma_conf.in_rst = 0; +} + +/** + * Start RX DMA. + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param addr Address of the beginning DMA descriptor. + */ +static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, lldesc_t *addr) +{ + dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; + dma_in->dma_in_link.start = 1; +} + +/** + * Enable DMA RX channel burst for data + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_out, bool enable) +{ + //This is not supported in esp32 +} + +/** + * Enable DMA RX channel burst for descriptor + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, bool enable) +{ + dma_in->dma_conf.indscr_burst_en = enable; +} + +/** + * Configuration of RX DMA EOF interrupt generation way + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ +static inline void spi_dma_ll_set_rx_eof_generation(spi_dma_dev_t *dma_in, bool enable) +{ + //does not available in ESP32 +} + +/** + * Reset TX DMA which transmits the data from RAM to a peripheral. + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + */ +static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out) +{ + //Reset TX DMA peripheral + dma_out->dma_conf.out_rst = 1; + dma_out->dma_conf.out_rst = 0; +} + +/** + * Start TX DMA. + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param addr Address of the beginning DMA descriptor. + */ +static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, lldesc_t *addr) +{ + dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; + dma_out->dma_out_link.start = 1; +} + +/** + * Enable DMA TX channel burst for data + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, bool enable) +{ + dma_out->dma_conf.out_data_burst_en = enable; +} + +/** + * Enable DMA TX channel burst for descriptor + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, bool enable) +{ + dma_out->dma_conf.outdscr_burst_en = enable; +} + +/** + * Enable automatic outlink-writeback + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, bool enable) +{ + //does not configure it in ESP32 +} #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/tools/sdk/esp32/include/hal/include/hal/dac_types.h b/tools/sdk/esp32/include/hal/include/hal/dac_types.h index b1f4b6fe..1adc511a 100644 --- a/tools/sdk/esp32/include/hal/include/hal/dac_types.h +++ b/tools/sdk/esp32/include/hal/include/hal/dac_types.h @@ -40,7 +40,7 @@ typedef struct { Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */ } dac_cw_config_t; -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 /** * @brief DAC digital controller (DMA mode) work mode. diff --git a/tools/sdk/esp32/include/hal/include/hal/dma_types.h b/tools/sdk/esp32/include/hal/include/hal/dma_types.h new file mode 100644 index 00000000..1c582361 --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/dma_types.h @@ -0,0 +1,45 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Type of DMA descriptor + * + */ +typedef struct dma_descriptor_s { + struct { + uint32_t size : 12; /*!< Buffer size */ + uint32_t length : 12; /*!< Number of valid bytes in the buffer */ + uint32_t reversed24_27 : 4; /*!< Reserved */ + uint32_t err_eof : 1; /*!< Whether the received buffer contains error */ + uint32_t reserved29 : 1; /*!< Reserved */ + uint32_t suc_eof : 1; /*!< Whether the descriptor is the last one in the link */ + uint32_t owner : 1; /*!< Who is allowed to access the buffer that this descriptor points to */ + } dw0; /*!< Descriptor Word 0 */ + void *buffer; /*!< Pointer to the buffer */ + struct dma_descriptor_s *next; /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */ +} dma_descriptor_t; + +_Static_assert(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occupy 12 bytes in memory"); + +#define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< DMA buffer is allowed to be accessed by CPU */ +#define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< DMA buffer is allowed to be accessed by DMA engine */ +#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ diff --git a/tools/sdk/esp32/include/hal/include/hal/gdma_hal.h b/tools/sdk/esp32/include/hal/include/hal/gdma_hal.h new file mode 100644 index 00000000..2a67d26a --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/gdma_hal.h @@ -0,0 +1,35 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/gdma_struct.h" + +typedef struct { + gdma_dev_t *dev; +} gdma_hal_context_t; + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/hal/include/hal/i2s_hal.h b/tools/sdk/esp32/include/hal/include/hal/i2s_hal.h index cff02d98..49b3c1a0 100644 --- a/tools/sdk/esp32/include/hal/include/hal/i2s_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/i2s_hal.h @@ -151,25 +151,6 @@ void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_ */ void i2s_hal_set_in_link(i2s_hal_context_t *hal, uint32_t rx_eof_num, uint32_t addr); -#if SOC_I2S_SUPPORTS_PDM -/** - * @brief Get I2S tx pdm - * - * @param hal Context of the HAL layer - * @param fp tx pdm fp - * @param fs tx pdm fs - */ -void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, int *fp, int *fs); -#endif - -/** - * @brief Get I2S rx sinc dsr 16 en - * - * @param hal Context of the HAL layer - * @param en 0: disable, 1: enable - */ -#define i2s_hal_get_rx_sinc_dsr_16_en(hal, en) i2s_ll_get_rx_sinc_dsr_16_en((hal)->dev, en) - /** * @brief Set I2S clk div * @@ -241,16 +222,6 @@ void i2s_hal_stop_tx(i2s_hal_context_t *hal); */ void i2s_hal_stop_rx(i2s_hal_context_t *hal); -#if SOC_I2S_SUPPORTS_PDM -/** - * @brief Set I2S pdm rx down sample - * - * @param hal Context of the HAL layer - * @param dsr 0:disable, 1: enable - */ -#define i2s_hal_set_pdm_rx_down_sample(hal, dsr) i2s_ll_set_rx_sinc_dsr_16_en((hal)->dev, dsr) -#endif - /** * @brief Config I2S param * @@ -288,6 +259,42 @@ void i2s_hal_enable_slave_mode(i2s_hal_context_t *hal); */ void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num); +#if SOC_I2S_SUPPORTS_PDM +/** + * @brief Set I2S tx pdm + * + * @param hal Context of the HAL layer + * @param fp tx pdm fp + * @param fs tx pdm fs + */ +void i2s_hal_tx_pdm_cfg(i2s_hal_context_t *hal, uint32_t fp, uint32_t fs); + +/** + * @brief Get I2S tx pdm + * + * @param hal Context of the HAL layer + * @param dsr rx pdm dsr + */ +void i2s_hal_rx_pdm_cfg(i2s_hal_context_t *hal, uint32_t dsr); + +/** + * @brief Get I2S tx pdm configuration + * + * @param hal Context of the HAL layer + * @param fp Pointer to receive tx PDM fp configuration + * @param fs Pointer to receive tx PDM fs configuration + */ +void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, uint32_t *fp, uint32_t *fs); + +/** + * @brief Get I2S rx pdm configuration + * + * @param hal Context of the HAL layer + * @param dsr rx pdm dsr + */ +void i2s_hal_get_rx_pdm(i2s_hal_context_t *hal, uint32_t *dsr); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/hal/include/hal/interrupt_controller_hal.h b/tools/sdk/esp32/include/hal/include/hal/interrupt_controller_hal.h new file mode 100644 index 00000000..ae230c8e --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/interrupt_controller_hal.h @@ -0,0 +1,170 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "hal/interrupt_controller_types.h" +#include "hal/interrupt_controller_ll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Gets target platform interrupt descriptor table + * + * @return Address of interrupt descriptor table + */ +__attribute__((pure)) const int_desc_t *interrupt_controller_hal_desc_table(void); + +/** + * @brief Gets the interrupt type given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt type + */ +__attribute__((pure)) int_type_t interrupt_controller_hal_desc_type(int interrupt_number); + +/** + * @brief Gets the interrupt level given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt level bitmask + */ +__attribute__((pure)) int interrupt_controller_hal_desc_level(int interrupt_number); + +/** + * @brief Gets the cpu flags given the interrupt number and target cpu. + * + * @param interrupt_number Interrupt number 0 to 31 + * @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1 + * @return flags for that interrupt number + */ +__attribute__((pure)) uint32_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number); + +/** + * @brief Gets the interrupt type given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt type + */ +static inline int_type_t interrupt_controller_hal_get_type(int interrupt_number) +{ + return interrupt_controller_hal_desc_type(interrupt_number); +} + +/** + * @brief Gets the interrupt level given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt level bitmask + */ +static inline int interrupt_controller_hal_get_level(int interrupt_number) +{ + return interrupt_controller_hal_desc_level(interrupt_number); +} + +/** + * @brief Gets the cpu flags given the interrupt number and target cpu. + * + * @param interrupt_number Interrupt number 0 to 31 + * @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1 + * @return flags for that interrupt number + */ +static inline uint32_t interrupt_controller_hal_get_cpu_desc_flags(int interrupt_number, int cpu_number) +{ + return interrupt_controller_hal_desc_flags(interrupt_number, cpu_number); +} + +/** + * @brief enable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be enabled + */ +static inline void interrupt_controller_hal_enable_interrupts(uint32_t mask) +{ + intr_cntrl_ll_enable_interrupts(mask); +} + +/** + * @brief disable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be disabled + */ +static inline void interrupt_controller_hal_disable_interrupts(uint32_t mask) +{ + intr_cntrl_ll_disable_interrupts(mask); +} + +/** + * @brief checks if given interrupt number has a valid handler + * + * @param intr interrupt number ranged from 0 to 31 + * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1 + * @return true for valid handler, false otherwise + */ +static inline bool interrupt_controller_hal_has_handler(int intr, int cpu) +{ + return intr_cntrl_ll_has_handler(intr, cpu); +} + +/** + * @brief sets interrupt handler and optional argument of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * @param handler handler invoked when an interrupt occurs + * @param arg optional argument to pass to the handler + */ +static inline void interrupt_controller_hal_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg) +{ + intr_cntrl_ll_set_int_handler(intr, handler, arg); +} + +/** + * @brief Gets argument passed to handler of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * + * @return argument used by handler of passed interrupt number + */ +static inline void * interrupt_controller_hal_get_int_handler_arg(uint8_t intr) +{ + return intr_cntrl_ll_get_int_handler_arg(intr); +} + +/** + * @brief Disables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + * @return oldmask where to store old interrupts state + */ +static inline uint32_t interrupt_controller_hal_disable_int_mask(uint32_t newmask) +{ + return intr_cntrl_ll_disable_int_mask(newmask); +} + +/** + * @brief Enables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + */ +static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask) +{ + intr_cntrl_ll_enable_int_mask(newmask); +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/hal/include/hal/interrupt_controller_types.h b/tools/sdk/esp32/include/hal/include/hal/interrupt_controller_types.h new file mode 100644 index 00000000..639317f4 --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/interrupt_controller_types.h @@ -0,0 +1,46 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + INTDESC_NORMAL=0, + INTDESC_RESVD, + INTDESC_SPECIAL +} int_desc_flag_t; + +typedef enum { + INTTP_LEVEL=0, + INTTP_EDGE, + INTTP_NA +} int_type_t; + +typedef struct { + int level; + int_type_t type; + int_desc_flag_t cpuflags[SOC_CPU_CORES_NUM]; +} int_desc_t; + +typedef void (*interrupt_handler_t)(void *arg); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/hal/include/hal/rmt_hal.h b/tools/sdk/esp32/include/hal/include/hal/rmt_hal.h index ba1cac07..6d44acf9 100644 --- a/tools/sdk/esp32/include/hal/include/hal/rmt_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/rmt_hal.h @@ -17,6 +17,7 @@ extern "C" { #endif +#include #include "soc/rmt_struct.h" #include "soc/rmt_caps.h" diff --git a/tools/sdk/esp32/include/soc/include/hal/rtc_hal.h b/tools/sdk/esp32/include/hal/include/hal/rtc_hal.h similarity index 100% rename from tools/sdk/esp32/include/soc/include/hal/rtc_hal.h rename to tools/sdk/esp32/include/hal/include/hal/rtc_hal.h diff --git a/tools/sdk/esp32/include/hal/include/hal/sha_types.h b/tools/sdk/esp32/include/hal/include/hal/sha_types.h new file mode 100644 index 00000000..c5038227 --- /dev/null +++ b/tools/sdk/esp32/include/hal/include/hal/sha_types.h @@ -0,0 +1,38 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "sdkconfig.h" + +/* Use enum from rom for backwards compatibility */ +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/sha.h" +typedef enum SHA_TYPE esp_sha_type; +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/sha.h" +typedef SHA_TYPE esp_sha_type; +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/sha.h" +typedef SHA_TYPE esp_sha_type; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/hal/include/hal/spi_hal.h b/tools/sdk/esp32/include/hal/include/hal/spi_hal.h index 6f0aa024..dd5e01df 100644 --- a/tools/sdk/esp32/include/hal/include/hal/spi_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/spi_hal.h @@ -38,83 +38,115 @@ #include #include "soc/lldesc.h" +/** + * Input parameters to the ``spi_hal_cal_clock_conf`` to calculate the timing configuration + */ +typedef struct { + uint32_t half_duplex; ///< Whether half duplex mode is used, device specific + uint32_t no_compensate; ///< No need to add dummy to compensate the timing, device specific + uint32_t clock_speed_hz; ///< Desired frequency. + uint32_t duty_cycle; ///< Desired duty cycle of SPI clock + uint32_t input_delay_ns; /**< Maximum delay between SPI launch clock and the data to be valid. + * This is used to compensate/calculate the maximum frequency allowed. + * Left 0 if not known. + */ + bool use_gpio; ///< True if the GPIO matrix is used, otherwise false +} spi_hal_timing_param_t; + /** * Timing configuration structure that should be calculated by - * ``spi_hal_setup_clock`` at initialization and hold. Filled into the + * ``spi_hal_cal_clock_conf`` at initialization and hold. Filled into the * ``timing_conf`` member of the context of HAL before setup a device. */ typedef struct { - spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer - int timing_dummy; ///< Extra dummy needed to compensate the timing - int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing + spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer + int timing_dummy; ///< Extra dummy needed to compensate the timing + int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing } spi_hal_timing_conf_t; +/** + * DMA configuration structure + * Should be set by driver at initialization + */ +typedef struct { + spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address + spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. +} spi_hal_dma_config_t; + +/** + * Transaction configuration structure, this should be assigned by driver each time. + * All these parameters will be updated to the peripheral every transaction. + */ +typedef struct { + uint16_t cmd; ///< Command value to be sent + int cmd_bits; ///< Length (in bits) of the command phase + int addr_bits; ///< Length (in bits) of the address phase + int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended. + int tx_bitlen; ///< TX length, in bits + int rx_bitlen; ///< RX length, in bits + uint64_t addr; ///< Address value to be sent + uint8_t *send_buffer; ///< Data to be sent + uint8_t *rcv_buffer; ///< Buffer to hold the receive data. + spi_ll_io_mode_t io_mode; ///< IO mode of the master +} spi_hal_trans_config_t; + /** * Context that should be maintained by both the driver and the HAL. */ typedef struct { - /* configured by driver at initialization, don't touch */ - spi_dev_t *hw; ///< Beginning address of the peripheral registers. - /* should be configured by driver at initialization */ - lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. - /* - * Device specific, all these parameters will be updated to the peripheral - * only when ``spi_hal_setup_device``. They may not get updated when - * ``spi_hal_setup_trans``. - */ + /* Configured by driver at initialization, don't touch */ + spi_dev_t *hw; ///< Beginning address of the peripheral registers. + spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM (DMA -> RAM). + spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral (RAM -> DMA). + bool dma_enabled; ///< Whether the DMA is enabled, do not update after initialization + spi_hal_dma_config_t dma_config; ///< DMA configuration + + /* Internal parameters, don't touch */ + spi_hal_trans_config_t trans_config; ///< Transaction configuration +} spi_hal_context_t; + +/** + * Device configuration structure, this should be initialised by driver based on different devices respectively. + * All these parameters will be updated to the peripheral only when ``spi_hal_setup_device``. + * They may not get updated when ``spi_hal_setup_trans``. + */ +typedef struct { int mode; ///< SPI mode, device specific int cs_setup; ///< Setup time of CS active edge before the first SPI clock, device specific int cs_hold; ///< Hold time of CS inactive edge after the last SPI clock, device specific int cs_pin_id; ///< CS pin to use, 0-2, otherwise all the CS pins are not used. Device specific - spi_hal_timing_conf_t *timing_conf; /**< Pointer to an structure holding - * the pre-calculated timing configuration for the device at initialization, - * device specific + spi_hal_timing_conf_t timing_conf; /**< This structure holds the pre-calculated timing configuration for the device + * at initialization, device specific */ struct { - uint32_t sio : 1; ///< Whether to use SIO mode, device specific - uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific - uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific - uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific - uint32_t dma_enabled : 1; ///< Whether the DMA is enabled, do not update after initialization - uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific + uint32_t sio : 1; ///< Whether to use SIO mode, device specific + uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific + uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific + uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific + uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific #ifdef SOC_SPI_SUPPORT_AS_CS - uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific + uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific #endif - uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific + uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific };//boolean configurations - - /* - * Transaction specific (data), all these parameters will be updated to the - * peripheral every transaction. - */ - uint16_t cmd; ///< Command value to be sent - int cmd_bits; ///< Length (in bits) of the command phase - int addr_bits; ///< Length (in bits) of the address phase - int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended. - int tx_bitlen; ///< TX length, in bits - int rx_bitlen; ///< RX length, in bits - uint64_t addr; ///< Address value to be sent - uint8_t *send_buffer; ///< Data to be sent - uint8_t *rcv_buffer; ///< Buffer to hold the receive data. - spi_ll_io_mode_t io_mode; ///< IO mode of the master - -} spi_hal_context_t; +} spi_hal_dev_config_t; /** * Init the peripheral and the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3). */ -void spi_hal_init(spi_hal_context_t *hal, int host_id); +void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_dma_config_t *hal_dma_config); /** * Deinit the peripheral (and the context if needed). @@ -126,23 +158,28 @@ void spi_hal_deinit(spi_hal_context_t *hal); /** * Setup device-related configurations according to the settings in the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration */ -void spi_hal_setup_device(const spi_hal_context_t *hal); +void spi_hal_setup_device(spi_hal_context_t *hal, const spi_hal_dev_config_t *hal_dev); /** * Setup transaction related configurations according to the settings in the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration + * @param hal_trans Transaction configuration */ -void spi_hal_setup_trans(const spi_hal_context_t *hal); +void spi_hal_setup_trans(spi_hal_context_t *hal, const spi_hal_dev_config_t *hal_dev, const spi_hal_trans_config_t *hal_trans); /** * Prepare the data for the current transaction. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration + * @param hal_trans Transaction configuration */ -void spi_hal_prepare_data(const spi_hal_context_t *hal); +void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *hal_dev, const spi_hal_trans_config_t *hal_trans); /** * Trigger start a user-defined transaction. @@ -161,7 +198,7 @@ bool spi_hal_usr_is_done(const spi_hal_context_t *hal); /** * Post transaction operations, mainly fetch data from the buffer. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. */ void spi_hal_fetch_result(const spi_hal_context_t *hal); @@ -173,50 +210,44 @@ void spi_hal_fetch_result(const spi_hal_context_t *hal); * * It is highly suggested to do this at initialization, since it takes long time. * - * @param hal Context of the HAL layer. - * @param speed_hz Desired frequency. - * @param duty_cycle Desired duty cycle of SPI clock - * @param use_gpio true if the GPIO matrix is used, otherwise false - * @param input_delay_ns Maximum delay between SPI launch clock and the data to - * be valid. This is used to compensate/calculate the maximum frequency - * allowed. Left 0 if not known. - * @param out_freq Output of the actual frequency, left NULL if not required. - * @param timing_conf Output of the timing configuration. + * @param timing_param Input parameters to calculate timing configuration + * @param out_freq Output of the actual frequency, left NULL if not required. + * @param timing_conf Output of the timing configuration. * * @return ESP_OK if desired is available, otherwise fail. */ -esp_err_t spi_hal_cal_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf); +esp_err_t spi_hal_cal_clock_conf(const spi_hal_timing_param_t *timing_param, int *out_freq, spi_hal_timing_conf_t *timing_conf); /** * Get the frequency actual used. * - * @param hal Context of the HAL layer. - * @param fapb APB clock frequency. - * @param hz Desired frequencyc. - * @param duty_cycle Desired duty cycle. + * @param hal Context of the HAL layer. + * @param fapb APB clock frequency. + * @param hz Desired frequencyc. + * @param duty_cycle Desired duty cycle. */ int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle); /** * Get the timing configuration for given parameters. * - * @param eff_clk Actual SPI clock frequency - * @param gpio_is_used true if the GPIO matrix is used, otherwise false. + * @param eff_clk Actual SPI clock frequency + * @param gpio_is_used true if the GPIO matrix is used, otherwise false. * @param input_delay_ns Maximum delay between SPI launch clock and the data to - * be valid. This is used to compensate/calculate the maximum frequency - * allowed. Left 0 if not known. - * @param dummy_n Dummy cycles required to correctly read the data. - * @param miso_delay_n suggested delay on the MISO line, in APB clocks. + * be valid. This is used to compensate/calculate the maximum frequency + * allowed. Left 0 if not known. + * @param dummy_n Dummy cycles required to correctly read the data. + * @param miso_delay_n suggested delay on the MISO line, in APB clocks. */ void spi_hal_cal_timing(int eff_clk, bool gpio_is_used, int input_delay_ns, int *dummy_n, int *miso_delay_n); /** * Get the maximum frequency allowed to read if no compensation is used. * - * @param gpio_is_used true if the GPIO matrix is used, otherwise false. + * @param gpio_is_used true if the GPIO matrix is used, otherwise false. * @param input_delay_ns Maximum delay between SPI launch clock and the data to - * be valid. This is used to compensate/calculate the maximum frequency - * allowed. Left 0 if not known. + * be valid. This is used to compensate/calculate the maximum frequency + * allowed. Left 0 if not known. */ int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns); diff --git a/tools/sdk/esp32/include/hal/include/hal/spi_slave_hal.h b/tools/sdk/esp32/include/hal/include/hal/spi_slave_hal.h index f8acf2d9..2beccd45 100644 --- a/tools/sdk/esp32/include/hal/include/hal/spi_slave_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/spi_slave_hal.h @@ -36,32 +36,35 @@ #include "soc/spi_struct.h" #include #include "soc/spi_caps.h" +#include "hal/spi_ll.h" /** * Context that should be maintained by both the driver and the HAL. */ typedef struct { /* configured by driver at initialization, don't touch */ - spi_dev_t *hw; ///< Beginning address of the peripheral registers. + spi_dev_t *hw; ///< Beginning address of the peripheral registers. + spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral. /* should be configured by driver at initialization */ - lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. /* * configurations to be filled after ``spi_slave_hal_init``. Updated to * peripheral registers when ``spi_slave_hal_setup_device`` is called. */ struct { - uint32_t rx_lsbfirst : 1; - uint32_t tx_lsbfirst : 1; - uint32_t use_dma : 1; + uint32_t rx_lsbfirst : 1; + uint32_t tx_lsbfirst : 1; + uint32_t use_dma : 1; }; int mode; @@ -69,21 +72,27 @@ typedef struct { * Transaction specific (data), all these parameters will be updated to the * peripheral every transaction. */ - uint32_t bitlen; ///< Expected maximum length of the transaction, in bits. - const void *tx_buffer; ///< Data to be sent - void *rx_buffer; ///< Buffer to hold the received data. + uint32_t bitlen; ///< Expected maximum length of the transaction, in bits. + const void *tx_buffer; ///< Data to be sent + void *rx_buffer; ///< Buffer to hold the received data. /* Other transaction result after one transaction */ - uint32_t rcv_bitlen; ///< Length of the last transaction, in bits. + uint32_t rcv_bitlen; ///< Length of the last transaction, in bits. } spi_slave_hal_context_t; +typedef struct { + uint32_t host_id; ///< SPI controller ID + spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address + spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address +} spi_slave_hal_config_t; + /** * Init the peripheral and the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3). */ -void spi_slave_hal_init(spi_slave_hal_context_t *hal, int host_id); +void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config); /** * Deinit the peripheral (and the context if needed). diff --git a/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h index 6e13e2c2..e1cb5bc5 100644 --- a/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h +++ b/tools/sdk/esp32/include/hal/include/hal/spi_slave_hd_hal.h @@ -22,7 +22,7 @@ * The HAL layer for SPI Slave HD mode, currently only segment mode is supported * * Usage: - * - Firstly, initialize the slave with `slave_hd_hal_init` + * - Firstly, initialize the slave with `spi_slave_hd_hal_init` * * - Event handling: * - (Optional) Call ``spi_slave_hd_hal_enable_event_intr`` to enable the used interrupts @@ -56,54 +56,56 @@ #include "hal/spi_ll.h" #include "hal/spi_types.h" - /// Configuration of the HAL typedef struct { - int host_id; ///< Host ID of the spi peripheral - int spics_io_num; ///< CS GPIO pin for this device - uint8_t mode; ///< SPI mode (0-3) - int command_bits; ///< command field bits, multiples of 8 and at least 8. - int address_bits; ///< address field bits, multiples of 8 and at least 8. - int dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. + uint32_t host_id; ///< Host ID of the spi peripheral + spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address + spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address + uint32_t spics_io_num; ///< CS GPIO pin for this device + uint8_t mode; ///< SPI mode (0-3) + uint32_t command_bits; ///< command field bits, multiples of 8 and at least 8. + uint32_t address_bits; ///< address field bits, multiples of 8 and at least 8. + uint32_t dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. struct { - uint32_t tx_lsbfirst : 1;///< Whether TX data should be sent with LSB first. - uint32_t rx_lsbfirst : 1;///< Whether RX data should be read with LSB first. + uint32_t tx_lsbfirst : 1; ///< Whether TX data should be sent with LSB first. + uint32_t rx_lsbfirst : 1; ///< Whether RX data should be read with LSB first. }; - int dma_chan; ///< The dma channel used. + uint32_t dma_chan; ///< The dma channel used. } spi_slave_hd_hal_config_t; -/// Context of the HAL, initialized by :cpp:func:`slave_hd_hal_init`. +/// Context of the HAL, initialized by :cpp:func:`spi_slave_hd_hal_init`. typedef struct { - spi_dev_t* dev; ///< Beginning address of the peripheral registers. - lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ + spi_dev_t *dev; ///< Beginning address of the peripheral registers. + spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ /* Internal status used by the HAL implementation, initialized as 0. */ - uint32_t intr_not_triggered; + uint32_t intr_not_triggered; } spi_slave_hd_hal_context_t; - /** * @brief Initialize the hardware and part of the context * - * @param hal Context of the HAL layer - * @param config Configuration of the HAL + * @param hal Context of the HAL layer + * @param hal_config Configuration of the HAL */ -void slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *config); +void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config); /** * @brief Check and clear signal of one event * * @param hal Context of the HAL layer * @param ev Event to check - * @return true if event triggered, otherwise false + * @return True if event triggered, otherwise false */ bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); @@ -116,7 +118,7 @@ bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_eve * * @param hal Context of the HAL layer * @param ev Event to check and disable - * @return true if event triggered, otherwise false + * @return True if event triggered, otherwise false */ bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); @@ -156,7 +158,7 @@ void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, s * @brief Get the length of total received data * * @param hal Context of the HAL layer - * @return The received length + * @return The received length */ int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal); @@ -167,8 +169,8 @@ int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal); * @brief Start the TX DMA operation with the specified buffer * * @param hal Context of the HAL layer - * @param data Buffer of data to send - * @param len Size of the buffer, also the maximum length to send + * @param data Buffer of data to send + * @param len Size of the buffer, also the maximum length to send */ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len); @@ -179,9 +181,9 @@ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size * @brief Read from the shared register buffer * * @param hal Context of the HAL layer - * @param addr Address of the shared regsiter to read - * @param out_data Buffer to store the read data - * @param len Length to read from the shared buffer + * @param addr Address of the shared regsiter to read + * @param out_data Buffer to store the read data + * @param len Length to read from the shared buffer */ void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len); @@ -199,7 +201,7 @@ void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, ui * @brief Get the length of previous transaction. * * @param hal Context of the HAL layer - * @return The length of previous transaction + * @return The length of previous transaction */ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); @@ -207,6 +209,6 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); * @brief Get the address of last transaction * * @param hal Context of the HAL layer - * @return The address of last transaction + * @return The address of last transaction */ int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); diff --git a/tools/sdk/esp32/include/idf_test/include/esp32s3/idf_performance_target.h b/tools/sdk/esp32/include/idf_test/include/esp32s3/idf_performance_target.h new file mode 100644 index 00000000..269a3c91 --- /dev/null +++ b/tools/sdk/esp32/include/idf_test/include/esp32s3/idf_performance_target.h @@ -0,0 +1,33 @@ +#pragma once + +#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 14.4 + +// SHA256 hardware throughput at 240MHz, threshold set lower than worst case +#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 19.8 +// esp_sha() time to process 32KB of input data from RAM +#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 1000 +#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 + +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 18000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1500000 + +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (309*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600 +#endif + +// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) +#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 +#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/tools/sdk/esp32/include/log/include/esp_log.h b/tools/sdk/esp32/include/log/include/esp_log.h index 1abc70c1..a6ac60ea 100644 --- a/tools/sdk/esp32/include/log/include/esp_log.h +++ b/tools/sdk/esp32/include/log/include/esp_log.h @@ -23,6 +23,8 @@ #include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/lwip/port/esp32/include/netdb.h b/tools/sdk/esp32/include/lwip/port/esp32/include/netdb.h index 363154f6..7f5d67a4 100644 --- a/tools/sdk/esp32/include/lwip/port/esp32/include/netdb.h +++ b/tools/sdk/esp32/include/lwip/port/esp32/include/netdb.h @@ -32,9 +32,17 @@ #include "lwip/netdb.h" +#ifdef __cplusplus +extern "C" { +#endif + #ifdef ESP_PLATFORM int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, char *host, socklen_t hostlen, char *serv, socklen_t servlen, int flags); #endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/mbedtls/port/include/aes_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/aes_alt.h index ee6cfed6..f313d508 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/aes_alt.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/aes_alt.h @@ -32,6 +32,8 @@ extern "C" { #include "esp32/aes.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/aes.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/aes.h" #endif typedef esp_aes_context mbedtls_aes_context; diff --git a/tools/sdk/esp32/include/mbedtls/port/include/esp32/sha.h b/tools/sdk/esp32/include/mbedtls/port/include/esp32/sha.h index 2009d198..b99d613c 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/esp32/sha.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/esp32/sha.h @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,201 +11,10 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _ESP_SHA_H_ -#define _ESP_SHA_H_ -#include "esp32/rom/sha.h" -#include "esp_types.h" +#pragma once -/** @brief Low-level support functions for the hardware SHA engine - * - * @note If you're looking for a SHA API to use, try mbedtls component - * mbedtls/shaXX.h. That API supports hardware acceleration. - * - * The API in this header provides some building blocks for implementing a - * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). - * - * Some technical details about the hardware SHA engine: - * - * - SHA accelerator engine calculates one digest at a time, per SHA - * algorithm type. It initialises and maintains the digest state - * internally. It is possible to read out an in-progress SHA digest - * state, but it is not possible to restore a SHA digest state - * into the engine. - * - * - The memory block SHA_TEXT_BASE is shared between all SHA digest - * engines, so all engines must be idle before this memory block is - * modified. - * - */ -#ifdef __cplusplus -extern "C" { -#endif - -/* Defined in esp32/rom/sha.h */ -typedef enum SHA_TYPE esp_sha_type; - -/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine - * - * @note For more versatile SHA calculations, where data doesn't need - * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The - * hardware-accelerated mbedTLS implementation is also faster when - * hashing large amounts of data. - * - * @note It is not necessary to lock any SHA hardware before calling - * this function, thread safety is managed internally. - * - * @note If a TLS connection is open then this function may block - * indefinitely waiting for a SHA engine to become available. Use the - * mbedTLS SHA API to avoid this problem. - * - * @param sha_type SHA algorithm to use. - * - * @param input Input data buffer. - * - * @param ilen Length of input data in bytes. - * - * @param output Buffer for output SHA digest. Output is 20 bytes for - * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for - * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. - */ -void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); - -/* @brief Begin to execute a single SHA block operation - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA - * algorithm. - * - * @note Call esp_sha_try_lock_engine() before calling this - * function. Do not call esp_sha_lock_memory_block() beforehand, this - * is done inside the function. - * - * @param sha_type SHA algorithm to use. - * - * @param data_block Pointer to block of data. Block size is - * determined by algorithm (SHA1/SHA2_256 = 64 bytes, - * SHA2_384/SHA2_512 = 128 bytes) - * - * @param is_first_block If this parameter is true, the SHA state will - * be initialised (with the initial state of the given SHA algorithm) - * before the block is calculated. If false, the existing state of the - * SHA engine will be used. - * - * @return As a performance optimisation, this function returns before - * the SHA block operation is complete. Both this function and - * esp_sha_read_state() will automatically wait for any previous - * operation to complete before they begin. If using the SHA registers - * directly in another way, call esp_sha_wait_idle() after calling this - * function but before accessing the SHA registers. - */ -void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block); - -/** @brief Read out the current state of the SHA digest loaded in the engine. - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. - * - * @note Call esp_sha_try_lock_engine() before calling this - * function. Do not call esp_sha_lock_memory_block() beforehand, this - * is done inside the function. - * - * If the SHA suffix padding block has been executed already, the - * value that is read is the SHA digest (in big endian - * format). Otherwise, the value that is read is an interim SHA state. - * - * @note If sha_type is SHA2_384, only 48 bytes of state will be read. - * This is enough for the final SHA2_384 digest, but if you want the - * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead. - * - * @param sha_type SHA algorithm in use. - * - * @param state Pointer to a memory buffer to hold the SHA state. Size - * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512). - * - */ -void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); - -/** - * @brief Obtain exclusive access to a particular SHA engine - * - * @param sha_type Type of SHA engine to use. - * - * Blocks until engine is available. Note: Can block indefinitely - * while a TLS connection is open, suggest using - * esp_sha_try_lock_engine() and failing over to software SHA. - */ -void esp_sha_lock_engine(esp_sha_type sha_type); - -/** - * @brief Try and obtain exclusive access to a particular SHA engine - * - * @param sha_type Type of SHA engine to use. - * - * @return Returns true if the SHA engine is locked for exclusive - * use. Call esp_sha_unlock_sha_engine() when done. Returns false if - * the SHA engine is already in use, caller should use software SHA - * algorithm for this digest. - */ -bool esp_sha_try_lock_engine(esp_sha_type sha_type); - -/** - * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine() - * - * @param sha_type Type of engine to release. - */ -void esp_sha_unlock_engine(esp_sha_type sha_type); - -/** - * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE - * - * This memory block is shared across all the SHA algorithm types. - * - * Caller should have already locked a SHA engine before calling this function. - * - * Note that it is possible to obtain exclusive access to the memory block even - * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle() - * to ensure the SHA engine is not reading from the memory block in hardware. - * - * @note This function enters a critical section. Do not block while holding this lock. - * - * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally. - * - * Call esp_sha_unlock_memory_block() when done. - */ -void esp_sha_lock_memory_block(void); - -/** - * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE - * - * Caller should have already locked a SHA engine before calling this function. - * - * This function releases the critical section entered by esp_sha_lock_memory_block(). - * - * Call following esp_sha_lock_memory_block(). - */ -void esp_sha_unlock_memory_block(void); - -/** @brief Wait for the SHA engine to finish any current operation - * - * @note This function does not ensure exclusive access to any SHA - * engine. Caller should use esp_sha_try_lock_engine() and - * esp_sha_lock_memory_block() as required. - * - * @note Functions declared in this header file wait for SHA engine - * completion automatically, so you don't need to use this API for - * these. However if accessing SHA registers directly, you will need - * to call this before accessing SHA registers if using the - * esp_sha_block() function. - * - * @note This function busy-waits, so wastes CPU resources. - * Best to delay calling until you are about to need it. - * - */ -void esp_sha_wait_idle(void); - -#ifdef __cplusplus -} -#endif - -#endif +#include "sha/sha_parallel_engine.h" +#warning esp32/sha.h is deprecated, please use sha_parallel_engine.h instead \ No newline at end of file diff --git a/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/esp_rsa_sign_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/esp_rsa_sign_alt.h new file mode 100644 index 00000000..51fc22e2 --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/esp_rsa_sign_alt.h @@ -0,0 +1,86 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifndef _ESP_RSA_SIGN_ALT_H_ +#define _ESP_RSA_SIGN_ALT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_ds.h" +#include "mbedtls/md.h" + +/** + * @brief ESP-DS data context + * + * @note This structure includes encrypted private key parameters such as ciphertext_c, initialization vector, efuse_key_id, RSA key length, which are obtained when DS peripheral is configured. + */ + +/* Context for encrypted private key data required for DS */ +typedef struct esp_ds_data_ctx { + esp_ds_data_t *esp_ds_data; + uint8_t efuse_key_id; /* efuse block id in which DS_KEY is stored e.g. 0,1*/ + uint16_t rsa_length_bits; /* length of RSA private key in bits e.g. 2048 */ +} esp_ds_data_ctx_t; + +/** + * @brief Initializes internal DS data context + * + * This function allocates and initializes internal ds data context which is used for Digital Signature operation. + * + * @in ds_data ds_data context containing encrypted private key parameters + * @return + * - ESP_OK In case of succees + * - ESP_ERR_NO_MEM In case internal context could not be allocated. + * - ESP_ERR_INVALID_ARG in case input parametrers are NULL + * + */ +esp_err_t esp_ds_init_data_ctx(esp_ds_data_ctx_t *ds_data); + +/** + * + * @brief Release the ds lock acquired for the DS operation (then the DS peripheral can be used for other TLS connection) + * + */ +void esp_ds_release_ds_lock(void); + +/** + * + * @brief Alternate implementation for mbedtls_rsa_rsassa_pkcs1_v15_sign, Internally makes use + * of DS module to perform hardware accelerated RSA sign operation + */ +int esp_ds_rsa_sign( void *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + int mode, mbedtls_md_type_t md_alg, unsigned int hashlen, + const unsigned char *hash, unsigned char *sig ); + +/* + * @brief Get RSA key length in bytes from internal DS context + * + * @return RSA key length in bytes + */ +size_t esp_ds_get_keylen(void *ctx); + +/* + * @brief Set timeout (equal to TLS session timeout), so that DS module usage can be synchronized in case of multiple TLS connections using DS module, + */ +void esp_ds_set_session_timeout(int timeout); +#ifdef __cplusplus +} +#endif + +#endif /* _ESP_RSA_SIGN_ALT_H_ */ diff --git a/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/sha.h b/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/sha.h index 58bd4394..12c6548d 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/sha.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/esp32s2/sha.h @@ -12,157 +12,10 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _ESP_SHA_H_ -#define _ESP_SHA_H_ +#pragma once -#include "esp32s2/rom/sha.h" +#include "sha/sha_dma.h" -/** @brief Low-level support functions for the hardware SHA engine using DMA - * - * @note If you're looking for a SHA API to use, try mbedtls component - * mbedtls/shaXX.h. That API supports hardware acceleration. - * - * The API in this header provides some building blocks for implementing a - * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). - * - * Some technical details about the hardware SHA engine: - * - * - The crypto DMA is shared between the SHA and AES engine, it is not - * possible for them to run calcalutions in parallel. - * - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Defined in rom/sha.h */ -typedef SHA_TYPE esp_sha_type; - -/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine - * - * @note For more versatile SHA calculations, where data doesn't need - * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. - * - * @note It is not necessary to lock any SHA hardware before calling - * this function, thread safety is managed internally. - * - * @param sha_type SHA algorithm to use. - * - * @param input Input data buffer. - * - * @param ilen Length of input data in bytes. - * - * @param output Buffer for output SHA digest. Output is 20 bytes for - * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for - * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. - */ -void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); - -/** @brief Execute SHA block operation using DMA - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA - * algorithm. - * - * @note Call esp_sha_aquire_hardware() before calling this - * function. - * - * @param sha_type SHA algorithm to use. - * - * @param input Pointer to the input data. Block size is - * determined by algorithm (SHA1/SHA2_256 = 64 bytes, - * SHA2_384/SHA2_512 = 128 bytes) - * - * @param ilen length of input data should be multiple of block length. - * - * @param buf Pointer to blocks of data that will be prepended - * to data_block before hashing. Useful when there is two sources of - * data that need to be efficiently calculated in a single SHA DMA - * operation. - * - * @param buf_len length of buf data should be multiple of block length. - * Should not be longer than the maximum amount of bytes in a single block - * (128 bytes) - * - * @param is_first_block If this parameter is true, the SHA state will - * be initialised (with the initial state of the given SHA algorithm) - * before the block is calculated. If false, the existing state of the - * SHA engine will be used. - * - * @param t The number of bits for the SHA512/t hash function, with - * output truncated to t bits. Used for calculating the inital hash. - * t is any positive integer between 1 and 512, except 384. - * - * @return 0 if successful - */ -int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, - const void *buf, uint32_t buf_len, bool is_first_block); - -/** - * @brief Read out the current state of the SHA digest - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. - * - * @note Call esp_sha_aquire_hardware() before calling this - * function. - * - * If the SHA suffix padding block has been executed already, the - * value that is read is the SHA digest. - * Otherwise, the value that is read is an interim SHA state. - * - * @param sha_type SHA algorithm in use. - * @param digest_state Pointer to a memory buffer to hold the SHA state. Size - * is 20 bytes (SHA1), 32 bytes (SHA2_256), or 64 bytes (SHA2_384, SHA2_512). - */ -void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); - -/** - * @brief Set the current state of the SHA digest - * - * @note Call esp_sha_aquire_hardware() before calling this - * function. - * - * When resuming a - * - * @param sha_type SHA algorithm in use. - * @param digest_state - */ -void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state); +#warning esp32s2/sha.h is deprecated, please use sha/sha_dma.h instead -/** - * @brief Enables the SHA and crypto DMA peripheral and takes the - * locks for both of them. - */ -void esp_sha_acquire_hardware(void); - -/** - * @brief Disables the SHA and crypto DMA peripheral and releases the - * locks. - */ -void esp_sha_release_hardware(void); - -/* -*/ - -/** - * @brief Sets the initial hash value for SHA512/t. - * - * @note Is generated according to the algorithm described in the TRM, - * chapter SHA-Accelerator - * - * @note The engine must be locked until the value is used for an operation - * or read out. Else you risk another operation overwriting it. - * - * @param t - * - * @return 0 if successful - */ -int esp_sha_512_t_init_hash(uint16_t t); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/aes.h b/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/aes.h new file mode 100644 index 00000000..904a0ecd --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/aes.h @@ -0,0 +1,369 @@ +/** + * \brief AES block cipher, ESP32 hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_AES_H +#define ESP_AES_H + +#include "esp_types.h" +#include "esp32s3/rom/aes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* padlock.c and aesni.c rely on these values! */ +#define ESP_AES_ENCRYPT 1 +#define ESP_AES_DECRYPT 0 + +#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ + + +/** + * \brief AES context structure + * + * \note buf is able to hold 32 extra bytes, which can be used: + * - for alignment purposes if VIA padlock is used, and/or + * - to simplify key expansion in the 256-bit case by + * generating an extra round key + */ +typedef struct { + uint8_t key_bytes; + volatile uint8_t key_in_hardware; /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ + uint8_t key[32]; +} esp_aes_context; + + +/** + * \brief The AES XTS context-type definition. + */ +typedef struct { + esp_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + esp_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} esp_aes_xts_context; + +/** + * \brief Lock access to AES hardware unit + * + * AES hardware unit can only be used by one + * consumer at a time. + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_acquire_hardware( void ); + +/** + * \brief Unlock access to AES hardware unit + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_release_hardware( void ); + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void esp_aes_init( esp_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void esp_aes_free( esp_aes_context *ctx ); + +/* + * \brief This function initializes the specified AES XTS context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES XTS context to initialize. + */ +void esp_aes_xts_init( esp_aes_xts_context *ctx ); + +/** + * \brief This function releases and clears the specified AES XTS context. + * + * \param ctx The AES XTS context to clear. + */ +void esp_aes_xts_free( esp_aes_xts_context *ctx ); + +/** + * \brief AES set key schedule (encryption or decryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ + +/** + * \brief AES set key schedule (encryption or decryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); + +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH + */ +int esp_aes_crypt_cbc( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb128( esp_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb8( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int esp_aes_crypt_ctr( esp_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs an AES-OFB (Output Feedback Mode) + * encryption or decryption operation. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int esp_aes_crypt_ofb( esp_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function prepares an XTS context for encryption and + * sets the encryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * \param key The encryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int esp_aes_xts_setkey_enc( esp_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +int esp_aes_xts_setkey_dec( esp_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +int esp_internal_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** Deprecated, see esp_aes_internal_encrypt */ +void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated)); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +int esp_internal_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** Deprecated, see esp_aes_internal_decrypt */ +void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated)); + +/** AES-XTS buffer encryption/decryption */ +int esp_aes_crypt_xts( esp_aes_xts_context *ctx, int mode, size_t length, const unsigned char data_unit[16], const unsigned char *input, unsigned char *output ); + + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/crypto_dma.h b/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/crypto_dma.h new file mode 100644 index 00000000..ce7d67ef --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/crypto_dma.h @@ -0,0 +1,40 @@ +/** + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_CRYPTO_DMA_H +#define ESP_CRYPTO_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Since crypto DMA is shared between DMA-AES and SHA blocks + * Needs to be taken by respective blocks before using Crypto DMA + */ +extern _lock_t crypto_dma_lock; + +#ifdef __cplusplus +} +#endif + +#endif /* crypto_dma.h */ diff --git a/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/gcm.h b/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/gcm.h new file mode 100644 index 00000000..07c80ad5 --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/esp32s3/gcm.h @@ -0,0 +1,238 @@ +/** + * \brief AES block cipher, ESP32C hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2019-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_GCM_H +#define ESP_GCM_H + +#include "aes.h" +#include "mbedtls/cipher.h" +#ifdef __cplusplus +extern "C" { +#endif + + +#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 /**< Authenticated decryption failed. */ +#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 /**< Bad input parameters to function.*/ + +typedef enum { + ESP_AES_GCM_STATE_INIT, + ESP_AES_GCM_STATE_UPDATE, + ESP_AES_GCM_STATE_FINISH +} esp_aes_gcm_state; +/** + * \brief The GCM context structure. + */ +typedef struct { + uint8_t H[16]; /*!< Initial hash value */ + uint8_t ghash[16]; /*!< GHASH value. */ + uint8_t J0[16]; + uint64_t HL[16]; /*!< Precalculated HTable low. */ + uint64_t HH[16]; /*!< Precalculated HTable high. */ + uint8_t ori_j0[16]; /*!< J0 from first iteration. */ + const uint8_t *iv; + size_t iv_len; /*!< The length of IV. */ + uint64_t aad_len; /*!< The total length of the additional data. */ + size_t data_len; + int mode; + const unsigned char *aad; /*!< The additional data. */ + esp_aes_context aes_ctx; + esp_aes_gcm_state gcm_state; +} esp_gcm_context; + +/** + * \brief This function initializes the specified GCM context + * + * \param ctx The GCM context to initialize. + */ +void esp_aes_gcm_init( esp_gcm_context *ctx); + +/** + * \brief This function associates a GCM context with a + * key. + * + * \param ctx The GCM context to initialize. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. + * \param keybits The key size in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int esp_aes_gcm_setkey( esp_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function starts a GCM encryption or decryption + * operation. + * + * \param ctx The GCM context. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data, or NULL + * if \p add_len is 0. + * \param add_len The length of the additional data. If 0, + * \p add is NULL. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_starts( esp_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *aad, + size_t aad_len ); + +/** + * \brief This function feeds an input buffer into an ongoing GCM + * encryption or decryption operation. + * + * ` The function expects input to be a multiple of 16 + * Bytes. Only the last call before calling + * mbedtls_gcm_finish() can be less than 16 Bytes. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_update( esp_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function finishes the GCM operation and generates + * the authentication tag. + * + * It wraps up the GCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \param ctx The GCM context. + * \param tag The buffer for holding the tag. + * \param tag_len The length of the tag to generate. Must be at least four. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_finish( esp_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ); + +/** + * \brief This function clears a GCM context + * + * \param ctx The GCM context to clear. + */ +void esp_aes_gcm_free( esp_gcm_context *ctx); + +/** + * \brief This function performs GCM encryption or decryption of a buffer. + * + * \note For encryption, the output buffer can be the same as the + * input buffer. For decryption, the output buffer cannot be + * the same as input buffer. If the buffers overlap, the output + * buffer must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context to use for encryption or decryption. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * \param tag_len The length of the tag to generate. + * \param tag The buffer for holding the tag. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_crypt_and_tag( esp_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ); + + +/** + * \brief This function performs a GCM authenticated decryption of a + * buffer. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple + * of 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param tag The buffer holding the tag. + * \param tag_len The length of the tag. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return 0 if successful and authenticated. + * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. + */ +int esp_aes_gcm_auth_decrypt( esp_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ); + +#ifdef __cplusplus +} +#endif + +#endif /* gcm.h */ diff --git a/tools/sdk/esp32/include/mbedtls/port/include/gcm_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/gcm_alt.h index c3d886a7..9a79850c 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/gcm_alt.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/gcm_alt.h @@ -29,6 +29,23 @@ extern "C" { #if defined(MBEDTLS_GCM_ALT) +#if CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/gcm.h" + + +typedef esp_gcm_context mbedtls_gcm_context; + +#define mbedtls_gcm_init esp_aes_gcm_init +#define mbedtls_gcm_free esp_aes_gcm_free +#define mbedtls_gcm_setkey esp_aes_gcm_setkey +#define mbedtls_gcm_starts esp_aes_gcm_starts +#define mbedtls_gcm_update esp_aes_gcm_update +#define mbedtls_gcm_finish esp_aes_gcm_finish +#define mbedtls_gcm_auth_decrypt esp_aes_gcm_auth_decrypt +#define mbedtls_gcm_crypt_and_tag esp_aes_gcm_crypt_and_tag + +#endif // CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/gcm.h" diff --git a/tools/sdk/esp32/include/mbedtls/port/include/rsa_sign_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/rsa_sign_alt.h new file mode 100644 index 00000000..a89311a7 --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/rsa_sign_alt.h @@ -0,0 +1,39 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifndef _RSA_SIGN_ALT_H_ +#define _RSA_SIGN_ALT_H_ + +#ifdef __cpluscplus +extern "C" { +#endif + +#ifdef CONFIG_ESP_TLS_USE_DS_PERIPHERAL + +#include "esp32s2/esp_rsa_sign_alt.h" + +#else + +#error "DS configuration flags not activated, please enable required menuconfig flags" + +#endif + +#ifdef __cpluscplus +} +#endif + +#endif + diff --git a/tools/sdk/esp32/include/mbedtls/port/include/sha/sha_dma.h b/tools/sdk/esp32/include/mbedtls/port/include/sha/sha_dma.h new file mode 100644 index 00000000..c71261d1 --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/sha/sha_dma.h @@ -0,0 +1,161 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "hal/sha_types.h" + +/** @brief Low-level support functions for the hardware SHA engine using DMA + * + * @note If you're looking for a SHA API to use, try mbedtls component + * mbedtls/shaXX.h. That API supports hardware acceleration. + * + * The API in this header provides some building blocks for implementing a + * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). + * + * Some technical details about the hardware SHA engine: + * + * - The crypto DMA is shared between the SHA and AES engine, it is not + * possible for them to run calcalutions in parallel. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine + * + * @note For more versatile SHA calculations, where data doesn't need + * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. + * + * @note It is not necessary to lock any SHA hardware before calling + * this function, thread safety is managed internally. + * + * @param sha_type SHA algorithm to use. + * + * @param input Input data buffer. + * + * @param ilen Length of input data in bytes. + * + * @param output Buffer for output SHA digest. Output is 20 bytes for + * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for + * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. + */ +void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); + +/** @brief Execute SHA block operation using DMA + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA + * algorithm. + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * @param sha_type SHA algorithm to use. + * + * @param input Pointer to the input data. Block size is + * determined by algorithm (SHA1/SHA2_256 = 64 bytes, + * SHA2_384/SHA2_512 = 128 bytes) + * + * @param ilen length of input data should be multiple of block length. + * + * @param buf Pointer to blocks of data that will be prepended + * to data_block before hashing. Useful when there is two sources of + * data that need to be efficiently calculated in a single SHA DMA + * operation. + * + * @param buf_len length of buf data should be multiple of block length. + * Should not be longer than the maximum amount of bytes in a single block + * (128 bytes) + * + * @param is_first_block If this parameter is true, the SHA state will + * be initialised (with the initial state of the given SHA algorithm) + * before the block is calculated. If false, the existing state of the + * SHA engine will be used. + * + * @param t The number of bits for the SHA512/t hash function, with + * output truncated to t bits. Used for calculating the inital hash. + * t is any positive integer between 1 and 512, except 384. + * + * @return 0 if successful + */ +int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, + const void *buf, uint32_t buf_len, bool is_first_block); + +/** + * @brief Read out the current state of the SHA digest + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * If the SHA suffix padding block has been executed already, the + * value that is read is the SHA digest. + * Otherwise, the value that is read is an interim SHA state. + * + * @param sha_type SHA algorithm in use. + * @param digest_state Pointer to a memory buffer to hold the SHA state. Size + * is 20 bytes (SHA1), 32 bytes (SHA2_256), or 64 bytes (SHA2_384, SHA2_512). + */ +void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); + +/** + * @brief Set the current state of the SHA digest + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * When resuming a + * + * @param sha_type SHA algorithm in use. + * @param digest_state + */ +void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state); + + +/** + * @brief Enables the SHA and crypto DMA peripheral and takes the + * locks for both of them. + */ +void esp_sha_acquire_hardware(void); + +/** + * @brief Disables the SHA and crypto DMA peripheral and releases the + * locks. + */ +void esp_sha_release_hardware(void); + +/** + * @brief Sets the initial hash value for SHA512/t. + * + * @note Is generated according to the algorithm described in the TRM, + * chapter SHA-Accelerator + * + * @note The engine must be locked until the value is used for an operation + * or read out. Else you risk another operation overwriting it. + * + * @param t + * + * @return 0 if successful + */ +int esp_sha_512_t_init_hash(uint16_t t); + +#ifdef __cplusplus +} +#endif + + diff --git a/tools/sdk/esp32/include/mbedtls/port/include/sha/sha_parallel_engine.h b/tools/sdk/esp32/include/mbedtls/port/include/sha/sha_parallel_engine.h new file mode 100644 index 00000000..51ac7add --- /dev/null +++ b/tools/sdk/esp32/include/mbedtls/port/include/sha/sha_parallel_engine.h @@ -0,0 +1,207 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "hal/sha_types.h" +#include "esp_types.h" + +/** @brief Low-level support functions for the hardware SHA engine + * + * @note If you're looking for a SHA API to use, try mbedtls component + * mbedtls/shaXX.h. That API supports hardware acceleration. + * + * The API in this header provides some building blocks for implementing a + * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). + * + * Some technical details about the hardware SHA engine: + * + * - SHA accelerator engine calculates one digest at a time, per SHA + * algorithm type. It initialises and maintains the digest state + * internally. It is possible to read out an in-progress SHA digest + * state, but it is not possible to restore a SHA digest state + * into the engine. + * + * - The memory block SHA_TEXT_BASE is shared between all SHA digest + * engines, so all engines must be idle before this memory block is + * modified. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine + * + * @note For more versatile SHA calculations, where data doesn't need + * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The + * hardware-accelerated mbedTLS implementation is also faster when + * hashing large amounts of data. + * + * @note It is not necessary to lock any SHA hardware before calling + * this function, thread safety is managed internally. + * + * @note If a TLS connection is open then this function may block + * indefinitely waiting for a SHA engine to become available. Use the + * mbedTLS SHA API to avoid this problem. + * + * @param sha_type SHA algorithm to use. + * + * @param input Input data buffer. + * + * @param ilen Length of input data in bytes. + * + * @param output Buffer for output SHA digest. Output is 20 bytes for + * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for + * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. + */ +void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); + +/* @brief Begin to execute a single SHA block operation + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA + * algorithm. + * + * @note Call esp_sha_try_lock_engine() before calling this + * function. Do not call esp_sha_lock_memory_block() beforehand, this + * is done inside the function. + * + * @param sha_type SHA algorithm to use. + * + * @param data_block Pointer to block of data. Block size is + * determined by algorithm (SHA1/SHA2_256 = 64 bytes, + * SHA2_384/SHA2_512 = 128 bytes) + * + * @param is_first_block If this parameter is true, the SHA state will + * be initialised (with the initial state of the given SHA algorithm) + * before the block is calculated. If false, the existing state of the + * SHA engine will be used. + * + * @return As a performance optimisation, this function returns before + * the SHA block operation is complete. Both this function and + * esp_sha_read_state() will automatically wait for any previous + * operation to complete before they begin. If using the SHA registers + * directly in another way, call esp_sha_wait_idle() after calling this + * function but before accessing the SHA registers. + */ +void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block); + +/** @brief Read out the current state of the SHA digest loaded in the engine. + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. + * + * @note Call esp_sha_try_lock_engine() before calling this + * function. Do not call esp_sha_lock_memory_block() beforehand, this + * is done inside the function. + * + * If the SHA suffix padding block has been executed already, the + * value that is read is the SHA digest (in big endian + * format). Otherwise, the value that is read is an interim SHA state. + * + * @note If sha_type is SHA2_384, only 48 bytes of state will be read. + * This is enough for the final SHA2_384 digest, but if you want the + * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead. + * + * @param sha_type SHA algorithm in use. + * + * @param state Pointer to a memory buffer to hold the SHA state. Size + * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512). + * + */ +void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); + +/** + * @brief Obtain exclusive access to a particular SHA engine + * + * @param sha_type Type of SHA engine to use. + * + * Blocks until engine is available. Note: Can block indefinitely + * while a TLS connection is open, suggest using + * esp_sha_try_lock_engine() and failing over to software SHA. + */ +void esp_sha_lock_engine(esp_sha_type sha_type); + +/** + * @brief Try and obtain exclusive access to a particular SHA engine + * + * @param sha_type Type of SHA engine to use. + * + * @return Returns true if the SHA engine is locked for exclusive + * use. Call esp_sha_unlock_sha_engine() when done. Returns false if + * the SHA engine is already in use, caller should use software SHA + * algorithm for this digest. + */ +bool esp_sha_try_lock_engine(esp_sha_type sha_type); + +/** + * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine() + * + * @param sha_type Type of engine to release. + */ +void esp_sha_unlock_engine(esp_sha_type sha_type); + +/** + * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE + * + * This memory block is shared across all the SHA algorithm types. + * + * Caller should have already locked a SHA engine before calling this function. + * + * Note that it is possible to obtain exclusive access to the memory block even + * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle() + * to ensure the SHA engine is not reading from the memory block in hardware. + * + * @note This function enters a critical section. Do not block while holding this lock. + * + * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally. + * + * Call esp_sha_unlock_memory_block() when done. + */ +void esp_sha_lock_memory_block(void); + +/** + * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE + * + * Caller should have already locked a SHA engine before calling this function. + * + * This function releases the critical section entered by esp_sha_lock_memory_block(). + * + * Call following esp_sha_lock_memory_block(). + */ +void esp_sha_unlock_memory_block(void); + +/** @brief Wait for the SHA engine to finish any current operation + * + * @note This function does not ensure exclusive access to any SHA + * engine. Caller should use esp_sha_try_lock_engine() and + * esp_sha_lock_memory_block() as required. + * + * @note Functions declared in this header file wait for SHA engine + * completion automatically, so you don't need to use this API for + * these. However if accessing SHA registers directly, you will need + * to call this before accessing SHA registers if using the + * esp_sha_block() function. + * + * @note This function busy-waits, so wastes CPU resources. + * Best to delay calling until you are about to need it. + * + */ +void esp_sha_wait_idle(void); + +#ifdef __cplusplus +} +#endif + + diff --git a/tools/sdk/esp32/include/mbedtls/port/include/sha1_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/sha1_alt.h index a3f05a84..7c145ae5 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/sha1_alt.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/sha1_alt.h @@ -23,15 +23,35 @@ #ifndef _SHA1_ALT_H_ #define _SHA1_ALT_H_ +#if defined(MBEDTLS_SHA1_ALT) + +#include "hal/sha_types.h" +#include "soc/sha_caps.h" + #ifdef __cplusplus extern "C" { #endif -#if defined(MBEDTLS_SHA1_ALT) +#if SOC_SHA_SUPPORT_PARALLEL_ENG -#if CONFIG_IDF_TARGET_ESP32S2 +typedef enum { + ESP_MBEDTLS_SHA1_UNUSED, /* first block hasn't been processed yet */ + ESP_MBEDTLS_SHA1_HARDWARE, /* using hardware SHA engine */ + ESP_MBEDTLS_SHA1_SOFTWARE, /* using software SHA */ +} esp_mbedtls_sha1_mode; + +/** + * \brief SHA-1 context structure + */ +typedef struct { + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[5]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ + esp_mbedtls_sha1_mode mode; +} mbedtls_sha1_context; + +#elif SOC_SHA_SUPPORT_DMA -#include "esp32s2/sha.h" typedef enum { ESP_SHA1_STATE_INIT, ESP_SHA1_STATE_IN_PROCESS @@ -49,28 +69,7 @@ typedef struct { esp_sha1_state sha_state; } mbedtls_sha1_context; -#endif //CONFIG_IDF_TARGET_ESP32S2 - -#if CONFIG_IDF_TARGET_ESP32 - -typedef enum { - ESP_MBEDTLS_SHA1_UNUSED, /* first block hasn't been processed yet */ - ESP_MBEDTLS_SHA1_HARDWARE, /* using hardware SHA engine */ - ESP_MBEDTLS_SHA1_SOFTWARE, /* using software SHA */ -} esp_mbedtls_sha1_mode; - -/** - * \brief SHA-1 context structure - */ -typedef struct { - uint32_t total[2]; /*!< number of bytes processed */ - uint32_t state[5]; /*!< intermediate digest state */ - unsigned char buffer[64]; /*!< data block being processed */ - esp_mbedtls_sha1_mode mode; -} -mbedtls_sha1_context; - -#endif //CONFIG_IDF_TARGET_ESP32 +#endif #endif diff --git a/tools/sdk/esp32/include/mbedtls/port/include/sha256_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/sha256_alt.h index db82fb64..3a1f385e 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/sha256_alt.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/sha256_alt.h @@ -23,39 +23,16 @@ #ifndef _SHA256_ALT_H_ #define _SHA256_ALT_H_ +#if defined(MBEDTLS_SHA256_ALT) + +#include "hal/sha_types.h" +#include "soc/sha_caps.h" + #ifdef __cplusplus extern "C" { #endif -#if defined(MBEDTLS_SHA256_ALT) - - -#if CONFIG_IDF_TARGET_ESP32S2 - -#include "esp32s2/sha.h" - -typedef enum { - ESP_SHA256_STATE_INIT, - ESP_SHA256_STATE_IN_PROCESS -} esp_sha256_state; - -/** - * \brief SHA-256 context structure - */ -typedef struct { - uint32_t total[2]; /*!< number of bytes processed */ - uint32_t state[8]; /*!< intermediate digest state */ - unsigned char buffer[64]; /*!< data block being processed */ - int first_block; /*!< if first then true, else false */ - esp_sha_type mode; - esp_sha256_state sha_state; -} -mbedtls_sha256_context; - -#endif //CONFIG_IDF_TARGET_ESP32S2 - -#if CONFIG_IDF_TARGET_ESP32 - +#if SOC_SHA_SUPPORT_PARALLEL_ENG typedef enum { ESP_MBEDTLS_SHA256_UNUSED, /* first block hasn't been processed yet */ ESP_MBEDTLS_SHA256_HARDWARE, /* using hardware SHA engine */ @@ -71,10 +48,27 @@ typedef struct { unsigned char buffer[64]; /*!< data block being processed */ int is224; /*!< 0 => SHA-256, else SHA-224 */ esp_mbedtls_sha256_mode mode; -} -mbedtls_sha256_context; +} mbedtls_sha256_context; -#endif //CONFIG_IDF_TARGET_ESP32 +#elif SOC_SHA_SUPPORT_DMA +typedef enum { + ESP_SHA256_STATE_INIT, + ESP_SHA256_STATE_IN_PROCESS +} esp_sha256_state; + +/** + * \brief SHA-256 context structure + */ +typedef struct { + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[8]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ + int first_block; /*!< if first then true, else false */ + esp_sha_type mode; + esp_sha256_state sha_state; +} mbedtls_sha256_context; + +#endif #endif diff --git a/tools/sdk/esp32/include/mbedtls/port/include/sha512_alt.h b/tools/sdk/esp32/include/mbedtls/port/include/sha512_alt.h index da58e8a7..4f5cc005 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/sha512_alt.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/sha512_alt.h @@ -23,15 +23,36 @@ #ifndef _SHA512_ALT_H_ #define _SHA512_ALT_H_ +#if defined(MBEDTLS_SHA512_ALT) + +#include "hal/sha_types.h" +#include "soc/sha_caps.h" #ifdef __cplusplus extern "C" { #endif -#if defined(MBEDTLS_SHA512_ALT) -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/sha.h" +#if SOC_SHA_SUPPORT_PARALLEL_ENG + +typedef enum { + ESP_MBEDTLS_SHA512_UNUSED, /* first block hasn't been processed yet */ + ESP_MBEDTLS_SHA512_HARDWARE, /* using hardware SHA engine */ + ESP_MBEDTLS_SHA512_SOFTWARE, /* using software SHA */ +} esp_mbedtls_sha512_mode; + +/** + * \brief SHA-512 context structure + */ +typedef struct { + uint64_t total[2]; /*!< number of bytes processed */ + uint64_t state[8]; /*!< intermediate digest state */ + unsigned char buffer[128]; /*!< data block being processed */ + int is384; /*!< 0 => SHA-512, else SHA-384 */ + esp_mbedtls_sha512_mode mode; +} mbedtls_sha512_context; + +#elif SOC_SHA_SUPPORT_DMA typedef enum { ESP_SHA512_STATE_INIT, @@ -64,29 +85,8 @@ void esp_sha512_set_mode(mbedtls_sha512_context *ctx, esp_sha_type type); /* For SHA512/t mode the intial hash value will depend on t */ void esp_sha512_set_t( mbedtls_sha512_context *ctx, uint16_t t_val); -#endif //CONFIG_IDF_TARGET_ESP32S2 -#if CONFIG_IDF_TARGET_ESP32 - -typedef enum { - ESP_MBEDTLS_SHA512_UNUSED, /* first block hasn't been processed yet */ - ESP_MBEDTLS_SHA512_HARDWARE, /* using hardware SHA engine */ - ESP_MBEDTLS_SHA512_SOFTWARE, /* using software SHA */ -} esp_mbedtls_sha512_mode; - -/** - * \brief SHA-512 context structure - */ -typedef struct { - uint64_t total[2]; /*!< number of bytes processed */ - uint64_t state[8]; /*!< intermediate digest state */ - unsigned char buffer[128]; /*!< data block being processed */ - int is384; /*!< 0 => SHA-512, else SHA-384 */ - esp_mbedtls_sha512_mode mode; -} -mbedtls_sha512_context; - -#endif //CONFIG_IDF_TARGET_ESP32 +#endif #endif diff --git a/tools/sdk/esp32/include/nvs_flash/include/nvs.h b/tools/sdk/esp32/include/nvs_flash/include/nvs.h index 3e877a65..2f4aa551 100644 --- a/tools/sdk/esp32/include/nvs_flash/include/nvs.h +++ b/tools/sdk/esp32/include/nvs_flash/include/nvs.h @@ -59,12 +59,14 @@ typedef nvs_handle_t nvs_handle IDF_DEPRECATED("Replace with nvs_handle_t"); #define ESP_ERR_NVS_ENCR_NOT_SUPPORTED (ESP_ERR_NVS_BASE + 0x15) /*!< NVS encryption is not supported in this version */ #define ESP_ERR_NVS_KEYS_NOT_INITIALIZED (ESP_ERR_NVS_BASE + 0x16) /*!< NVS key partition is uninitialized */ #define ESP_ERR_NVS_CORRUPT_KEY_PART (ESP_ERR_NVS_BASE + 0x17) /*!< NVS key partition is corrupt */ +#define ESP_ERR_NVS_WRONG_ENCRYPTION (ESP_ERR_NVS_BASE + 0x19) /*!< NVS partition is marked as encrypted with generic flash encryption. This is forbidden since the NVS encryption works differently. */ #define ESP_ERR_NVS_CONTENT_DIFFERS (ESP_ERR_NVS_BASE + 0x18) /*!< Internal error; never returned by nvs API functions. NVS key is different in comparison */ #define NVS_DEFAULT_PART_NAME "nvs" /*!< Default partition name of the NVS partition in the partition table */ #define NVS_PART_NAME_MAX_SIZE 16 /*!< maximum length of partition name (excluding null terminator) */ +#define NVS_KEY_NAME_MAX_SIZE 16 /*!< Maximal length of NVS key name (including null terminator) */ /** * @brief Mode of opening the non-volatile storage @@ -121,9 +123,7 @@ typedef struct nvs_opaque_iterator_t *nvs_iterator_t; * The default NVS partition is the one that is labelled "nvs" in the partition * table. * - * @param[in] name Namespace name. Maximal length is determined by the - * underlying implementation, but is guaranteed to be - * at least 15 characters. Shouldn't be empty. + * @param[in] name Namespace name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] open_mode NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will * open a handle for reading only. All write requests will * be rejected for this handle. @@ -149,9 +149,7 @@ esp_err_t nvs_open(const char* name, nvs_open_mode_t open_mode, nvs_handle_t *ou * with NVS using nvs_flash_init_partition() API. * * @param[in] part_name Label (name) of the partition of interest for object read/write/erase - * @param[in] name Namespace name. Maximal length is determined by the - * underlying implementation, but is guaranteed to be - * at least 15 characters. Shouldn't be empty. + * @param[in] name Namespace name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] open_mode NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will * open a handle for reading only. All write requests will * be rejected for this handle. @@ -178,9 +176,7 @@ esp_err_t nvs_open_from_partition(const char *part_name, const char* name, nvs_o * * @param[in] handle Handle obtained from nvs_open function. * Handles that were opened read only cannot be used. - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] value The value to set. * For strings, the maximum length (including null character) is * 4000 bytes. @@ -217,7 +213,7 @@ esp_err_t nvs_set_str (nvs_handle_t handle, const char* key, const char* value); * * @param[in] handle Handle obtained from nvs_open function. * Handles that were opened read only cannot be used. - * @param[in] key Key name. Maximal length is 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] value The value to set. * @param[in] length length of binary value to set, in bytes; Maximum length is * 508000 bytes or (97.6% of the partition size - 4000) bytes @@ -262,9 +258,7 @@ esp_err_t nvs_set_blob(nvs_handle_t handle, const char* key, const void* value, * \endcode * * @param[in] handle Handle obtained from nvs_open function. - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param out_value Pointer to the output value. * May be NULL for nvs_get_str and nvs_get_blob, in this * case required length will be returned in length argument. @@ -323,9 +317,7 @@ esp_err_t nvs_get_u64 (nvs_handle_t handle, const char* key, uint64_t* out_value * \endcode * * @param[in] handle Handle obtained from nvs_open function. - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param out_value Pointer to the output value. * May be NULL for nvs_get_str and nvs_get_blob, in this * case required length will be returned in length argument. @@ -355,9 +347,7 @@ esp_err_t nvs_get_blob(nvs_handle_t handle, const char* key, void* out_value, si * @param[in] handle Storage handle obtained with nvs_open. * Handles that were opened read only cannot be used. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * * @return * - ESP_OK if erase operation was successful diff --git a/tools/sdk/esp32/include/nvs_flash/include/nvs_handle.hpp b/tools/sdk/esp32/include/nvs_flash/include/nvs_handle.hpp index d87c1c28..537d2f9f 100644 --- a/tools/sdk/esp32/include/nvs_flash/include/nvs_handle.hpp +++ b/tools/sdk/esp32/include/nvs_flash/include/nvs_handle.hpp @@ -44,9 +44,7 @@ public: * * Sets value for key. Note that physical storage will not be updated until nvs_commit function is called. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] value The value to set. Allowed types are the ones declared in ItemType as well as enums. * For strings, the maximum length (including null character) is * 4000 bytes. @@ -79,9 +77,7 @@ public: * * In case of any error, out_value is not modified. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param value The output value. All integral types which are declared in ItemType as well as enums * are allowed. Note however that enums lost their type information when stored in NVS. * Ensure that the correct enum type is used during retrieval with \ref get_item! @@ -101,7 +97,7 @@ public: * This family of functions set value for the key, given its name. Note that * actual storage will not be updated until nvs_commit function is called. * - * @param[in] key Key name. Maximal length is 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] blob The blob value to set. * @param[in] len length of binary value to set, in bytes; Maximum length is * 508000 bytes or (97.6% of the partition size - 4000) bytes @@ -138,9 +134,7 @@ public: * It is suggested that nvs_get/set_str is used for zero-terminated C strings, and * nvs_get/set_blob used for arbitrary data structures. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param out_str/ Pointer to the output value. * out_blob * @param[inout] length A non-zero pointer to the variable holding the length of out_value. diff --git a/tools/sdk/esp32/include/soc/include/hal/sha_hal.h b/tools/sdk/esp32/include/soc/include/hal/sha_hal.h new file mode 100644 index 00000000..ff3e7e23 --- /dev/null +++ b/tools/sdk/esp32/include/soc/include/hal/sha_hal.h @@ -0,0 +1,91 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include +#include "soc/sha_caps.h" +#include "soc/lldesc.h" +#include "hal/sha_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Hashes a single message block + * + * @param sha_type SHA algorithm to hash with + * @param data_block Input message to be hashed + * @param block_word_len Length of the input message + * @param first_block Is this the first block in a message or a continuation? + */ +void sha_hal_hash_block(esp_sha_type sha_type, const void *data_block, size_t block_word_len, bool first_block); + +/** + * @brief Polls and waits until the SHA engine is idle + * + */ +void sha_hal_wait_idle(void); + +/** + * @brief Reads the current message digest from the SHA engine + * + * @param sha_type SHA algorithm used + * @param digest_state Output buffer to which to read message digest to + */ +void sha_hal_read_digest(esp_sha_type sha_type, void *digest_state); + +#if SOC_SHA_SUPPORT_RESUME +/** + * @brief Writes the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + */ +void sha_hal_write_digest(esp_sha_type sha_type, void *digest_state); +#endif + +#if SOC_SHA_SUPPORT_DMA +/** + * @brief Hashes a number of message blocks using DMA + * + * @param sha_type SHA algorithm to hash with + * @param input Input message to be hashed + * @param num_blocks Number of blocks to hash + * @param first_block Is this the first block in a message or a continuation? + */ +void sha_hal_hash_dma(esp_sha_type sha_type, lldesc_t *input, size_t num_blocks, bool first_block); +#endif + +#if SOC_SHA_SUPPORT_SHA512_T +/** + * @brief Calculates and sets the initial digiest for SHA512_t + * + * @param t_string + * @param t_len + */ +void sha_hal_sha512_init_hash(uint32_t t_string, uint8_t t_len); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h index 8aa78999..f6b6137c 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h @@ -104,7 +104,7 @@ #define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 /* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: chip package */ +/*description: least significant bits of chip package */ #define EFUSE_RD_CHIP_VER_PKG 0x00000007 #define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) #define EFUSE_RD_CHIP_VER_PKG_V 0x7 @@ -127,12 +127,12 @@ #define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) #define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 #define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 -/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_RD_CHIP_VER_32PAD (BIT(2)) -#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) -#define EFUSE_RD_CHIP_VER_32PAD_V 0x1 -#define EFUSE_RD_CHIP_VER_32PAD_S 2 +/* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: most significant bit of chip package */ +#define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2)) +#define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2)) +#define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1 +#define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2 /* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) @@ -381,7 +381,7 @@ #define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 #define EFUSE_CHIP_CPU_FREQ_LOW_S 12 /* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ -/*description: */ +/*description: least significant bits of chip package */ #define EFUSE_CHIP_VER_PKG 0x00000007 #define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) #define EFUSE_CHIP_VER_PKG_V 0x7 @@ -391,6 +391,7 @@ #define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 #define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 #define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ /*description: program for SPI_pad_config_hd*/ #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F @@ -403,12 +404,12 @@ #define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) #define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 #define EFUSE_CHIP_VER_DIS_CACHE_S 3 -/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define EFUSE_CHIP_VER_32PAD (BIT(2)) -#define EFUSE_CHIP_VER_32PAD_M (BIT(2)) -#define EFUSE_CHIP_VER_32PAD_V 0x1 -#define EFUSE_CHIP_VER_32PAD_S 2 +/* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: most significant bit of chip package */ +#define EFUSE_CHIP_VER_PKG_4BIT (BIT(2)) +#define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2)) +#define EFUSE_CHIP_VER_PKG_4BIT_V 0x1 +#define EFUSE_CHIP_VER_PKG_4BIT_S 2 /* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ /*description: */ #define EFUSE_CHIP_VER_DIS_BT (BIT(1)) diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_caps.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rsa_caps.h similarity index 86% rename from tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_caps.h rename to tools/sdk/esp32/include/soc/soc/esp32/include/soc/rsa_caps.h index e3a7b1a1..475dc4fe 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_caps.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rsa_caps.h @@ -18,7 +18,8 @@ extern "C" { #endif -#define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ + +#define SOC_RSA_MAX_BIT_LEN (4096) #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h index e955a69f..c6cccfb2 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h @@ -19,6 +19,8 @@ #include "soc/soc.h" #include "soc/rtc_periph.h" +#define MHZ (1000000) + #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/sha_caps.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/sha_caps.h new file mode 100644 index 00000000..b409013f --- /dev/null +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/sha_caps.h @@ -0,0 +1,34 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_SHA_SUPPORT_DMA (0) + +/* ESP32 style SHA engine, where multiple states can be stored in parallel */ +#define SOC_SHA_SUPPORT_PARALLEL_ENG (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) +#define SOC_SHA_SUPPORT_SHA384 (1) +#define SOC_SHA_SUPPORT_SHA512 (1) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h index a6c62f28..a707c8af 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h @@ -256,6 +256,8 @@ #define SOC_EXTRAM_DATA_LOW 0x3F800000 #define SOC_EXTRAM_DATA_HIGH 0x3FC00000 +#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) + //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x400A0000 #define SOC_DIRAM_IRAM_HIGH 0x400C0000 diff --git a/tools/sdk/esp32/include/spi_flash/include/esp_partition.h b/tools/sdk/esp32/include/spi_flash/include/esp_partition.h index 72c543bd..930f7d69 100644 --- a/tools/sdk/esp32/include/spi_flash/include/esp_partition.h +++ b/tools/sdk/esp32/include/spi_flash/include/esp_partition.h @@ -202,6 +202,9 @@ const esp_partition_t *esp_partition_verify(const esp_partition_t *partition); /** * @brief Read data from the partition * + * Partitions marked with an encryption flag will automatically be + * be read and decrypted via a cache mapping. + * * @param partition Pointer to partition structure obtained using * esp_partition_find_first or esp_partition_get. * Must be non-NULL. @@ -250,7 +253,59 @@ esp_err_t esp_partition_read(const esp_partition_t* partition, * or one of error codes from lower-level flash driver. */ esp_err_t esp_partition_write(const esp_partition_t* partition, - size_t dst_offset, const void* src, size_t size); + size_t dst_offset, const void* src, size_t size); + +/** + * @brief Read data from the partition + * + * @note This function is essentially the same as \c esp_partition_write() above. + * It just never decrypts data but returns it as is. + * + * @param partition Pointer to partition structure obtained using + * esp_partition_find_first or esp_partition_get. + * Must be non-NULL. + * @param dst Pointer to the buffer where data should be stored. + * Pointer must be non-NULL and buffer must be at least 'size' bytes long. + * @param src_offset Address of the data to be read, relative to the + * beginning of the partition. + * @param size Size of data to be read, in bytes. + * + * @return ESP_OK, if data was read successfully; + * ESP_ERR_INVALID_ARG, if src_offset exceeds partition size; + * ESP_ERR_INVALID_SIZE, if read would go out of bounds of the partition; + * or one of error codes from lower-level flash driver. + */ +esp_err_t esp_partition_read_raw(const esp_partition_t* partition, + size_t src_offset, void* dst, size_t size); + +/** + * @brief Write data to the partition without any transformation/encryption. + * + * @note This function is essentially the same as \c esp_partition_write() above. + * It just never encrypts data but writes it as is. + * + * Before writing data to flash, corresponding region of flash needs to be erased. + * This can be done using esp_partition_erase_range function. + * + * @param partition Pointer to partition structure obtained using + * esp_partition_find_first or esp_partition_get. + * Must be non-NULL. + * @param dst_offset Address where the data should be written, relative to the + * beginning of the partition. + * @param src Pointer to the source buffer. Pointer must be non-NULL and + * buffer must be at least 'size' bytes long. + * @param size Size of data to be written, in bytes. + * + * @note Prior to writing to flash memory, make sure it has been erased with + * esp_partition_erase_range call. + * + * @return ESP_OK, if data was written successfully; + * ESP_ERR_INVALID_ARG, if dst_offset exceeds partition size; + * ESP_ERR_INVALID_SIZE, if write would go out of bounds of the partition; + * or one of the error codes from lower-level flash driver. + */ +esp_err_t esp_partition_write_raw(const esp_partition_t* partition, + size_t dst_offset, const void* src, size_t size); /** * @brief Erase part of the partition diff --git a/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h b/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h index 814502d2..372a1e1b 100644 --- a/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h +++ b/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h @@ -188,6 +188,7 @@ esp_err_t spi_flash_chip_generic_set_write_protect(esp_flash_t *chip, bool write */ esp_err_t spi_flash_chip_generic_get_write_protect(esp_flash_t *chip, bool *out_write_protect); +#define ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT -1 /** * @brief Read flash status via the RDSR command and wait for bit 0 (write in * progress bit) to be cleared. diff --git a/tools/sdk/esp32/include/tcp_transport/include/esp_transport_ssl.h b/tools/sdk/esp32/include/tcp_transport/include/esp_transport_ssl.h index ff3f9d62..4d53d4d2 100644 --- a/tools/sdk/esp32/include/tcp_transport/include/esp_transport_ssl.h +++ b/tools/sdk/esp32/include/tcp_transport/include/esp_transport_ssl.h @@ -141,6 +141,16 @@ void esp_transport_ssl_skip_common_name_check(esp_transport_handle_t t); */ void esp_transport_ssl_use_secure_element(esp_transport_handle_t t); + +/** + * @brief Set the ds_data handle in ssl context.(used for the digital signature operation) + * + * @param t ssl transport + * ds_data the handle for ds data params + */ + +void esp_transport_ssl_set_ds_data(esp_transport_handle_t t, void *ds_data); + /** * @brief Set PSK key and hint for PSK server/client verification in esp-tls component. * Important notes: diff --git a/tools/sdk/esp32/include/ulp/include/esp32s3/ulp.h b/tools/sdk/esp32/include/ulp/include/esp32s3/ulp.h new file mode 100644 index 00000000..9207a00e --- /dev/null +++ b/tools/sdk/esp32/include/ulp/include/esp32s3/ulp.h @@ -0,0 +1,840 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include +#include "esp_err.h" +#include "soc/soc.h" +#include "ulp_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */ +#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */ + +/** + * @defgroup ulp_registers ULP coprocessor registers + * @{ + */ + + +#define R0 0 /*!< general purpose register 0 */ +#define R1 1 /*!< general purpose register 1 */ +#define R2 2 /*!< general purpose register 2 */ +#define R3 3 /*!< general purpose register 3 */ +/**@}*/ + +/** @defgroup ulp_opcodes ULP coprocessor opcodes, sub opcodes, and various modifiers/flags + * + * These definitions are not intended to be used directly. + * They are used in definitions of instructions later on. + * + * @{ + */ + +#define OPCODE_WR_REG 1 /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define OPCODE_RD_REG 2 /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_I2C 3 /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */ + +#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ + +#define OPCODE_DELAY 4 /*!< Instruction: delay (nop) for a given number of cycles */ + +#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */ + +#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */ +#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */ + +#define OPCODE_ALU 7 /*!< Arithmetic instructions */ +#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */ +#define SUB_OPCODE_ALU_IMM 1 /*!< Arithmetic instruction, one source value is an immediate */ +#define SUB_OPCODE_ALU_CNT 2 /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/ +#define ALU_SEL_ADD 0 /*!< Addition */ +#define ALU_SEL_SUB 1 /*!< Subtraction */ +#define ALU_SEL_AND 2 /*!< Logical AND */ +#define ALU_SEL_OR 3 /*!< Logical OR */ +#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */ +#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */ +#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */ + +#define OPCODE_BRANCH 8 /*!< Branch instructions */ +#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */ +#define BX_JUMP_TYPE_DIRECT 0 /*!< Unconditional jump */ +#define BX_JUMP_TYPE_ZERO 1 /*!< Branch if last ALU result is zero */ +#define BX_JUMP_TYPE_OVF 2 /*!< Branch if last ALU operation caused and overflow */ +#define SUB_OPCODE_B 1 /*!< Branch to a relative offset */ +#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */ +#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */ + +#define OPCODE_END 9 /*!< Stop executing the program */ +#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */ +#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */ + +#define OPCODE_TSENS 10 /*!< Instruction: temperature sensor measurement (not implemented yet) */ + +#define OPCODE_HALT 11 /*!< Halt the coprocessor */ + +#define OPCODE_LD 13 /*!< Indirect load lower 16 bits from RTC memory */ + +#define OPCODE_MACRO 15 /*!< Not a real opcode. Used to identify labels and branches in the program */ +#define SUB_OPCODE_MACRO_LABEL 0 /*!< Label macro */ +#define SUB_OPCODE_MACRO_BRANCH 1 /*!< Branch macro */ +/**@}*/ + +/** + * @brief Instruction format structure + * + * All ULP instructions are 32 bit long. + * This union contains field layouts used by all of the supported instructions. + * This union also includes a special "macro" instruction layout. + * This is not a real instruction which can be executed by the CPU. It acts + * as a token which is removed from the program by the + * ulp_process_macros_and_load function. + * + * These structures are not intended to be used directly. + * Preprocessor definitions provided below fill the fields of these structure with + * the right arguments. + */ +union ulp_insn { + + struct { + uint32_t cycles : 16; /*!< Number of cycles to sleep */ + uint32_t unused : 12; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_DELAY) */ + } delay; /*!< Format of DELAY instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains data to store */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ST) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ST) */ + } st; /*!< Format of ST instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where the data should be loaded to */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 7; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_LD) */ + } ld; /*!< Format of LD instruction */ + + struct { + uint32_t unused : 28; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_HALT) */ + } halt; /*!< Format of HALT instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */ + uint32_t addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t reg : 1; /*!< Target PC in register (1) or immediate (0) */ + uint32_t type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } bx; /*!< Format of BRANCH instruction (absolute address) */ + + struct { + uint32_t imm : 16; /*!< Immediate value to compare against */ + uint32_t cmp : 1; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */ + uint32_t offset : 7; /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */ + uint32_t sign : 1; /*!< Sign of target PC offset: 0: positive, 1: negative */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_B) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } b; /*!< Format of BRANCH instruction (relative address) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t treg : 2; /*!< Register with operand B */ + uint32_t unused : 15; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t imm : 16; /*!< Immediate value of operand B */ + uint32_t unused : 1; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_imm; /*!< Format of ALU instruction (one source is an immediate) */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t data : 8; /*!< 8 bits of data to write */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } wr_reg; /*!< Format of WR_REG instruction */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } rd_reg; /*!< Format of RD_REG instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store ADC result */ + uint32_t mux : 4; /*!< Select SARADC pad (mux + 1) */ + uint32_t sar_sel : 1; /*!< Select SARADC0 (0) or SARADC1 (1) */ + uint32_t unused1 : 1; /*!< Unused */ + uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_ADC) */ + } adc; /*!< Format of ADC instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store temperature measurement result */ + uint32_t wait_delay: 14; /*!< Cycles to wait after measurement is done */ + uint32_t reserved: 12; /*!< Reserved, set to 0 */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_TSENS) */ + } tsens; /*!< Format of TSENS instruction */ + + struct { + uint32_t i2c_addr : 8; /*!< I2C slave address */ + uint32_t data : 8; /*!< Data to read or write */ + uint32_t low_bits : 3; /*!< TBD */ + uint32_t high_bits : 3; /*!< TBD */ + uint32_t i2c_sel : 4; /*!< TBD, select reg_i2c_slave_address[7:0] */ + uint32_t unused : 1; /*!< Unused */ + uint32_t rw : 1; /*!< Write (1) or read (0) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_I2C) */ + } i2c; /*!< Format of I2C instruction */ + + struct { + uint32_t wakeup : 1; /*!< Set to 1 to wake up chip */ + uint32_t unused : 24; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } end; /*!< Format of END instruction with wakeup */ + + struct { + uint32_t cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */ + uint32_t unused : 21; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } sleep; /*!< Format of END instruction with sleep */ + + struct { + uint32_t label : 16; /*!< Label number */ + uint32_t unused : 8; /*!< Unused */ + uint32_t sub_opcode : 4; /*!< SUB_OPCODE_MACRO_LABEL or SUB_OPCODE_MACRO_BRANCH */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_MACRO) */ + } macro; /*!< Format of tokens used by LABEL and BRANCH macros */ + +}; + +typedef union ulp_insn ulp_insn_t; + +_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes"); + +/** + * Delay (nop) for a given number of cycles + */ +#define I_DELAY(cycles_) { .delay = {\ + .cycles = cycles_, \ + .unused = 0, \ + .opcode = OPCODE_DELAY } } + +/** + * Halt the coprocessor. + * + * This instruction halts the coprocessor, but keeps ULP timer active. + * As such, ULP program will be restarted again by timer. + * To stop the program and prevent the timer from restarting the program, + * use I_END(0) instruction. + */ +#define I_HALT() { .halt = {\ + .unused = 0, \ + .opcode = OPCODE_HALT } } + +/** + * Map SoC peripheral register to periph_sel field of RD_REG and WR_REG + * instructions. + * + * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. + * @return periph_sel value for the peripheral to which this register belongs. + */ +static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) +{ + uint32_t ret = 3; + if (reg < DR_REG_RTCCNTL_BASE) { + assert(0 && "invalid register base"); + } else if (reg < DR_REG_RTCIO_BASE) { + ret = RD_REG_PERIPH_RTC_CNTL; + } else if (reg < DR_REG_SENS_BASE) { + ret = RD_REG_PERIPH_RTC_IO; + } else if (reg < DR_REG_RTC_I2C_BASE) { + ret = RD_REG_PERIPH_SENS; + } else if (reg < DR_REG_IO_MUX_BASE) { + ret = RD_REG_PERIPH_RTC_I2C; + } else { + assert(0 && "invalid register base"); + } + return ret; +} + +/** + * Write literal value to a peripheral register + * + * reg[high_bit : low_bit] = val + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .data = val, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_WR_REG } } + +/** + * Read from peripheral register into R0 + * + * R0 = reg[high_bit : low_bit] + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .unused = 0, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_RD_REG } } + +/** + * Set or clear a bit in the peripheral register. + * + * Sets bit (1 << shift) of register reg to value val. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) + +/** + * Wake the SoC from deep sleep. + * + * This instruction initiates wake up from deep sleep. + * Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup + * triggered by the ULP before going into deep sleep. + * Note that ULP program will still keep running until the I_HALT + * instruction, and it will still be restarted by timer at regular + * intervals, even when the SoC is woken up. + * + * To stop the ULP program, use I_HALT instruction. + * + * To disable the timer which start ULP program, use I_END() + * instruction. I_END instruction clears the + * RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG + * register, which controls the ULP timer. + */ +#define I_WAKE() { .end = { \ + .wakeup = 1, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_END, \ + .opcode = OPCODE_END } } + +/** + * Stop ULP program timer. + * + * This is a convenience macro which disables the ULP program timer. + * Once this instruction is used, ULP program will not be restarted + * anymore until ulp_run function is called. + * + * ULP program will continue running after this instruction. To stop + * the currently running program, use I_HALT(). + */ +#define I_END() \ + I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0) +/** + * Select the time interval used to run ULP program. + * + * This instructions selects which of the SENS_SLEEP_CYCLES_Sx + * registers' value is used by the ULP program timer. + * When the ULP program stops at I_HALT instruction, ULP program + * timer start counting. When the counter reaches the value of + * the selected SENS_SLEEP_CYCLES_Sx register, ULP program + * start running again from the start address (passed to the ulp_run + * function). + * There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5. + * + * By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP + * program timer. + */ +#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \ + .cycle_sel = timer_idx, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_SLEEP, \ + .opcode = OPCODE_END } } + +/** + * Perform temperature sensor measurement and store it into reg_dest. + * + * Delay can be set between 1 and ((1 << 14) - 1). Higher values give + * higher measurement resolution. + */ +#define I_TSENS(reg_dest, delay) { .tsens = { \ + .dreg = reg_dest, \ + .wait_delay = delay, \ + .reserved = 0, \ + .opcode = OPCODE_TSENS } } + +/** + * Perform ADC measurement and store result in reg_dest. + * + * adc_idx selects ADC (0 or 1). + * pad_idx selects ADC pad (0 - 7). + */ +#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ + .dreg = reg_dest, \ + .mux = pad_idx + 1, \ + .sar_sel = adc_idx, \ + .unused1 = 0, \ + .cycles = 0, \ + .unused2 = 0, \ + .opcode = OPCODE_ADC } } + +/** + * Store value from register reg_val into RTC memory. + * + * The value is written to an offset calculated by adding value of + * reg_addr register and offset_ field (this offset is expressed in 32-bit words). + * 32 bits written to RTC memory are built as follows: + * - bits [31:21] hold the PC of current instruction, expressed in 32-bit words + * - bits [20:16] = 5'b1 + * - bits [15:0] are assigned the contents of reg_val + * + * RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] } + */ +#define I_ST(reg_val, reg_addr, offset_) { .st = { \ + .dreg = reg_val, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .sub_opcode = SUB_OPCODE_ST, \ + .opcode = OPCODE_ST } } + + +/** + * Load value from RTC memory into reg_dest register. + * + * Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and + * value of offset_. + */ +#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ + .dreg = reg_dest, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .opcode = OPCODE_LD } } + + +/** + * Branch relative if R0 less than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BL(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_L, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch relative if R0 greater or equal than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BGE(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_GE, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXZR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXZI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, address in register + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXFR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, immediate address + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXFI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + + +/** + * Addition: dest = src1 + src2 + */ +#define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Subtraction: dest = src1 - src2 + */ +#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND: dest = src1 & src2 + */ +#define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR: dest = src1 | src2 + */ +#define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Copy: dest = src + */ +#define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = 0, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left: dest = src << shift + */ +#define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right: dest = src >> shift + */ +#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Add register and an immediate value: dest = src1 + imm + */ +#define I_ADDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Subtract register and an immediate value: dest = src - imm + */ +#define I_SUBI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND register and an immediate value: dest = src & imm + */ +#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR register and an immediate value: dest = src | imm + */ +#define I_ORI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Copy an immediate value into register: dest = imm + */ +#define I_MOVI(reg_dest, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = 0, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left register value by an immediate: dest = src << imm + */ +#define I_LSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right register value by an immediate: dest = val >> imm + */ +#define I_RSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Define a label with number label_num. + * + * This is a macro which doesn't generate a real instruction. + * The token generated by this macro is removed by ulp_process_macros_and_load + * function. Label defined using this macro can be used in branch macros defined + * below. + */ +#define M_LABEL(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_LABEL, \ + .opcode = OPCODE_MACRO } } + +/** + * Token macro used by M_B and M_BX macros. Not to be used directly. + */ +#define M_BRANCH(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_BRANCH, \ + .opcode = OPCODE_MACRO } } + +/** + * Macro: branch to label label_num if R0 is less than immediate value. + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BL(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BL(0, imm_value) + +/** + * Macro: branch to label label_num if R0 is greater or equal than immediate value + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BGE(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BGE(0, imm_value) + +/** + * Macro: unconditional branch to label + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BX(label_num) \ + M_BRANCH(label_num), \ + I_BXI(0) + +/** + * Macro: branch to label if ALU result is zero + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXZ(label_num) \ + M_BRANCH(label_num), \ + I_BXZI(0) + +/** + * Macro: branch to label if ALU overflow + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXF(label_num) \ + M_BRANCH(label_num), \ + I_BXFI(0) + + + +#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/xtensa/include/esp_attr.h b/tools/sdk/esp32/include/xtensa/include/esp_attr.h index 2b59f16e..27db5cbf 100644 --- a/tools/sdk/esp32/include/xtensa/include/esp_attr.h +++ b/tools/sdk/esp32/include/xtensa/include/esp_attr.h @@ -14,6 +14,7 @@ #ifndef __ESP_ATTR_H__ #define __ESP_ATTR_H__ +#include #include "sdkconfig.h" #define ROMFN_ATTR diff --git a/tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_api.h b/tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_api.h new file mode 100644 index 00000000..7f263b83 --- /dev/null +++ b/tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_api.h @@ -0,0 +1,181 @@ +/******************************************************************************* +Copyright (c) 2006-2015 Cadence Design Systems Inc. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +******************************************************************************/ + +/****************************************************************************** + Xtensa-specific API for RTOS ports. +******************************************************************************/ + +#ifndef __XTENSA_API_H__ +#define __XTENSA_API_H__ + +#include +#include +#include "xtensa_context.h" + + +/* Typedef for C-callable interrupt handler function */ +typedef void (*xt_handler)(void *); + +/* Typedef for C-callable exception handler function */ +typedef void (*xt_exc_handler)(XtExcFrame *); + + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified exception. The handler + will be installed on the core that calls this function. + + n - Exception number (type) + f - Handler function address, NULL to uninstall handler. + + The handler will be passed a pointer to the exception frame, which is created + on the stack of the thread that caused the exception. + + If the handler returns, the thread context will be restored and the faulting + instruction will be retried. Any values in the exception frame that are + modified by the handler will be restored as part of the context. For details + of the exception frame structure see xtensa_context.h. +------------------------------------------------------------------------------- +*/ +extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f); + + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified interrupt. The handler + will be installed on the core that calls this function. + + n - Interrupt number. + f - Handler function address, NULL to uninstall handler. + arg - Argument to be passed to handler. +------------------------------------------------------------------------------- +*/ +extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg); + + +/* +------------------------------------------------------------------------------- + Call this function to enable the specified interrupts on the core that runs + this code. + + mask - Bit mask of interrupts to be enabled. +------------------------------------------------------------------------------- +*/ +extern void xt_ints_on(unsigned int mask); + + +/* +------------------------------------------------------------------------------- + Call this function to disable the specified interrupts on the core that runs + this code. + + mask - Bit mask of interrupts to be disabled. +------------------------------------------------------------------------------- +*/ +extern void xt_ints_off(unsigned int mask); + + +/* +------------------------------------------------------------------------------- + Call this function to set the specified (s/w) interrupt. +------------------------------------------------------------------------------- +*/ +static inline void xt_set_intset(unsigned int arg) +{ + xthal_set_intset(arg); +} + + +/* +------------------------------------------------------------------------------- + Call this function to clear the specified (s/w or edge-triggered) + interrupt. +------------------------------------------------------------------------------- +*/ +static inline void xt_set_intclear(unsigned int arg) +{ + xthal_set_intclear(arg); +} + +/* +------------------------------------------------------------------------------- + Call this function to get handler's argument for the specified interrupt. + + n - Interrupt number. +------------------------------------------------------------------------------- +*/ +extern void * xt_get_interrupt_handler_arg(int n); + +/* +------------------------------------------------------------------------------- + Call this function to check if the specified interrupt is free to use. + + intr - Interrupt number. + cpu - cpu number. +------------------------------------------------------------------------------- +*/ +bool xt_int_has_handler(int intr, int cpu); + +/* +------------------------------------------------------------------------------- + Call this function to disable non iram located interrupts. + + newmask - mask containing the interrupts to disable. +------------------------------------------------------------------------------- +*/ +static inline uint32_t xt_int_disable_mask(uint32_t newmask) +{ + uint32_t oldint; + asm volatile ( + "movi %0,0\n" + "xsr %0,INTENABLE\n" //disable all ints first + "rsync\n" + "and a3,%0,%1\n" //mask ints that need disabling + "wsr a3,INTENABLE\n" //write back + "rsync\n" + :"=&r"(oldint):"r"(newmask):"a3"); + + return oldint; +} + +/* +------------------------------------------------------------------------------- + Call this function to enable non iram located interrupts. + + newmask - mask containing the interrupts to enable. +------------------------------------------------------------------------------- +*/ +static inline void xt_int_enable_mask(uint32_t newmask) +{ + asm volatile ( + "movi a3,0\n" + "xsr a3,INTENABLE\n" + "rsync\n" + "or a3,a3,%0\n" + "wsr a3,INTENABLE\n" + "rsync\n" + ::"r"(newmask):"a3"); +} + +#endif /* __XTENSA_API_H__ */ + diff --git a/tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_context.h b/tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_context.h new file mode 100644 index 00000000..120676da --- /dev/null +++ b/tools/sdk/esp32/include/xtensa/include/xtensa/xtensa_context.h @@ -0,0 +1,387 @@ +/******************************************************************************* +Copyright (c) 2006-2015 Cadence Design Systems Inc. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + + XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES + +This header contains definitions and macros for use primarily by Xtensa +RTOS assembly coded source files. It includes and uses the Xtensa hardware +abstraction layer (HAL) to deal with config specifics. It may also be +included in C source files. + +!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !! + +NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. + +*******************************************************************************/ + +#ifndef XTENSA_CONTEXT_H +#define XTENSA_CONTEXT_H + +#ifdef __ASSEMBLER__ +#include +#endif + +#include +#include +#include +#include + + +/* Align a value up to nearest n-byte boundary, where n is a power of 2. */ +#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) + + +/* +------------------------------------------------------------------------------- + Macros that help define structures for both C and assembler. +------------------------------------------------------------------------------- +*/ + +#ifdef STRUCT_BEGIN +#undef STRUCT_BEGIN +#undef STRUCT_FIELD +#undef STRUCT_AFIELD +#undef STRUCT_END +#endif + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size +#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) +#define STRUCT_END(sname) sname##Size:; .popsection + +#else + +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,asname,name) ctype name; +#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; +#define STRUCT_END(sname) } sname; + +#endif //_ASMLANGUAGE || __ASSEMBLER__ + + +/* +------------------------------------------------------------------------------- + INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT + + A stack frame of this structure is allocated for any interrupt or exception. + It goes on the current stack. If the RTOS has a system stack for handling + interrupts, every thread stack must allow space for just one interrupt stack + frame, then nested interrupt stack frames go on the system stack. + + The frame includes basic registers (explicit) and "extra" registers introduced + by user TIE or the use of the MAC16 option in the user's Xtensa config. + The frame size is minimized by omitting regs not applicable to user's config. + + For Windowed ABI, this stack frame includes the interruptee's base save area, + another base save area to manage gcc nested functions, and a little temporary + space to help manage the spilling of the register windows. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ +STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ +STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ +STRUCT_FIELD (long, 4, XT_STK_A0, a0) +STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ +STRUCT_FIELD (long, 4, XT_STK_A2, a2) +STRUCT_FIELD (long, 4, XT_STK_A3, a3) +STRUCT_FIELD (long, 4, XT_STK_A4, a4) +STRUCT_FIELD (long, 4, XT_STK_A5, a5) +STRUCT_FIELD (long, 4, XT_STK_A6, a6) +STRUCT_FIELD (long, 4, XT_STK_A7, a7) +STRUCT_FIELD (long, 4, XT_STK_A8, a8) +STRUCT_FIELD (long, 4, XT_STK_A9, a9) +STRUCT_FIELD (long, 4, XT_STK_A10, a10) +STRUCT_FIELD (long, 4, XT_STK_A11, a11) +STRUCT_FIELD (long, 4, XT_STK_A12, a12) +STRUCT_FIELD (long, 4, XT_STK_A13, a13) +STRUCT_FIELD (long, 4, XT_STK_A14, a14) +STRUCT_FIELD (long, 4, XT_STK_A15, a15) +STRUCT_FIELD (long, 4, XT_STK_SAR, sar) +STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) +STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) +STRUCT_FIELD (long, 4, XT_STK_LEND, lend) +STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) +#endif +#ifndef __XTENSA_CALL0_ABI__ +/* Temporary space for saving stuff during window spill */ +STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) +STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) +STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) +#endif +#ifdef XT_USE_SWPRI +/* Storage for virtual priority mask */ +STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) +#endif +#ifdef XT_USE_OVLY +/* Storage for overlay state */ +STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) +#endif +STRUCT_END(XtExcFrame) + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define XT_STK_NEXT1 XtExcFrameSize +#else +#define XT_STK_NEXT1 sizeof(XtExcFrame) +#endif + +/* Allocate extra storage if needed */ +#if XCHAL_EXTRA_SA_SIZE != 0 + +#if XCHAL_EXTRA_SA_ALIGN <= 16 +#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) +#else +/* If need more alignment than stack, add space for dynamic alignment */ +#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) +#endif +#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) + +#else + +#define XT_STK_NEXT2 XT_STK_NEXT1 + +#endif + +/* +------------------------------------------------------------------------------- + This is the frame size. Add space for 4 registers (interruptee's base save + area) and some space for gcc nested functions if any. +------------------------------------------------------------------------------- +*/ +#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) + + +/* +------------------------------------------------------------------------------- + SOLICITED STACK FRAME FOR A THREAD + + A stack frame of this structure is allocated whenever a thread enters the + RTOS kernel intentionally (and synchronously) to submit to thread scheduling. + It goes on the current thread's stack. + + The solicited frame only includes registers that are required to be preserved + by the callee according to the compiler's ABI conventions, some space to save + the return address for returning to the caller, and the caller's PS register. + + For Windowed ABI, this stack frame includes the caller's base save area. + + Note on XT_SOL_EXIT field: + It is necessary to distinguish a solicited from an interrupt stack frame. + This field corresponds to XT_STK_EXIT in the interrupt stack frame and is + always at the same offset (0). It can be written with a code (usually 0) + to distinguish a solicted frame from an interrupt frame. An RTOS port may + opt to ignore this field if it has another way of distinguishing frames. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A13, a13) +STRUCT_FIELD (long, 4, XT_SOL_A14, a14) +STRUCT_FIELD (long, 4, XT_SOL_A15, a15) +#else +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A1, a1) +STRUCT_FIELD (long, 4, XT_SOL_A2, a2) +STRUCT_FIELD (long, 4, XT_SOL_A3, a3) +#endif +STRUCT_END(XtSolFrame) + +/* Size of solicited stack frame */ +#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) + + +/* +------------------------------------------------------------------------------- + CO-PROCESSOR STATE SAVE AREA FOR A THREAD + + The RTOS must provide an area per thread to save the state of co-processors + when that thread does not have control. Co-processors are context-switched + lazily (on demand) only when a new thread uses a co-processor instruction, + otherwise a thread retains ownership of the co-processor even when it loses + control of the processor. An Xtensa co-processor exception is triggered when + any co-processor instruction is executed by a thread that is not the owner, + and the context switch of that co-processor is then peformed by the handler. + Ownership represents which thread's state is currently in the co-processor. + + Co-processors may not be used by interrupt or exception handlers. If an + co-processor instruction is executed by an interrupt or exception handler, + the co-processor exception handler will trigger a kernel panic and freeze. + This restriction is introduced to reduce the overhead of saving and restoring + co-processor state (which can be quite large) and in particular remove that + overhead from interrupt handlers. + + The co-processor state save area may be in any convenient per-thread location + such as in the thread control block or above the thread stack area. It need + not be in the interrupt stack frame since interrupts don't use co-processors. + + Along with the save area for each co-processor, two bitmasks with flags per + co-processor (laid out as in the CPENABLE reg) help manage context-switching + co-processors as efficiently as possible: + + XT_CPENABLE + The contents of a non-running thread's CPENABLE register. + It represents the co-processors owned (and whose state is still needed) + by the thread. When a thread is preempted, its CPENABLE is saved here. + When a thread solicits a context-swtich, its CPENABLE is cleared - the + compiler has saved the (caller-saved) co-proc state if it needs to. + When a non-running thread loses ownership of a CP, its bit is cleared. + When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. + Avoids co-processor exceptions when no change of ownership is needed. + + XT_CPSTORED + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether the state of each co-processor is saved in the state + save area. When a thread enters the kernel, only the state of co-procs + still enabled in CPENABLE is saved. When the co-processor exception + handler assigns ownership of a co-processor to a thread, it restores + the saved state only if this bit is set, and clears this bit. + + XT_CP_CS_ST + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether callee-saved state is saved in the state save area. + Callee-saved state is saved by itself on a solicited context switch, + and restored when needed by the coprocessor exception handler. + Unsolicited switches will cause the entire coprocessor to be saved + when necessary. + + XT_CP_ASA + Pointer to the aligned save area. Allows it to be aligned more than + the overall save area (which might only be stack-aligned or TCB-aligned). + Especially relevant for Xtensa cores configured with a very large data + path that requires alignment greater than 16 bytes (ABI stack alignment). +------------------------------------------------------------------------------- +*/ + +#if XCHAL_CP_NUM > 0 + +/* Offsets of each coprocessor save area within the 'aligned save area': */ +#define XT_CP0_SA 0 +#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) +#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) + +/* Offsets within the overall save area: */ +#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ +#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ +#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ +#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ +/* Overall size allows for dynamic alignment: */ +#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) +#else +#define XT_CP_SIZE 0 +#endif + + +/* + Macro to get the current core ID. Only uses the reg given as an argument. + Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0) + and 0xABAB on the APP CPU (1). We can distinguish between the two by checking + bit 13: it's 1 on the APP and 0 on the PRO processor. +*/ +#ifdef __ASSEMBLER__ + .macro getcoreid reg + rsr.prid \reg + extui \reg,\reg,13,1 + .endm +#endif + +/* Note: These are different to xCoreID used in ESP-IDF FreeRTOS, most places use + 0 and 1 which are determined by checking bit 13 (see previous comment) +*/ +#define CORE_ID_REGVAL_PRO 0xCDCD +#define CORE_ID_REGVAL_APP 0xABAB + +/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */ +#define CORE_ID_PRO CORE_ID_REGVAL_PRO + +/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */ +#define CORE_ID_APP CORE_ID_REGVAL_APP + +/* +------------------------------------------------------------------------------- + MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN + + Convenient where the frame size requirements are the same for both ABIs. + ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + ENTRY0, RET0 are for frameless functions (no locals, no calls). + + where size = size of stack frame in bytes (must be >0 and aligned to 16). + For framed functions the frame is created and the return address saved at + base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + For frameless functions, there is no frame and return address remains in a0. + Note: Because CPP macros expand to a single line, macros requiring multi-line + expansions are implemented as assembler macros. +------------------------------------------------------------------------------- +*/ + +#ifdef __ASSEMBLER__ +#ifdef __XTENSA_CALL0_ABI__ + /* Call0 */ + #define ENTRY(sz) entry1 sz + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + #define ENTRY0 + #define RET(sz) ret1 sz + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + #define RET0 ret +#else + /* Windowed */ + #define ENTRY(sz) entry sp, sz + #define ENTRY0 entry sp, 0x10 + #define RET(sz) retw + #define RET0 retw +#endif +#endif + + + + + +#endif /* XTENSA_CONTEXT_H */ + diff --git a/tools/sdk/esp32/ld/esp32.project.ld b/tools/sdk/esp32/ld/esp32.project.ld index eba9a876..e36073de 100644 --- a/tools/sdk/esp32/ld/esp32.project.ld +++ b/tools/sdk/esp32/ld/esp32.project.ld @@ -14,9 +14,14 @@ SECTIONS { . = ALIGN(4); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.literal EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.text EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.text.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.literal EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.text EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.text.*) + *libfreertos.a:port.*( .rtc.text.*) *libfreertos.a:queue.*( .rtc.text.*) + *libfreertos.a:port.*(.rtc.text.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.text.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.text.main_task) *libfreertos.a:queue.*(.rtc.text.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.literal .rtc.text .rtc.text.*) *libhal.a:uart_hal_iram.*( .rtc.literal .rtc.text .rtc.text.*) *rtc_wake_stub*.*(.literal .text .literal.* .text.*) @@ -45,9 +50,14 @@ SECTIONS _rtc_force_fast_start = ABSOLUTE(.); _coredump_rtc_fast_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.fast.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.fast.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.fast.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .rtc.fast.coredump.*) + *libfreertos.a:port.*( .rtc.fast.coredump.*) *libfreertos.a:queue.*( .rtc.fast.coredump.*) + *libfreertos.a:port.*(.rtc.fast.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.fast.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.fast.coredump.main_task) *libfreertos.a:queue.*(.rtc.fast.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.fast.coredump .rtc.fast.coredump.*) *libhal.a:uart_hal_iram.*( .rtc.fast.coredump .rtc.fast.coredump.*) _coredump_rtc_fast_end = ABSOLUTE(.); @@ -70,16 +80,26 @@ SECTIONS /* coredump mapping */ _coredump_rtc_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.coredump.*) + *libfreertos.a:port.*( .rtc.coredump.*) *libfreertos.a:queue.*( .rtc.coredump.*) + *libfreertos.a:port.*(.rtc.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.coredump.main_task) *libfreertos.a:queue.*(.rtc.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.coredump .rtc.coredump.*) *libhal.a:uart_hal_iram.*( .rtc.coredump .rtc.coredump.*) _coredump_rtc_end = ABSOLUTE(.); /* should be placed after coredump mapping */ - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.rodata EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.rodata.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.rodata EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.rodata.*) + *libfreertos.a:port.*( .rtc.data.* .rtc.rodata.*) *libfreertos.a:queue.*( .rtc.data.* .rtc.rodata.*) + *libfreertos.a:port.*(.rtc.data.esp_startup_start_app .rtc.rodata.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.data.esp_startup_start_app_other_cores .rtc.rodata.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.data.main_task .rtc.rodata.main_task) *libfreertos.a:queue.*(.rtc.data.xQueueGenericCreateStatic .rtc.rodata.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.data .rtc.data.* .rtc.rodata .rtc.rodata.*) *libhal.a:uart_hal_iram.*( .rtc.data .rtc.data.* .rtc.rodata .rtc.rodata.*) *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*) @@ -94,7 +114,8 @@ SECTIONS *rtc_wake_stub*.*(.bss .bss.*) *rtc_wake_stub*.*(COMMON) - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.bss) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.bss) + *libhal.a:twai_hal_iram.*( .rtc.bss) *libhal.a:uart_hal_iram.*( .rtc.bss) _rtc_bss_end = ABSOLUTE(.); @@ -190,7 +211,7 @@ SECTIONS /* Code marked as runnning out of IRAM */ _iram_text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .iram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram1.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .iram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .iram1.*) *libapp_trace.a:SEGGER_RTT_esp32.*( .literal .literal.* .text .text.*) *libapp_trace.a:SEGGER_SYSVIEW.*( .literal .literal.* .text .text.*) *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.*( .literal .literal.* .text .text.*) @@ -330,8 +351,12 @@ SECTIONS *libesp_system.a:panic_handler.*( .literal .literal.* .text .text.*) *libesp_system.a:reset_reason.*( .literal .literal.* .text .text.*) *libesp_system.a:system_api.*(.literal.esp_system_abort .text.esp_system_abort) - *libfreertos.a:( .literal EXCLUDE_FILE(*libfreertos.a:queue.*) .literal.* .text EXCLUDE_FILE(*libfreertos.a:queue.*) .text.*) + *libfreertos.a:( .literal EXCLUDE_FILE(*libfreertos.a:port.* *libfreertos.a:queue.*) .literal.* .text EXCLUDE_FILE(*libfreertos.a:port.* *libfreertos.a:queue.*) .text.*) + *libfreertos.a:port.*(.iram1.27.literal .iram1.28.literal .iram1.27 .iram1.28 .literal.pxPortInitialiseStack .literal.xPortStartScheduler .literal.vPortYieldOtherCore .literal.vPortReleaseTaskMPUSettings .literal.xPortInIsrContext .literal.xPortSysTickHandler .literal.vPortAssertIfInISR .literal.vPortSetStackWatchpoint .literal.vPortEnterCritical .literal.vPortExitCritical .literal.vApplicationStackOverflowHook .text.pxPortInitialiseStack .text.vPortEndScheduler .text.xPortStartScheduler .text.vPortYieldOtherCore .text.vPortStoreTaskMPUSettings .text.vPortReleaseTaskMPUSettings .text.xPortInIsrContext .text.xPortSysTickHandler .text.vPortAssertIfInISR .text.vPortSetStackWatchpoint .text.xPortGetTickRateHz .text.vPortEnterCritical .text.vPortExitCritical .text.vApplicationStackOverflowHook) *libfreertos.a:queue.*( .iram1.* .literal.prvCopyDataToQueue .literal.prvCopyDataFromQueue .literal.prvNotifyQueueSetContainer .literal.xQueueGenericReset .literal.xQueueGenericCreate .literal.xQueueGetMutexHolder .literal.xQueueCreateCountingSemaphoreStatic .literal.xQueueCreateCountingSemaphore .literal.xQueueGenericSend .literal.xQueueCreateMutexStatic .literal.xQueueGiveMutexRecursive .literal.xQueueCreateMutex .literal.xQueueGenericSendFromISR .literal.xQueueGiveFromISR .literal.xQueueGenericReceive .literal.xQueueTakeMutexRecursive .literal.xQueueReceiveFromISR .literal.xQueuePeekFromISR .literal.uxQueueMessagesWaiting .literal.uxQueueSpacesAvailable .literal.uxQueueMessagesWaitingFromISR .literal.vQueueDelete .literal.xQueueIsQueueEmptyFromISR .literal.xQueueIsQueueFullFromISR .literal.vQueueWaitForMessageRestricted .literal.xQueueCreateSet .literal.xQueueAddToSet .literal.xQueueRemoveFromSet .literal.xQueueSelectFromSet .literal.xQueueSelectFromSetFromISR .text.prvCopyDataToQueue .text.prvCopyDataFromQueue .text.prvNotifyQueueSetContainer .text.xQueueGenericReset .text.xQueueGenericCreate .text.xQueueGetMutexHolder .text.xQueueCreateCountingSemaphoreStatic .text.xQueueCreateCountingSemaphore .text.xQueueGenericSend .text.xQueueCreateMutexStatic .text.xQueueGiveMutexRecursive .text.xQueueCreateMutex .text.xQueueGenericSendFromISR .text.xQueueGiveFromISR .text.xQueueGenericReceive .text.xQueueTakeMutexRecursive .text.xQueueReceiveFromISR .text.xQueuePeekFromISR .text.uxQueueMessagesWaiting .text.uxQueueSpacesAvailable .text.uxQueueMessagesWaitingFromISR .text.vQueueDelete .text.xQueueIsQueueEmptyFromISR .text.xQueueIsQueueFullFromISR .text.vQueueWaitForMessageRestricted .text.xQueueCreateSet .text.xQueueAddToSet .text.xQueueRemoveFromSet .text.xQueueSelectFromSet .text.xQueueSelectFromSetFromISR) + *libfreertos.a:port.*(.iram1.esp_startup_start_app) + *libfreertos.a:port.*(.iram1.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.iram1.main_task) *libfreertos.a:queue.*(.iram1.xQueueGenericCreateStatic) *libgcc.a:_divsf3.*( .literal .literal.* .text .text.*) *libgcc.a:lib2funcs.*( .literal .literal.* .text .text.*) @@ -345,6 +370,7 @@ SECTIONS *libhal.a:spi_hal_iram.*( .literal .literal.* .text .text.*) *libhal.a:spi_slave_hal_iram.*( .literal .literal.* .text .text.*) *libhal.a:systimer_hal.*( .literal .literal.* .text .text.*) + *libhal.a:twai_hal_iram.*( .iram1 .iram1.*) *libhal.a:uart_hal_iram.*( .iram1 .iram1.*) *libhal.a:wdt_hal_iram.*( .literal .literal.* .text .text.*) *libheap.a:multi_heap.*( .literal .literal.* .text .text.*) @@ -408,9 +434,14 @@ SECTIONS /* coredump mapping */ _coredump_dram_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .dram1.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .dram1.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .dram1.coredump.*) + *libfreertos.a:port.*( .dram1.coredump.*) *libfreertos.a:queue.*( .dram1.coredump.*) + *libfreertos.a:port.*(.dram1.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.dram1.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.dram1.coredump.main_task) *libfreertos.a:queue.*(.dram1.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .dram1.coredump .dram1.coredump.*) *libhal.a:uart_hal_iram.*( .dram1.coredump .dram1.coredump.*) _coredump_dram_end = ABSOLUTE(.); @@ -419,7 +450,7 @@ SECTIONS KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*))) _esp_system_init_fn_array_end = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .dram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .dram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .dram1.*) *libapp_trace.a:SEGGER_RTT_esp32.*( .rodata .rodata.*) *libapp_trace.a:SEGGER_SYSVIEW.*( .rodata .rodata.*) *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.*( .rodata .rodata.*) @@ -558,7 +589,11 @@ SECTIONS *libesp_system.a:panic_handler.*( .rodata .rodata.*) *libesp_system.a:reset_reason.*( .rodata .rodata.*) *libesp_system.a:system_api.*(.rodata.esp_system_abort) + *libfreertos.a:port.*( .data.* .dram1.*) *libfreertos.a:queue.*( .data.* .dram1.*) + *libfreertos.a:port.*(.data.esp_startup_start_app .dram1.esp_startup_start_app) + *libfreertos.a:port.*(.data.esp_startup_start_app_other_cores .dram1.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.data.main_task .dram1.main_task) *libfreertos.a:queue.*(.data.xQueueGenericCreateStatic .dram1.xQueueGenericCreateStatic) *libgcc.a:_divsf3.*( .rodata .rodata.*) *libgcov.a:( .rodata .rodata.*) @@ -571,6 +606,7 @@ SECTIONS *libhal.a:spi_hal_iram.*( .rodata .rodata.*) *libhal.a:spi_slave_hal_iram.*( .rodata .rodata.*) *libhal.a:systimer_hal.*( .rodata .rodata.*) + *libhal.a:twai_hal_iram.*( .data .data.* .dram1 .dram1.*) *libhal.a:uart_hal_iram.*( .data .data.* .dram1 .dram1.*) *libhal.a:wdt_hal_iram.*( .rodata .rodata.*) *libheap.a:multi_heap.*( .rodata .rodata.*) @@ -632,9 +668,14 @@ SECTIONS . = ALIGN (4); _nimble_bss_end = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .bss EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .bss.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) COMMON) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .bss EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .bss.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) COMMON) + *libfreertos.a:port.*(.bss.port_uxOldInterruptState .bss.port_uxCriticalNesting .bss.port_interruptNesting .bss.port_xSchedulerRunning) *libfreertos.a:queue.*( .bss.*) + *libfreertos.a:port.*(.bss.esp_startup_start_app) + *libfreertos.a:port.*(.bss.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.bss.main_task) *libfreertos.a:queue.*(.bss.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .bss .bss.* COMMON) *libhal.a:uart_hal_iram.*( .bss .bss.* COMMON) *(.dynsbss) @@ -664,12 +705,17 @@ SECTIONS *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log_freertos.* *liblog.a:log.* *libgcc.a:_divsf3.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a:queue.* *libphy.a) .rodata.*) + *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log_freertos.* *liblog.a:log.* *libgcc.a:_divsf3.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.* *libphy.a) .rodata.*) *libesp_event.a:default_event_loop.*(.rodata.esp_event_loop_create_default.str1.4 .rodata.esp_event_send_to_default_loop) - *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$9003 .rodata.__func__$8990 .rodata.__func__$8957 .rodata.__func__$8925 .rodata.__func__$8900 .rodata.__func__$8859 .rodata.__func__$8850) + *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$9037 .rodata.__func__$9024 .rodata.__func__$8991 .rodata.__func__$8959 .rodata.__func__$8934 .rodata.__func__$8893 .rodata.__func__$8884) *libesp_system.a:system_api.*(.rodata.esp_get_idf_version.str1.4) - *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.__FUNCTION__$5329 .rodata.__FUNCTION__$5319 .rodata.__FUNCTION__$5299 .rodata.__FUNCTION__$5294 .rodata.__FUNCTION__$5288 .rodata.__FUNCTION__$5282 .rodata.__FUNCTION__$5276 .rodata.__FUNCTION__$5267 .rodata.__FUNCTION__$5257 .rodata.__FUNCTION__$5246 .rodata.__FUNCTION__$5238 .rodata.__FUNCTION__$5365 .rodata.__FUNCTION__$5227 .rodata.__FUNCTION__$5216 .rodata.__FUNCTION__$5210 .rodata.__FUNCTION__$5203 .rodata.__FUNCTION__$5196 .rodata.__FUNCTION__$5162 .rodata.__FUNCTION__$5152 .rodata.__FUNCTION__$5143) + *libfreertos.a:port.*(.rodata.main_task.str1.4 .rodata.vPortAssertIfInISR.str1.4 .rodata.vPortEnterCritical.str1.4 .rodata.vPortExitCritical.str1.4 .rodata.vApplicationStackOverflowHook.str1.4 .rodata.esp_startup_start_app.str1.4 .rodata.__func__$5469 .rodata.__func__$5482 .rodata.__func__$4347 .rodata.__func__$4334 .rodata.__FUNCTION__$5431) + *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.__FUNCTION__$5362 .rodata.__FUNCTION__$5352 .rodata.__FUNCTION__$5332 .rodata.__FUNCTION__$5327 .rodata.__FUNCTION__$5321 .rodata.__FUNCTION__$5315 .rodata.__FUNCTION__$5309 .rodata.__FUNCTION__$5300 .rodata.__FUNCTION__$5290 .rodata.__FUNCTION__$5279 .rodata.__FUNCTION__$5271 .rodata.__FUNCTION__$5398 .rodata.__FUNCTION__$5260 .rodata.__FUNCTION__$5249 .rodata.__FUNCTION__$5243 .rodata.__FUNCTION__$5236 .rodata.__FUNCTION__$5229 .rodata.__FUNCTION__$5195 .rodata.__FUNCTION__$5185 .rodata.__FUNCTION__$5176) + *libfreertos.a:port.*(.rodata.esp_startup_start_app) + *libfreertos.a:port.*(.rodata.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rodata.main_task) *libfreertos.a:queue.*(.rodata.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rodata .rodata.*) *libhal.a:uart_hal_iram.*( .rodata .rodata.*) *liblog.a:log.*(.rodata.esp_log_level_set.str1.4 .rodata.__func__$3544 .rodata.__func__$3515) *liblog.a:log_freertos.*(.rodata.esp_log_system_timestamp.str1.4) @@ -735,12 +781,17 @@ SECTIONS _stext = .; _text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifirxiram.*) + *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .wifirxiram.*) *libesp_event.a:default_event_loop.*(.literal.esp_event_handler_register .literal.esp_event_handler_instance_register .literal.esp_event_handler_unregister .literal.esp_event_handler_instance_unregister .literal.esp_event_post .literal.esp_event_loop_create_default .literal.esp_event_loop_delete_default .literal.esp_event_send_to_default_loop .text.esp_event_handler_register .text.esp_event_handler_instance_register .text.esp_event_handler_unregister .text.esp_event_handler_instance_unregister .text.esp_event_post .text.esp_event_loop_create_default .text.esp_event_loop_delete_default .text.esp_event_send_to_default_loop) *libesp_event.a:esp_event.*(.literal.handler_instances_add .literal.base_node_add_handler .literal.loop_node_add_handler .literal.handler_instances_remove .literal.handler_instances_remove_all$isra$1 .literal.esp_event_loop_create .literal.esp_event_loop_run .literal.esp_event_loop_run_task .literal.esp_event_loop_delete .literal.esp_event_handler_register_with_internal .literal.esp_event_handler_register_with .literal.esp_event_handler_instance_register_with .literal.esp_event_handler_unregister_with_internal .literal.esp_event_handler_unregister_with .literal.esp_event_handler_instance_unregister_with .literal.esp_event_post_to .text.handler_instances_add .text.base_node_add_handler .text.loop_node_add_handler .text.handler_instances_remove .text.handler_instances_remove_all$isra$1 .text.esp_event_loop_create .text.esp_event_loop_run .text.esp_event_loop_run_task .text.esp_event_loop_delete .text.esp_event_handler_register_with_internal .text.esp_event_handler_register_with .text.esp_event_handler_instance_register_with .text.esp_event_handler_unregister_with_internal .text.esp_event_handler_unregister_with .text.esp_event_handler_instance_unregister_with .text.esp_event_post_to .text.esp_event_dump) *libesp_system.a:system_api.*(.literal.esp_register_shutdown_handler .literal.esp_unregister_shutdown_handler .literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_minimum_free_heap_size .literal.esp_get_idf_version .text.esp_register_shutdown_handler .text.esp_unregister_shutdown_handler .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_minimum_free_heap_size .text.esp_get_idf_version) + *libfreertos.a:port.*( .wifi0iram.* .wifirxiram.*) *libfreertos.a:queue.*( .wifi0iram.* .wifirxiram.*) + *libfreertos.a:port.*(.literal.esp_startup_start_app .text.esp_startup_start_app .wifi0iram.esp_startup_start_app .wifirxiram.esp_startup_start_app) + *libfreertos.a:port.*(.literal.esp_startup_start_app_other_cores .text.esp_startup_start_app_other_cores .wifi0iram.esp_startup_start_app_other_cores .wifirxiram.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.literal.main_task .text.main_task .wifi0iram.main_task .wifirxiram.main_task) *libfreertos.a:queue.*(.literal.xQueueGenericCreateStatic .text.xQueueGenericCreateStatic .wifi0iram.xQueueGenericCreateStatic .wifirxiram.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .literal .literal.* .text .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *libhal.a:uart_hal_iram.*( .literal .literal.* .text .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *liblog.a:log.*(.literal.heap_bubble_down .literal.esp_log_set_vprintf .literal.esp_log_level_set .literal.esp_log_writev .text.heap_bubble_down .text.esp_log_set_vprintf .text.esp_log_level_set .text.esp_log_writev) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text.esp_log_system_timestamp) @@ -775,16 +826,26 @@ SECTIONS /* coredump mapping */ _coredump_iram_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .iram.data.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram.data.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .iram.data.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .iram.data.coredump.*) + *libfreertos.a:port.*( .iram.data.coredump.*) *libfreertos.a:queue.*( .iram.data.coredump.*) + *libfreertos.a:port.*(.iram.data.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.iram.data.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.iram.data.coredump.main_task) *libfreertos.a:queue.*(.iram.data.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .iram.data.coredump .iram.data.coredump.*) *libhal.a:uart_hal_iram.*( .iram.data.coredump .iram.data.coredump.*) _coredump_iram_end = ABSOLUTE(.); /* should be placed after coredump mapping */ - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .iram.data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram.data.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .iram.data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .iram.data.*) + *libfreertos.a:port.*( .iram.data.*) *libfreertos.a:queue.*( .iram.data.*) + *libfreertos.a:port.*(.iram.data.esp_startup_start_app) + *libfreertos.a:port.*(.iram.data.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.iram.data.main_task) *libfreertos.a:queue.*(.iram.data.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .iram.data .iram.data.*) *libhal.a:uart_hal_iram.*( .iram.data .iram.data.*) _iram_data_end = ABSOLUTE(.); @@ -795,9 +856,14 @@ SECTIONS . = ALIGN(4); _iram_bss_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .iram.bss EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram.bss.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .iram.bss EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .iram.bss.*) + *libfreertos.a:port.*( .iram.bss.*) *libfreertos.a:queue.*( .iram.bss.*) + *libfreertos.a:port.*(.iram.bss.esp_startup_start_app) + *libfreertos.a:port.*(.iram.bss.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.iram.bss.main_task) *libfreertos.a:queue.*(.iram.bss.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .iram.bss .iram.bss.*) *libhal.a:uart_hal_iram.*( .iram.bss .iram.bss.*) _iram_bss_end = ABSOLUTE(.); diff --git a/tools/sdk/esp32/ld/esp32.rom.ld b/tools/sdk/esp32/ld/esp32.rom.ld index 79798402..4d4d20f8 100644 --- a/tools/sdk/esp32/ld/esp32.rom.ld +++ b/tools/sdk/esp32/ld/esp32.rom.ld @@ -111,6 +111,8 @@ PROVIDE ( hci_fc_env = 0x3ffb9340 ); PROVIDE ( jd_decomp = 0x400613e8 ); PROVIDE ( jd_prepare = 0x40060fa8 ); PROVIDE ( ke_env = 0x3ffb93cc ); +PROVIDE ( ke_handler_search = 0x4001a430 ); +PROVIDE ( ke_task_env = 0x3ffb81d4 ); PROVIDE ( lb_default_handler = 0x3ff982b8 ); PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); PROVIDE ( lb_env = 0x3ffb9424 ); @@ -663,6 +665,7 @@ PROVIDE ( ld_acl_sniff_frm_cbk = 0x4003482c ); PROVIDE ( ld_inq_end = 0x4003ab48 ); PROVIDE ( ld_inq_sched = 0x4003aba4 ); PROVIDE ( ld_inq_frm_cbk = 0x4003ae4c ); +PROVIDE ( ld_pscan_frm_cbk = 0x4003ebe4 ); PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 ); PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 ); PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 ); diff --git a/tools/sdk/esp32/ld/libbtdm_app.a b/tools/sdk/esp32/ld/libbtdm_app.a index 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b/tools/sdk/esp32/sdkconfig index b6ee91bd..8d644892 100644 --- a/tools/sdk/esp32/sdkconfig +++ b/tools/sdk/esp32/sdkconfig @@ -74,7 +74,7 @@ CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 # Serial flasher config # CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 -CONFIG_ESPTOOLPY_WITH_STUB=y +# CONFIG_ESPTOOLPY_NO_STUB is not set # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set CONFIG_ESPTOOLPY_FLASHMODE_DIO=y @@ -344,6 +344,12 @@ CONFIG_SPI_MASTER_ISR_IN_IRAM=y CONFIG_SPI_SLAVE_ISR_IN_IRAM=y # end of SPI configuration +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI configuration + # # UART configuration # @@ -489,12 +495,6 @@ CONFIG_ESP32_XTAL_FREQ=0 CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5 # end of ESP32-specific -# -# Power Management -# -# CONFIG_PM_ENABLE is not set -# end of Power Management - # # ADC-Calibration # @@ -605,6 +605,12 @@ CONFIG_ESP_NETIF_TCPIP_LWIP=y CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y # end of ESP NETIF Adapter +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# end of Power Management + # # ESP System Settings # @@ -618,6 +624,7 @@ CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y # High resolution timer (esp_timer) # # CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIMER_RTC_USE=y CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096 # CONFIG_ESP_TIMER_IMPL_FRC2 is not set CONFIG_ESP_TIMER_IMPL_TG0_LAC=y @@ -661,9 +668,9 @@ CONFIG_ESP32_PHY_MAX_TX_POWER=20 # # Core dump # -# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set -# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set -CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y # end of Core dump # @@ -1134,6 +1141,7 @@ CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 # CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set # # Auto-detect flash chips @@ -1277,8 +1285,9 @@ CONFIG_HP_NANO1=y # # Camera configuration # -CONFIG_OV2640_SUPPORT=y +CONFIG_OV7670_SUPPORT=y # CONFIG_OV7725_SUPPORT is not set +CONFIG_OV2640_SUPPORT=y CONFIG_OV3660_SUPPORT=y CONFIG_OV5640_SUPPORT=y # CONFIG_SCCB_HARDWARE_I2C_PORT0 is not set @@ -1440,6 +1449,9 @@ CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y # CONFIG_ESP32S2_PANIC_GDBSTUB is not set CONFIG_TIMER_TASK_STACK_SIZE=4096 CONFIG_SW_COEXIST_ENABLE=y +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 CONFIG_MB_QUEUE_LENGTH=20 diff --git a/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin b/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin index 0280b459..c298229a 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin and b/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin b/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin index 2cf297cc..96f7aeac 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin and b/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin b/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin index 0280b459..c298229a 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin and b/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dout_80m.bin b/tools/sdk/esp32s2/bin/bootloader_dout_80m.bin index 2cf297cc..96f7aeac 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dout_80m.bin and b/tools/sdk/esp32s2/bin/bootloader_dout_80m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qio_40m.bin b/tools/sdk/esp32s2/bin/bootloader_qio_40m.bin index 0280b459..c298229a 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_qio_40m.bin and b/tools/sdk/esp32s2/bin/bootloader_qio_40m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qio_80m.bin b/tools/sdk/esp32s2/bin/bootloader_qio_80m.bin index 2cf297cc..96f7aeac 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_qio_80m.bin and b/tools/sdk/esp32s2/bin/bootloader_qio_80m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qout_40m.bin b/tools/sdk/esp32s2/bin/bootloader_qout_40m.bin index 0280b459..c298229a 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_qout_40m.bin and b/tools/sdk/esp32s2/bin/bootloader_qout_40m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin b/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin index 2cf297cc..96f7aeac 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin and b/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin differ diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h index e444271e..baf36702 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_common.h @@ -21,6 +21,8 @@ #include "esp32/rom/rtc.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/rtc.h" #endif #ifdef __cplusplus @@ -167,6 +169,13 @@ esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t */ uint8_t bootloader_common_get_chip_revision(void); +/** + * @brief Get chip package + * + * @return Chip package number + */ +uint32_t bootloader_common_get_chip_ver_pkg(void); + /** * @brief Query reset reason * diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash.h b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash.h new file mode 100644 index 00000000..5b745965 --- /dev/null +++ b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash.h @@ -0,0 +1,30 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include /* including in bootloader for error values */ +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_CACHE_SUPPORT_WRAP +/** + * @brief Set the burst mode setting command for specified wrap mode. + * + * @param mode The specified warp mode. + * @return always ESP_OK + */ +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); +#endif + diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_encrypt.h b/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_encrypt.h index fc1b3729..ef3b8027 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_encrypt.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_encrypt.h @@ -49,7 +49,7 @@ typedef enum { */ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_enabled(void) { - uint32_t flash_crypt_cnt; + uint32_t flash_crypt_cnt = 0; #if CONFIG_IDF_TARGET_ESP32 flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_RD_FLASH_CRYPT_CNT); #elif CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32s2/include/config/sdkconfig.h b/tools/sdk/esp32s2/include/config/sdkconfig.h index 690879ca..7bc47974 100644 --- a/tools/sdk/esp32s2/include/config/sdkconfig.h +++ b/tools/sdk/esp32s2/include/config/sdkconfig.h @@ -25,7 +25,6 @@ #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 #define CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE 1 #define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 -#define CONFIG_ESPTOOLPY_WITH_STUB 1 #define CONFIG_ESPTOOLPY_FLASHMODE_QIO 1 #define CONFIG_ESPTOOLPY_FLASHMODE "dio" #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 @@ -81,6 +80,7 @@ #define CONFIG_ADC_DISABLE_DAC 1 #define CONFIG_EFUSE_MAX_BLK_LEN 256 #define CONFIG_ESP_TLS_USING_MBEDTLS 1 +#define CONFIG_ESP_TLS_USE_DS_PERIPHERAL 1 #define CONFIG_ESP_TLS_SERVER 1 #define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 1 #define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 240 @@ -113,6 +113,7 @@ #define CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC 1 #define CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES 576 #define CONFIG_ESP32S2_KEEP_USB_ALIVE 1 +#define CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP 1 #define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 #define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 #define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2048 @@ -130,6 +131,7 @@ #define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5 #define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1 #define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1 +#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT_OFFSET 1 #define CONFIG_ETH_ENABLED 1 #define CONFIG_ETH_USE_SPI_ETHERNET 1 #define CONFIG_ETH_SPI_ETHERNET_DM9051 1 @@ -147,6 +149,7 @@ #define CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER 1 #define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1 #define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1 +#define CONFIG_ESP_TIMER_RTC_USE 1 #define CONFIG_ESP_TIMER_TASK_STACK_SIZE 4096 #define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 #define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 16 @@ -165,7 +168,7 @@ #define CONFIG_ESP32_WIFI_IRAM_OPT 1 #define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20 #define CONFIG_ESP32_PHY_MAX_TX_POWER 20 -#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1 +#define CONFIG_ESP_COREDUMP_ENABLE_TO_NONE 1 #define CONFIG_FATFS_CODEPAGE_850 1 #define CONFIG_FATFS_CODEPAGE 850 #define CONFIG_FATFS_LFN_STACK 1 @@ -422,6 +425,7 @@ #define CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE #define CONFIG_ESP32S2_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT #define CONFIG_ESP32_APPTRACE_DEST_NONE CONFIG_APPTRACE_DEST_NONE +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE CONFIG_ESP_COREDUMP_ENABLE_TO_NONE #define CONFIG_ESP32_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT #define CONFIG_ESP32_PTHREAD_STACK_MIN CONFIG_PTHREAD_STACK_MIN #define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT CONFIG_PTHREAD_TASK_NAME_DEFAULT @@ -488,5 +492,5 @@ #define CONFIG_TOOLPREFIX CONFIG_SDK_TOOLPREFIX #define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS -#define CONFIG_ARDUINO_IDF_COMMIT "8bc19ba89" +#define CONFIG_ARDUINO_IDF_COMMIT "0b71a0a46" #define CONFIG_ARDUINO_IDF_BRANCH "master" diff --git a/tools/sdk/esp32s2/include/driver/include/driver/twai.h b/tools/sdk/esp32s2/include/driver/include/driver/twai.h index 383a9956..ef240a38 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/twai.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/twai.h @@ -40,10 +40,11 @@ extern "C" { * configured. The other members of the general configuration structure are * assigned default values. */ -#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ - .clkout_io = TWAI_IO_UNUSED, .bus_off_io = TWAI_IO_UNUSED, \ - .tx_queue_len = 5, .rx_queue_len = 5, \ - .alerts_enabled = TWAI_ALERT_NONE, .clkout_divider = 0, } +#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ + .clkout_io = TWAI_IO_UNUSED, .bus_off_io = TWAI_IO_UNUSED, \ + .tx_queue_len = 5, .rx_queue_len = 5, \ + .alerts_enabled = TWAI_ALERT_NONE, .clkout_divider = 0, \ + .intr_flags = ESP_INTR_FLAG_LEVEL1} /** * @brief Alert flags @@ -70,7 +71,7 @@ extern "C" { #define TWAI_ALERT_BUS_OFF 0x1000 /**< Alert(4096): Bus-off condition occurred. TWAI controller can no longer influence bus */ #define TWAI_ALERT_ALL 0x1FFF /**< Bit mask to enable all alerts during configuration */ #define TWAI_ALERT_NONE 0x0000 /**< Bit mask to disable all alerts during configuration */ -#define TWAI_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur */ +#define TWAI_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur. Note that logging from the ISR is disabled if CONFIG_TWAI_ISR_IN_IRAM is enabled (see docs). */ /** @endcond */ @@ -103,6 +104,7 @@ typedef struct { uint32_t rx_queue_len; /**< Number of messages RX queue can hold */ uint32_t alerts_enabled; /**< Bit field of alerts to enable (see documentation) */ uint32_t clkout_divider; /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */ + int intr_flags; /**< Interrupt flags to set the priority of the driver's ISR. Note that to use the ESP_INTR_FLAG_IRAM, the CONFIG_TWAI_ISR_IN_IRAM option should be enabled first. */ } twai_general_config_t; /** diff --git a/tools/sdk/esp32s2/include/efuse/include/esp32s3/esp_efuse.h b/tools/sdk/esp32s2/include/efuse/include/esp32s3/esp_efuse.h new file mode 100644 index 00000000..c33eca5b --- /dev/null +++ b/tools/sdk/esp32s2/include/efuse/include/esp32s3/esp_efuse.h @@ -0,0 +1,69 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32S3 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/efuse/include/esp_efuse.h b/tools/sdk/esp32s2/include/efuse/include/esp_efuse.h index ab792a49..84d03c5a 100644 --- a/tools/sdk/esp32s2/include/efuse/include/esp_efuse.h +++ b/tools/sdk/esp32s2/include/efuse/include/esp_efuse.h @@ -27,6 +27,8 @@ extern "C" { #include "esp32/esp_efuse.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/esp_efuse.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/esp_efuse.h" #endif #define ESP_ERR_EFUSE 0x1600 /*!< Base error code for efuse api. */ diff --git a/tools/sdk/esp32s2/include/esp-tls/esp_tls.h b/tools/sdk/esp32s2/include/esp-tls/esp_tls.h index 10941700..752c18e1 100644 --- a/tools/sdk/esp32s2/include/esp-tls/esp_tls.h +++ b/tools/sdk/esp32s2/include/esp-tls/esp_tls.h @@ -205,6 +205,7 @@ typedef struct esp_tls_cfg { /*!< Function pointer to esp_crt_bundle_attach. Enables the use of certification bundle for server verification, must be enabled in menuconfig */ + void *ds_data; /*!< Pointer for digital signature peripheral context */ } esp_tls_cfg_t; #ifdef CONFIG_ESP_TLS_SERVER diff --git a/tools/sdk/esp32s2/include/esp32s2/include/cp_dma.h b/tools/sdk/esp32s2/include/esp32s2/include/cp_dma.h deleted file mode 100644 index e95959ec..00000000 --- a/tools/sdk/esp32s2/include/esp32s2/include/cp_dma.h +++ /dev/null @@ -1,126 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "esp_err.h" - -/** - * @brief Handle of CP_DMA driver - * - */ -typedef struct cp_dma_driver_context_s *cp_dma_driver_t; - -/** - * @brief CP_DMA event ID - * - */ -typedef enum { - CP_DMA_EVENT_M2M_DONE, /*!< One or more memory copy transactions are done */ -} cp_dma_event_id_t; - -/** - * @brief Type defined for CP_DMA event object (including event ID, event data) - * - */ -typedef struct { - cp_dma_event_id_t id; /*!< Event ID */ - void *data; /*!< Event data */ -} cp_dma_event_t; - -/** - * @brief Type defined for cp_dma ISR callback function - * - * @param drv_hdl Handle of CP_DMA driver - * @param event Event object, which contains the event ID, event data, and so on - * @param cb_args User defined arguments for the callback function. It's passed in cp_dma_memcpy function - * @return Whether a high priority task is woken up by the callback function - * - */ -typedef bool (*cp_dma_isr_cb_t)(cp_dma_driver_t drv_hdl, cp_dma_event_t *event, void *cb_args); - -/** - * @brief Type defined for configuration of CP_DMA driver - * - */ -typedef struct { - uint32_t max_out_stream; /*!< maximum number of out link streams that can work simultaneously */ - uint32_t max_in_stream; /*!< maximum number of in link streams that can work simultaneously */ - uint32_t flags; /*!< Extra flags to control some special behaviour of CP_DMA, OR'ed of CP_DMA_FLAGS_xxx macros */ -} cp_dma_config_t; - -#define CP_DMA_FLAGS_WORK_WITH_CACHE_DISABLED (1 << 0) /*!< CP_DMA can work even when cache is diabled */ - -/** - * @brief Default configuration for CP_DMA driver - * - */ -#define CP_DMA_DEFAULT_CONFIG() \ - { \ - .max_out_stream = 8, \ - .max_in_stream = 8, \ - .flags = 0, \ - } - -/** - * @brief Install CP_DMA driver - * - * @param[in] config Configuration of CP_DMA driver - * @param[out] drv_hdl Returned handle of CP_DMA driver or NULL if driver installation failed - * @return - * - ESP_OK: Install CP_DMA driver successfully - * - ESP_ERR_INVALID_ARG: Install CP_DMA driver failed because of some invalid argument - * - ESP_ERR_NO_MEM: Install CP_DMA driver failed because there's no enough capable memory - * - ESP_FAIL: Install CP_DMA driver failed because of other error - */ -esp_err_t cp_dma_driver_install(const cp_dma_config_t *config, cp_dma_driver_t *drv_hdl); - -/** - * @brief Uninstall CP_DMA driver - * - * @param[in] drv_hdl Handle of CP_DMA driver that returned from cp_dma_driver_install - * @return - * - ESP_OK: Uninstall CP_DMA driver successfully - * - ESP_ERR_INVALID_ARG: Uninstall CP_DMA driver failed because of some invalid argument - * - ESP_FAIL: Uninstall CP_DMA driver failed because of other error - */ -esp_err_t cp_dma_driver_uninstall(cp_dma_driver_t drv_hdl); - -/** - * @brief Send an asynchronous memory copy request - * - * @param[in] drv_hdl Handle of CP_DMA driver that returned from cp_dma_driver_install - * @param[in] dst Destination address (copy to) - * @param[in] src Source address (copy from) - * @param[in] n Number of bytes to copy - * @param[in] cb_isr Callback function, which got invoked in ISR context. A NULL pointer here can bypass the callback. - * @param[in] cb_args User defined argument to be passed to the callback function - * @return - * - ESP_OK: Send memcopy request successfully - * - ESP_ERR_INVALID_ARG: Send memcopy request failed because of some invalid argument - * - ESP_FAIL: Send memcopy request failed because of other error - * - * @note The callback function is invoked in ISR context, please never handle heavy load in the callback. - * The default ISR handler is placed in IRAM, please place callback function in IRAM as well by applying IRAM_ATTR to it. - */ -esp_err_t cp_dma_memcpy(cp_dma_driver_t drv_hdl, void *dst, void *src, size_t n, cp_dma_isr_cb_t cb_isr, void *cb_args); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/memprot.h b/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/memprot.h index 72468265..e86ebbe3 100644 --- a/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/memprot.h +++ b/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/memprot.h @@ -18,15 +18,24 @@ */ #pragma once +#include +#include +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif typedef enum { - MEMPROT_IRAM0 = 0x00000000, - MEMPROT_DRAM0 = 0x00000001, - MEMPROT_UNKNOWN + MEMPROT_NONE = 0x00000000, + MEMPROT_IRAM0_SRAM = 0x00000001, //0x40020000-0x4006FFFF, RWX + MEMPROT_DRAM0_SRAM = 0x00000002, //0x3FFB0000-0x3FFFFFFF, RW + MEMPROT_IRAM0_RTCFAST = 0x00000004, //0x40070000-0x40071FFF, RWX + MEMPROT_DRAM0_RTCFAST = 0x00000008, //0x3FF9E000-0x3FF9FFFF, RW + MEMPROT_PERI1_RTCSLOW = 0x00000010, //0x3F421000-0x3F423000, RW + MEMPROT_PERI2_RTCSLOW_0 = 0x00000020, //0x50001000-0x50003000, RWX + MEMPROT_PERI2_RTCSLOW_1 = 0x00000040, //0x60002000-0x60004000, RWX + MEMPROT_ALL = 0xFFFFFFFF } mem_type_prot_t; @@ -60,22 +69,6 @@ void esp_memprot_intr_init(mem_type_prot_t mem_type); */ void esp_memprot_intr_ena(mem_type_prot_t mem_type, bool enable); -/** - * @brief Detects whether any of the memory protection interrupts is active - * - * @return true/false - */ -bool esp_memprot_is_assoc_intr_any(void); - -/** - * @brief Detects whether specific memory protection interrupt is active - * - * @param mem_type Memory protection area type (see mem_type_prot_t enum) - * - * @return true/false - */ -bool esp_memprot_is_assoc_intr(mem_type_prot_t mem_type); - /** * @brief Sets a request for clearing interrupt-on flag for specified memory region (register write) * @@ -87,11 +80,17 @@ bool esp_memprot_is_assoc_intr(mem_type_prot_t mem_type); void esp_memprot_clear_intr(mem_type_prot_t mem_type); /** - * @brief Detects which memory protection interrupt is active, check order: IRAM0, DRAM0 + * @brief Detects which memory protection interrupt is active + * + * @note Check order + * MEMPROT_IRAM0_SRAM + * MEMPROT_IRAM0_RTCFAST + * MEMPROT_DRAM0_SRAM + * MEMPROT_DRAM0_RTCFAST * * @return Memory protection area type (see mem_type_prot_t enum) */ -mem_type_prot_t IRAM_ATTR esp_memprot_get_intr_memtype(void); +mem_type_prot_t IRAM_ATTR esp_memprot_get_active_intr_memtype(void); /** * @brief Gets interrupt status register contents for specified memory region @@ -151,13 +150,13 @@ void esp_memprot_set_lock(mem_type_prot_t mem_type); bool esp_memprot_get_lock(mem_type_prot_t mem_type); /** - * @brief Gets interrupt permission control register contents for required memory region + * @brief Gets permission control configuration register contents for required memory region * * @param mem_type Memory protection area type (see mem_type_prot_t enum) * * @return Permission control register contents */ -uint32_t esp_memprot_get_ena_reg(mem_type_prot_t mem_type); +uint32_t esp_memprot_get_conf_reg(mem_type_prot_t mem_type); /** * @brief Gets interrupt permission settings for unified management block @@ -321,11 +320,12 @@ void esp_memprot_set_prot_iram(mem_type_prot_t mem_type, uint32_t *split_addr, b * * @param invoke_panic_handler map mem.prot interrupt to ETS_MEMACCESS_ERR_INUM and thus invokes panic handler when fired ('true' not suitable for testing) * @param lock_feature sets LOCK bit, see esp_memprot_set_lock() ('true' not suitable for testing) + * @param mem_type_mask holds a set of required memory protection types (bitmask built of mem_type_prot_t). NULL means default (MEMPROT_ALL in this version) */ -void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature); +void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uint32_t *mem_type_mask); /** - * @brief Get permission settings bits for IRAM split mgmt based on current split address + * @brief Get permission settings bits for IRAM0 split mgmt. Only IRAM0 memory types allowed * * @param mem_type Memory protection area type (see mem_type_prot_t enum) * @param lw Low segment Write permission flag @@ -338,7 +338,7 @@ void esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature); void esp_memprot_get_perm_split_bits_iram(mem_type_prot_t mem_type, bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx); /** - * @brief Get permission settings bits for DRAM split mgmt based on current split address + * @brief Get permission settings bits for DRAM0 split mgmt. Only DRAM0 memory types allowed * * @param mem_type Memory protection area type (see mem_type_prot_t enum) * @param lw Low segment Write permission flag @@ -348,6 +348,145 @@ void esp_memprot_get_perm_split_bits_iram(mem_type_prot_t mem_type, bool *lw, bo */ void esp_memprot_get_perm_split_bits_dram(mem_type_prot_t mem_type, bool *lw, bool *lr, bool *hw, bool *hr); +/** + * @brief Sets permissions for high and low memory segment in PERIBUS1 region + * + * Sets Read and Write permission for both low and high memory segments given by splitting address. + * Applicable only to PERIBUS1 memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param split_addr Address to split the memory region to lower and higher segment + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + */ +void esp_memprot_set_prot_peri1(mem_type_prot_t mem_type, uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr); + +/** + * @brief Get permission settings bits for PERIBUS1 split mgmt. Only PERIBUS1 memory types allowed + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + */ +void esp_memprot_get_perm_split_bits_peri1(mem_type_prot_t mem_type, bool *lw, bool *lr, bool *hw, bool *hr); + +/** + * @brief Get permission settings bits for PERIBUS2 split mgmt. Only PERIBUS2 memory types allowed + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + */ +void esp_memprot_get_perm_split_bits_peri2(mem_type_prot_t mem_type, bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx); + +/** + * @brief Sets permissions for high and low memory segment in PERIBUS2 region + * + * Sets Read Write permission for both low and high memory segments given by splitting address. + * Applicable only to PERIBUS2 memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param split_addr Address to split the memory region to lower and higher segment + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + */ +void esp_memprot_set_prot_peri2(mem_type_prot_t mem_type, uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx); + +/** + * @brief Get permissions for specified memory type. Irrelevant bits are ignored + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lw Low segment Write permission flag + * @param lr Low segment Read permission flag + * @param lx Low segment Execute permission flag + * @param hw High segment Write permission flag + * @param hr High segment Read permission flag + * @param hx High segment Execute permission flag + */ +void esp_memprot_get_permissions(mem_type_prot_t mem_type, bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx); + +/** + * @brief Get Read permission settings for low and high regions of given memory type + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Read permission flag + * @param hr High segment Read permission flag + */ +void esp_memprot_get_perm_read(mem_type_prot_t mem_type, bool *lr, bool *hr); + +/** + * @brief Get Write permission settings for low and high regions of given memory type + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Write permission flag + * @param hr High segment Write permission flag + */ +void esp_memprot_get_perm_write(mem_type_prot_t mem_type, bool *lw, bool *hw); + +/** + * @brief Get Execute permission settings for low and high regions of given memory type + * Applicable only to IBUS-compatible memory types + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Exec permission flag + * @param hr High segment Exec permission flag + */ +void esp_memprot_get_perm_exec(mem_type_prot_t mem_type, bool *lx, bool *hx); + +/** + * @brief Returns the lowest address in required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + */ +uint32_t esp_memprot_get_low_limit(mem_type_prot_t mem_type); + +/** + * @brief Returns the highest address in required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + */ +uint32_t esp_memprot_get_high_limit(mem_type_prot_t mem_type); + +/** + * @brief Sets READ permission bit for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Read permission flag + * @param hr High segment Read permission flag + */ +void esp_memprot_set_read_perm(mem_type_prot_t mem_type, bool lr, bool hr); + +/** + * @brief Sets WRITE permission bit for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Write permission flag + * @param hr High segment Write permission flag + */ +void esp_memprot_set_write_perm(mem_type_prot_t mem_type, bool lw, bool hw); + +/** + * @brief Sets EXECUTE permission bit for required memory region + * + * @param mem_type Memory protection area type (see mem_type_prot_t enum) + * @param lr Low segment Exec permission flag + * @param hr High segment Exec permission flag + */ +void esp_memprot_set_exec_perm(mem_type_prot_t mem_type, bool lx, bool hx); + + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_mac.h b/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_mac.h index f12c66ae..a9052eee 100644 --- a/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_mac.h +++ b/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_mac.h @@ -298,8 +298,8 @@ typedef struct { uint32_t sw_reset_timeout_ms; /*!< Software reset timeout value (Unit: ms) */ uint32_t rx_task_stack_size; /*!< Stack size of the receive task */ uint32_t rx_task_prio; /*!< Priority of the receive task */ - int smi_mdc_gpio_num; /*!< SMI MDC GPIO number */ - int smi_mdio_gpio_num; /*!< SMI MDIO GPIO number */ + int smi_mdc_gpio_num; /*!< SMI MDC GPIO number, set to -1 could bypass the SMI GPIO configuration */ + int smi_mdio_gpio_num; /*!< SMI MDIO GPIO number, set to -1 could bypass the SMI GPIO configuration */ uint32_t flags; /*!< Flags that specify extra capability for mac driver */ } eth_mac_config_t; diff --git a/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h index a942426a..a6da8573 100644 --- a/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h @@ -537,7 +537,7 @@ int esp_http_client_read_response(esp_http_client_handle_t client, char *buffer, * - ESP_FAIL If failed to read response * - ESP_ERR_INVALID_ARG If the client is NULL */ -int esp_http_client_flush_response(esp_http_client_handle_t client, int *len); +esp_err_t esp_http_client_flush_response(esp_http_client_handle_t client, int *len); /** * @brief Get URL from client diff --git a/tools/sdk/esp32s2/include/esp_pm/include/esp32/pm.h b/tools/sdk/esp32s2/include/esp_pm/include/esp32/pm.h new file mode 100644 index 00000000..8c3682cc --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_pm/include/esp32/pm.h @@ -0,0 +1,42 @@ +// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once +#include +#include +#include "esp_err.h" + +#include "soc/rtc.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Power management config for ESP32 + * + * Pass a pointer to this structure as an argument to esp_pm_configure function. + */ +typedef struct { + int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */ + int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */ + bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */ +} esp_pm_config_esp32_t; + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_pm/include/esp32s2/pm.h b/tools/sdk/esp32s2/include/esp_pm/include/esp32s2/pm.h new file mode 100644 index 00000000..dac31e0c --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_pm/include/esp32s2/pm.h @@ -0,0 +1,42 @@ +// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once +#include +#include +#include "esp_err.h" + +#include "soc/rtc.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Power management config for ESP32 + * + * Pass a pointer to this structure as an argument to esp_pm_configure function. + */ +typedef struct { + int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */ + int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */ + bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */ +} esp_pm_config_esp32s2_t; + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_pm/include/esp32s3/pm.h b/tools/sdk/esp32s2/include/esp_pm/include/esp32s3/pm.h new file mode 100644 index 00000000..0b29c66a --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_pm/include/esp32s3/pm.h @@ -0,0 +1,42 @@ +// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once +#include +#include +#include "esp_err.h" + +#include "soc/rtc.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Power management config for ESP32 + * + * Pass a pointer to this structure as an argument to esp_pm_configure function. + */ +typedef struct { + int max_freq_mhz; /*!< Maximum CPU frequency, in MHz */ + int min_freq_mhz; /*!< Minimum CPU frequency to use when no locks are taken, in MHz */ + bool light_sleep_enable; /*!< Enter light sleep when no locks are taken */ +} esp_pm_config_esp32s3_t; + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_pm.h b/tools/sdk/esp32s2/include/esp_pm/include/esp_pm.h similarity index 99% rename from tools/sdk/esp32s2/include/esp_common/include/esp_pm.h rename to tools/sdk/esp32s2/include/esp_pm/include/esp_pm.h index 15af6a4a..d15a904b 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_pm.h +++ b/tools/sdk/esp32s2/include/esp_pm/include/esp_pm.h @@ -21,6 +21,8 @@ #include "esp32/pm.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/pm.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/pm.h" #endif #ifdef __cplusplus @@ -175,8 +177,6 @@ esp_err_t esp_pm_lock_delete(esp_pm_lock_handle_t handle); */ esp_err_t esp_pm_dump_locks(FILE* stream); - - #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_common/include/esp_private/pm_impl.h b/tools/sdk/esp32s2/include/esp_pm/include/esp_private/pm_impl.h similarity index 98% rename from tools/sdk/esp32/include/esp_common/include/esp_private/pm_impl.h rename to tools/sdk/esp32s2/include/esp_pm/include/esp_private/pm_impl.h index 71d41bd7..122190f2 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_private/pm_impl.h +++ b/tools/sdk/esp32s2/include/esp_pm/include/esp_private/pm_impl.h @@ -26,6 +26,9 @@ #include "esp_timer.h" #include "sdkconfig.h" +#ifdef __cplusplus +extern "C" { +#endif /** * This is an enum of possible power modes supported by the implementation @@ -151,3 +154,7 @@ static inline pm_time_t IRAM_ATTR pm_get_time(void) return esp_timer_get_time(); } #endif // WITH_PROFILING + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/esp_common/include/esp_private/pm_trace.h b/tools/sdk/esp32s2/include/esp_pm/include/esp_private/pm_trace.h similarity index 95% rename from tools/sdk/esp32/include/esp_common/include/esp_private/pm_trace.h rename to tools/sdk/esp32s2/include/esp_pm/include/esp_private/pm_trace.h index 24e67190..7bc35c15 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_private/pm_trace.h +++ b/tools/sdk/esp32s2/include/esp_pm/include/esp_private/pm_trace.h @@ -16,6 +16,10 @@ #include "sdkconfig.h" +#ifdef __cplusplus +extern "C" { +#endif + typedef enum { ESP_PM_TRACE_IDLE, ESP_PM_TRACE_TICK, @@ -43,3 +47,7 @@ void esp_pm_trace_exit(esp_pm_trace_event_t event, int core_id); #define ESP_PM_TRACE_EXIT(type, core_id) do { (void) core_id; } while(0) #endif // CONFIG_PM_TRACE + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h index 1ec326ca..259e7bab 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h @@ -81,11 +81,11 @@ typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; * * This function is used to verify the bootloader before burning its public key hash into Efuse. * Also, it is used to verify the app on loading the image on boot and on OTA. - * + * * @param sig The signature block flashed aligned 4096 bytes from the firmware. * @param image_digest The SHA-256 Digest of the firmware to be verified * @param trusted_key_digest The SHA-256 Digest of the public key (ets_rsa_pubkey_t) of a single signature block. - * @param verified_digest RSA-PSS signature of image_digest. Pass an uninitialised array. + * @param verified_digest RSA-PSS signature of image_digest. Pass an uninitialised array. * * @return SBV2_SUCCESS if signature is valid * SBV2_FAILED for failures. @@ -94,16 +94,16 @@ secure_boot_v2_status_t ets_secure_boot_verify_signature(const ets_secure_boot_s /** @brief This function verifies the 1st stage bootloader. Implemented in the ROM. * Reboots post verification. It reads the Efuse key for verification of the public key. - * + * * This function is not used in the current workflow. - * + * */ void ets_secure_boot_verify_boot_bootloader(void); /** @brief Confirms if the secure boot V2 has been enabled. Implemented in the ROM. - * + * * In ESP32-ECO3 - It checks the value of ABS_DONE_1 in EFuse. - * + * * @return true if is Secure boot v2 has been enabled * False if Secure boot v2 has not been enabled. */ @@ -111,4 +111,8 @@ bool ets_use_secure_boot_v2(void); #endif /* CONFIG_ESP32_REV_MIN_3 */ +#ifdef __cplusplus +} +#endif + #endif /* _ROM_SECURE_BOOT_H_ */ \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/sha.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/sha.h index 323749ef..f43c19d1 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/sha.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/sha.h @@ -24,6 +24,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -44,7 +45,7 @@ enum SHA_TYPE { SHA_INVALID = -1, }; -/* Do not use these function in multi core mode due to +/* Do not use these function in multi core mode due to * inside they have no safe implementation (without DPORT workaround). */ void ets_sha_init(SHA_CTX *ctx); diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/spi_flash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/spi_flash.h index b78a6130..c71b8100 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/spi_flash.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/spi_flash.h @@ -121,6 +121,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) //Extra dummy for flash read #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/opi_flash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/opi_flash.h index bb209f67..c985810b 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/opi_flash.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/opi_flash.h @@ -40,6 +40,7 @@ typedef struct { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_OP_MODE_RDCMD_DOUT 0x3B #define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/spi_flash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/spi_flash.h index 1eee20a5..2cf63166 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/spi_flash.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/spi_flash.h @@ -119,6 +119,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_ID_GD25LQ32C 0xC86016 diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h index 432c65ef..1df00a1d 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h @@ -21,8 +21,6 @@ extern "C" { #endif -#define AES_BLOCK_SIZE (16) - enum AES_TYPE { AES_ENC, AES_DEC, diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/opi_flash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/opi_flash.h new file mode 100644 index 00000000..be7fcb06 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/opi_flash.h @@ -0,0 +1,300 @@ +/* + * copyright (c) Espressif System 2019 + * + */ + +#ifndef _ROM_OPI_FLASH_H_ +#define _ROM_OPI_FLASH_H_ +#include +#include +#include +#include "spi_flash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint16_t cmd; /*!< Command value */ + uint16_t cmdBitLen; /*!< Command byte length*/ + uint32_t *addr; /*!< Point to address value*/ + uint32_t addrBitLen; /*!< Address byte length*/ + uint32_t *txData; /*!< Point to send data buffer*/ + uint32_t txDataBitLen; /*!< Send data byte length.*/ + uint32_t *rxData; /*!< Point to recevie data buffer*/ + uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/ + uint32_t dummyBitLen; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +// Definition of MX25UM25645G Octa Flash +// SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +// FLASH commands +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +// Definitions for GigaDevice GD25LX256E Flash +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +// spi user mode command config + +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission + */ +void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ +void esp_rom_opiflash_pin_config(void); + +// set SPI read/write mode +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ +void esp_rom_opiflash_mode_reset(int spi_num); + +#if 0 +// MX25UM25645G opi flash interface +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase flash operation + */ +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash ID(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash id + */ +uint32_t esp_rom_opiflash_read_id(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read opi flash status register(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @return opi flash status value + */ +uint8_t esp_rom_opiflash_rdsr(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief wait opi flash status register to be idle + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_wait_idle(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of configure register + * @return value of config register2 + */ +uint8_t esp_rom_opiflash_rdcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr); + +/** + * @brief to write the config register2(for MX25UM25645G) + * @param spi_num spi port + * @param mode Flash Operation Mode + * @param addr the address of config register + * @param val the value to write + */ +void esp_rom_opiflash_wrcr2(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t addr, uint8_t val); + +/** + * @brief to erase flash sector(for MX25UM25645G) + * @param spi_num spi port + * @param address the sector address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase flash block(for MX25UM25645G) + * @param spi_num spi port + * @param address the block address to be erased + * @param mode Flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t address, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to erase a flash area define by start address and length(for MX25UM25645G) + * @param spi_num spi port + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @param mode flash operation mode + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(int spi_num, uint32_t start_addr, uint32_t area_len, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief to read data from opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_read(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, int len); + +/** + * @brief to write data to opi flash(for MX25UM25645G) + * @param spi_num spi port + * @param mode flash operation mode + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_write(int spi_num, esp_rom_spiflash_read_mode_t mode, uint32_t flash_addr, uint8_t *data_addr, uint32_t len); + +/** + * @brief to set opi flash operation mode(for MX25UM25645G) + * @param spi_num spi port + * @param cur_mode current operation mode + * @param target the target operation mode to be set + */ +void esp_rom_opiflash_set_mode(int spi_num, esp_rom_spiflash_read_mode_t cur_mode, esp_rom_spiflash_read_mode_t target_mode); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h index 15adc528..a5a1ecb6 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h @@ -16,8 +16,7 @@ #include #include -#include "ets_sys.h" -#include "soc/soc.h" +#include "soc/rtc_cntl_reg.h" #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h index fb060c15..44d447e9 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h @@ -111,6 +111,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_ID_GD25LQ32C 0xC86016 diff --git a/tools/sdk/esp32s2/include/esp_system/include/esp_async_memcpy.h b/tools/sdk/esp32s2/include/esp_system/include/esp_async_memcpy.h new file mode 100644 index 00000000..67194e44 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_async_memcpy.h @@ -0,0 +1,115 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "esp_err.h" + +/** + * @brief Type of async memcpy handle + * + */ +typedef struct async_memcpy_context_t *async_memcpy_t; + +/** + * @brief Type of async memcpy event object + * + */ +typedef struct { + void *data; /*!< Event data */ +} async_memcpy_event_t; + +/** + * @brief Type of async memcpy interrupt callback function + * + * @param mcp_hdl Handle of async memcpy + * @param event Event object, which contains related data, reserved for future + * @param cb_args User defined arguments, passed from esp_async_memcpy function + * @return Whether a high priority task is woken up by the callback function + * + * @note User can call OS primitives (semaphore, mutex, etc) in the callback function. + * Keep in mind, if any OS primitive wakes high priority task up, the callback should return true. + */ +typedef bool (*async_memcpy_isr_cb_t)(async_memcpy_t mcp_hdl, async_memcpy_event_t *event, void *cb_args); + +/** + * @brief Type of async memcpy configuration + * + */ +typedef struct { + uint32_t backlog; /*!< Maximum number of streams that can be handled simultaneously */ + uint32_t flags; /*!< Extra flags to control async memcpy feature */ +} async_memcpy_config_t; + +/** + * @brief Default configuration for async memcpy + * + */ +#define ASYNC_MEMCPY_DEFAULT_CONFIG() \ + { \ + .backlog = 8, \ + .flags = 0, \ + } + +/** + * @brief Install async memcpy driver + * + * @param[in] config Configuration of async memcpy + * @param[out] asmcp Handle of async memcpy that returned from this API. If driver installation is failed, asmcp would be assigned to NULL. + * @return + * - ESP_OK: Install async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Install async memcpy driver failed because of invalid argument + * - ESP_ERR_NO_MEM: Install async memcpy driver failed because out of memory + * - ESP_FAIL: Install async memcpy driver failed because of other error + */ +esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_t *asmcp); + +/** + * @brief Uninstall async memcpy driver + * + * @param[in] asmcp Handle of async memcpy driver that returned from esp_async_memcpy_install + * @return + * - ESP_OK: Uninstall async memcpy driver successfully + * - ESP_ERR_INVALID_ARG: Uninstall async memcpy driver failed because of invalid argument + * - ESP_FAIL: Uninstall async memcpy driver failed because of other error + */ +esp_err_t esp_async_memcpy_uninstall(async_memcpy_t asmcp); + +/** + * @brief Send an asynchronous memory copy request + * + * @param[in] asmcp Handle of async memcpy driver that returned from esp_async_memcpy_install + * @param[in] dst Destination address (copy to) + * @param[in] src Source address (copy from) + * @param[in] n Number of bytes to copy + * @param[in] cb_isr Callback function, which got invoked in interrupt context. Set to NULL can bypass the callback. + * @param[in] cb_args User defined argument to be passed to the callback function + * @return + * - ESP_OK: Send memory copy request successfully + * - ESP_ERR_INVALID_ARG: Send memory copy request failed because of invalid argument + * - ESP_FAIL: Send memory copy request failed because of other error + * + * @note The callback function is invoked in interrupt context, never do blocking jobs in the callback. + */ +esp_err_t esp_async_memcpy(async_memcpy_t asmcp, void *dst, void *src, size_t n, async_memcpy_isr_cb_t cb_isr, void *cb_args); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp32s2/include/esp_intr_alloc.h b/tools/sdk/esp32s2/include/esp_system/include/esp_intr_alloc.h similarity index 91% rename from tools/sdk/esp32s2/include/esp32s2/include/esp_intr_alloc.h rename to tools/sdk/esp32s2/include/esp_system/include/esp_intr_alloc.h index 9b0b3c39..ace95cbb 100644 --- a/tools/sdk/esp32s2/include/esp32s2/include/esp_intr_alloc.h +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_intr_alloc.h @@ -18,7 +18,6 @@ #include #include #include "esp_err.h" -#include "freertos/xtensa_api.h" #ifdef __cplusplus extern "C" { @@ -68,9 +67,9 @@ extern "C" { * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources, * pass these pseudo-sources to the functions. */ -#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 ///< Xtensa timer 0 interrupt source -#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 ///< Xtensa timer 1 interrupt source -#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 ///< Xtensa timer 2 interrupt source +#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 ///< Platform timer 0 interrupt source +#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 ///< Platform timer 1 interrupt source +#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 ///< Platform timer 2 interrupt source #define ETS_INTERNAL_SW0_INTR_SOURCE -4 ///< Software int source 1 #define ETS_INTERNAL_SW1_INTR_SOURCE -5 ///< Software int source 2 #define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 ///< Int source for profiling @@ -82,10 +81,10 @@ extern "C" { #define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE) /** Enable interrupt by interrupt number */ -#define ESP_INTR_ENABLE(inum) xt_ints_on((1< #include "esp_rom_sys.h" #include "sdkconfig.h" +#include "freertos/xtensa_api.h" #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS #include "soc/soc_memory_layout.h" #endif -//#include "xtensa_context.h" - /*----------------------------------------------------------- * Port specific definitions. * diff --git a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_api.h b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_api.h index 19630ce5..bdfd7151 100644 --- a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_api.h +++ b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_api.h @@ -1,130 +1,2 @@ -/******************************************************************************* -Copyright (c) 2006-2015 Cadence Design Systems Inc. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be included -in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -******************************************************************************/ - -/****************************************************************************** - Xtensa-specific API for RTOS ports. -******************************************************************************/ - -#ifndef __XTENSA_API_H__ -#define __XTENSA_API_H__ - -#include - -#include "xtensa_context.h" - - -/* Typedef for C-callable interrupt handler function */ -typedef void (*xt_handler)(void *); - -/* Typedef for C-callable exception handler function */ -typedef void (*xt_exc_handler)(XtExcFrame *); - - -/* -------------------------------------------------------------------------------- - Call this function to set a handler for the specified exception. The handler - will be installed on the core that calls this function. - - n - Exception number (type) - f - Handler function address, NULL to uninstall handler. - - The handler will be passed a pointer to the exception frame, which is created - on the stack of the thread that caused the exception. - - If the handler returns, the thread context will be restored and the faulting - instruction will be retried. Any values in the exception frame that are - modified by the handler will be restored as part of the context. For details - of the exception frame structure see xtensa_context.h. -------------------------------------------------------------------------------- -*/ -extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f); - - -/* -------------------------------------------------------------------------------- - Call this function to set a handler for the specified interrupt. The handler - will be installed on the core that calls this function. - - n - Interrupt number. - f - Handler function address, NULL to uninstall handler. - arg - Argument to be passed to handler. -------------------------------------------------------------------------------- -*/ -extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg); - - -/* -------------------------------------------------------------------------------- - Call this function to enable the specified interrupts on the core that runs - this code. - - mask - Bit mask of interrupts to be enabled. -------------------------------------------------------------------------------- -*/ -extern void xt_ints_on(unsigned int mask); - - -/* -------------------------------------------------------------------------------- - Call this function to disable the specified interrupts on the core that runs - this code. - - mask - Bit mask of interrupts to be disabled. -------------------------------------------------------------------------------- -*/ -extern void xt_ints_off(unsigned int mask); - - -/* -------------------------------------------------------------------------------- - Call this function to set the specified (s/w) interrupt. -------------------------------------------------------------------------------- -*/ -static inline void xt_set_intset(unsigned int arg) -{ - xthal_set_intset(arg); -} - - -/* -------------------------------------------------------------------------------- - Call this function to clear the specified (s/w or edge-triggered) - interrupt. -------------------------------------------------------------------------------- -*/ -static inline void xt_set_intclear(unsigned int arg) -{ - xthal_set_intclear(arg); -} - -/* -------------------------------------------------------------------------------- - Call this function to get handler's argument for the specified interrupt. - - n - Interrupt number. -------------------------------------------------------------------------------- -*/ -extern void * xt_get_interrupt_handler_arg(int n); - -#endif /* __XTENSA_API_H__ */ - +/* This header file has been moved, please include in future */ +#include diff --git a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_context.h b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_context.h index 120676da..1d0f4e58 100644 --- a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_context.h +++ b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/xtensa_context.h @@ -1,387 +1,2 @@ -/******************************************************************************* -Copyright (c) 2006-2015 Cadence Design Systems Inc. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be included -in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. --------------------------------------------------------------------------------- - - XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES - -This header contains definitions and macros for use primarily by Xtensa -RTOS assembly coded source files. It includes and uses the Xtensa hardware -abstraction layer (HAL) to deal with config specifics. It may also be -included in C source files. - -!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !! - -NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. - -*******************************************************************************/ - -#ifndef XTENSA_CONTEXT_H -#define XTENSA_CONTEXT_H - -#ifdef __ASSEMBLER__ -#include -#endif - -#include -#include -#include -#include - - -/* Align a value up to nearest n-byte boundary, where n is a power of 2. */ -#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) - - -/* -------------------------------------------------------------------------------- - Macros that help define structures for both C and assembler. -------------------------------------------------------------------------------- -*/ - -#ifdef STRUCT_BEGIN -#undef STRUCT_BEGIN -#undef STRUCT_FIELD -#undef STRUCT_AFIELD -#undef STRUCT_END -#endif - -#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) - -#define STRUCT_BEGIN .pushsection .text; .struct 0 -#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size -#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) -#define STRUCT_END(sname) sname##Size:; .popsection - -#else - -#define STRUCT_BEGIN typedef struct { -#define STRUCT_FIELD(ctype,size,asname,name) ctype name; -#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; -#define STRUCT_END(sname) } sname; - -#endif //_ASMLANGUAGE || __ASSEMBLER__ - - -/* -------------------------------------------------------------------------------- - INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT - - A stack frame of this structure is allocated for any interrupt or exception. - It goes on the current stack. If the RTOS has a system stack for handling - interrupts, every thread stack must allow space for just one interrupt stack - frame, then nested interrupt stack frames go on the system stack. - - The frame includes basic registers (explicit) and "extra" registers introduced - by user TIE or the use of the MAC16 option in the user's Xtensa config. - The frame size is minimized by omitting regs not applicable to user's config. - - For Windowed ABI, this stack frame includes the interruptee's base save area, - another base save area to manage gcc nested functions, and a little temporary - space to help manage the spilling of the register windows. -------------------------------------------------------------------------------- -*/ - -STRUCT_BEGIN -STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ -STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ -STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ -STRUCT_FIELD (long, 4, XT_STK_A0, a0) -STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ -STRUCT_FIELD (long, 4, XT_STK_A2, a2) -STRUCT_FIELD (long, 4, XT_STK_A3, a3) -STRUCT_FIELD (long, 4, XT_STK_A4, a4) -STRUCT_FIELD (long, 4, XT_STK_A5, a5) -STRUCT_FIELD (long, 4, XT_STK_A6, a6) -STRUCT_FIELD (long, 4, XT_STK_A7, a7) -STRUCT_FIELD (long, 4, XT_STK_A8, a8) -STRUCT_FIELD (long, 4, XT_STK_A9, a9) -STRUCT_FIELD (long, 4, XT_STK_A10, a10) -STRUCT_FIELD (long, 4, XT_STK_A11, a11) -STRUCT_FIELD (long, 4, XT_STK_A12, a12) -STRUCT_FIELD (long, 4, XT_STK_A13, a13) -STRUCT_FIELD (long, 4, XT_STK_A14, a14) -STRUCT_FIELD (long, 4, XT_STK_A15, a15) -STRUCT_FIELD (long, 4, XT_STK_SAR, sar) -STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) -STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) -#if XCHAL_HAVE_LOOPS -STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) -STRUCT_FIELD (long, 4, XT_STK_LEND, lend) -STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) -#endif -#ifndef __XTENSA_CALL0_ABI__ -/* Temporary space for saving stuff during window spill */ -STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) -STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) -STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) -#endif -#ifdef XT_USE_SWPRI -/* Storage for virtual priority mask */ -STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) -#endif -#ifdef XT_USE_OVLY -/* Storage for overlay state */ -STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) -#endif -STRUCT_END(XtExcFrame) - -#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) -#define XT_STK_NEXT1 XtExcFrameSize -#else -#define XT_STK_NEXT1 sizeof(XtExcFrame) -#endif - -/* Allocate extra storage if needed */ -#if XCHAL_EXTRA_SA_SIZE != 0 - -#if XCHAL_EXTRA_SA_ALIGN <= 16 -#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) -#else -/* If need more alignment than stack, add space for dynamic alignment */ -#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) -#endif -#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) - -#else - -#define XT_STK_NEXT2 XT_STK_NEXT1 - -#endif - -/* -------------------------------------------------------------------------------- - This is the frame size. Add space for 4 registers (interruptee's base save - area) and some space for gcc nested functions if any. -------------------------------------------------------------------------------- -*/ -#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) - - -/* -------------------------------------------------------------------------------- - SOLICITED STACK FRAME FOR A THREAD - - A stack frame of this structure is allocated whenever a thread enters the - RTOS kernel intentionally (and synchronously) to submit to thread scheduling. - It goes on the current thread's stack. - - The solicited frame only includes registers that are required to be preserved - by the callee according to the compiler's ABI conventions, some space to save - the return address for returning to the caller, and the caller's PS register. - - For Windowed ABI, this stack frame includes the caller's base save area. - - Note on XT_SOL_EXIT field: - It is necessary to distinguish a solicited from an interrupt stack frame. - This field corresponds to XT_STK_EXIT in the interrupt stack frame and is - always at the same offset (0). It can be written with a code (usually 0) - to distinguish a solicted frame from an interrupt frame. An RTOS port may - opt to ignore this field if it has another way of distinguishing frames. -------------------------------------------------------------------------------- -*/ - -STRUCT_BEGIN -#ifdef __XTENSA_CALL0_ABI__ -STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) -STRUCT_FIELD (long, 4, XT_SOL_PC, pc) -STRUCT_FIELD (long, 4, XT_SOL_PS, ps) -STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) -STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ -STRUCT_FIELD (long, 4, XT_SOL_A13, a13) -STRUCT_FIELD (long, 4, XT_SOL_A14, a14) -STRUCT_FIELD (long, 4, XT_SOL_A15, a15) -#else -STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) -STRUCT_FIELD (long, 4, XT_SOL_PC, pc) -STRUCT_FIELD (long, 4, XT_SOL_PS, ps) -STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) -STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ -STRUCT_FIELD (long, 4, XT_SOL_A1, a1) -STRUCT_FIELD (long, 4, XT_SOL_A2, a2) -STRUCT_FIELD (long, 4, XT_SOL_A3, a3) -#endif -STRUCT_END(XtSolFrame) - -/* Size of solicited stack frame */ -#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) - - -/* -------------------------------------------------------------------------------- - CO-PROCESSOR STATE SAVE AREA FOR A THREAD - - The RTOS must provide an area per thread to save the state of co-processors - when that thread does not have control. Co-processors are context-switched - lazily (on demand) only when a new thread uses a co-processor instruction, - otherwise a thread retains ownership of the co-processor even when it loses - control of the processor. An Xtensa co-processor exception is triggered when - any co-processor instruction is executed by a thread that is not the owner, - and the context switch of that co-processor is then peformed by the handler. - Ownership represents which thread's state is currently in the co-processor. - - Co-processors may not be used by interrupt or exception handlers. If an - co-processor instruction is executed by an interrupt or exception handler, - the co-processor exception handler will trigger a kernel panic and freeze. - This restriction is introduced to reduce the overhead of saving and restoring - co-processor state (which can be quite large) and in particular remove that - overhead from interrupt handlers. - - The co-processor state save area may be in any convenient per-thread location - such as in the thread control block or above the thread stack area. It need - not be in the interrupt stack frame since interrupts don't use co-processors. - - Along with the save area for each co-processor, two bitmasks with flags per - co-processor (laid out as in the CPENABLE reg) help manage context-switching - co-processors as efficiently as possible: - - XT_CPENABLE - The contents of a non-running thread's CPENABLE register. - It represents the co-processors owned (and whose state is still needed) - by the thread. When a thread is preempted, its CPENABLE is saved here. - When a thread solicits a context-swtich, its CPENABLE is cleared - the - compiler has saved the (caller-saved) co-proc state if it needs to. - When a non-running thread loses ownership of a CP, its bit is cleared. - When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. - Avoids co-processor exceptions when no change of ownership is needed. - - XT_CPSTORED - A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether the state of each co-processor is saved in the state - save area. When a thread enters the kernel, only the state of co-procs - still enabled in CPENABLE is saved. When the co-processor exception - handler assigns ownership of a co-processor to a thread, it restores - the saved state only if this bit is set, and clears this bit. - - XT_CP_CS_ST - A bitmask with the same layout as CPENABLE, a bit per co-processor. - Indicates whether callee-saved state is saved in the state save area. - Callee-saved state is saved by itself on a solicited context switch, - and restored when needed by the coprocessor exception handler. - Unsolicited switches will cause the entire coprocessor to be saved - when necessary. - - XT_CP_ASA - Pointer to the aligned save area. Allows it to be aligned more than - the overall save area (which might only be stack-aligned or TCB-aligned). - Especially relevant for Xtensa cores configured with a very large data - path that requires alignment greater than 16 bytes (ABI stack alignment). -------------------------------------------------------------------------------- -*/ - -#if XCHAL_CP_NUM > 0 - -/* Offsets of each coprocessor save area within the 'aligned save area': */ -#define XT_CP0_SA 0 -#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) -#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) -#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) -#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) -#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) -#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) -#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) -#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) - -/* Offsets within the overall save area: */ -#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ -#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ -#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ -#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ -/* Overall size allows for dynamic alignment: */ -#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) -#else -#define XT_CP_SIZE 0 -#endif - - -/* - Macro to get the current core ID. Only uses the reg given as an argument. - Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0) - and 0xABAB on the APP CPU (1). We can distinguish between the two by checking - bit 13: it's 1 on the APP and 0 on the PRO processor. -*/ -#ifdef __ASSEMBLER__ - .macro getcoreid reg - rsr.prid \reg - extui \reg,\reg,13,1 - .endm -#endif - -/* Note: These are different to xCoreID used in ESP-IDF FreeRTOS, most places use - 0 and 1 which are determined by checking bit 13 (see previous comment) -*/ -#define CORE_ID_REGVAL_PRO 0xCDCD -#define CORE_ID_REGVAL_APP 0xABAB - -/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */ -#define CORE_ID_PRO CORE_ID_REGVAL_PRO - -/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */ -#define CORE_ID_APP CORE_ID_REGVAL_APP - -/* -------------------------------------------------------------------------------- - MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN - - Convenient where the frame size requirements are the same for both ABIs. - ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). - ENTRY0, RET0 are for frameless functions (no locals, no calls). - - where size = size of stack frame in bytes (must be >0 and aligned to 16). - For framed functions the frame is created and the return address saved at - base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). - For frameless functions, there is no frame and return address remains in a0. - Note: Because CPP macros expand to a single line, macros requiring multi-line - expansions are implemented as assembler macros. -------------------------------------------------------------------------------- -*/ - -#ifdef __ASSEMBLER__ -#ifdef __XTENSA_CALL0_ABI__ - /* Call0 */ - #define ENTRY(sz) entry1 sz - .macro entry1 size=0x10 - addi sp, sp, -\size - s32i a0, sp, 0 - .endm - #define ENTRY0 - #define RET(sz) ret1 sz - .macro ret1 size=0x10 - l32i a0, sp, 0 - addi sp, sp, \size - ret - .endm - #define RET0 ret -#else - /* Windowed */ - #define ENTRY(sz) entry sp, sz - #define ENTRY0 entry sp, 0x10 - #define RET(sz) retw - #define RET0 retw -#endif -#endif - - - - - -#endif /* XTENSA_CONTEXT_H */ - +/* This header file has been moved, please include in future */ +#include \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/adc_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/adc_ll.h index 13949394..415f1050 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/adc_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/adc_ll.h @@ -69,62 +69,6 @@ typedef enum { ADC2_CTRL_FORCE_DIG = 6, /*!> 8; uint8_t lsb = param & 0xFF; /* Should be called before writing I2C registers. */ - void phy_get_romfunc_addr(void); - phy_get_romfunc_addr(); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18)); - SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16)); + SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16)); if (adc_n == ADC_NUM_1) { - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR, msb); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR, lsb); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb); } else { - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR, msb); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR, lsb); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb); } } /* Temp code end. */ @@ -1275,23 +1213,21 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) { /* Should be called before writing I2C registers. */ - void phy_get_romfunc_addr(void); - phy_get_romfunc_addr(); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18)); - SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16)); + SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16)); if (en) { if (adc == ADC_NUM_1) { /* Config test mux to route v_ref to ADC1 Channels */ - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 1); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 1); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1); } else { /* Config test mux to route v_ref to ADC2 Channels */ - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 0); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); } //in sleep force to use rtc to control ADC SENS.sar_meas2_mux.sar2_rtc_force = 1; @@ -1302,8 +1238,8 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b //set en_pad for ADC2 channels (bits 0x380) SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel; } else { - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0); - I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); SENS.sar_meas2_mux.sar2_rtc_force = 0; //set sar2_en_test SENS.sar_meas2_ctrl1.sar2_en_test = 0; diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cp_dma_hal.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cp_dma_hal.h index bec3dcfc..03d91739 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cp_dma_hal.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cp_dma_hal.h @@ -33,48 +33,29 @@ extern "C" { #include #include #include "esp_attr.h" +#include "hal/dma_types.h" #include "soc/cp_dma_struct.h" -typedef struct cp_dma_descriptor { - struct { - uint32_t size : 12; /*!< buffer size */ - uint32_t length : 12; /*!< specify number of valid bytes in the buffer */ - uint32_t reversed24_27 : 4; /*!< reserved */ - uint32_t err : 1; /*!< specify whether a received buffer contains error */ - uint32_t reserved29 : 1; /*!< reserved */ - uint32_t eof : 1; /*!< if this dma link is the last one, you shoule set this bit 1 */ - uint32_t owner : 1; /*!< specify the owner of buffer that this descriptor points to, 1=DMA, 0=CPU. DMA will clear it after use. */ - } dw0; /*!< descriptor word 0 */ - void *buffer; /*!< pointer to the buffer */ - struct cp_dma_descriptor *next; /*!< pointer to the next descriptor or NULL if this descriptor is the last one */ -} cp_dma_descriptor_t; - -_Static_assert(sizeof(cp_dma_descriptor_t) == 12, "cp_dma_descriptor_t should occupy 12 bytes in memory"); - /** * @brief HAL context * - * @note `tx_desc` and `rx_desc` are internal state of the HAL, will be modified during the operations. - * Upper layer of HAL should keep the buffer address themselves and make sure the buffers are freed when the HAL is no longer used. - * */ typedef struct { cp_dma_dev_t *dev; - cp_dma_descriptor_t *tx_desc; - cp_dma_descriptor_t *rx_desc; - cp_dma_descriptor_t *next_rx_desc_to_check; } cp_dma_hal_context_t; +typedef struct { + dma_descriptor_t *outlink_base; /*!< Address of the first outlink descriptor */ + dma_descriptor_t *inlink_base; /*!< Address of the first inlink descriptor */ +} cp_dma_hal_config_t; + /** * @brief Initialize HAL layer context * - * @param hal HAL layer context, memroy should be allocated at driver layer - * @param tx_descriptors out link descriptor pool - * @param tx_desc_num number of out link descriptors - * @param rx_descriptors in line descriptor pool - * @param rx_desc_num number of in link descriptors + * @param hal HAL layer context, whose memroy should be allocated at driver layer + * @param config configuration for the HAL layer */ -void cp_dma_hal_init(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *tx_descriptors[], uint32_t tx_desc_num, cp_dma_descriptor_t *rx_descriptors[], uint32_t rx_desc_num); +void cp_dma_hal_init(cp_dma_hal_context_t *hal, const cp_dma_hal_config_t *config); /** * @brief Deinitialize HAL layer context @@ -105,39 +86,6 @@ uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal) IRAM_ATTR; */ void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask) IRAM_ATTR; -/** - * @brief Get next RX descriptor that needs recycling - * - * @param eof_desc EOF descriptor for this iteration - * @param[out] next_desc Next descriptor needs to check - * @return Whether to continue - */ -bool cp_dma_hal_get_next_rx_descriptor(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *eof_desc, cp_dma_descriptor_t **next_desc); - -/** - * @brief Prepare buffer to be transmitted - * - * @param hal HAL layer context - * @param buffer buffer address - * @param len buffer size - * @param[out] start_desc The first descriptor that carry the TX transaction - * @param[out] end_desc The last descriptor that carry the TX transaction - * @return Number of bytes has been parepared to transmit - */ -int cp_dma_hal_prepare_transmit(cp_dma_hal_context_t *hal, void *buffer, size_t len, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc); - -/** - * @brief Prepare buffer to receive - * - * @param hal HAL layer context - * @param buffer buffer address - * @param size buffer size - * @param[out] start_desc The first descriptor that carries the RX transaction - * @param[out] end_desc The last descriptor that carries the RX transaction - * @return Number of bytes has been parepared to receive - */ -int cp_dma_hal_prepare_receive(cp_dma_hal_context_t *hal, void *buffer, size_t size, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc); - /**@{*/ /** * @brief Give the owner of descriptors between [start_desc, end_desc] to DMA, and restart DMA HW engine @@ -146,8 +94,8 @@ int cp_dma_hal_prepare_receive(cp_dma_hal_context_t *hal, void *buffer, size_t s * @param start_desc The first descriptor that carries one transaction * @param end_desc The last descriptor that carries one transaction */ -void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc); -void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc); +void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal); +void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal); /**@}*/ #ifdef __cplusplus diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/crypto_dma_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/crypto_dma_ll.h new file mode 100644 index 00000000..075aa0bd --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/crypto_dma_ll.h @@ -0,0 +1,81 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ +#pragma once + +#include "soc/hwcrypto_reg.h" +#include "soc/dport_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + CRYPTO_DMA_AES = 0, + CRYPTO_DMA_SHA, +} crypto_dma_mode_t; + +/** + * @brief Resets set the outlink + * + */ +static inline void crypto_dma_ll_outlink_reset(void) +{ + SET_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); + CLEAR_PERI_REG_MASK(CRYPTO_DMA_CONF0_REG, CONF0_REG_AHBM_RST | CONF0_REG_OUT_RST | CONF0_REG_AHBM_FIFO_RST); +} + + +/** + * @brief Selects the crypto DMA mode + * + * @param mode Mode to use, AES or SHA + */ +static inline void crypto_dma_ll_set_mode(crypto_dma_mode_t mode) +{ + REG_WRITE(CRYPTO_DMA_AES_SHA_SELECT_REG, mode); +} + +/** + * @brief Sets up the outlink for a transfer + * + * @param outlink_addr Address of the outlink buffer + */ +static inline void crypto_dma_ll_outlink_set(uint32_t outlink_addr) +{ + CLEAR_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_ADDR); + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, outlink_addr & OUT_LINK_REG_OUTLINK_ADDR); +} + +/** + * @brief Starts the outlink + * + */ +static inline void crypto_dma_ll_outlink_start(void) +{ + SET_PERI_REG_MASK(CRYPTO_DMA_OUT_LINK_REG, OUT_LINK_REG_OUTLINK_START); +} + + +#ifdef __cplusplus +} +#endif + + + diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/dac_hal.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/dac_hal.h similarity index 100% rename from tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/dac_hal.h rename to tools/sdk/esp32s2/include/hal/esp32s2/include/hal/dac_hal.h diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpspi_flash_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpspi_flash_ll.h index f9cf4e26..aa948225 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpspi_flash_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpspi_flash_ll.h @@ -156,7 +156,7 @@ static inline void gpspi_flash_ll_user_start(spi_dev_t *dev) */ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev) { - return dev->fsm.st != 0; + return dev->fsm.st == 0; } /** diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/interrupt_controller_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/interrupt_controller_ll.h new file mode 100644 index 00000000..3c3d5981 --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/interrupt_controller_ll.h @@ -0,0 +1,105 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "soc/soc_caps.h" +#include "soc/soc.h" +#include "xtensa/xtensa_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief enable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be enabled + */ +static inline void intr_cntrl_ll_enable_interrupts(uint32_t mask) +{ + xt_ints_on(mask); +} + +/** + * @brief disable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be disabled + */ +static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask) +{ + xt_ints_off(mask); +} + +/** + * @brief checks if given interrupt number has a valid handler + * + * @param intr interrupt number ranged from 0 to 31 + * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1 + * @return true for valid handler, false otherwise + */ +static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu) +{ + return xt_int_has_handler(intr, cpu); +} + +/** + * @brief sets interrupt handler and optional argument of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * @param handler handler invoked when an interrupt occurs + * @param arg optional argument to pass to the handler + */ +static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg) +{ + xt_set_interrupt_handler(intr, (xt_handler)handler, arg); +} + +/** + * @brief Gets argument passed to handler of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * + * @return argument used by handler of passed interrupt number + */ +static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr) +{ + return xt_get_interrupt_handler_arg(intr); +} + +/** + * @brief Disables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + * @return oldmask where to store old interrupts state + */ +static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask) +{ + return xt_int_disable_mask(newmask); +} + +/** + * @brief Enables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + */ +static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask) +{ + xt_int_enable_mask(newmask); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_ll.h index d7769972..bf99e149 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_ll.h @@ -19,38 +19,18 @@ extern "C" { #endif /** - * === IRAM0 ==== + * ======================================================================================== + * === IRAM0 common + * ======================================================================================== */ - -#define IRAM0_TOTAL_UNI_BLOCKS 4 -#define IRAM0_UNI_BLOCK_0 0 -#define IRAM0_UNI_BLOCK_1 1 -#define IRAM0_UNI_BLOCK_2 2 -#define IRAM0_UNI_BLOCK_3 3 - -#define IRAM0_SPL_BLOCK_BASE 0x40000000 - -//unified management (SRAM blocks 0-3) -#define IRAM0_UNI_BLOCK_0_LOW 0x40020000 -#define IRAM0_UNI_BLOCK_0_HIGH 0x40021FFF -#define IRAM0_UNI_BLOCK_1_LOW 0x40022000 -#define IRAM0_UNI_BLOCK_1_HIGH 0x40023FFF -#define IRAM0_UNI_BLOCK_2_LOW 0x40024000 -#define IRAM0_UNI_BLOCK_2_HIGH 0x40025FFF -#define IRAM0_UNI_BLOCK_3_LOW 0x40026000 -#define IRAM0_UNI_BLOCK_3_HIGH 0x40027FFF - -//split management (SRAM blocks 4-21) -#define IRAM0_SPL_BLOCK_LOW 0x40028000 //block 4 low -#define IRAM0_SPL_BLOCK_HIGH 0x4006FFFF //block 21 high -#define IRAM0_SPLTADDR_MIN 0x40030000 //block 6 low - minimum splitting address - //IRAM0 interrupt status bitmasks -#define IRAM0_INTR_ST_FAULTADDR_M 0x003FFFFC //(bits 21:6 in the reg, as well as in real address) -#define IRAM0_INTR_ST_FAULTADDR_HI 0x40000000 //(high nonsignificant bits 31:22 of the faulting address - constant) -#define IRAM0_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1 -#define IRAM0_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1 +#define IRAM0_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1 +#define IRAM0_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1 +static inline void esp_memprot_iram0_clear_intr(void) +{ + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR); +} static inline uint32_t esp_memprot_iram0_get_intr_source_num(void) { @@ -59,14 +39,14 @@ static inline uint32_t esp_memprot_iram0_get_intr_source_num(void) static inline void esp_memprot_iram0_intr_ena(bool enable) { - if ( enable ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN ); + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN); } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN ); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN); } } -static inline uint32_t esp_memprot_iram0_get_ena_reg(void) +static inline uint32_t esp_memprot_iram0_get_conf_reg(void) { return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_4_REG); } @@ -76,13 +56,9 @@ static inline uint32_t esp_memprot_iram0_get_fault_reg(void) return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_5_REG); } -static inline void esp_memprot_iram0_get_fault_status(uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype) +static inline void esp_memprot_iram0_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype) { uint32_t status_bits = esp_memprot_iram0_get_fault_reg(); - - uint32_t fault_addr = (status_bits & IRAM0_INTR_ST_FAULTADDR_M); - *faulting_address = (uint32_t *)(fault_addr | IRAM0_INTR_ST_FAULTADDR_HI); - *op_type = (uint32_t)status_bits & IRAM0_INTR_ST_OP_RW_BIT; *op_subtype = (uint32_t)status_bits & IRAM0_INTR_ST_OP_TYPE_BIT; } @@ -92,11 +68,6 @@ static inline bool esp_memprot_iram0_is_assoc_intr(void) return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_INTR) > 0; } -static inline void esp_memprot_iram0_clear_intr(void) -{ - DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR); -} - static inline uint32_t esp_memprot_iram0_get_intr_ena_bit(void) { return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN); @@ -128,29 +99,72 @@ static inline uint32_t esp_memprot_iram0_get_lock_bit(void) return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK); } -//block 0-3 -static inline void esp_memprot_iram0_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm, bool exec_perm) +/** + * ======================================================================================== + * === IRAM0 SRAM + * ======================================================================================== + */ +#define IRAM0_SRAM_ADDRESS_LOW 0x40020000 +#define IRAM0_SRAM_ADDRESS_HIGH 0x4006FFFF + +#define IRAM0_SRAM_TOTAL_UNI_BLOCKS 4 +#define IRAM0_SRAM_UNI_BLOCK_0 0 +#define IRAM0_SRAM_UNI_BLOCK_1 1 +#define IRAM0_SRAM_UNI_BLOCK_2 2 +#define IRAM0_SRAM_UNI_BLOCK_3 3 + +//unified management (SRAM blocks 0-3) +#define IRAM0_SRAM_UNI_BLOCK_0_LOW 0x40020000 +#define IRAM0_SRAM_UNI_BLOCK_1_LOW 0x40022000 +#define IRAM0_SRAM_UNI_BLOCK_2_LOW 0x40024000 +#define IRAM0_SRAM_UNI_BLOCK_3_LOW 0x40026000 + +//split management (SRAM blocks 4-21) +#define IRAM0_SRAM_SPL_BLOCK_LOW 0x40028000 //block 4 low +#define IRAM0_SRAM_SPL_BLOCK_HIGH 0x4006FFFF //block 21 high + +#define IRAM0_INTR_ST_FAULTADDR_M 0x003FFFFC //bits 21:6 in the reg, as well as in real address +#define IRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x40000000 //high nonsignificant bits 31:22 of the faulting address - constant + + +static inline uint32_t *esp_memprot_iram0_sram_get_fault_address(void) { - assert(block < IRAM0_TOTAL_UNI_BLOCKS); + uint32_t status_bits = esp_memprot_iram0_get_fault_reg(); + return (uint32_t *)((status_bits & IRAM0_INTR_ST_FAULTADDR_M) | IRAM0_SRAM_INTR_ST_FAULTADDR_HI); +} + +static inline bool esp_memprot_iram0_sram_is_intr_mine(void) +{ + if (esp_memprot_iram0_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_iram0_sram_get_fault_address(); + return (uint32_t)faulting_address >= IRAM0_SRAM_ADDRESS_LOW && (uint32_t)faulting_address <= IRAM0_SRAM_ADDRESS_HIGH; + } + return false; +} + +//block 0-3 +static inline void esp_memprot_iram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm, bool exec_perm) +{ + assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS); uint32_t write_bit, read_bit, exec_bit; - switch ( block ) { - case IRAM0_UNI_BLOCK_0: + switch (block) { + case IRAM0_SRAM_UNI_BLOCK_0: write_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_W; read_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_R; exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_F; break; - case IRAM0_UNI_BLOCK_1: + case IRAM0_SRAM_UNI_BLOCK_1: write_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_W; read_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_R; exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_F; break; - case IRAM0_UNI_BLOCK_2: + case IRAM0_SRAM_UNI_BLOCK_2: write_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_W; read_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_R; exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_F; break; - case IRAM0_UNI_BLOCK_3: + case IRAM0_SRAM_UNI_BLOCK_3: write_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_W; read_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_R; exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_F; @@ -159,100 +173,100 @@ static inline void esp_memprot_iram0_set_uni_block_perm(uint32_t block, bool wri abort(); } - if ( write_perm ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_1_REG, write_bit ); + if (write_perm) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, write_bit); } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_1_REG, write_bit ); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, write_bit); } - if ( read_perm ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_1_REG, read_bit ); + if (read_perm) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, read_bit); } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_1_REG, read_bit ); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, read_bit); } - if ( exec_perm ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_1_REG, exec_bit ); + if (exec_perm) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, exec_bit); } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_IRAM0_1_REG, exec_bit ); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, exec_bit); } } -static inline uint32_t esp_memprot_iram0_get_uni_block_read_bit(uint32_t block) +static inline uint32_t esp_memprot_iram0_sram_get_uni_block_read_bit(uint32_t block) { - assert(block < IRAM0_TOTAL_UNI_BLOCKS); + assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS); - switch ( block ) { - case IRAM0_UNI_BLOCK_0: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_R ); - case IRAM0_UNI_BLOCK_1: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_R ); - case IRAM0_UNI_BLOCK_2: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_R ); - case IRAM0_UNI_BLOCK_3: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_R ); + switch (block) { + case IRAM0_SRAM_UNI_BLOCK_0: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_R); + case IRAM0_SRAM_UNI_BLOCK_1: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_R); + case IRAM0_SRAM_UNI_BLOCK_2: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_R); + case IRAM0_SRAM_UNI_BLOCK_3: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_R); default: abort(); } } -static inline uint32_t esp_memprot_iram0_get_uni_block_write_bit(uint32_t block) +static inline uint32_t esp_memprot_iram0_sram_get_uni_block_write_bit(uint32_t block) { - assert(block < IRAM0_TOTAL_UNI_BLOCKS); + assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS); - switch ( block ) { - case IRAM0_UNI_BLOCK_0: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_W ); - case IRAM0_UNI_BLOCK_1: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_W ); - case IRAM0_UNI_BLOCK_2: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_W ); - case IRAM0_UNI_BLOCK_3: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_W ); + switch (block) { + case IRAM0_SRAM_UNI_BLOCK_0: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_W); + case IRAM0_SRAM_UNI_BLOCK_1: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_W); + case IRAM0_SRAM_UNI_BLOCK_2: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_W); + case IRAM0_SRAM_UNI_BLOCK_3: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_W); default: abort(); } } -static inline uint32_t esp_memprot_iram0_get_uni_block_exec_bit(uint32_t block) +static inline uint32_t esp_memprot_iram0_sram_get_uni_block_exec_bit(uint32_t block) { - assert(block < IRAM0_TOTAL_UNI_BLOCKS); + assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS); - switch ( block ) { - case IRAM0_UNI_BLOCK_0: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_F ); - case IRAM0_UNI_BLOCK_1: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_F ); - case IRAM0_UNI_BLOCK_2: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_F ); - case IRAM0_UNI_BLOCK_3: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_F ); + switch (block) { + case IRAM0_SRAM_UNI_BLOCK_0: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_F); + case IRAM0_SRAM_UNI_BLOCK_1: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_F); + case IRAM0_SRAM_UNI_BLOCK_2: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_F); + case IRAM0_SRAM_UNI_BLOCK_3: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_F); default: abort(); } } -static inline void esp_memprot_iram0_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit, uint32_t *exec_bit) +static inline void esp_memprot_iram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit, uint32_t *exec_bit) { - assert(block < IRAM0_TOTAL_UNI_BLOCKS); + assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS); - switch ( block ) { - case IRAM0_UNI_BLOCK_0: + switch (block) { + case IRAM0_SRAM_UNI_BLOCK_0: *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_W; *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_R; *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_F; break; - case IRAM0_UNI_BLOCK_1: + case IRAM0_SRAM_UNI_BLOCK_1: *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_W; *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_R; *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_F; break; - case IRAM0_UNI_BLOCK_2: + case IRAM0_SRAM_UNI_BLOCK_2: *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_W; *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_R; *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_F; break; - case IRAM0_UNI_BLOCK_3: + case IRAM0_SRAM_UNI_BLOCK_3: *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_W; *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_R; *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_F; @@ -262,33 +276,33 @@ static inline void esp_memprot_iram0_get_uni_block_sgnf_bits(uint32_t block, uin } } -static inline uint32_t esp_memprot_iram0_get_perm_uni_reg(void) +static inline uint32_t esp_memprot_iram0_sram_get_perm_uni_reg(void) { return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_1_REG); } -static inline uint32_t esp_memprot_iram0_get_perm_split_reg(void) +static inline uint32_t esp_memprot_iram0_sram_get_perm_split_reg(void) { return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_2_REG); } -static inline void esp_memprot_iram0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +static inline void esp_memprot_iram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) { uint32_t addr = (uint32_t)split_addr; - assert( addr <= IRAM0_SPL_BLOCK_HIGH ); + assert(addr <= IRAM0_SRAM_SPL_BLOCK_HIGH); //find possible split.address in low region blocks int uni_blocks_low = -1; - if ( addr >= IRAM0_UNI_BLOCK_0_LOW ) { + if (addr >= IRAM0_SRAM_UNI_BLOCK_0_LOW) { uni_blocks_low++; } - if ( addr >= IRAM0_UNI_BLOCK_1_LOW ) { + if (addr >= IRAM0_SRAM_UNI_BLOCK_1_LOW) { uni_blocks_low++; } - if ( addr >= IRAM0_UNI_BLOCK_2_LOW ) { + if (addr >= IRAM0_SRAM_UNI_BLOCK_2_LOW) { uni_blocks_low++; } - if ( addr >= IRAM0_UNI_BLOCK_3_LOW ) { + if (addr >= IRAM0_SRAM_UNI_BLOCK_3_LOW) { uni_blocks_low++; } @@ -296,9 +310,9 @@ static inline void esp_memprot_iram0_set_prot(uint32_t *split_addr, bool lw, boo uint32_t write_bit, read_bit, exec_bit; uint32_t uni_block_perm = 0; - for ( size_t x = 0; x < IRAM0_TOTAL_UNI_BLOCKS; x++ ) { - esp_memprot_iram0_get_uni_block_sgnf_bits(x, &write_bit, &read_bit, &exec_bit); - if ( x <= uni_blocks_low ) { + for (size_t x = 0; x < IRAM0_SRAM_TOTAL_UNI_BLOCKS; x++) { + esp_memprot_iram0_sram_get_uni_block_sgnf_bits(x, &write_bit, &read_bit, &exec_bit); + if (x <= uni_blocks_low) { if (lw) { uni_block_perm |= write_bit; } @@ -324,85 +338,175 @@ static inline void esp_memprot_iram0_set_prot(uint32_t *split_addr, bool lw, boo //if splt.ddr not set yet, do required normalization to make the addr writeble into splt.mgmt cfg register uint32_t reg_split_addr = 0; - if ( addr >= IRAM0_SPL_BLOCK_LOW ) { + if (addr >= IRAM0_SRAM_SPL_BLOCK_LOW) { - //split Address must be WORD aligned + //[16:0] reg_split_addr = addr >> 2; assert(addr == (reg_split_addr << 2)); - - //use only 17 signf.bits as the cropped parts are constant for whole section (bits [16:0]) - reg_split_addr = (reg_split_addr << DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S) & DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_M; + reg_split_addr &= DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_M; } //prepare high & low permission mask (bits: [22:20] high range, [19:17] low range) uint32_t permission_mask = 0; - if ( lw ) { + if (lw) { permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_L_W; } - if ( lr ) { + if (lr) { permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_L_R; } - if ( lx ) { + if (lx) { permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_L_F; } - if ( hw ) { + if (hw) { permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_H_W; } - if ( hr ) { + if (hr) { permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_H_R; } - if ( hx ) { + if (hx) { permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_H_F; } - //write both cfg. registers - DPORT_WRITE_PERI_REG( DPORT_PMS_PRO_IRAM0_1_REG, uni_block_perm ); - DPORT_WRITE_PERI_REG( DPORT_PMS_PRO_IRAM0_2_REG, reg_split_addr | permission_mask ); + //write IRAM SRAM uni & splt cfg. registers + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_1_REG, uni_block_perm); + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_2_REG, (uint32_t)(reg_split_addr | permission_mask)); } -static inline void esp_memprot_iram0_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) +static inline void esp_memprot_iram0_sram_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) { - *lw = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_W ); - *lr = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_R ); - *lx = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_F ); - *hw = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_W ); - *hr = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_R ); - *hx = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F ); + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_R); + *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_F); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_R); + *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F); } +static inline void esp_memprot_iram0_sram_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_iram0_sram_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_W, hw ? 1 : 0); +} + +static inline void esp_memprot_iram0_sram_set_exec_perm(bool lx, bool hx) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_F, lx ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F, hx ? 1 : 0); +} + + /** - * === DRAM0 ==== + * ======================================================================================== + * === IRAM0 RTC FAST + * ======================================================================================== */ +#define IRAM0_RTCFAST_ADDRESS_LOW 0x40070000 +#define IRAM0_RTCFAST_ADDRESS_HIGH 0x40071FFF +#define IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x40070000 //RTCFAST faulting address high bits (31:22, constant) -#define DRAM0_TOTAL_UNI_BLOCKS 4 -#define DRAM0_UNI_BLOCK_0 0 -#define DRAM0_UNI_BLOCK_1 1 -#define DRAM0_UNI_BLOCK_2 2 -#define DRAM0_UNI_BLOCK_3 3 -#define DRAM0_SPL_BLOCK_BASE 0x3FFB0000 +static inline uint32_t *esp_memprot_iram0_rtcfast_get_fault_address(void) +{ + uint32_t status_bits = esp_memprot_iram0_get_fault_reg(); + return (uint32_t *)((status_bits & IRAM0_INTR_ST_FAULTADDR_M) | IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI); +} -//unified management (SRAM blocks 0-3) -#define DRAM0_UNI_BLOCK_0_LOW 0x3FFB0000 -#define DRAM0_UNI_BLOCK_0_HIGH 0x3FFB1FFF -#define DRAM0_UNI_BLOCK_1_LOW 0x3FFB2000 -#define DRAM0_UNI_BLOCK_1_HIGH 0x3FFB3FFF -#define DRAM0_UNI_BLOCK_2_LOW 0x3FFB4000 -#define DRAM0_UNI_BLOCK_2_HIGH 0x3FFB5FFF -#define DRAM0_UNI_BLOCK_3_LOW 0x3FFB6000 -#define DRAM0_UNI_BLOCK_3_HIGH 0x3FFB7FFF +static inline bool esp_memprot_iram0_rtcfast_is_intr_mine(void) +{ + if (esp_memprot_iram0_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_iram0_rtcfast_get_fault_address(); + return (uint32_t)faulting_address >= IRAM0_RTCFAST_ADDRESS_LOW && (uint32_t)faulting_address <= IRAM0_RTCFAST_ADDRESS_HIGH; + } + return false; +} -//split management (SRAM blocks 4-21) -#define DRAM0_SPL_BLOCK_LOW 0x3FFB8000 //block 4 low -#define DRAM0_SPL_BLOCK_HIGH 0x3FFFFFFF //block 21 high -#define DRAM0_SPLTADDR_MIN 0x3FFC0000 //block 6 low - minimum splitting address +static inline uint32_t esp_memprot_iram0_rtcfast_get_perm_split_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_3_REG); +} +static inline void esp_memprot_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +{ + uint32_t addr = (uint32_t)split_addr; + + //if splt.ddr not set yet, do required normalization to make the addr writeble into splt.mgmt cfg register + uint32_t reg_split_addr = 0; + + //[10:0] + reg_split_addr = addr >> 2; + assert(addr == (reg_split_addr << 2)); + reg_split_addr &= DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_M; + + //prepare high & low permission mask (bits: [16:14] high range, [13:11] low range) + uint32_t permission_mask = 0; + if (lw) { + permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_L_W; + } + if (lr) { + permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_L_R; + } + if (lx) { + permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_L_F; + } + if (hw) { + permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_H_W; + } + if (hr) { + permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_H_R; + } + if (hx) { + permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_H_F; + } + + //write IRAM0 RTCFAST cfg register + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_3_REG, reg_split_addr | permission_mask); +} + +static inline void esp_memprot_iram0_rtcfast_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) +{ + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_R); + *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_F); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_R); + *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_F); +} + +static inline void esp_memprot_iram0_rtcfast_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_iram0_rtcfast_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_W, hw ? 1 : 0); +} + +static inline void esp_memprot_iram0_rtcfast_set_exec_perm(bool lx, bool hx) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_F, lx ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_F, hx ? 1 : 0); +} + + +/** + * ======================================================================================== + * === DRAM0 common + * ======================================================================================== + */ //DRAM0 interrupt status bitmasks -#define DRAM0_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg) -#define DRAM0_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address) -#define DRAM0_INTR_ST_FAULTADDR_HI 0x3FF00000 //(high nonsignificant bits 31:22 of the faulting address - constant) -#define DRAM0_INTR_ST_OP_RW_BIT BIT(4) //read: 0, write: 1 -#define DRAM0_INTR_ST_OP_ATOMIC_BIT BIT(5) //non-atomic: 0, atomic: 1 +#define DRAM0_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg) +#define DRAM0_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address) +#define DRAM0_INTR_ST_OP_RW_BIT BIT(4) //read: 0, write: 1 +#define DRAM0_INTR_ST_OP_ATOMIC_BIT BIT(5) //non-atomic: 0, atomic: 1 static inline uint32_t esp_memprot_dram0_get_intr_source_num(void) @@ -412,10 +516,10 @@ static inline uint32_t esp_memprot_dram0_get_intr_source_num(void) static inline void esp_memprot_dram0_intr_ena(bool enable) { - if ( enable ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN ); + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN); } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN ); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN); } } @@ -444,91 +548,10 @@ static inline uint32_t esp_memprot_dram0_get_intr_clr_bit(void) return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR); } -static inline uint32_t esp_memprot_dram0_get_lock_bit(void) +//lock resets automatically on CPU restart +static inline void esp_memprot_dram0_set_lock(void) { - return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_0_REG, DPORT_PMS_PRO_DRAM0_LOCK); -} - -static inline void esp_memprot_dram0_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit) -{ - assert(block < DRAM0_TOTAL_UNI_BLOCKS); - - switch ( block ) { - case DRAM0_UNI_BLOCK_0: - *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_0_W; - *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_0_R; - break; - case DRAM0_UNI_BLOCK_1: - *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_1_W; - *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_1_R; - break; - case DRAM0_UNI_BLOCK_2: - *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_2_W; - *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_2_R; - break; - case DRAM0_UNI_BLOCK_3: - *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_3_W; - *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_3_R; - break; - default: - abort(); - } -} - -static inline void esp_memprot_dram0_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm) -{ - assert(block < DRAM0_TOTAL_UNI_BLOCKS); - - uint32_t write_bit, read_bit; - esp_memprot_dram0_get_uni_block_sgnf_bits(block, &write_bit, &read_bit); - - if ( write_perm ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_1_REG, write_bit ); - } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_1_REG, write_bit ); - } - - if ( read_perm ) { - DPORT_SET_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_1_REG, read_bit ); - } else { - DPORT_CLEAR_PERI_REG_MASK( DPORT_PMS_PRO_DRAM0_1_REG, read_bit ); - } -} - -static inline uint32_t esp_memprot_dram0_get_uni_block_read_bit(uint32_t block) -{ - assert(block < DRAM0_TOTAL_UNI_BLOCKS); - - switch ( block ) { - case DRAM0_UNI_BLOCK_0: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_0_R ); - case DRAM0_UNI_BLOCK_1: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_1_R ); - case DRAM0_UNI_BLOCK_2: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_2_R ); - case DRAM0_UNI_BLOCK_3: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_3_R ); - default: - abort(); - } -} - -static inline uint32_t esp_memprot_dram0_get_uni_block_write_bit(uint32_t block) -{ - assert(block < DRAM0_TOTAL_UNI_BLOCKS); - - switch ( block ) { - case DRAM0_UNI_BLOCK_0: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_0_W ); - case DRAM0_UNI_BLOCK_1: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_1_W ); - case DRAM0_UNI_BLOCK_2: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_2_W ); - case DRAM0_UNI_BLOCK_3: - return DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_3_W ); - default: - abort(); - } + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_0_REG, DPORT_PMS_PRO_DRAM0_LOCK); } static inline uint32_t esp_memprot_dram0_get_lock_reg(void) @@ -536,18 +559,12 @@ static inline uint32_t esp_memprot_dram0_get_lock_reg(void) return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_0_REG); } -//lock resets automatically on CPU restart -static inline void esp_memprot_dram0_set_lock(void) +static inline uint32_t esp_memprot_dram0_get_lock_bit(void) { - DPORT_WRITE_PERI_REG( DPORT_PMS_PRO_DRAM0_0_REG, DPORT_PMS_PRO_DRAM0_LOCK); + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_0_REG, DPORT_PMS_PRO_DRAM0_LOCK); } -static inline uint32_t esp_memprot_dram0_get_perm_reg(void) -{ - return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG); -} - -static inline uint32_t esp_memprot_dram0_get_ena_reg(void) +static inline uint32_t esp_memprot_dram0_get_conf_reg(void) { return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_3_REG); } @@ -557,44 +574,169 @@ static inline uint32_t esp_memprot_dram0_get_fault_reg(void) return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_4_REG); } -static inline void esp_memprot_dram0_get_fault_status(uint32_t **faulting_address, uint32_t *op_type, uint32_t *op_subtype) +static inline void esp_memprot_dram0_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype) { uint32_t status_bits = esp_memprot_dram0_get_fault_reg(); - - uint32_t fault_addr = (status_bits & DRAM0_INTR_ST_FAULTADDR_M) >> DRAM0_INTR_ST_FAULTADDR_S; - *faulting_address = (uint32_t *)(fault_addr | DRAM0_INTR_ST_FAULTADDR_HI); - - *op_type = (uint32_t)status_bits & DRAM0_INTR_ST_OP_RW_BIT; - *op_subtype = (uint32_t)status_bits & DRAM0_INTR_ST_OP_ATOMIC_BIT; + *op_type = status_bits & DRAM0_INTR_ST_OP_RW_BIT; + *op_subtype = status_bits & DRAM0_INTR_ST_OP_ATOMIC_BIT; } -static inline void esp_memprot_dram0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) + +/** + * ======================================================================================== + * === DRAM0 SRAM + * ======================================================================================== + */ +#define DRAM0_SRAM_ADDRESS_LOW 0x3FFB0000 +#define DRAM0_SRAM_ADDRESS_HIGH 0x3FFFFFFF + +#define DRAM0_SRAM_TOTAL_UNI_BLOCKS 4 +#define DRAM0_SRAM_UNI_BLOCK_0 0 +#define DRAM0_SRAM_UNI_BLOCK_1 1 +#define DRAM0_SRAM_UNI_BLOCK_2 2 +#define DRAM0_SRAM_UNI_BLOCK_3 3 + +//unified management (SRAM blocks 0-3) +#define DRAM0_SRAM_UNI_BLOCK_0_LOW 0x3FFB0000 +#define DRAM0_SRAM_UNI_BLOCK_1_LOW 0x3FFB2000 +#define DRAM0_SRAM_UNI_BLOCK_2_LOW 0x3FFB4000 +#define DRAM0_SRAM_UNI_BLOCK_3_LOW 0x3FFB6000 + +//split management (SRAM blocks 4-21) +#define DRAM0_SRAM_SPL_BLOCK_HIGH 0x3FFFFFFF //block 21 high +#define DRAM0_SRAM_INTR_ST_FAULTADDR_HI 0x3FF00000 //SRAM high bits 31:22 of the faulting address - constant + + +static inline uint32_t *esp_memprot_dram0_sram_get_fault_address(void) +{ + uint32_t status_bits = esp_memprot_dram0_get_fault_reg(); + return (uint32_t *)(((status_bits & DRAM0_INTR_ST_FAULTADDR_M) >> DRAM0_INTR_ST_FAULTADDR_S) | DRAM0_SRAM_INTR_ST_FAULTADDR_HI); +} + +static inline bool esp_memprot_dram0_sram_is_intr_mine(void) +{ + if (esp_memprot_dram0_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_dram0_sram_get_fault_address(); + return (uint32_t)faulting_address >= DRAM0_SRAM_ADDRESS_LOW && (uint32_t)faulting_address <= DRAM0_SRAM_ADDRESS_HIGH; + } + return false; +} + +static inline void esp_memprot_dram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit) +{ + assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS); + + switch (block) { + case DRAM0_SRAM_UNI_BLOCK_0: + *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_0_W; + *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_0_R; + break; + case DRAM0_SRAM_UNI_BLOCK_1: + *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_1_W; + *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_1_R; + break; + case DRAM0_SRAM_UNI_BLOCK_2: + *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_2_W; + *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_2_R; + break; + case DRAM0_SRAM_UNI_BLOCK_3: + *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_3_W; + *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_3_R; + break; + default: + abort(); + } +} + +static inline void esp_memprot_dram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm) +{ + assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS); + + uint32_t write_bit, read_bit; + esp_memprot_dram0_sram_get_uni_block_sgnf_bits(block, &write_bit, &read_bit); + + if (write_perm) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, write_bit); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, write_bit); + } + + if (read_perm) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, read_bit); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, read_bit); + } +} + +static inline uint32_t esp_memprot_dram0_sram_get_uni_block_read_bit(uint32_t block) +{ + assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS); + + switch (block) { + case DRAM0_SRAM_UNI_BLOCK_0: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_0_R); + case DRAM0_SRAM_UNI_BLOCK_1: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_1_R); + case DRAM0_SRAM_UNI_BLOCK_2: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_2_R); + case DRAM0_SRAM_UNI_BLOCK_3: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_3_R); + default: + abort(); + } +} + +static inline uint32_t esp_memprot_dram0_sram_get_uni_block_write_bit(uint32_t block) +{ + assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS); + + switch (block) { + case DRAM0_SRAM_UNI_BLOCK_0: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_0_W); + case DRAM0_SRAM_UNI_BLOCK_1: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_1_W); + case DRAM0_SRAM_UNI_BLOCK_2: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_2_W); + case DRAM0_SRAM_UNI_BLOCK_3: + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_3_W); + default: + abort(); + } +} + +//DRAM0 has both unified blocks and split address configured in 1 register +static inline uint32_t esp_memprot_dram0_sram_get_perm_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG); +} + +static inline void esp_memprot_dram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) { uint32_t addr = (uint32_t)split_addr; - //low boundary check provided by LD script. see comment in esp_memprot_iram0_set_prot() - assert( addr <= DRAM0_SPL_BLOCK_HIGH ); + //low boundary check provided by LD script. see comment in esp_memprot_iram0_sram_set_prot() + assert( addr <= DRAM0_SRAM_SPL_BLOCK_HIGH ); //set low region int uni_blocks_low = -1; - if ( addr >= DRAM0_UNI_BLOCK_0_LOW ) { + if (addr >= DRAM0_SRAM_UNI_BLOCK_0_LOW) { uni_blocks_low++; } - if ( addr >= DRAM0_UNI_BLOCK_1_LOW ) { + if (addr >= DRAM0_SRAM_UNI_BLOCK_1_LOW) { uni_blocks_low++; } - if ( addr >= DRAM0_UNI_BLOCK_2_LOW ) { + if (addr >= DRAM0_SRAM_UNI_BLOCK_2_LOW) { uni_blocks_low++; } - if ( addr >= DRAM0_UNI_BLOCK_3_LOW ) { + if (addr >= DRAM0_SRAM_UNI_BLOCK_3_LOW) { uni_blocks_low++; } //set unified mgmt region uint32_t write_bit, read_bit, uni_block_perm = 0; - for ( size_t x = 0; x < DRAM0_TOTAL_UNI_BLOCKS; x++ ) { - esp_memprot_dram0_get_uni_block_sgnf_bits(x, &write_bit, &read_bit); - if ( x <= uni_blocks_low ) { + for (size_t x = 0; x < DRAM0_SRAM_TOTAL_UNI_BLOCKS; x++) { + esp_memprot_dram0_sram_get_uni_block_sgnf_bits(x, &write_bit, &read_bit); + if (x <= uni_blocks_low) { if (lw) { uni_block_perm |= write_bit; } @@ -611,12 +753,10 @@ static inline void esp_memprot_dram0_set_prot(uint32_t *split_addr, bool lw, boo } } - //check split address is WORD aligned + //[24:8] uint32_t reg_split_addr = addr >> 2; assert(addr == (reg_split_addr << 2)); - - //shift aligned split address to proper bit offset - reg_split_addr = (reg_split_addr << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S) & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_M; + reg_split_addr = (reg_split_addr & DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_V) << DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S; //prepare high & low permission mask uint32_t permission_mask = 0; @@ -633,18 +773,108 @@ static inline void esp_memprot_dram0_set_prot(uint32_t *split_addr, bool lw, boo permission_mask |= DPORT_PMS_PRO_DRAM0_SRAM_4_H_R; } - //write configuration to DPORT_PMS_PRO_DRAM0_1_REG + //write DRAM0 SRAM cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG, reg_split_addr | permission_mask | uni_block_perm); } -static inline void esp_memprot_dram0_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) +static inline void esp_memprot_dram0_sram_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) { - *lw = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_W ); - *lr = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_R ); - *hw = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W ); - *hr = DPORT_REG_GET_FIELD( DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_R ); + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_R); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_R); } +static inline void esp_memprot_dram0_sram_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_dram0_sram_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W, hw ? 1 : 0); +} + + +/** + * ======================================================================================== + * === DRAM0 RTC FAST + * ======================================================================================== + */ +#define DRAM0_RTCFAST_ADDRESS_LOW 0x3FF9E000 +#define DRAM0_RTCFAST_ADDRESS_HIGH 0x3FF9FFFF +#define DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI 0x3FF00000 //RTCFAST high bits 31:22 of the faulting address - constant + + +static inline uint32_t *esp_memprot_dram0_rtcfast_get_fault_address(void) +{ + uint32_t status_bits = esp_memprot_dram0_get_fault_reg(); + return (uint32_t *)(((status_bits & DRAM0_INTR_ST_FAULTADDR_M) >> DRAM0_INTR_ST_FAULTADDR_S) | DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI); +} + +static inline bool esp_memprot_dram0_rtcfast_is_intr_mine(void) +{ + if (esp_memprot_dram0_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_dram0_rtcfast_get_fault_address(); + return (uint32_t)faulting_address >= DRAM0_RTCFAST_ADDRESS_LOW && (uint32_t)faulting_address <= DRAM0_RTCFAST_ADDRESS_HIGH; + } + return false; +} + +static inline void esp_memprot_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) +{ + uint32_t addr = (uint32_t)split_addr; + + //[10:0] + uint32_t reg_split_addr = addr >> 2; + assert(addr == (reg_split_addr << 2)); + reg_split_addr &= DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_M; + + //prepare high & low permission mask + uint32_t permission_mask = 0; + if (lw) { + permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_L_W; + } + if (lr) { + permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_L_R; + } + if (hw) { + permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_H_W; + } + if (hr) { + permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_H_R; + } + + //write DRAM0 RTC FAST cfg register + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_2_REG, reg_split_addr | permission_mask); +} + +static inline void esp_memprot_dram0_rtcfast_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) +{ + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_R); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_R); +} + +static inline uint32_t esp_memprot_dram0_rtcfast_get_perm_split_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_2_REG); +} + +static inline void esp_memprot_dram0_rtcfast_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_dram0_rtcfast_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_W, hw ? 1 : 0); +} #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/sha_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/sha_ll.h new file mode 100644 index 00000000..0a5e1b6c --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/sha_ll.h @@ -0,0 +1,173 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/hwcrypto_reg.h" +#include "hal/sha_types.h" +#include "soc/dport_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Start a new SHA block conversions (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_block(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_START_REG, 1); +} + +/** + * @brief Continue a SHA block conversion (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_block(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_CONTINUE_REG, 1); +} + +/** + * @brief Start a new SHA message conversion using DMA (no initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_start_dma(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_DMA_START_REG, 1); +} + +/** + * @brief Continue a SHA message conversion using DMA (initial hash in HW) + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_continue_dma(esp_sha_type sha_type) +{ + REG_WRITE(SHA_MODE_REG, sha_type); + REG_WRITE(SHA_DMA_CONTINUE_REG, 1); +} + +/** + * @brief Load the current hash digest to digest register + * + * @note Happens automatically on ESP32S2 + * + * @param sha_type The SHA algorithm type + */ +static inline void sha_ll_load(esp_sha_type sha_type) +{ +} + +/** + * @brief Sets the number of message blocks to be hashed + * + * @note DMA operation only + * + * @param num_blocks Number of message blocks to process + */ +static inline void sha_ll_set_block_num(size_t num_blocks) +{ + REG_WRITE(SHA_BLOCK_NUM_REG, num_blocks); +} + +/** + * @brief Checks if the SHA engine is currently busy hashing a block + * + * @return true SHA engine busy + * @return false SHA engine idle + */ +static inline bool sha_ll_busy(void) +{ + return REG_READ(SHA_BUSY_REG); +} + +/** + * @brief Write a text (message) block to the SHA engine + * + * @param input_text Input buffer to be written to the SHA engine + * @param block_word_len Number of words in block + */ +static inline void sha_ll_fill_text_block(const void *input_text, size_t block_word_len) +{ + uint32_t *data_words = (uint32_t *)input_text; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_TEXT_BASE); + + for (int i = 0; i < block_word_len; i++) { + REG_WRITE(®_addr_buf[i], data_words[i]); + } +} + +/** + * @brief Read the message digest from the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Buffer that message digest will be written to + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_read_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + + esp_dport_access_read_buffer(digest_state_words, SHA_H_BASE, digest_word_len); +} + +/** + * @brief Write the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + * @param digest_word_len Length of the message digest + */ +static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state, size_t digest_word_len) +{ + uint32_t *digest_state_words = (uint32_t *)digest_state; + uint32_t *reg_addr_buf = (uint32_t *)(SHA_H_BASE); + + for (int i = 0; i < digest_word_len; i++) { + REG_WRITE(®_addr_buf[i], digest_state_words[i]); + } +} + +/** + * @brief Sets SHA512_t T_string parameter + * + * @param t_string T_string parameter + */ +static inline void sha_ll_t_string_set(uint32_t t_string) +{ + REG_WRITE(SHA_T_STRING_REG, t_string); +} + +/** + * @brief Sets SHA512_t T_string parameter's length + * + * @param t_len T_string parameter length + */ +static inline void sha_ll_t_len_set(uint8_t t_len) +{ + REG_WRITE(SHA_T_LENGTH_REG, t_len); +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spi_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spi_ll.h index ca8f685c..0506ed6b 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spi_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spi_ll.h @@ -35,7 +35,7 @@ extern "C" { #endif /// Registers to reset during initialization. Don't use in app. -#define SPI_LL_RST_MASK (SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST) +#define SPI_LL_DMA_FIFO_RST_MASK (SPI_AHBM_RST | SPI_AHBM_FIFO_RST) /// Interrupt not used. Don't use in app. #define SPI_LL_UNUSED_INT_MASK (SPI_INT_TRANS_DONE_EN | SPI_INT_WR_DMA_DONE_EN | SPI_INT_RD_DMA_DONE_EN | SPI_INT_WR_BUF_DONE_EN | SPI_INT_RD_BUF_DONE_EN) /// Swap the bit order to its correct place to send @@ -50,6 +50,9 @@ extern "C" { */ typedef uint32_t spi_ll_clock_val_t; +//On ESP32-S2 and earlier chips, DMA registers are part of SPI registers. So set the registers of SPI peripheral to control DMA. +typedef spi_dev_t spi_dma_dev_t; + /** IO modes supported by the master. */ typedef enum { SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases @@ -59,12 +62,6 @@ typedef enum { SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases } spi_ll_io_mode_t; -/// Interrupt type for different working pattern -typedef enum { - SPI_LL_INT_TYPE_NORMAL = 0, ///< Typical pattern, only wait for trans done - SPI_LL_INT_TYPE_SEG = 1, ///< Wait for DMA signals -} spi_ll_slave_intr_type; - /// Type definition of all supported interrupts typedef enum { SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done @@ -104,11 +101,6 @@ FLAG_ATTR(spi_ll_trans_len_cond_t) */ static inline void spi_ll_master_init(spi_dev_t *hw) { - //Reset DMA - hw->dma_conf.val |= SPI_LL_RST_MASK; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~SPI_LL_RST_MASK; //Reset timing hw->ctrl2.val = 0; @@ -137,52 +129,26 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) hw->user.doutdin = 1; //we only support full duplex hw->user.sio = 0; hw->slave.slave_mode = 1; - hw->dma_conf.val |= SPI_LL_RST_MASK; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~SPI_LL_RST_MASK; hw->slave.soft_reset = 1; hw->slave.soft_reset = 0; //use all 64 bytes of the buffer hw->user.usr_miso_highpart = 0; hw->user.usr_mosi_highpart = 0; - //by default seg mode is disabled - hw->dma_conf.dma_continue = 0; //Disable unneeded ints hw->slave.val &= ~SPI_LL_UNUSED_INT_MASK; - hw->dma_int_ena.val = 0; } -static inline void spi_ll_slave_hd_init(spi_dev_t* hw) +static inline void spi_ll_slave_hd_init(spi_dev_t *hw) { hw->clock.val = 0; hw->user.val = 0; hw->ctrl.val = 0; hw->user.sio = 0; - //hw->user.tx_start_bit = 7; hw->slave.soft_reset = 1; hw->slave.soft_reset = 0; - //Reset DMA - hw->dma_conf.val |= SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~(SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST); - - if (hw == &GPSPI2) { - hw->dma_conf.out_data_burst_en = 1; - } else { - hw->dma_conf.out_data_burst_en = 0; - } - hw->dma_conf.outdscr_burst_en = 1; - hw->dma_conf.indscr_burst_en = 1; - - hw->dma_conf.rx_eof_en = 0; - hw->dma_conf.out_eof_mode = 1; - hw->dma_conf.out_auto_wrback = 1; - hw->user.doutdin = 0; //we only support full duplex hw->slave.slave_mode = 1; } @@ -221,103 +187,83 @@ static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) return hw->cmd.val; } -/*------------------------------------------------------------------------------ - * DMA - *----------------------------------------------------------------------------*/ /** - * Reset TX and RX DMAs. + * Reset SPI CPU FIFO * * @param hw Beginning address of the peripheral registers. */ -static inline void spi_ll_reset_dma(spi_dev_t *hw) +static inline void spi_ll_cpu_fifo_reset(spi_dev_t *hw) { - //Reset DMA peripheral - hw->dma_conf.val |= SPI_LL_RST_MASK; - hw->dma_out_link.start = 0; - hw->dma_in_link.start = 0; - hw->dma_conf.val &= ~SPI_LL_RST_MASK; - hw->dma_conf.out_data_burst_en = 0; - hw->dma_conf.indscr_burst_en = 1; - hw->dma_conf.outdscr_burst_en = 1; - hw->dma_in_link.dma_rx_ena = 0; - assert(hw->dma_in_link.dma_rx_ena == 0); + //This is not used in esp32s2 } /** - * Start RX DMA. + * Reset SPI DMA FIFO * * @param hw Beginning address of the peripheral registers. - * @param addr Address of the beginning DMA descriptor. */ -static inline void spi_ll_rxdma_start(spi_dev_t *hw, lldesc_t *addr) +static inline void spi_ll_dma_fifo_reset(spi_dev_t *hw) { - hw->dma_in_link.addr = (int) addr & 0xFFFFF; - hw->dma_in_link.start = 1; + hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK; + hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK; } /** - * Start TX DMA. - * + * Clear in fifo full error + * * @param hw Beginning address of the peripheral registers. - * @param addr Address of the beginning DMA descriptor. */ -static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr) +static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - hw->dma_out_link.addr = (int) addr & 0xFFFFF; - hw->dma_out_link.start = 1; -} - -static inline void spi_ll_rxdma_reset(spi_dev_t* hw) -{ - hw->dma_conf.in_rst = 1; - hw->dma_conf.in_rst = 0; hw->dma_conf.infifo_full_clr = 1; hw->dma_conf.infifo_full_clr = 0; } -static inline void spi_ll_txdma_reset(spi_dev_t* hw) +/** + * Clear out fifo empty error + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - hw->dma_conf.out_rst = 1; - hw->dma_conf.out_rst = 0; hw->dma_conf.outfifo_empty_clr = 1; hw->dma_conf.outfifo_empty_clr = 0; } -static inline void spi_ll_rxdma_restart(spi_dev_t* hw) +/*------------------------------------------------------------------------------ + * SPI configuration for DMA + *----------------------------------------------------------------------------*/ +/** + * Enable/Disable RX DMA (Peripherals->DMA->RAM) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable) { - hw->dma_in_link.restart = 1; + //This is not used in esp32s2 } -static inline void spi_ll_txdma_restart(spi_dev_t* hw) +/** + * Enable/Disable TX DMA (RAM->DMA->Peripherals) + * + * @param hw Beginning address of the peripheral registers. + * @param enable 1: enable; 2: disable + */ +static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable) { - hw->dma_out_link.restart = 1; + //This is not used in esp32s2 } -static inline void spi_ll_rxdma_disable(spi_dev_t* hw) +/** + * Configuration of OUT EOF flag generation way + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. + */ +static inline void spi_ll_dma_set_out_eof_generation(spi_dma_dev_t *dma_out, bool enable) { - hw->dma_in_link.dma_rx_ena = 0; -} - -static inline void spi_ll_txdma_disable(spi_dev_t* hw) -{ - hw->dma_out_link.dma_tx_ena = 0; - hw->dma_out_link.stop = 1; -} - -static inline void spi_ll_rxdma_clr_err(spi_dev_t* hw) -{ - hw->dma_conf.infifo_full_clr = 1; - hw->dma_conf.infifo_full_clr = 0; -} - -static inline void spi_ll_txdma_clr_err(spi_dev_t* hw) -{ - hw->dma_int_clr.outfifo_empty_err= 1; -} - -static inline bool spi_ll_txdma_get_empty_err(spi_dev_t* hw) -{ - return hw->dma_int_raw.outfifo_empty_err; + dma_out->dma_conf.out_eof_mode = enable; } /*------------------------------------------------------------------------------ @@ -415,7 +361,7 @@ static inline void spi_ll_master_set_pos_cs(spi_dev_t *hw, int cs, uint32_t pos_ if (pos_cs) { hw->misc.master_cs_pol |= (1 << cs); } else { - hw->misc.master_cs_pol &= (1 << cs); + hw->misc.master_cs_pol &= ~(1 << cs); } } @@ -559,7 +505,7 @@ static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_ } } -static inline void spi_ll_slave_set_seg_mode(spi_dev_t* hw, bool seg_trans) +static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { hw->dma_conf.dma_seg_trans_en = seg_trans; hw->dma_conf.rx_eof_en = seg_trans; @@ -590,7 +536,7 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) * @param hw Beginning address of the peripheral registers. * @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``). */ -static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val) +static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val) { hw->clock.val = *(uint32_t *)val; } @@ -784,7 +730,7 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) * Enable/disable the segment transfer feature for the slave. * * @param hw Beginning address of the peripheral registers. - * @param en true to enable, false to disable. + * @param en true to enable, false to disable. */ static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en) { @@ -982,7 +928,7 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof, dma_int_raw.out_eof, dma_int_clr.out_eof=1) \ item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof, dma_int_raw.out_total_eof, dma_int_clr.out_total_eof=1) \ item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \ - item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \ + item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \ item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err=1) \ item(SPI_LL_INTR_WR_DONE, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \ @@ -1047,7 +993,6 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { hw->slave.trans_done = 0; - hw->dma_int_clr.val = UINT32_MAX; } /** @@ -1070,27 +1015,6 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) hw->slave.int_trans_done_en = 1; } -/** - * Set different interrupt types for the slave. - * - * @param hw Beginning address of the peripheral registers. - * @param int_type Interrupt type - */ -static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type) -{ - switch (int_type) { - case SPI_LL_INT_TYPE_SEG: - hw->dma_int_ena.in_suc_eof = 1; - hw->dma_int_ena.out_total_eof = 1; - hw->slave.int_trans_done_en = 0; - break; - default: - hw->dma_int_ena.in_suc_eof = 0; - hw->dma_int_ena.out_total_eof = 0; - hw->slave.int_trans_done_en = 1; - } -} - /*------------------------------------------------------------------------------ * Slave HD *----------------------------------------------------------------------------*/ @@ -1111,6 +1035,157 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw) { return hw->slave1.last_addr; } + +/*------------------------------------------------------------------------------ + * DMA: + * RX DMA (Peripherals->DMA->RAM) + * TX DMA (RAM->DMA->Peripherals) + *----------------------------------------------------------------------------*/ +/** + * Reset RX DMA which stores the data received from a peripheral into RAM. + * + * @param hw Beginning address of the peripheral registers. + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + */ +static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in) +{ + //Reset RX DMA peripheral + dma_in->dma_in_link.dma_rx_ena = 0; + assert(dma_in->dma_in_link.dma_rx_ena == 0); + + dma_in->dma_conf.in_rst = 1; + dma_in->dma_conf.in_rst = 0; +} + +/** + * Start RX DMA. + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param addr Address of the beginning DMA descriptor. + */ +static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, lldesc_t *addr) +{ + dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; + dma_in->dma_in_link.start = 1; +} + +/** + * Enable DMA RX channel burst for data + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_out, bool enable) +{ + //This is not supported in esp32s2 +} + +/** + * Enable DMA TX channel burst for descriptor + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, bool enable) +{ + dma_in->dma_conf.indscr_burst_en = enable; +} + +/** + * Configuration of RX DMA EOF interrupt generation way + * + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param enable 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ +static inline void spi_dma_ll_set_rx_eof_generation(spi_dma_dev_t *dma_in, bool enable) +{ + dma_in->dma_conf.rx_eof_en = enable; +} + +/** + * Reset TX DMA which transmits the data from RAM to a peripheral. + * + * @param hw Beginning address of the peripheral registers. + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + */ +static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out) +{ + //Reset TX DMA peripheral + dma_out->dma_conf.out_rst = 1; + dma_out->dma_conf.out_rst = 0; +} + +/** + * Start TX DMA. + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param addr Address of the beginning DMA descriptor. + */ +static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, lldesc_t *addr) +{ + dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; + dma_out->dma_out_link.start = 1; +} + +/** + * Enable DMA TX channel burst for data + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, bool enable) +{ + dma_out->dma_conf.out_data_burst_en = enable; +} + +/** + * Enable DMA TX channel burst for descriptor + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, bool enable) +{ + dma_out->dma_conf.outdscr_burst_en = enable; +} + +/** + * Enable automatic outlink-writeback + * + * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param enable True to enable, false to disable + */ +static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, bool enable) +{ + dma_out->dma_conf.out_auto_wrback = enable; +} + +static inline void spi_dma_ll_rx_restart(spi_dma_dev_t *dma_in) +{ + dma_in->dma_in_link.restart = 1; +} + +static inline void spi_dma_ll_tx_restart(spi_dma_dev_t *dma_out) +{ + dma_out->dma_out_link.restart = 1; +} + +static inline void spi_dma_ll_rx_disable(spi_dma_dev_t *dma_in) +{ + dma_in->dma_in_link.dma_rx_ena = 0; +} + +static inline void spi_dma_ll_tx_disable(spi_dma_dev_t *dma_out) +{ + dma_out->dma_out_link.dma_tx_ena = 0; + dma_out->dma_out_link.stop = 1; +} + +static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw) +{ + return hw->dma_int_raw.outfifo_empty_err; +} + #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spimem_flash_ll.h b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spimem_flash_ll.h index ced88ab2..90f808aa 100644 --- a/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spimem_flash_ll.h +++ b/tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spimem_flash_ll.h @@ -202,7 +202,7 @@ static inline void spimem_flash_ll_user_start(spi_mem_dev_t *dev) */ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev) { - return dev->fsm.st != 0; + return dev->fsm.st == 0; } /** diff --git a/tools/sdk/esp32s2/include/hal/include/hal/dac_types.h b/tools/sdk/esp32s2/include/hal/include/hal/dac_types.h index b1f4b6fe..1adc511a 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/dac_types.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/dac_types.h @@ -40,7 +40,7 @@ typedef struct { Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */ } dac_cw_config_t; -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 /** * @brief DAC digital controller (DMA mode) work mode. diff --git a/tools/sdk/esp32s2/include/hal/include/hal/dma_types.h b/tools/sdk/esp32s2/include/hal/include/hal/dma_types.h new file mode 100644 index 00000000..1c582361 --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/dma_types.h @@ -0,0 +1,45 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Type of DMA descriptor + * + */ +typedef struct dma_descriptor_s { + struct { + uint32_t size : 12; /*!< Buffer size */ + uint32_t length : 12; /*!< Number of valid bytes in the buffer */ + uint32_t reversed24_27 : 4; /*!< Reserved */ + uint32_t err_eof : 1; /*!< Whether the received buffer contains error */ + uint32_t reserved29 : 1; /*!< Reserved */ + uint32_t suc_eof : 1; /*!< Whether the descriptor is the last one in the link */ + uint32_t owner : 1; /*!< Who is allowed to access the buffer that this descriptor points to */ + } dw0; /*!< Descriptor Word 0 */ + void *buffer; /*!< Pointer to the buffer */ + struct dma_descriptor_s *next; /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */ +} dma_descriptor_t; + +_Static_assert(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occupy 12 bytes in memory"); + +#define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< DMA buffer is allowed to be accessed by CPU */ +#define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< DMA buffer is allowed to be accessed by DMA engine */ +#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ diff --git a/tools/sdk/esp32s2/include/hal/include/hal/gdma_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/gdma_hal.h new file mode 100644 index 00000000..2a67d26a --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/gdma_hal.h @@ -0,0 +1,35 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/gdma_struct.h" + +typedef struct { + gdma_dev_t *dev; +} gdma_hal_context_t; + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/hal/include/hal/i2s_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/i2s_hal.h index cff02d98..49b3c1a0 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/i2s_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/i2s_hal.h @@ -151,25 +151,6 @@ void i2s_hal_set_rx_mode(i2s_hal_context_t *hal, i2s_channel_t ch, i2s_bits_per_ */ void i2s_hal_set_in_link(i2s_hal_context_t *hal, uint32_t rx_eof_num, uint32_t addr); -#if SOC_I2S_SUPPORTS_PDM -/** - * @brief Get I2S tx pdm - * - * @param hal Context of the HAL layer - * @param fp tx pdm fp - * @param fs tx pdm fs - */ -void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, int *fp, int *fs); -#endif - -/** - * @brief Get I2S rx sinc dsr 16 en - * - * @param hal Context of the HAL layer - * @param en 0: disable, 1: enable - */ -#define i2s_hal_get_rx_sinc_dsr_16_en(hal, en) i2s_ll_get_rx_sinc_dsr_16_en((hal)->dev, en) - /** * @brief Set I2S clk div * @@ -241,16 +222,6 @@ void i2s_hal_stop_tx(i2s_hal_context_t *hal); */ void i2s_hal_stop_rx(i2s_hal_context_t *hal); -#if SOC_I2S_SUPPORTS_PDM -/** - * @brief Set I2S pdm rx down sample - * - * @param hal Context of the HAL layer - * @param dsr 0:disable, 1: enable - */ -#define i2s_hal_set_pdm_rx_down_sample(hal, dsr) i2s_ll_set_rx_sinc_dsr_16_en((hal)->dev, dsr) -#endif - /** * @brief Config I2S param * @@ -288,6 +259,42 @@ void i2s_hal_enable_slave_mode(i2s_hal_context_t *hal); */ void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num); +#if SOC_I2S_SUPPORTS_PDM +/** + * @brief Set I2S tx pdm + * + * @param hal Context of the HAL layer + * @param fp tx pdm fp + * @param fs tx pdm fs + */ +void i2s_hal_tx_pdm_cfg(i2s_hal_context_t *hal, uint32_t fp, uint32_t fs); + +/** + * @brief Get I2S tx pdm + * + * @param hal Context of the HAL layer + * @param dsr rx pdm dsr + */ +void i2s_hal_rx_pdm_cfg(i2s_hal_context_t *hal, uint32_t dsr); + +/** + * @brief Get I2S tx pdm configuration + * + * @param hal Context of the HAL layer + * @param fp Pointer to receive tx PDM fp configuration + * @param fs Pointer to receive tx PDM fs configuration + */ +void i2s_hal_get_tx_pdm(i2s_hal_context_t *hal, uint32_t *fp, uint32_t *fs); + +/** + * @brief Get I2S rx pdm configuration + * + * @param hal Context of the HAL layer + * @param dsr rx pdm dsr + */ +void i2s_hal_get_rx_pdm(i2s_hal_context_t *hal, uint32_t *dsr); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/hal/include/hal/interrupt_controller_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/interrupt_controller_hal.h new file mode 100644 index 00000000..ae230c8e --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/interrupt_controller_hal.h @@ -0,0 +1,170 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "hal/interrupt_controller_types.h" +#include "hal/interrupt_controller_ll.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Gets target platform interrupt descriptor table + * + * @return Address of interrupt descriptor table + */ +__attribute__((pure)) const int_desc_t *interrupt_controller_hal_desc_table(void); + +/** + * @brief Gets the interrupt type given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt type + */ +__attribute__((pure)) int_type_t interrupt_controller_hal_desc_type(int interrupt_number); + +/** + * @brief Gets the interrupt level given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt level bitmask + */ +__attribute__((pure)) int interrupt_controller_hal_desc_level(int interrupt_number); + +/** + * @brief Gets the cpu flags given the interrupt number and target cpu. + * + * @param interrupt_number Interrupt number 0 to 31 + * @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1 + * @return flags for that interrupt number + */ +__attribute__((pure)) uint32_t interrupt_controller_hal_desc_flags(int interrupt_number, int cpu_number); + +/** + * @brief Gets the interrupt type given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt type + */ +static inline int_type_t interrupt_controller_hal_get_type(int interrupt_number) +{ + return interrupt_controller_hal_desc_type(interrupt_number); +} + +/** + * @brief Gets the interrupt level given an interrupt number. + * + * @param interrupt_number Interrupt number 0 to 31 + * @return interrupt level bitmask + */ +static inline int interrupt_controller_hal_get_level(int interrupt_number) +{ + return interrupt_controller_hal_desc_level(interrupt_number); +} + +/** + * @brief Gets the cpu flags given the interrupt number and target cpu. + * + * @param interrupt_number Interrupt number 0 to 31 + * @param cpu_number CPU number between 0 and SOC_CPU_CORES_NUM - 1 + * @return flags for that interrupt number + */ +static inline uint32_t interrupt_controller_hal_get_cpu_desc_flags(int interrupt_number, int cpu_number) +{ + return interrupt_controller_hal_desc_flags(interrupt_number, cpu_number); +} + +/** + * @brief enable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be enabled + */ +static inline void interrupt_controller_hal_enable_interrupts(uint32_t mask) +{ + intr_cntrl_ll_enable_interrupts(mask); +} + +/** + * @brief disable interrupts specified by the mask + * + * @param mask bitmask of interrupts that needs to be disabled + */ +static inline void interrupt_controller_hal_disable_interrupts(uint32_t mask) +{ + intr_cntrl_ll_disable_interrupts(mask); +} + +/** + * @brief checks if given interrupt number has a valid handler + * + * @param intr interrupt number ranged from 0 to 31 + * @param cpu cpu number ranged betweeen 0 to SOC_CPU_CORES_NUM - 1 + * @return true for valid handler, false otherwise + */ +static inline bool interrupt_controller_hal_has_handler(int intr, int cpu) +{ + return intr_cntrl_ll_has_handler(intr, cpu); +} + +/** + * @brief sets interrupt handler and optional argument of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * @param handler handler invoked when an interrupt occurs + * @param arg optional argument to pass to the handler + */ +static inline void interrupt_controller_hal_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg) +{ + intr_cntrl_ll_set_int_handler(intr, handler, arg); +} + +/** + * @brief Gets argument passed to handler of a given interrupt number + * + * @param intr interrupt number ranged from 0 to 31 + * + * @return argument used by handler of passed interrupt number + */ +static inline void * interrupt_controller_hal_get_int_handler_arg(uint8_t intr) +{ + return intr_cntrl_ll_get_int_handler_arg(intr); +} + +/** + * @brief Disables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + * @return oldmask where to store old interrupts state + */ +static inline uint32_t interrupt_controller_hal_disable_int_mask(uint32_t newmask) +{ + return intr_cntrl_ll_disable_int_mask(newmask); +} + +/** + * @brief Enables interrupts that are not located in iram + * + * @param newmask mask of interrupts needs to be disabled + */ +static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask) +{ + intr_cntrl_ll_enable_int_mask(newmask); +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/hal/include/hal/interrupt_controller_types.h b/tools/sdk/esp32s2/include/hal/include/hal/interrupt_controller_types.h new file mode 100644 index 00000000..639317f4 --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/interrupt_controller_types.h @@ -0,0 +1,46 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc_caps.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + INTDESC_NORMAL=0, + INTDESC_RESVD, + INTDESC_SPECIAL +} int_desc_flag_t; + +typedef enum { + INTTP_LEVEL=0, + INTTP_EDGE, + INTTP_NA +} int_type_t; + +typedef struct { + int level; + int_type_t type; + int_desc_flag_t cpuflags[SOC_CPU_CORES_NUM]; +} int_desc_t; + +typedef void (*interrupt_handler_t)(void *arg); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/hal/include/hal/rmt_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/rmt_hal.h index ba1cac07..6d44acf9 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/rmt_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/rmt_hal.h @@ -17,6 +17,7 @@ extern "C" { #endif +#include #include "soc/rmt_struct.h" #include "soc/rmt_caps.h" diff --git a/tools/sdk/esp32s2/include/soc/include/hal/rtc_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/rtc_hal.h similarity index 100% rename from tools/sdk/esp32s2/include/soc/include/hal/rtc_hal.h rename to tools/sdk/esp32s2/include/hal/include/hal/rtc_hal.h diff --git a/tools/sdk/esp32s2/include/hal/include/hal/sha_types.h b/tools/sdk/esp32s2/include/hal/include/hal/sha_types.h new file mode 100644 index 00000000..c5038227 --- /dev/null +++ b/tools/sdk/esp32s2/include/hal/include/hal/sha_types.h @@ -0,0 +1,38 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "sdkconfig.h" + +/* Use enum from rom for backwards compatibility */ +#if CONFIG_IDF_TARGET_ESP32 +#include "esp32/rom/sha.h" +typedef enum SHA_TYPE esp_sha_type; +#elif CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/sha.h" +typedef SHA_TYPE esp_sha_type; +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/sha.h" +typedef SHA_TYPE esp_sha_type; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/hal/include/hal/spi_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/spi_hal.h index 6f0aa024..dd5e01df 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/spi_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/spi_hal.h @@ -38,83 +38,115 @@ #include #include "soc/lldesc.h" +/** + * Input parameters to the ``spi_hal_cal_clock_conf`` to calculate the timing configuration + */ +typedef struct { + uint32_t half_duplex; ///< Whether half duplex mode is used, device specific + uint32_t no_compensate; ///< No need to add dummy to compensate the timing, device specific + uint32_t clock_speed_hz; ///< Desired frequency. + uint32_t duty_cycle; ///< Desired duty cycle of SPI clock + uint32_t input_delay_ns; /**< Maximum delay between SPI launch clock and the data to be valid. + * This is used to compensate/calculate the maximum frequency allowed. + * Left 0 if not known. + */ + bool use_gpio; ///< True if the GPIO matrix is used, otherwise false +} spi_hal_timing_param_t; + /** * Timing configuration structure that should be calculated by - * ``spi_hal_setup_clock`` at initialization and hold. Filled into the + * ``spi_hal_cal_clock_conf`` at initialization and hold. Filled into the * ``timing_conf`` member of the context of HAL before setup a device. */ typedef struct { - spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer - int timing_dummy; ///< Extra dummy needed to compensate the timing - int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing + spi_ll_clock_val_t clock_reg; ///< Register value used by the LL layer + int timing_dummy; ///< Extra dummy needed to compensate the timing + int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing } spi_hal_timing_conf_t; +/** + * DMA configuration structure + * Should be set by driver at initialization + */ +typedef struct { + spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address + spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. +} spi_hal_dma_config_t; + +/** + * Transaction configuration structure, this should be assigned by driver each time. + * All these parameters will be updated to the peripheral every transaction. + */ +typedef struct { + uint16_t cmd; ///< Command value to be sent + int cmd_bits; ///< Length (in bits) of the command phase + int addr_bits; ///< Length (in bits) of the address phase + int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended. + int tx_bitlen; ///< TX length, in bits + int rx_bitlen; ///< RX length, in bits + uint64_t addr; ///< Address value to be sent + uint8_t *send_buffer; ///< Data to be sent + uint8_t *rcv_buffer; ///< Buffer to hold the receive data. + spi_ll_io_mode_t io_mode; ///< IO mode of the master +} spi_hal_trans_config_t; + /** * Context that should be maintained by both the driver and the HAL. */ typedef struct { - /* configured by driver at initialization, don't touch */ - spi_dev_t *hw; ///< Beginning address of the peripheral registers. - /* should be configured by driver at initialization */ - lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. - /* - * Device specific, all these parameters will be updated to the peripheral - * only when ``spi_hal_setup_device``. They may not get updated when - * ``spi_hal_setup_trans``. - */ + /* Configured by driver at initialization, don't touch */ + spi_dev_t *hw; ///< Beginning address of the peripheral registers. + spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM (DMA -> RAM). + spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral (RAM -> DMA). + bool dma_enabled; ///< Whether the DMA is enabled, do not update after initialization + spi_hal_dma_config_t dma_config; ///< DMA configuration + + /* Internal parameters, don't touch */ + spi_hal_trans_config_t trans_config; ///< Transaction configuration +} spi_hal_context_t; + +/** + * Device configuration structure, this should be initialised by driver based on different devices respectively. + * All these parameters will be updated to the peripheral only when ``spi_hal_setup_device``. + * They may not get updated when ``spi_hal_setup_trans``. + */ +typedef struct { int mode; ///< SPI mode, device specific int cs_setup; ///< Setup time of CS active edge before the first SPI clock, device specific int cs_hold; ///< Hold time of CS inactive edge after the last SPI clock, device specific int cs_pin_id; ///< CS pin to use, 0-2, otherwise all the CS pins are not used. Device specific - spi_hal_timing_conf_t *timing_conf; /**< Pointer to an structure holding - * the pre-calculated timing configuration for the device at initialization, - * device specific + spi_hal_timing_conf_t timing_conf; /**< This structure holds the pre-calculated timing configuration for the device + * at initialization, device specific */ struct { - uint32_t sio : 1; ///< Whether to use SIO mode, device specific - uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific - uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific - uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific - uint32_t dma_enabled : 1; ///< Whether the DMA is enabled, do not update after initialization - uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific + uint32_t sio : 1; ///< Whether to use SIO mode, device specific + uint32_t half_duplex : 1; ///< Whether half duplex mode is used, device specific + uint32_t tx_lsbfirst : 1; ///< Whether LSB is sent first for TX data, device specific + uint32_t rx_lsbfirst : 1; ///< Whether LSB is received first for RX data, device specific + uint32_t no_compensate : 1; ///< No need to add dummy to compensate the timing, device specific #ifdef SOC_SPI_SUPPORT_AS_CS - uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific + uint32_t as_cs : 1; ///< Whether to toggle the CS while the clock toggles, device specific #endif - uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific + uint32_t positive_cs : 1; ///< Whether the postive CS feature is abled, device specific };//boolean configurations - - /* - * Transaction specific (data), all these parameters will be updated to the - * peripheral every transaction. - */ - uint16_t cmd; ///< Command value to be sent - int cmd_bits; ///< Length (in bits) of the command phase - int addr_bits; ///< Length (in bits) of the address phase - int dummy_bits; ///< Base length (in bits) of the dummy phase. Note when the compensation is enabled, some extra dummy bits may be appended. - int tx_bitlen; ///< TX length, in bits - int rx_bitlen; ///< RX length, in bits - uint64_t addr; ///< Address value to be sent - uint8_t *send_buffer; ///< Data to be sent - uint8_t *rcv_buffer; ///< Buffer to hold the receive data. - spi_ll_io_mode_t io_mode; ///< IO mode of the master - -} spi_hal_context_t; +} spi_hal_dev_config_t; /** * Init the peripheral and the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3). */ -void spi_hal_init(spi_hal_context_t *hal, int host_id); +void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_dma_config_t *hal_dma_config); /** * Deinit the peripheral (and the context if needed). @@ -126,23 +158,28 @@ void spi_hal_deinit(spi_hal_context_t *hal); /** * Setup device-related configurations according to the settings in the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration */ -void spi_hal_setup_device(const spi_hal_context_t *hal); +void spi_hal_setup_device(spi_hal_context_t *hal, const spi_hal_dev_config_t *hal_dev); /** * Setup transaction related configurations according to the settings in the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration + * @param hal_trans Transaction configuration */ -void spi_hal_setup_trans(const spi_hal_context_t *hal); +void spi_hal_setup_trans(spi_hal_context_t *hal, const spi_hal_dev_config_t *hal_dev, const spi_hal_trans_config_t *hal_trans); /** * Prepare the data for the current transaction. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. + * @param hal_dev Device configuration + * @param hal_trans Transaction configuration */ -void spi_hal_prepare_data(const spi_hal_context_t *hal); +void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *hal_dev, const spi_hal_trans_config_t *hal_trans); /** * Trigger start a user-defined transaction. @@ -161,7 +198,7 @@ bool spi_hal_usr_is_done(const spi_hal_context_t *hal); /** * Post transaction operations, mainly fetch data from the buffer. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. */ void spi_hal_fetch_result(const spi_hal_context_t *hal); @@ -173,50 +210,44 @@ void spi_hal_fetch_result(const spi_hal_context_t *hal); * * It is highly suggested to do this at initialization, since it takes long time. * - * @param hal Context of the HAL layer. - * @param speed_hz Desired frequency. - * @param duty_cycle Desired duty cycle of SPI clock - * @param use_gpio true if the GPIO matrix is used, otherwise false - * @param input_delay_ns Maximum delay between SPI launch clock and the data to - * be valid. This is used to compensate/calculate the maximum frequency - * allowed. Left 0 if not known. - * @param out_freq Output of the actual frequency, left NULL if not required. - * @param timing_conf Output of the timing configuration. + * @param timing_param Input parameters to calculate timing configuration + * @param out_freq Output of the actual frequency, left NULL if not required. + * @param timing_conf Output of the timing configuration. * * @return ESP_OK if desired is available, otherwise fail. */ -esp_err_t spi_hal_cal_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf); +esp_err_t spi_hal_cal_clock_conf(const spi_hal_timing_param_t *timing_param, int *out_freq, spi_hal_timing_conf_t *timing_conf); /** * Get the frequency actual used. * - * @param hal Context of the HAL layer. - * @param fapb APB clock frequency. - * @param hz Desired frequencyc. - * @param duty_cycle Desired duty cycle. + * @param hal Context of the HAL layer. + * @param fapb APB clock frequency. + * @param hz Desired frequencyc. + * @param duty_cycle Desired duty cycle. */ int spi_hal_master_cal_clock(int fapb, int hz, int duty_cycle); /** * Get the timing configuration for given parameters. * - * @param eff_clk Actual SPI clock frequency - * @param gpio_is_used true if the GPIO matrix is used, otherwise false. + * @param eff_clk Actual SPI clock frequency + * @param gpio_is_used true if the GPIO matrix is used, otherwise false. * @param input_delay_ns Maximum delay between SPI launch clock and the data to - * be valid. This is used to compensate/calculate the maximum frequency - * allowed. Left 0 if not known. - * @param dummy_n Dummy cycles required to correctly read the data. - * @param miso_delay_n suggested delay on the MISO line, in APB clocks. + * be valid. This is used to compensate/calculate the maximum frequency + * allowed. Left 0 if not known. + * @param dummy_n Dummy cycles required to correctly read the data. + * @param miso_delay_n suggested delay on the MISO line, in APB clocks. */ void spi_hal_cal_timing(int eff_clk, bool gpio_is_used, int input_delay_ns, int *dummy_n, int *miso_delay_n); /** * Get the maximum frequency allowed to read if no compensation is used. * - * @param gpio_is_used true if the GPIO matrix is used, otherwise false. + * @param gpio_is_used true if the GPIO matrix is used, otherwise false. * @param input_delay_ns Maximum delay between SPI launch clock and the data to - * be valid. This is used to compensate/calculate the maximum frequency - * allowed. Left 0 if not known. + * be valid. This is used to compensate/calculate the maximum frequency + * allowed. Left 0 if not known. */ int spi_hal_get_freq_limit(bool gpio_is_used, int input_delay_ns); diff --git a/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hal.h index f8acf2d9..2beccd45 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hal.h @@ -36,32 +36,35 @@ #include "soc/spi_struct.h" #include #include "soc/spi_caps.h" +#include "hal/spi_ll.h" /** * Context that should be maintained by both the driver and the HAL. */ typedef struct { /* configured by driver at initialization, don't touch */ - spi_dev_t *hw; ///< Beginning address of the peripheral registers. + spi_dev_t *hw; ///< Beginning address of the peripheral registers. + spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral. /* should be configured by driver at initialization */ - lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. /* * configurations to be filled after ``spi_slave_hal_init``. Updated to * peripheral registers when ``spi_slave_hal_setup_device`` is called. */ struct { - uint32_t rx_lsbfirst : 1; - uint32_t tx_lsbfirst : 1; - uint32_t use_dma : 1; + uint32_t rx_lsbfirst : 1; + uint32_t tx_lsbfirst : 1; + uint32_t use_dma : 1; }; int mode; @@ -69,21 +72,27 @@ typedef struct { * Transaction specific (data), all these parameters will be updated to the * peripheral every transaction. */ - uint32_t bitlen; ///< Expected maximum length of the transaction, in bits. - const void *tx_buffer; ///< Data to be sent - void *rx_buffer; ///< Buffer to hold the received data. + uint32_t bitlen; ///< Expected maximum length of the transaction, in bits. + const void *tx_buffer; ///< Data to be sent + void *rx_buffer; ///< Buffer to hold the received data. /* Other transaction result after one transaction */ - uint32_t rcv_bitlen; ///< Length of the last transaction, in bits. + uint32_t rcv_bitlen; ///< Length of the last transaction, in bits. } spi_slave_hal_context_t; +typedef struct { + uint32_t host_id; ///< SPI controller ID + spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address + spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address +} spi_slave_hal_config_t; + /** * Init the peripheral and the context. * - * @param hal Context of the HAL layer. + * @param hal Context of the HAL layer. * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3). */ -void spi_slave_hal_init(spi_slave_hal_context_t *hal, int host_id); +void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config); /** * Deinit the peripheral (and the context if needed). diff --git a/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h index 6e13e2c2..e1cb5bc5 100644 --- a/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h +++ b/tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h @@ -22,7 +22,7 @@ * The HAL layer for SPI Slave HD mode, currently only segment mode is supported * * Usage: - * - Firstly, initialize the slave with `slave_hd_hal_init` + * - Firstly, initialize the slave with `spi_slave_hd_hal_init` * * - Event handling: * - (Optional) Call ``spi_slave_hd_hal_enable_event_intr`` to enable the used interrupts @@ -56,54 +56,56 @@ #include "hal/spi_ll.h" #include "hal/spi_types.h" - /// Configuration of the HAL typedef struct { - int host_id; ///< Host ID of the spi peripheral - int spics_io_num; ///< CS GPIO pin for this device - uint8_t mode; ///< SPI mode (0-3) - int command_bits; ///< command field bits, multiples of 8 and at least 8. - int address_bits; ///< address field bits, multiples of 8 and at least 8. - int dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. + uint32_t host_id; ///< Host ID of the spi peripheral + spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address + spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address + uint32_t spics_io_num; ///< CS GPIO pin for this device + uint8_t mode; ///< SPI mode (0-3) + uint32_t command_bits; ///< command field bits, multiples of 8 and at least 8. + uint32_t address_bits; ///< address field bits, multiples of 8 and at least 8. + uint32_t dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. struct { - uint32_t tx_lsbfirst : 1;///< Whether TX data should be sent with LSB first. - uint32_t rx_lsbfirst : 1;///< Whether RX data should be read with LSB first. + uint32_t tx_lsbfirst : 1; ///< Whether TX data should be sent with LSB first. + uint32_t rx_lsbfirst : 1; ///< Whether RX data should be read with LSB first. }; - int dma_chan; ///< The dma channel used. + uint32_t dma_chan; ///< The dma channel used. } spi_slave_hd_hal_config_t; -/// Context of the HAL, initialized by :cpp:func:`slave_hd_hal_init`. +/// Context of the HAL, initialized by :cpp:func:`spi_slave_hd_hal_init`. typedef struct { - spi_dev_t* dev; ///< Beginning address of the peripheral registers. - lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ - lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. - * The amount should be larger than dmadesc_n. The driver should ensure that - * the data to be sent is shorter than the descriptors can hold. - */ + spi_dev_t *dev; ///< Beginning address of the peripheral registers. + spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ /* Internal status used by the HAL implementation, initialized as 0. */ - uint32_t intr_not_triggered; + uint32_t intr_not_triggered; } spi_slave_hd_hal_context_t; - /** * @brief Initialize the hardware and part of the context * - * @param hal Context of the HAL layer - * @param config Configuration of the HAL + * @param hal Context of the HAL layer + * @param hal_config Configuration of the HAL */ -void slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *config); +void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config); /** * @brief Check and clear signal of one event * * @param hal Context of the HAL layer * @param ev Event to check - * @return true if event triggered, otherwise false + * @return True if event triggered, otherwise false */ bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); @@ -116,7 +118,7 @@ bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_eve * * @param hal Context of the HAL layer * @param ev Event to check and disable - * @return true if event triggered, otherwise false + * @return True if event triggered, otherwise false */ bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); @@ -156,7 +158,7 @@ void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, s * @brief Get the length of total received data * * @param hal Context of the HAL layer - * @return The received length + * @return The received length */ int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal); @@ -167,8 +169,8 @@ int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal); * @brief Start the TX DMA operation with the specified buffer * * @param hal Context of the HAL layer - * @param data Buffer of data to send - * @param len Size of the buffer, also the maximum length to send + * @param data Buffer of data to send + * @param len Size of the buffer, also the maximum length to send */ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len); @@ -179,9 +181,9 @@ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size * @brief Read from the shared register buffer * * @param hal Context of the HAL layer - * @param addr Address of the shared regsiter to read - * @param out_data Buffer to store the read data - * @param len Length to read from the shared buffer + * @param addr Address of the shared regsiter to read + * @param out_data Buffer to store the read data + * @param len Length to read from the shared buffer */ void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len); @@ -199,7 +201,7 @@ void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, ui * @brief Get the length of previous transaction. * * @param hal Context of the HAL layer - * @return The length of previous transaction + * @return The length of previous transaction */ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); @@ -207,6 +209,6 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); * @brief Get the address of last transaction * * @param hal Context of the HAL layer - * @return The address of last transaction + * @return The address of last transaction */ int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); diff --git a/tools/sdk/esp32s2/include/idf_test/include/esp32s3/idf_performance_target.h b/tools/sdk/esp32s2/include/idf_test/include/esp32s3/idf_performance_target.h new file mode 100644 index 00000000..269a3c91 --- /dev/null +++ b/tools/sdk/esp32s2/include/idf_test/include/esp32s3/idf_performance_target.h @@ -0,0 +1,33 @@ +#pragma once + +#define IDF_PERFORMANCE_MIN_AES_CBC_THROUGHPUT_MBSEC 14.4 + +// SHA256 hardware throughput at 240MHz, threshold set lower than worst case +#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 19.8 +// esp_sha() time to process 32KB of input data from RAM +#define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 1000 +#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 + +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 18000 +#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 210000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PUBLIC_OP 80000 +#define IDF_PERFORMANCE_MAX_RSA_4096KEY_PRIVATE_OP 1500000 + +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (309*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600 +#endif + +// floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) +#define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 +#define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/tools/sdk/esp32s2/include/log/include/esp_log.h b/tools/sdk/esp32s2/include/log/include/esp_log.h index 1abc70c1..a6ac60ea 100644 --- a/tools/sdk/esp32s2/include/log/include/esp_log.h +++ b/tools/sdk/esp32s2/include/log/include/esp_log.h @@ -23,6 +23,8 @@ #include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif #ifdef __cplusplus diff --git a/tools/sdk/esp32s2/include/lwip/port/esp32/include/netdb.h b/tools/sdk/esp32s2/include/lwip/port/esp32/include/netdb.h index 363154f6..7f5d67a4 100644 --- a/tools/sdk/esp32s2/include/lwip/port/esp32/include/netdb.h +++ b/tools/sdk/esp32s2/include/lwip/port/esp32/include/netdb.h @@ -32,9 +32,17 @@ #include "lwip/netdb.h" +#ifdef __cplusplus +extern "C" { +#endif + #ifdef ESP_PLATFORM int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, char *host, socklen_t hostlen, char *serv, socklen_t servlen, int flags); #endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/aes_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/aes_alt.h index ee6cfed6..f313d508 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/aes_alt.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/aes_alt.h @@ -32,6 +32,8 @@ extern "C" { #include "esp32/aes.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/aes.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/aes.h" #endif typedef esp_aes_context mbedtls_aes_context; diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32/sha.h b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32/sha.h index 2009d198..b99d613c 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32/sha.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32/sha.h @@ -1,4 +1,4 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -11,201 +11,10 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _ESP_SHA_H_ -#define _ESP_SHA_H_ -#include "esp32/rom/sha.h" -#include "esp_types.h" +#pragma once -/** @brief Low-level support functions for the hardware SHA engine - * - * @note If you're looking for a SHA API to use, try mbedtls component - * mbedtls/shaXX.h. That API supports hardware acceleration. - * - * The API in this header provides some building blocks for implementing a - * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). - * - * Some technical details about the hardware SHA engine: - * - * - SHA accelerator engine calculates one digest at a time, per SHA - * algorithm type. It initialises and maintains the digest state - * internally. It is possible to read out an in-progress SHA digest - * state, but it is not possible to restore a SHA digest state - * into the engine. - * - * - The memory block SHA_TEXT_BASE is shared between all SHA digest - * engines, so all engines must be idle before this memory block is - * modified. - * - */ -#ifdef __cplusplus -extern "C" { -#endif - -/* Defined in esp32/rom/sha.h */ -typedef enum SHA_TYPE esp_sha_type; - -/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine - * - * @note For more versatile SHA calculations, where data doesn't need - * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The - * hardware-accelerated mbedTLS implementation is also faster when - * hashing large amounts of data. - * - * @note It is not necessary to lock any SHA hardware before calling - * this function, thread safety is managed internally. - * - * @note If a TLS connection is open then this function may block - * indefinitely waiting for a SHA engine to become available. Use the - * mbedTLS SHA API to avoid this problem. - * - * @param sha_type SHA algorithm to use. - * - * @param input Input data buffer. - * - * @param ilen Length of input data in bytes. - * - * @param output Buffer for output SHA digest. Output is 20 bytes for - * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for - * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. - */ -void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); - -/* @brief Begin to execute a single SHA block operation - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA - * algorithm. - * - * @note Call esp_sha_try_lock_engine() before calling this - * function. Do not call esp_sha_lock_memory_block() beforehand, this - * is done inside the function. - * - * @param sha_type SHA algorithm to use. - * - * @param data_block Pointer to block of data. Block size is - * determined by algorithm (SHA1/SHA2_256 = 64 bytes, - * SHA2_384/SHA2_512 = 128 bytes) - * - * @param is_first_block If this parameter is true, the SHA state will - * be initialised (with the initial state of the given SHA algorithm) - * before the block is calculated. If false, the existing state of the - * SHA engine will be used. - * - * @return As a performance optimisation, this function returns before - * the SHA block operation is complete. Both this function and - * esp_sha_read_state() will automatically wait for any previous - * operation to complete before they begin. If using the SHA registers - * directly in another way, call esp_sha_wait_idle() after calling this - * function but before accessing the SHA registers. - */ -void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block); - -/** @brief Read out the current state of the SHA digest loaded in the engine. - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. - * - * @note Call esp_sha_try_lock_engine() before calling this - * function. Do not call esp_sha_lock_memory_block() beforehand, this - * is done inside the function. - * - * If the SHA suffix padding block has been executed already, the - * value that is read is the SHA digest (in big endian - * format). Otherwise, the value that is read is an interim SHA state. - * - * @note If sha_type is SHA2_384, only 48 bytes of state will be read. - * This is enough for the final SHA2_384 digest, but if you want the - * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead. - * - * @param sha_type SHA algorithm in use. - * - * @param state Pointer to a memory buffer to hold the SHA state. Size - * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512). - * - */ -void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); - -/** - * @brief Obtain exclusive access to a particular SHA engine - * - * @param sha_type Type of SHA engine to use. - * - * Blocks until engine is available. Note: Can block indefinitely - * while a TLS connection is open, suggest using - * esp_sha_try_lock_engine() and failing over to software SHA. - */ -void esp_sha_lock_engine(esp_sha_type sha_type); - -/** - * @brief Try and obtain exclusive access to a particular SHA engine - * - * @param sha_type Type of SHA engine to use. - * - * @return Returns true if the SHA engine is locked for exclusive - * use. Call esp_sha_unlock_sha_engine() when done. Returns false if - * the SHA engine is already in use, caller should use software SHA - * algorithm for this digest. - */ -bool esp_sha_try_lock_engine(esp_sha_type sha_type); - -/** - * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine() - * - * @param sha_type Type of engine to release. - */ -void esp_sha_unlock_engine(esp_sha_type sha_type); - -/** - * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE - * - * This memory block is shared across all the SHA algorithm types. - * - * Caller should have already locked a SHA engine before calling this function. - * - * Note that it is possible to obtain exclusive access to the memory block even - * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle() - * to ensure the SHA engine is not reading from the memory block in hardware. - * - * @note This function enters a critical section. Do not block while holding this lock. - * - * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally. - * - * Call esp_sha_unlock_memory_block() when done. - */ -void esp_sha_lock_memory_block(void); - -/** - * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE - * - * Caller should have already locked a SHA engine before calling this function. - * - * This function releases the critical section entered by esp_sha_lock_memory_block(). - * - * Call following esp_sha_lock_memory_block(). - */ -void esp_sha_unlock_memory_block(void); - -/** @brief Wait for the SHA engine to finish any current operation - * - * @note This function does not ensure exclusive access to any SHA - * engine. Caller should use esp_sha_try_lock_engine() and - * esp_sha_lock_memory_block() as required. - * - * @note Functions declared in this header file wait for SHA engine - * completion automatically, so you don't need to use this API for - * these. However if accessing SHA registers directly, you will need - * to call this before accessing SHA registers if using the - * esp_sha_block() function. - * - * @note This function busy-waits, so wastes CPU resources. - * Best to delay calling until you are about to need it. - * - */ -void esp_sha_wait_idle(void); - -#ifdef __cplusplus -} -#endif - -#endif +#include "sha/sha_parallel_engine.h" +#warning esp32/sha.h is deprecated, please use sha_parallel_engine.h instead \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/esp_rsa_sign_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/esp_rsa_sign_alt.h new file mode 100644 index 00000000..51fc22e2 --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/esp_rsa_sign_alt.h @@ -0,0 +1,86 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifndef _ESP_RSA_SIGN_ALT_H_ +#define _ESP_RSA_SIGN_ALT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_ds.h" +#include "mbedtls/md.h" + +/** + * @brief ESP-DS data context + * + * @note This structure includes encrypted private key parameters such as ciphertext_c, initialization vector, efuse_key_id, RSA key length, which are obtained when DS peripheral is configured. + */ + +/* Context for encrypted private key data required for DS */ +typedef struct esp_ds_data_ctx { + esp_ds_data_t *esp_ds_data; + uint8_t efuse_key_id; /* efuse block id in which DS_KEY is stored e.g. 0,1*/ + uint16_t rsa_length_bits; /* length of RSA private key in bits e.g. 2048 */ +} esp_ds_data_ctx_t; + +/** + * @brief Initializes internal DS data context + * + * This function allocates and initializes internal ds data context which is used for Digital Signature operation. + * + * @in ds_data ds_data context containing encrypted private key parameters + * @return + * - ESP_OK In case of succees + * - ESP_ERR_NO_MEM In case internal context could not be allocated. + * - ESP_ERR_INVALID_ARG in case input parametrers are NULL + * + */ +esp_err_t esp_ds_init_data_ctx(esp_ds_data_ctx_t *ds_data); + +/** + * + * @brief Release the ds lock acquired for the DS operation (then the DS peripheral can be used for other TLS connection) + * + */ +void esp_ds_release_ds_lock(void); + +/** + * + * @brief Alternate implementation for mbedtls_rsa_rsassa_pkcs1_v15_sign, Internally makes use + * of DS module to perform hardware accelerated RSA sign operation + */ +int esp_ds_rsa_sign( void *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + int mode, mbedtls_md_type_t md_alg, unsigned int hashlen, + const unsigned char *hash, unsigned char *sig ); + +/* + * @brief Get RSA key length in bytes from internal DS context + * + * @return RSA key length in bytes + */ +size_t esp_ds_get_keylen(void *ctx); + +/* + * @brief Set timeout (equal to TLS session timeout), so that DS module usage can be synchronized in case of multiple TLS connections using DS module, + */ +void esp_ds_set_session_timeout(int timeout); +#ifdef __cplusplus +} +#endif + +#endif /* _ESP_RSA_SIGN_ALT_H_ */ diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/sha.h b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/sha.h index 58bd4394..12c6548d 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/sha.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s2/sha.h @@ -12,157 +12,10 @@ // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _ESP_SHA_H_ -#define _ESP_SHA_H_ +#pragma once -#include "esp32s2/rom/sha.h" +#include "sha/sha_dma.h" -/** @brief Low-level support functions for the hardware SHA engine using DMA - * - * @note If you're looking for a SHA API to use, try mbedtls component - * mbedtls/shaXX.h. That API supports hardware acceleration. - * - * The API in this header provides some building blocks for implementing a - * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). - * - * Some technical details about the hardware SHA engine: - * - * - The crypto DMA is shared between the SHA and AES engine, it is not - * possible for them to run calcalutions in parallel. - * - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Defined in rom/sha.h */ -typedef SHA_TYPE esp_sha_type; - -/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine - * - * @note For more versatile SHA calculations, where data doesn't need - * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. - * - * @note It is not necessary to lock any SHA hardware before calling - * this function, thread safety is managed internally. - * - * @param sha_type SHA algorithm to use. - * - * @param input Input data buffer. - * - * @param ilen Length of input data in bytes. - * - * @param output Buffer for output SHA digest. Output is 20 bytes for - * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for - * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. - */ -void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); - -/** @brief Execute SHA block operation using DMA - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA - * algorithm. - * - * @note Call esp_sha_aquire_hardware() before calling this - * function. - * - * @param sha_type SHA algorithm to use. - * - * @param input Pointer to the input data. Block size is - * determined by algorithm (SHA1/SHA2_256 = 64 bytes, - * SHA2_384/SHA2_512 = 128 bytes) - * - * @param ilen length of input data should be multiple of block length. - * - * @param buf Pointer to blocks of data that will be prepended - * to data_block before hashing. Useful when there is two sources of - * data that need to be efficiently calculated in a single SHA DMA - * operation. - * - * @param buf_len length of buf data should be multiple of block length. - * Should not be longer than the maximum amount of bytes in a single block - * (128 bytes) - * - * @param is_first_block If this parameter is true, the SHA state will - * be initialised (with the initial state of the given SHA algorithm) - * before the block is calculated. If false, the existing state of the - * SHA engine will be used. - * - * @param t The number of bits for the SHA512/t hash function, with - * output truncated to t bits. Used for calculating the inital hash. - * t is any positive integer between 1 and 512, except 384. - * - * @return 0 if successful - */ -int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, - const void *buf, uint32_t buf_len, bool is_first_block); - -/** - * @brief Read out the current state of the SHA digest - * - * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. - * - * @note Call esp_sha_aquire_hardware() before calling this - * function. - * - * If the SHA suffix padding block has been executed already, the - * value that is read is the SHA digest. - * Otherwise, the value that is read is an interim SHA state. - * - * @param sha_type SHA algorithm in use. - * @param digest_state Pointer to a memory buffer to hold the SHA state. Size - * is 20 bytes (SHA1), 32 bytes (SHA2_256), or 64 bytes (SHA2_384, SHA2_512). - */ -void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); - -/** - * @brief Set the current state of the SHA digest - * - * @note Call esp_sha_aquire_hardware() before calling this - * function. - * - * When resuming a - * - * @param sha_type SHA algorithm in use. - * @param digest_state - */ -void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state); +#warning esp32s2/sha.h is deprecated, please use sha/sha_dma.h instead -/** - * @brief Enables the SHA and crypto DMA peripheral and takes the - * locks for both of them. - */ -void esp_sha_acquire_hardware(void); - -/** - * @brief Disables the SHA and crypto DMA peripheral and releases the - * locks. - */ -void esp_sha_release_hardware(void); - -/* -*/ - -/** - * @brief Sets the initial hash value for SHA512/t. - * - * @note Is generated according to the algorithm described in the TRM, - * chapter SHA-Accelerator - * - * @note The engine must be locked until the value is used for an operation - * or read out. Else you risk another operation overwriting it. - * - * @param t - * - * @return 0 if successful - */ -int esp_sha_512_t_init_hash(uint16_t t); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/aes.h b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/aes.h new file mode 100644 index 00000000..904a0ecd --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/aes.h @@ -0,0 +1,369 @@ +/** + * \brief AES block cipher, ESP32 hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_AES_H +#define ESP_AES_H + +#include "esp_types.h" +#include "esp32s3/rom/aes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* padlock.c and aesni.c rely on these values! */ +#define ESP_AES_ENCRYPT 1 +#define ESP_AES_DECRYPT 0 + +#define ERR_ESP_AES_INVALID_KEY_LENGTH -0x0020 /**< Invalid key length. */ +#define ERR_ESP_AES_INVALID_INPUT_LENGTH -0x0022 /**< Invalid data input length. */ + + +/** + * \brief AES context structure + * + * \note buf is able to hold 32 extra bytes, which can be used: + * - for alignment purposes if VIA padlock is used, and/or + * - to simplify key expansion in the 256-bit case by + * generating an extra round key + */ +typedef struct { + uint8_t key_bytes; + volatile uint8_t key_in_hardware; /* This variable is used for fault injection checks, so marked volatile to avoid optimisation */ + uint8_t key[32]; +} esp_aes_context; + + +/** + * \brief The AES XTS context-type definition. + */ +typedef struct { + esp_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + esp_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} esp_aes_xts_context; + +/** + * \brief Lock access to AES hardware unit + * + * AES hardware unit can only be used by one + * consumer at a time. + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_acquire_hardware( void ); + +/** + * \brief Unlock access to AES hardware unit + * + * esp_aes_xxx API calls automatically manage locking & unlocking of + * hardware, this function is only needed if you want to call + * ets_aes_xxx functions directly. + */ +void esp_aes_release_hardware( void ); + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void esp_aes_init( esp_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void esp_aes_free( esp_aes_context *ctx ); + +/* + * \brief This function initializes the specified AES XTS context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES XTS context to initialize. + */ +void esp_aes_xts_init( esp_aes_xts_context *ctx ); + +/** + * \brief This function releases and clears the specified AES XTS context. + * + * \param ctx The AES XTS context to clear. + */ +void esp_aes_xts_free( esp_aes_xts_context *ctx ); + +/** + * \brief AES set key schedule (encryption or decryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ + +/** + * \brief AES set key schedule (encryption or decryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128, 192 or 256 + * + * \return 0 if successful, or ERR_AES_INVALID_KEY_LENGTH + */ +int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] ); + +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or ERR_AES_INVALID_INPUT_LENGTH + */ +int esp_aes_crypt_cbc( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + + +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb128( esp_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode AES_ENCRYPT or AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int esp_aes_crypt_cfb8( esp_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int esp_aes_crypt_ctr( esp_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function performs an AES-OFB (Output Feedback Mode) + * encryption or decryption operation. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +int esp_aes_crypt_ofb( esp_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function prepares an XTS context for encryption and + * sets the encryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * \param key The encryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +int esp_aes_xts_setkey_enc( esp_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +int esp_aes_xts_setkey_dec( esp_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits ); + + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +int esp_internal_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** Deprecated, see esp_aes_internal_encrypt */ +void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated)); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +int esp_internal_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ); + +/** Deprecated, see esp_aes_internal_decrypt */ +void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] ) __attribute__((deprecated)); + +/** AES-XTS buffer encryption/decryption */ +int esp_aes_crypt_xts( esp_aes_xts_context *ctx, int mode, size_t length, const unsigned char data_unit[16], const unsigned char *input, unsigned char *output ); + + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/crypto_dma.h b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/crypto_dma.h new file mode 100644 index 00000000..ce7d67ef --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/crypto_dma.h @@ -0,0 +1,40 @@ +/** + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_CRYPTO_DMA_H +#define ESP_CRYPTO_DMA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Since crypto DMA is shared between DMA-AES and SHA blocks + * Needs to be taken by respective blocks before using Crypto DMA + */ +extern _lock_t crypto_dma_lock; + +#ifdef __cplusplus +} +#endif + +#endif /* crypto_dma.h */ diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/gcm.h b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/gcm.h new file mode 100644 index 00000000..07c80ad5 --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/esp32s3/gcm.h @@ -0,0 +1,238 @@ +/** + * \brief AES block cipher, ESP32C hardware accelerated version + * Based on mbedTLS FIPS-197 compliant version. + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Additions Copyright (C) 2019-2020, Espressif Systems (Shanghai) PTE Ltd + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + */ + +#ifndef ESP_GCM_H +#define ESP_GCM_H + +#include "aes.h" +#include "mbedtls/cipher.h" +#ifdef __cplusplus +extern "C" { +#endif + + +#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 /**< Authenticated decryption failed. */ +#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 /**< Bad input parameters to function.*/ + +typedef enum { + ESP_AES_GCM_STATE_INIT, + ESP_AES_GCM_STATE_UPDATE, + ESP_AES_GCM_STATE_FINISH +} esp_aes_gcm_state; +/** + * \brief The GCM context structure. + */ +typedef struct { + uint8_t H[16]; /*!< Initial hash value */ + uint8_t ghash[16]; /*!< GHASH value. */ + uint8_t J0[16]; + uint64_t HL[16]; /*!< Precalculated HTable low. */ + uint64_t HH[16]; /*!< Precalculated HTable high. */ + uint8_t ori_j0[16]; /*!< J0 from first iteration. */ + const uint8_t *iv; + size_t iv_len; /*!< The length of IV. */ + uint64_t aad_len; /*!< The total length of the additional data. */ + size_t data_len; + int mode; + const unsigned char *aad; /*!< The additional data. */ + esp_aes_context aes_ctx; + esp_aes_gcm_state gcm_state; +} esp_gcm_context; + +/** + * \brief This function initializes the specified GCM context + * + * \param ctx The GCM context to initialize. + */ +void esp_aes_gcm_init( esp_gcm_context *ctx); + +/** + * \brief This function associates a GCM context with a + * key. + * + * \param ctx The GCM context to initialize. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. + * \param keybits The key size in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int esp_aes_gcm_setkey( esp_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits ); + +/** + * \brief This function starts a GCM encryption or decryption + * operation. + * + * \param ctx The GCM context. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data, or NULL + * if \p add_len is 0. + * \param add_len The length of the additional data. If 0, + * \p add is NULL. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_starts( esp_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len, + const unsigned char *aad, + size_t aad_len ); + +/** + * \brief This function feeds an input buffer into an ongoing GCM + * encryption or decryption operation. + * + * ` The function expects input to be a multiple of 16 + * Bytes. Only the last call before calling + * mbedtls_gcm_finish() can be less than 16 Bytes. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_update( esp_gcm_context *ctx, + size_t length, + const unsigned char *input, + unsigned char *output ); + +/** + * \brief This function finishes the GCM operation and generates + * the authentication tag. + * + * It wraps up the GCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \param ctx The GCM context. + * \param tag The buffer for holding the tag. + * \param tag_len The length of the tag to generate. Must be at least four. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure. + */ +int esp_aes_gcm_finish( esp_gcm_context *ctx, + unsigned char *tag, + size_t tag_len ); + +/** + * \brief This function clears a GCM context + * + * \param ctx The GCM context to clear. + */ +void esp_aes_gcm_free( esp_gcm_context *ctx); + +/** + * \brief This function performs GCM encryption or decryption of a buffer. + * + * \note For encryption, the output buffer can be the same as the + * input buffer. For decryption, the output buffer cannot be + * the same as input buffer. If the buffers overlap, the output + * buffer must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context to use for encryption or decryption. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param length The length of the input data. This must be a multiple of + * 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * \param tag_len The length of the tag to generate. + * \param tag The buffer for holding the tag. + * + * \return \c 0 on success. + */ +int esp_aes_gcm_crypt_and_tag( esp_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag ); + + +/** + * \brief This function performs a GCM authenticated decryption of a + * buffer. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. + * \param length The length of the input data. This must be a multiple + * of 16 except in the last call before mbedtls_gcm_finish(). + * \param iv The initialization vector. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. + * \param add_len The length of the additional data. + * \param tag The buffer holding the tag. + * \param tag_len The length of the tag. + * \param input The buffer holding the input data. + * \param output The buffer for holding the output data. + * + * \return 0 if successful and authenticated. + * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. + */ +int esp_aes_gcm_auth_decrypt( esp_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output ); + +#ifdef __cplusplus +} +#endif + +#endif /* gcm.h */ diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/gcm_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/gcm_alt.h index c3d886a7..9a79850c 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/gcm_alt.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/gcm_alt.h @@ -29,6 +29,23 @@ extern "C" { #if defined(MBEDTLS_GCM_ALT) +#if CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/gcm.h" + + +typedef esp_gcm_context mbedtls_gcm_context; + +#define mbedtls_gcm_init esp_aes_gcm_init +#define mbedtls_gcm_free esp_aes_gcm_free +#define mbedtls_gcm_setkey esp_aes_gcm_setkey +#define mbedtls_gcm_starts esp_aes_gcm_starts +#define mbedtls_gcm_update esp_aes_gcm_update +#define mbedtls_gcm_finish esp_aes_gcm_finish +#define mbedtls_gcm_auth_decrypt esp_aes_gcm_auth_decrypt +#define mbedtls_gcm_crypt_and_tag esp_aes_gcm_crypt_and_tag + +#endif // CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/gcm.h" diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/rsa_sign_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/rsa_sign_alt.h new file mode 100644 index 00000000..a89311a7 --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/rsa_sign_alt.h @@ -0,0 +1,39 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifndef _RSA_SIGN_ALT_H_ +#define _RSA_SIGN_ALT_H_ + +#ifdef __cpluscplus +extern "C" { +#endif + +#ifdef CONFIG_ESP_TLS_USE_DS_PERIPHERAL + +#include "esp32s2/esp_rsa_sign_alt.h" + +#else + +#error "DS configuration flags not activated, please enable required menuconfig flags" + +#endif + +#ifdef __cpluscplus +} +#endif + +#endif + diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/sha/sha_dma.h b/tools/sdk/esp32s2/include/mbedtls/port/include/sha/sha_dma.h new file mode 100644 index 00000000..c71261d1 --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/sha/sha_dma.h @@ -0,0 +1,161 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "hal/sha_types.h" + +/** @brief Low-level support functions for the hardware SHA engine using DMA + * + * @note If you're looking for a SHA API to use, try mbedtls component + * mbedtls/shaXX.h. That API supports hardware acceleration. + * + * The API in this header provides some building blocks for implementing a + * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). + * + * Some technical details about the hardware SHA engine: + * + * - The crypto DMA is shared between the SHA and AES engine, it is not + * possible for them to run calcalutions in parallel. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine + * + * @note For more versatile SHA calculations, where data doesn't need + * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. + * + * @note It is not necessary to lock any SHA hardware before calling + * this function, thread safety is managed internally. + * + * @param sha_type SHA algorithm to use. + * + * @param input Input data buffer. + * + * @param ilen Length of input data in bytes. + * + * @param output Buffer for output SHA digest. Output is 20 bytes for + * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for + * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. + */ +void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); + +/** @brief Execute SHA block operation using DMA + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA + * algorithm. + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * @param sha_type SHA algorithm to use. + * + * @param input Pointer to the input data. Block size is + * determined by algorithm (SHA1/SHA2_256 = 64 bytes, + * SHA2_384/SHA2_512 = 128 bytes) + * + * @param ilen length of input data should be multiple of block length. + * + * @param buf Pointer to blocks of data that will be prepended + * to data_block before hashing. Useful when there is two sources of + * data that need to be efficiently calculated in a single SHA DMA + * operation. + * + * @param buf_len length of buf data should be multiple of block length. + * Should not be longer than the maximum amount of bytes in a single block + * (128 bytes) + * + * @param is_first_block If this parameter is true, the SHA state will + * be initialised (with the initial state of the given SHA algorithm) + * before the block is calculated. If false, the existing state of the + * SHA engine will be used. + * + * @param t The number of bits for the SHA512/t hash function, with + * output truncated to t bits. Used for calculating the inital hash. + * t is any positive integer between 1 and 512, except 384. + * + * @return 0 if successful + */ +int esp_sha_dma(esp_sha_type sha_type, const void *input, uint32_t ilen, + const void *buf, uint32_t buf_len, bool is_first_block); + +/** + * @brief Read out the current state of the SHA digest + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * If the SHA suffix padding block has been executed already, the + * value that is read is the SHA digest. + * Otherwise, the value that is read is an interim SHA state. + * + * @param sha_type SHA algorithm in use. + * @param digest_state Pointer to a memory buffer to hold the SHA state. Size + * is 20 bytes (SHA1), 32 bytes (SHA2_256), or 64 bytes (SHA2_384, SHA2_512). + */ +void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); + +/** + * @brief Set the current state of the SHA digest + * + * @note Call esp_sha_aquire_hardware() before calling this + * function. + * + * When resuming a + * + * @param sha_type SHA algorithm in use. + * @param digest_state + */ +void esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state); + + +/** + * @brief Enables the SHA and crypto DMA peripheral and takes the + * locks for both of them. + */ +void esp_sha_acquire_hardware(void); + +/** + * @brief Disables the SHA and crypto DMA peripheral and releases the + * locks. + */ +void esp_sha_release_hardware(void); + +/** + * @brief Sets the initial hash value for SHA512/t. + * + * @note Is generated according to the algorithm described in the TRM, + * chapter SHA-Accelerator + * + * @note The engine must be locked until the value is used for an operation + * or read out. Else you risk another operation overwriting it. + * + * @param t + * + * @return 0 if successful + */ +int esp_sha_512_t_init_hash(uint16_t t); + +#ifdef __cplusplus +} +#endif + + diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/sha/sha_parallel_engine.h b/tools/sdk/esp32s2/include/mbedtls/port/include/sha/sha_parallel_engine.h new file mode 100644 index 00000000..51ac7add --- /dev/null +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/sha/sha_parallel_engine.h @@ -0,0 +1,207 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "hal/sha_types.h" +#include "esp_types.h" + +/** @brief Low-level support functions for the hardware SHA engine + * + * @note If you're looking for a SHA API to use, try mbedtls component + * mbedtls/shaXX.h. That API supports hardware acceleration. + * + * The API in this header provides some building blocks for implementing a + * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha(). + * + * Some technical details about the hardware SHA engine: + * + * - SHA accelerator engine calculates one digest at a time, per SHA + * algorithm type. It initialises and maintains the digest state + * internally. It is possible to read out an in-progress SHA digest + * state, but it is not possible to restore a SHA digest state + * into the engine. + * + * - The memory block SHA_TEXT_BASE is shared between all SHA digest + * engines, so all engines must be idle before this memory block is + * modified. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine + * + * @note For more versatile SHA calculations, where data doesn't need + * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The + * hardware-accelerated mbedTLS implementation is also faster when + * hashing large amounts of data. + * + * @note It is not necessary to lock any SHA hardware before calling + * this function, thread safety is managed internally. + * + * @note If a TLS connection is open then this function may block + * indefinitely waiting for a SHA engine to become available. Use the + * mbedTLS SHA API to avoid this problem. + * + * @param sha_type SHA algorithm to use. + * + * @param input Input data buffer. + * + * @param ilen Length of input data in bytes. + * + * @param output Buffer for output SHA digest. Output is 20 bytes for + * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for + * sha_type SHA2_384, 64 bytes for sha_type SHA2_512. + */ +void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output); + +/* @brief Begin to execute a single SHA block operation + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA + * algorithm. + * + * @note Call esp_sha_try_lock_engine() before calling this + * function. Do not call esp_sha_lock_memory_block() beforehand, this + * is done inside the function. + * + * @param sha_type SHA algorithm to use. + * + * @param data_block Pointer to block of data. Block size is + * determined by algorithm (SHA1/SHA2_256 = 64 bytes, + * SHA2_384/SHA2_512 = 128 bytes) + * + * @param is_first_block If this parameter is true, the SHA state will + * be initialised (with the initial state of the given SHA algorithm) + * before the block is calculated. If false, the existing state of the + * SHA engine will be used. + * + * @return As a performance optimisation, this function returns before + * the SHA block operation is complete. Both this function and + * esp_sha_read_state() will automatically wait for any previous + * operation to complete before they begin. If using the SHA registers + * directly in another way, call esp_sha_wait_idle() after calling this + * function but before accessing the SHA registers. + */ +void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block); + +/** @brief Read out the current state of the SHA digest loaded in the engine. + * + * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm. + * + * @note Call esp_sha_try_lock_engine() before calling this + * function. Do not call esp_sha_lock_memory_block() beforehand, this + * is done inside the function. + * + * If the SHA suffix padding block has been executed already, the + * value that is read is the SHA digest (in big endian + * format). Otherwise, the value that is read is an interim SHA state. + * + * @note If sha_type is SHA2_384, only 48 bytes of state will be read. + * This is enough for the final SHA2_384 digest, but if you want the + * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead. + * + * @param sha_type SHA algorithm in use. + * + * @param state Pointer to a memory buffer to hold the SHA state. Size + * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512). + * + */ +void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state); + +/** + * @brief Obtain exclusive access to a particular SHA engine + * + * @param sha_type Type of SHA engine to use. + * + * Blocks until engine is available. Note: Can block indefinitely + * while a TLS connection is open, suggest using + * esp_sha_try_lock_engine() and failing over to software SHA. + */ +void esp_sha_lock_engine(esp_sha_type sha_type); + +/** + * @brief Try and obtain exclusive access to a particular SHA engine + * + * @param sha_type Type of SHA engine to use. + * + * @return Returns true if the SHA engine is locked for exclusive + * use. Call esp_sha_unlock_sha_engine() when done. Returns false if + * the SHA engine is already in use, caller should use software SHA + * algorithm for this digest. + */ +bool esp_sha_try_lock_engine(esp_sha_type sha_type); + +/** + * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine() + * + * @param sha_type Type of engine to release. + */ +void esp_sha_unlock_engine(esp_sha_type sha_type); + +/** + * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE + * + * This memory block is shared across all the SHA algorithm types. + * + * Caller should have already locked a SHA engine before calling this function. + * + * Note that it is possible to obtain exclusive access to the memory block even + * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle() + * to ensure the SHA engine is not reading from the memory block in hardware. + * + * @note This function enters a critical section. Do not block while holding this lock. + * + * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally. + * + * Call esp_sha_unlock_memory_block() when done. + */ +void esp_sha_lock_memory_block(void); + +/** + * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE + * + * Caller should have already locked a SHA engine before calling this function. + * + * This function releases the critical section entered by esp_sha_lock_memory_block(). + * + * Call following esp_sha_lock_memory_block(). + */ +void esp_sha_unlock_memory_block(void); + +/** @brief Wait for the SHA engine to finish any current operation + * + * @note This function does not ensure exclusive access to any SHA + * engine. Caller should use esp_sha_try_lock_engine() and + * esp_sha_lock_memory_block() as required. + * + * @note Functions declared in this header file wait for SHA engine + * completion automatically, so you don't need to use this API for + * these. However if accessing SHA registers directly, you will need + * to call this before accessing SHA registers if using the + * esp_sha_block() function. + * + * @note This function busy-waits, so wastes CPU resources. + * Best to delay calling until you are about to need it. + * + */ +void esp_sha_wait_idle(void); + +#ifdef __cplusplus +} +#endif + + diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/sha1_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/sha1_alt.h index a3f05a84..7c145ae5 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/sha1_alt.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/sha1_alt.h @@ -23,15 +23,35 @@ #ifndef _SHA1_ALT_H_ #define _SHA1_ALT_H_ +#if defined(MBEDTLS_SHA1_ALT) + +#include "hal/sha_types.h" +#include "soc/sha_caps.h" + #ifdef __cplusplus extern "C" { #endif -#if defined(MBEDTLS_SHA1_ALT) +#if SOC_SHA_SUPPORT_PARALLEL_ENG -#if CONFIG_IDF_TARGET_ESP32S2 +typedef enum { + ESP_MBEDTLS_SHA1_UNUSED, /* first block hasn't been processed yet */ + ESP_MBEDTLS_SHA1_HARDWARE, /* using hardware SHA engine */ + ESP_MBEDTLS_SHA1_SOFTWARE, /* using software SHA */ +} esp_mbedtls_sha1_mode; + +/** + * \brief SHA-1 context structure + */ +typedef struct { + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[5]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ + esp_mbedtls_sha1_mode mode; +} mbedtls_sha1_context; + +#elif SOC_SHA_SUPPORT_DMA -#include "esp32s2/sha.h" typedef enum { ESP_SHA1_STATE_INIT, ESP_SHA1_STATE_IN_PROCESS @@ -49,28 +69,7 @@ typedef struct { esp_sha1_state sha_state; } mbedtls_sha1_context; -#endif //CONFIG_IDF_TARGET_ESP32S2 - -#if CONFIG_IDF_TARGET_ESP32 - -typedef enum { - ESP_MBEDTLS_SHA1_UNUSED, /* first block hasn't been processed yet */ - ESP_MBEDTLS_SHA1_HARDWARE, /* using hardware SHA engine */ - ESP_MBEDTLS_SHA1_SOFTWARE, /* using software SHA */ -} esp_mbedtls_sha1_mode; - -/** - * \brief SHA-1 context structure - */ -typedef struct { - uint32_t total[2]; /*!< number of bytes processed */ - uint32_t state[5]; /*!< intermediate digest state */ - unsigned char buffer[64]; /*!< data block being processed */ - esp_mbedtls_sha1_mode mode; -} -mbedtls_sha1_context; - -#endif //CONFIG_IDF_TARGET_ESP32 +#endif #endif diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/sha256_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/sha256_alt.h index db82fb64..3a1f385e 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/sha256_alt.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/sha256_alt.h @@ -23,39 +23,16 @@ #ifndef _SHA256_ALT_H_ #define _SHA256_ALT_H_ +#if defined(MBEDTLS_SHA256_ALT) + +#include "hal/sha_types.h" +#include "soc/sha_caps.h" + #ifdef __cplusplus extern "C" { #endif -#if defined(MBEDTLS_SHA256_ALT) - - -#if CONFIG_IDF_TARGET_ESP32S2 - -#include "esp32s2/sha.h" - -typedef enum { - ESP_SHA256_STATE_INIT, - ESP_SHA256_STATE_IN_PROCESS -} esp_sha256_state; - -/** - * \brief SHA-256 context structure - */ -typedef struct { - uint32_t total[2]; /*!< number of bytes processed */ - uint32_t state[8]; /*!< intermediate digest state */ - unsigned char buffer[64]; /*!< data block being processed */ - int first_block; /*!< if first then true, else false */ - esp_sha_type mode; - esp_sha256_state sha_state; -} -mbedtls_sha256_context; - -#endif //CONFIG_IDF_TARGET_ESP32S2 - -#if CONFIG_IDF_TARGET_ESP32 - +#if SOC_SHA_SUPPORT_PARALLEL_ENG typedef enum { ESP_MBEDTLS_SHA256_UNUSED, /* first block hasn't been processed yet */ ESP_MBEDTLS_SHA256_HARDWARE, /* using hardware SHA engine */ @@ -71,10 +48,27 @@ typedef struct { unsigned char buffer[64]; /*!< data block being processed */ int is224; /*!< 0 => SHA-256, else SHA-224 */ esp_mbedtls_sha256_mode mode; -} -mbedtls_sha256_context; +} mbedtls_sha256_context; -#endif //CONFIG_IDF_TARGET_ESP32 +#elif SOC_SHA_SUPPORT_DMA +typedef enum { + ESP_SHA256_STATE_INIT, + ESP_SHA256_STATE_IN_PROCESS +} esp_sha256_state; + +/** + * \brief SHA-256 context structure + */ +typedef struct { + uint32_t total[2]; /*!< number of bytes processed */ + uint32_t state[8]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ + int first_block; /*!< if first then true, else false */ + esp_sha_type mode; + esp_sha256_state sha_state; +} mbedtls_sha256_context; + +#endif #endif diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/sha512_alt.h b/tools/sdk/esp32s2/include/mbedtls/port/include/sha512_alt.h index da58e8a7..4f5cc005 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/sha512_alt.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/sha512_alt.h @@ -23,15 +23,36 @@ #ifndef _SHA512_ALT_H_ #define _SHA512_ALT_H_ +#if defined(MBEDTLS_SHA512_ALT) + +#include "hal/sha_types.h" +#include "soc/sha_caps.h" #ifdef __cplusplus extern "C" { #endif -#if defined(MBEDTLS_SHA512_ALT) -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/sha.h" +#if SOC_SHA_SUPPORT_PARALLEL_ENG + +typedef enum { + ESP_MBEDTLS_SHA512_UNUSED, /* first block hasn't been processed yet */ + ESP_MBEDTLS_SHA512_HARDWARE, /* using hardware SHA engine */ + ESP_MBEDTLS_SHA512_SOFTWARE, /* using software SHA */ +} esp_mbedtls_sha512_mode; + +/** + * \brief SHA-512 context structure + */ +typedef struct { + uint64_t total[2]; /*!< number of bytes processed */ + uint64_t state[8]; /*!< intermediate digest state */ + unsigned char buffer[128]; /*!< data block being processed */ + int is384; /*!< 0 => SHA-512, else SHA-384 */ + esp_mbedtls_sha512_mode mode; +} mbedtls_sha512_context; + +#elif SOC_SHA_SUPPORT_DMA typedef enum { ESP_SHA512_STATE_INIT, @@ -64,29 +85,8 @@ void esp_sha512_set_mode(mbedtls_sha512_context *ctx, esp_sha_type type); /* For SHA512/t mode the intial hash value will depend on t */ void esp_sha512_set_t( mbedtls_sha512_context *ctx, uint16_t t_val); -#endif //CONFIG_IDF_TARGET_ESP32S2 -#if CONFIG_IDF_TARGET_ESP32 - -typedef enum { - ESP_MBEDTLS_SHA512_UNUSED, /* first block hasn't been processed yet */ - ESP_MBEDTLS_SHA512_HARDWARE, /* using hardware SHA engine */ - ESP_MBEDTLS_SHA512_SOFTWARE, /* using software SHA */ -} esp_mbedtls_sha512_mode; - -/** - * \brief SHA-512 context structure - */ -typedef struct { - uint64_t total[2]; /*!< number of bytes processed */ - uint64_t state[8]; /*!< intermediate digest state */ - unsigned char buffer[128]; /*!< data block being processed */ - int is384; /*!< 0 => SHA-512, else SHA-384 */ - esp_mbedtls_sha512_mode mode; -} -mbedtls_sha512_context; - -#endif //CONFIG_IDF_TARGET_ESP32 +#endif #endif diff --git a/tools/sdk/esp32s2/include/nvs_flash/include/nvs.h b/tools/sdk/esp32s2/include/nvs_flash/include/nvs.h index 3e877a65..2f4aa551 100644 --- a/tools/sdk/esp32s2/include/nvs_flash/include/nvs.h +++ b/tools/sdk/esp32s2/include/nvs_flash/include/nvs.h @@ -59,12 +59,14 @@ typedef nvs_handle_t nvs_handle IDF_DEPRECATED("Replace with nvs_handle_t"); #define ESP_ERR_NVS_ENCR_NOT_SUPPORTED (ESP_ERR_NVS_BASE + 0x15) /*!< NVS encryption is not supported in this version */ #define ESP_ERR_NVS_KEYS_NOT_INITIALIZED (ESP_ERR_NVS_BASE + 0x16) /*!< NVS key partition is uninitialized */ #define ESP_ERR_NVS_CORRUPT_KEY_PART (ESP_ERR_NVS_BASE + 0x17) /*!< NVS key partition is corrupt */ +#define ESP_ERR_NVS_WRONG_ENCRYPTION (ESP_ERR_NVS_BASE + 0x19) /*!< NVS partition is marked as encrypted with generic flash encryption. This is forbidden since the NVS encryption works differently. */ #define ESP_ERR_NVS_CONTENT_DIFFERS (ESP_ERR_NVS_BASE + 0x18) /*!< Internal error; never returned by nvs API functions. NVS key is different in comparison */ #define NVS_DEFAULT_PART_NAME "nvs" /*!< Default partition name of the NVS partition in the partition table */ #define NVS_PART_NAME_MAX_SIZE 16 /*!< maximum length of partition name (excluding null terminator) */ +#define NVS_KEY_NAME_MAX_SIZE 16 /*!< Maximal length of NVS key name (including null terminator) */ /** * @brief Mode of opening the non-volatile storage @@ -121,9 +123,7 @@ typedef struct nvs_opaque_iterator_t *nvs_iterator_t; * The default NVS partition is the one that is labelled "nvs" in the partition * table. * - * @param[in] name Namespace name. Maximal length is determined by the - * underlying implementation, but is guaranteed to be - * at least 15 characters. Shouldn't be empty. + * @param[in] name Namespace name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] open_mode NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will * open a handle for reading only. All write requests will * be rejected for this handle. @@ -149,9 +149,7 @@ esp_err_t nvs_open(const char* name, nvs_open_mode_t open_mode, nvs_handle_t *ou * with NVS using nvs_flash_init_partition() API. * * @param[in] part_name Label (name) of the partition of interest for object read/write/erase - * @param[in] name Namespace name. Maximal length is determined by the - * underlying implementation, but is guaranteed to be - * at least 15 characters. Shouldn't be empty. + * @param[in] name Namespace name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] open_mode NVS_READWRITE or NVS_READONLY. If NVS_READONLY, will * open a handle for reading only. All write requests will * be rejected for this handle. @@ -178,9 +176,7 @@ esp_err_t nvs_open_from_partition(const char *part_name, const char* name, nvs_o * * @param[in] handle Handle obtained from nvs_open function. * Handles that were opened read only cannot be used. - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] value The value to set. * For strings, the maximum length (including null character) is * 4000 bytes. @@ -217,7 +213,7 @@ esp_err_t nvs_set_str (nvs_handle_t handle, const char* key, const char* value); * * @param[in] handle Handle obtained from nvs_open function. * Handles that were opened read only cannot be used. - * @param[in] key Key name. Maximal length is 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] value The value to set. * @param[in] length length of binary value to set, in bytes; Maximum length is * 508000 bytes or (97.6% of the partition size - 4000) bytes @@ -262,9 +258,7 @@ esp_err_t nvs_set_blob(nvs_handle_t handle, const char* key, const void* value, * \endcode * * @param[in] handle Handle obtained from nvs_open function. - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param out_value Pointer to the output value. * May be NULL for nvs_get_str and nvs_get_blob, in this * case required length will be returned in length argument. @@ -323,9 +317,7 @@ esp_err_t nvs_get_u64 (nvs_handle_t handle, const char* key, uint64_t* out_value * \endcode * * @param[in] handle Handle obtained from nvs_open function. - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param out_value Pointer to the output value. * May be NULL for nvs_get_str and nvs_get_blob, in this * case required length will be returned in length argument. @@ -355,9 +347,7 @@ esp_err_t nvs_get_blob(nvs_handle_t handle, const char* key, void* out_value, si * @param[in] handle Storage handle obtained with nvs_open. * Handles that were opened read only cannot be used. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * * @return * - ESP_OK if erase operation was successful diff --git a/tools/sdk/esp32s2/include/nvs_flash/include/nvs_handle.hpp b/tools/sdk/esp32s2/include/nvs_flash/include/nvs_handle.hpp index d87c1c28..537d2f9f 100644 --- a/tools/sdk/esp32s2/include/nvs_flash/include/nvs_handle.hpp +++ b/tools/sdk/esp32s2/include/nvs_flash/include/nvs_handle.hpp @@ -44,9 +44,7 @@ public: * * Sets value for key. Note that physical storage will not be updated until nvs_commit function is called. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] value The value to set. Allowed types are the ones declared in ItemType as well as enums. * For strings, the maximum length (including null character) is * 4000 bytes. @@ -79,9 +77,7 @@ public: * * In case of any error, out_value is not modified. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param value The output value. All integral types which are declared in ItemType as well as enums * are allowed. Note however that enums lost their type information when stored in NVS. * Ensure that the correct enum type is used during retrieval with \ref get_item! @@ -101,7 +97,7 @@ public: * This family of functions set value for the key, given its name. Note that * actual storage will not be updated until nvs_commit function is called. * - * @param[in] key Key name. Maximal length is 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param[in] blob The blob value to set. * @param[in] len length of binary value to set, in bytes; Maximum length is * 508000 bytes or (97.6% of the partition size - 4000) bytes @@ -138,9 +134,7 @@ public: * It is suggested that nvs_get/set_str is used for zero-terminated C strings, and * nvs_get/set_blob used for arbitrary data structures. * - * @param[in] key Key name. Maximal length is determined by the underlying - * implementation, but is guaranteed to be at least - * 15 characters. Shouldn't be empty. + * @param[in] key Key name. Maximal length is (NVS_KEY_NAME_MAX_SIZE-1) characters. Shouldn't be empty. * @param out_str/ Pointer to the output value. * out_blob * @param[inout] length A non-zero pointer to the variable holding the length of out_value. diff --git a/tools/sdk/esp32s2/include/soc/include/hal/sha_hal.h b/tools/sdk/esp32s2/include/soc/include/hal/sha_hal.h new file mode 100644 index 00000000..ff3e7e23 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/include/hal/sha_hal.h @@ -0,0 +1,91 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#include +#include +#include "soc/sha_caps.h" +#include "soc/lldesc.h" +#include "hal/sha_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Hashes a single message block + * + * @param sha_type SHA algorithm to hash with + * @param data_block Input message to be hashed + * @param block_word_len Length of the input message + * @param first_block Is this the first block in a message or a continuation? + */ +void sha_hal_hash_block(esp_sha_type sha_type, const void *data_block, size_t block_word_len, bool first_block); + +/** + * @brief Polls and waits until the SHA engine is idle + * + */ +void sha_hal_wait_idle(void); + +/** + * @brief Reads the current message digest from the SHA engine + * + * @param sha_type SHA algorithm used + * @param digest_state Output buffer to which to read message digest to + */ +void sha_hal_read_digest(esp_sha_type sha_type, void *digest_state); + +#if SOC_SHA_SUPPORT_RESUME +/** + * @brief Writes the message digest to the SHA engine + * + * @param sha_type The SHA algorithm type + * @param digest_state Message digest to be written to SHA engine + */ +void sha_hal_write_digest(esp_sha_type sha_type, void *digest_state); +#endif + +#if SOC_SHA_SUPPORT_DMA +/** + * @brief Hashes a number of message blocks using DMA + * + * @param sha_type SHA algorithm to hash with + * @param input Input message to be hashed + * @param num_blocks Number of blocks to hash + * @param first_block Is this the first block in a message or a continuation? + */ +void sha_hal_hash_dma(esp_sha_type sha_type, lldesc_t *input, size_t num_blocks, bool first_block); +#endif + +#if SOC_SHA_SUPPORT_SHA512_T +/** + * @brief Calculates and sets the initial digiest for SHA512_t + * + * @param t_string + * @param t_len + */ +void sha_hal_sha512_init_hash(uint32_t t_string, uint8_t t_len); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/i2c_saradc.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/i2c_saradc.h new file mode 100644 index 00000000..5aa64517 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/i2c_saradc.h @@ -0,0 +1,77 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_sar.h + * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC. + * + * This file lists register fields of SAR, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * function in adc_ll.h. + */ + +#define I2C_SAR_ADC 0X69 +#define I2C_SAR_ADC_HOSTID 0 + +#define ADC_ANA_CONFIG2_REG 0x6000E048 + +#define ADC_SAR1_ENCAL_GND_ADDR 0x7 +#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5 +#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5 + +#define ADC_SAR2_ENCAL_GND_ADDR 0x7 +#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7 +#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7 + +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3 +#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0 + +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7 +#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0 + +#define ADC_SAR1_DREF_ADDR 0x2 +#define ADC_SAR1_DREF_ADDR_MSB 0x6 +#define ADC_SAR1_DREF_ADDR_LSB 0x4 + +#define ADC_SAR2_DREF_ADDR 0x5 +#define ADC_SAR2_DREF_ADDR_MSB 0x6 +#define ADC_SAR2_DREF_ADDR_LSB 0x4 + +#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 +#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 + +#define ADC_SARADC_DTEST_RTC_ADDR 0x7 +#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1 +#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0 + +#define ADC_SARADC_ENT_TSENS_ADDR 0x7 +#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2 +#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2 + +#define ADC_SARADC_ENT_RTC_ADDR 0x7 +#define ADC_SARADC_ENT_RTC_ADDR_MSB 3 +#define ADC_SARADC_ENT_RTC_ADDR_LSB 3 diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cpu.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cpu.h deleted file mode 100644 index a09e458b..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cpu.h +++ /dev/null @@ -1,142 +0,0 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _SOC_CPU_H -#define _SOC_CPU_H - -#include -#include -#include -#include "xtensa/corebits.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* C macros for xtensa special register read/write/exchange */ - -#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval)); -#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval)); -#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval)); - -/** @brief Read current stack pointer address - * - */ -static inline void *get_sp(void) -{ - void *sp; - asm volatile ("mov %0, sp;" : "=r" (sp)); - return sp; -} - -/* Functions to set page attributes for Region Protection option in the CPU. - * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2). - */ - -static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr) -{ - asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr)); -} - - -static inline void cpu_write_itlb(unsigned vpn, unsigned attr) -{ - asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); -} - -/** - * @brief Configure memory region protection - * - * Make page 0 access raise an exception. - * Also protect some other unused pages so we can catch weirdness. - * Useful attribute values: - * 0 — cached, RW - * 2 — bypass cache, RWX (default value after CPU reset) - * 15 — no access, raise exception - */ - -static inline void cpu_configure_region_protection(void) -{ - const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000}; - for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) { - cpu_write_dtlb(pages_to_protect[i], 0xf); - cpu_write_itlb(pages_to_protect[i], 0xf); - } - cpu_write_dtlb(0x20000000, 0); - cpu_write_itlb(0x20000000, 0); -} - -/** - * @brief Stall CPU using RTC controller - * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP) - */ -void esp_cpu_stall(int cpu_id); - -/** - * @brief Un-stall CPU using RTC controller - * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP) - */ -void esp_cpu_unstall(int cpu_id); - -/** - * @brief Reset CPU using RTC controller - * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP) - */ -void esp_cpu_reset(int cpu_id); - - -/** - * @brief Returns true if a JTAG debugger is attached to CPU - * OCD (on chip debug) port. - * - * @note If "Make exception and panic handlers JTAG/OCD aware" - * is disabled, this function always returns false. - */ -bool esp_cpu_in_ocd_debug_mode(void); - -/** - * @brief Convert the PC register value to its true address - * - * The address of the current instruction is not stored as an exact uint32_t - * representation in PC register. This function will convert the value stored in - * the PC register to a uint32_t address. - * - * @param pc_raw The PC as stored in register format. - * - * @return Address in uint32_t format - */ -static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc) -{ - if (pc & 0x80000000) { - //Top two bits of a0 (return address) specify window increment. Overwrite to map to address space. - pc = (pc & 0x3fffffff) | 0x40000000; - } - //Minus 3 to get PC of previous instruction (i.e. instruction executed before return address) - return pc - 3; -} - -typedef uint32_t esp_cpu_ccount_t; - -static inline esp_cpu_ccount_t esp_cpu_get_ccount(void) -{ - uint32_t result; - RSR(CCOUNT, result); - return result; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/efuse_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/efuse_reg.h index 84414c7d..4f92f812 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/efuse_reg.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/efuse_reg.h @@ -917,12 +917,24 @@ extern "C" { #define EFUSE_SPI_PAD_CONF_1_S 0 #define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x050) -/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */ -/*description: Stores the fist 14 bits of the zeroth part of system data.*/ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF +/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:25] ;default: 7'h0 ; */ +/*description: Stores the fist 7 bits of the zeroth part of system data.*/ +#define EFUSE_SYS_DATA_PART0_0 0x0000007F #define EFUSE_SYS_DATA_PART0_0_M ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S)) -#define EFUSE_SYS_DATA_PART0_0_V 0x3FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_SYS_DATA_PART0_0_V 0x7F +#define EFUSE_SYS_DATA_PART0_0_S 25 +/* EFUSE_PKG_VERSION : RO ;bitpos:[24:21] ;default: 4'h0 ; */ +/*description: Package version 0:ESP32-S2, 1:ESP32-S2FH16, 2:ESP32-S2FH32 */ +#define EFUSE_PKG_VERSION 0x0000000F +#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S)) +#define EFUSE_PKG_VERSION_V 0xF +#define EFUSE_PKG_VERSION_S 21 +/* EFUSE_WAFER_VERSION : RO ;bitpos:[20:18] ;default: 3'h0 ; */ +/*description: WAFER version 0:A */ +#define EFUSE_WAFER_VERSION 0x00000007 +#define EFUSE_WAFER_VERSION_M ((EFUSE_WAFER_VERSION_V)<<(EFUSE_WAFER_VERSION_S)) +#define EFUSE_WAFER_VERSION_V 0x7 +#define EFUSE_WAFER_VERSION_S 18 /* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */ /*description: Stores the second part of SPI_PAD_CONF.*/ #define EFUSE_SPI_PAD_CONF_2 0x0003FFFF diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rsa_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rsa_caps.h new file mode 100644 index 00000000..475dc4fe --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rsa_caps.h @@ -0,0 +1,26 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + + +#define SOC_RSA_MAX_BIT_LEN (4096) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sha_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sha_caps.h new file mode 100644 index 00000000..10118590 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sha_caps.h @@ -0,0 +1,54 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* ESP32 style SHA engine, where multiple states can be stored in parallel */ +#define SOC_SHA_SUPPORT_PARALLEL_ENG (0) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has "crypto DMA", which is shared with AES */ +#define SOC_SHA_CRYPTO_DMA (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GENERAL_DMA (0) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) +#define SOC_SHA_SUPPORT_SHA384 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) +#define SOC_SHA_SUPPORT_SHA512 (1) +#define SOC_SHA_SUPPORT_SHA512_224 (1) +#define SOC_SHA_SUPPORT_SHA512_256 (1) +#define SOC_SHA_SUPPORT_SHA512_T (1) + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h index 1db40881..a8c4cd7b 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h @@ -270,6 +270,8 @@ #define SOC_EXTRAM_DATA_LOW 0x3F500000 #define SOC_EXTRAM_DATA_HIGH 0x3FF80000 +#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) + //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40020000 #define SOC_DIRAM_IRAM_HIGH 0x40070000 diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h index 4d0b9fc4..86e111db 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h @@ -6,7 +6,10 @@ #pragma once #define SOC_TWAI_SUPPORTED 1 +#define SOC_CP_DMA_SUPPORTED 1 #define SOC_CPU_CORES_NUM 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_RISCV_COPROC_SUPPORTED 1 #define SOC_USB_SUPPORTED 1 + +#define SOC_CACHE_SUPPORT_WRAP 1 \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/i2c_rtc_clk.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/i2c_rtc_clk.h index 0fff0eb0..11d6af18 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/i2c_rtc_clk.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/i2c_rtc_clk.h @@ -17,6 +17,7 @@ #include "i2c_apll.h" #include "i2c_bbpll.h" #include "i2c_ulp.h" +#include "i2c_saradc.h" #ifdef __cplusplus extern "C" { @@ -31,26 +32,27 @@ extern "C" { /* Clear to enable BBPLL */ #define I2C_BBPLL_M (BIT(17)) -/* ROM functions which read/write internal control bus */ -uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); -uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); -void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); -void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); +/* Read/Write internal control bus */ +uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add); +uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); +void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); +void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); +void i2c_rtc_init(void); /* Convenience macros for the above functions, these use register definitions * from i2c_apll.h/i2c_bbpll.h header files. */ #define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ - rom_i2c_writeReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + i2c_rtc_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) #define I2C_READREG_MASK_RTC(block, reg_add) \ - rom_i2c_readReg_Mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + i2c_rtc_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) #define I2C_WRITEREG_RTC(block, reg_add, indata) \ - rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) + i2c_rtc_write_reg(block, block##_HOSTID, reg_add, indata) #define I2C_READREG_RTC(block, reg_add) \ - rom_i2c_readReg(block, block##_HOSTID, reg_add) + i2c_rtc_read_reg(block, block##_HOSTID, reg_add) #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/memprot_peri_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/memprot_peri_ll.h new file mode 100644 index 00000000..35dc03ce --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/memprot_peri_ll.h @@ -0,0 +1,453 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTCSLOW_MEMORY_SIZE 0x00002000 + +/** + * ======================================================================================== + * === PeriBus1 common + * ======================================================================================== + */ +//PeriBus1 interrupt status bitmasks +#define PERI1_INTR_ST_OP_TYPE_BIT BIT(4) //0: non-atomic, 1: atomic +#define PERI1_INTR_ST_OP_HIGH_BITS BIT(5) //0: high bits = unchanged, 1: high bits = 0x03F40000 +#define PERI1_INTR_ST_FAULTADDR_M 0x03FFFFC0 //(bits 25:6 in the reg) +#define PERI1_INTR_ST_FAULTADDR_S 0x4 //(bits 21:2 of real address) + +static inline void esp_memprot_peri1_clear_intr(void) +{ + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR); +} + +static inline uint32_t esp_memprot_peri1_get_intr_source_num(void) +{ + return ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE; +} + +static inline void esp_memprot_peri1_intr_ena(bool enable) +{ + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN); + } +} + +static inline uint32_t esp_memprot_peri1_get_ctrl_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_6_REG); +} + +static inline uint32_t esp_memprot_peri1_get_fault_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_7_REG); +} + +static inline void esp_memprot_peri1_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype) +{ + uint32_t status_bits = esp_memprot_peri1_get_fault_reg(); + //*op_type = (uint32_t)status_bits & PERI1_INTR_ST_OP_RW_BIT; + *op_type = 0; + //! DPORT_PMS_PRO_DPORT_7_REG is missing op_type bit + *op_subtype = (uint32_t)status_bits & PERI1_INTR_ST_OP_TYPE_BIT; +} + +static inline bool esp_memprot_peri1_is_assoc_intr(void) +{ + return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DPORT_7_REG, DPORT_PMS_PRO_DPORT_ILG_INTR) > 0; +} + +static inline uint32_t esp_memprot_peri1_get_intr_ena_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_EN); +} + +static inline uint32_t esp_memprot_peri1_get_intr_on_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_INTR); +} + +static inline uint32_t esp_memprot_peri1_get_intr_clr_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_6_REG, DPORT_PMS_PRO_DPORT_ILG_CLR); +} + +static inline uint32_t esp_memprot_peri1_get_lock_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG); +} + +//resets automatically on CPU restart +static inline void esp_memprot_peri1_set_lock(void) +{ + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK); +} + +static inline uint32_t esp_memprot_peri1_get_lock_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_0_REG, DPORT_PMS_PRO_DPORT_LOCK); +} + + +/** + * ======================================================================================== + * === PeriBus1 RTC SLOW + * ======================================================================================== + */ +#define PERI1_RTCSLOW_ADDRESS_BASE 0x3F421000 +#define PERI1_RTCSLOW_ADDRESS_LOW PERI1_RTCSLOW_ADDRESS_BASE +#define PERI1_RTCSLOW_ADDRESS_HIGH PERI1_RTCSLOW_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE +#define PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 0x3F400000 + + +static inline uint32_t *esp_memprot_peri1_rtcslow_get_fault_address(void) +{ + uint32_t status_bits = esp_memprot_peri1_get_fault_reg(); + uint32_t fault_address = (status_bits & PERI1_INTR_ST_FAULTADDR_M) >> PERI1_INTR_ST_FAULTADDR_S; + uint32_t high_bits = (status_bits & PERI1_INTR_ST_OP_HIGH_BITS) ? PERI1_RTCSLOW_INTR_ST_FAULTADDR_HI_0 : 0; + return (uint32_t *)(fault_address | high_bits); +} + +static inline bool esp_memprot_peri1_rtcslow_is_intr_mine(void) +{ + if (esp_memprot_dram0_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_peri1_rtcslow_get_fault_address(); + return (uint32_t)faulting_address >= PERI1_RTCSLOW_ADDRESS_LOW && (uint32_t)faulting_address <= PERI1_RTCSLOW_ADDRESS_HIGH; + } + return false; +} + +static inline void esp_memprot_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) +{ + uint32_t addr = (uint32_t)split_addr; + + //check split address is WORD aligned + uint32_t reg_split_addr = addr >> 2; + assert(addr == (reg_split_addr << 2)); + reg_split_addr &= DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_M; + + //prepare high & low permission mask + uint32_t permission_mask = 0; + if (lw) { + permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_W; + } + if (lr) { + permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_L_R; + } + if (hw) { + permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_W; + } + if (hr) { + permission_mask |= DPORT_PMS_PRO_DPORT_RTCSLOW_H_R; + } + + //write PERIBUS1 RTC SLOW cfg register + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG, reg_split_addr | permission_mask); +} + +static inline void esp_memprot_peri1_rtcslow_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) +{ + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R); +} + +static inline void esp_memprot_peri1_rtcslow_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_peri1_rtcslow_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DPORT_1_REG, DPORT_PMS_PRO_DPORT_RTCSLOW_H_W, hw ? 1 : 0); +} + +static inline uint32_t esp_memprot_peri1_rtcslow_get_conf_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG); +} + + +/** + * ======================================================================================== + * === PeriBus2 common + * ======================================================================================== + */ +//PeriBus2 interrupt status bitmasks +#define PERI2_INTR_ST_OP_TYPE_BIT BIT(1) //instruction: 0, data: 1 +#define PERI2_INTR_ST_OP_RW_BIT BIT(0) //read: 0, write: 1 +#define PERI2_INTR_ST_FAULTADDR_M 0xFFFFFFFC //(bits 31:2 in the reg) + +static inline void esp_memprot_peri2_clear_intr(void) +{ + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR); +} + +static inline uint32_t esp_memprot_peri2_get_intr_source_num(void) +{ + return ETS_PMS_PRO_AHB_ILG_INTR_SOURCE; +} + +static inline void esp_memprot_peri2_intr_ena(bool enable) +{ + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN); + } +} + +static inline uint32_t esp_memprot_peri2_get_ctrl_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_3_REG); +} + +static inline uint32_t esp_memprot_peri2_get_fault_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_4_REG); +} + +static inline void esp_memprot_peri2_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype) +{ + uint32_t status_bits = esp_memprot_peri2_get_fault_reg(); + *op_type = (uint32_t)status_bits & PERI2_INTR_ST_OP_RW_BIT; + *op_subtype = (uint32_t)status_bits & PERI2_INTR_ST_OP_TYPE_BIT; +} + +static inline bool esp_memprot_peri2_is_assoc_intr(void) +{ + return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR) > 0; +} + +static inline uint32_t esp_memprot_peri2_get_intr_ena_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_EN); +} + +static inline uint32_t esp_memprot_peri2_get_intr_on_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_INTR); +} + +static inline uint32_t esp_memprot_peri2_get_intr_clr_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_3_REG, DPORT_PMS_PRO_AHB_ILG_CLR); +} + +static inline uint32_t esp_memprot_peri2_get_lock_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_AHB_0_REG); +} + +//resets automatically on CPU restart +static inline void esp_memprot_peri2_set_lock(void) +{ + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK); +} + +static inline uint32_t esp_memprot_peri2_get_lock_bit(void) +{ + return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_0_REG, DPORT_PMS_PRO_AHB_LOCK); +} + +static inline uint32_t *esp_memprot_peri2_rtcslow_get_fault_address(void) +{ + uint32_t status_bits = esp_memprot_peri2_get_fault_reg(); + return (uint32_t *)(status_bits & PERI2_INTR_ST_FAULTADDR_M); +} + + +/** + * ======================================================================================== + * === PeriBus2 RTC SLOW 0 (AHB0) + * ======================================================================================== + */ +#define PERI2_RTCSLOW_0_ADDRESS_BASE 0x50000000 +#define PERI2_RTCSLOW_0_ADDRESS_LOW PERI2_RTCSLOW_0_ADDRESS_BASE +#define PERI2_RTCSLOW_0_ADDRESS_HIGH PERI2_RTCSLOW_0_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE + +static inline bool esp_memprot_peri2_rtcslow_0_is_intr_mine(void) +{ + if (esp_memprot_peri2_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_peri2_rtcslow_get_fault_address(); + return (uint32_t)faulting_address >= PERI2_RTCSLOW_0_ADDRESS_LOW && (uint32_t)faulting_address <= PERI2_RTCSLOW_0_ADDRESS_HIGH; + } + return false; +} + +static inline void esp_memprot_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +{ + uint32_t addr = (uint32_t)split_addr; + + //check split address is WORD aligned + uint32_t reg_split_addr = addr >> 2; + assert(addr == (reg_split_addr << 2)); + reg_split_addr &= DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_M; + + //prepare high & low permission mask + uint32_t permission_mask = 0; + if (lw) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W; + } + if (lr) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R; + } + if (lx) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F; + } + if (hw) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W; + } + if (hr) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R; + } + if (hx) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F; + } + + //write PERIBUS1 RTC SLOW cfg register + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_1_REG, reg_split_addr | permission_mask); +} + +static inline void esp_memprot_peri2_rtcslow_0_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) +{ + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R); + *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R); + *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F); +} + +static inline void esp_memprot_peri2_rtcslow_0_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_peri2_rtcslow_0_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W, hw ? 1 : 0); +} + +static inline void esp_memprot_peri2_rtcslow_0_set_exec_perm(bool lx, bool hx) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F, lx ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_1_REG, DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F, hx ? 1 : 0); +} + +static inline uint32_t esp_memprot_peri2_rtcslow_0_get_conf_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG); +} + +/** + * ======================================================================================== + * === PeriBus2 RTC SLOW 1 (AHB1) + * ======================================================================================== + */ +#define PERI2_RTCSLOW_1_ADDRESS_BASE 0x60021000 +#define PERI2_RTCSLOW_1_ADDRESS_LOW PERI2_RTCSLOW_1_ADDRESS_BASE +#define PERI2_RTCSLOW_1_ADDRESS_HIGH PERI2_RTCSLOW_1_ADDRESS_LOW + RTCSLOW_MEMORY_SIZE + + +static inline bool esp_memprot_peri2_rtcslow_1_is_intr_mine(void) +{ + if (esp_memprot_peri2_is_assoc_intr()) { + uint32_t *faulting_address = esp_memprot_peri2_rtcslow_get_fault_address(); + return (uint32_t)faulting_address >= PERI2_RTCSLOW_1_ADDRESS_LOW && (uint32_t)faulting_address <= PERI2_RTCSLOW_1_ADDRESS_HIGH; + } + return false; +} + +static inline void esp_memprot_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +{ + uint32_t addr = (uint32_t)split_addr; + + //check split address is WORD aligned + uint32_t reg_split_addr = addr >> 2; + assert(addr == (reg_split_addr << 2)); + reg_split_addr &= DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_M; + + //prepare high & low permission mask + uint32_t permission_mask = 0; + if (lw) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W; + } + if (lr) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R; + } + if (lx) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F; + } + if (hw) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W; + } + if (hr) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R; + } + if (hx) { + permission_mask |= DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F; + } + + //write PERIBUS1 RTC SLOW cfg register + DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_2_REG, reg_split_addr | permission_mask); +} + +static inline void esp_memprot_peri2_rtcslow_1_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) +{ + *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W); + *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R); + *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F); + *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W); + *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R); + *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F); +} + +static inline void esp_memprot_peri2_rtcslow_1_set_read_perm(bool lr, bool hr) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R, lr ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R, hr ? 1 : 0); +} + +static inline void esp_memprot_peri2_rtcslow_1_set_write_perm(bool lw, bool hw) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W, lw ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W, hw ? 1 : 0); +} + +static inline void esp_memprot_peri2_rtcslow_1_set_exec_perm(bool lx, bool hx) +{ + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F, lx ? 1 : 0); + DPORT_REG_SET_FIELD(DPORT_PMS_PRO_AHB_2_REG, DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F, hx ? 1 : 0); +} + +static inline uint32_t esp_memprot_peri2_rtcslow_1_get_conf_reg(void) +{ + return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DPORT_2_REG); +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/spi_flash/include/esp_partition.h b/tools/sdk/esp32s2/include/spi_flash/include/esp_partition.h index 72c543bd..930f7d69 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/esp_partition.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/esp_partition.h @@ -202,6 +202,9 @@ const esp_partition_t *esp_partition_verify(const esp_partition_t *partition); /** * @brief Read data from the partition * + * Partitions marked with an encryption flag will automatically be + * be read and decrypted via a cache mapping. + * * @param partition Pointer to partition structure obtained using * esp_partition_find_first or esp_partition_get. * Must be non-NULL. @@ -250,7 +253,59 @@ esp_err_t esp_partition_read(const esp_partition_t* partition, * or one of error codes from lower-level flash driver. */ esp_err_t esp_partition_write(const esp_partition_t* partition, - size_t dst_offset, const void* src, size_t size); + size_t dst_offset, const void* src, size_t size); + +/** + * @brief Read data from the partition + * + * @note This function is essentially the same as \c esp_partition_write() above. + * It just never decrypts data but returns it as is. + * + * @param partition Pointer to partition structure obtained using + * esp_partition_find_first or esp_partition_get. + * Must be non-NULL. + * @param dst Pointer to the buffer where data should be stored. + * Pointer must be non-NULL and buffer must be at least 'size' bytes long. + * @param src_offset Address of the data to be read, relative to the + * beginning of the partition. + * @param size Size of data to be read, in bytes. + * + * @return ESP_OK, if data was read successfully; + * ESP_ERR_INVALID_ARG, if src_offset exceeds partition size; + * ESP_ERR_INVALID_SIZE, if read would go out of bounds of the partition; + * or one of error codes from lower-level flash driver. + */ +esp_err_t esp_partition_read_raw(const esp_partition_t* partition, + size_t src_offset, void* dst, size_t size); + +/** + * @brief Write data to the partition without any transformation/encryption. + * + * @note This function is essentially the same as \c esp_partition_write() above. + * It just never encrypts data but writes it as is. + * + * Before writing data to flash, corresponding region of flash needs to be erased. + * This can be done using esp_partition_erase_range function. + * + * @param partition Pointer to partition structure obtained using + * esp_partition_find_first or esp_partition_get. + * Must be non-NULL. + * @param dst_offset Address where the data should be written, relative to the + * beginning of the partition. + * @param src Pointer to the source buffer. Pointer must be non-NULL and + * buffer must be at least 'size' bytes long. + * @param size Size of data to be written, in bytes. + * + * @note Prior to writing to flash memory, make sure it has been erased with + * esp_partition_erase_range call. + * + * @return ESP_OK, if data was written successfully; + * ESP_ERR_INVALID_ARG, if dst_offset exceeds partition size; + * ESP_ERR_INVALID_SIZE, if write would go out of bounds of the partition; + * or one of the error codes from lower-level flash driver. + */ +esp_err_t esp_partition_write_raw(const esp_partition_t* partition, + size_t dst_offset, const void* src, size_t size); /** * @brief Erase part of the partition diff --git a/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h b/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h index 814502d2..372a1e1b 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h @@ -188,6 +188,7 @@ esp_err_t spi_flash_chip_generic_set_write_protect(esp_flash_t *chip, bool write */ esp_err_t spi_flash_chip_generic_get_write_protect(esp_flash_t *chip, bool *out_write_protect); +#define ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT -1 /** * @brief Read flash status via the RDSR command and wait for bit 0 (write in * progress bit) to be cleared. diff --git a/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_ssl.h b/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_ssl.h index ff3f9d62..4d53d4d2 100644 --- a/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_ssl.h +++ b/tools/sdk/esp32s2/include/tcp_transport/include/esp_transport_ssl.h @@ -141,6 +141,16 @@ void esp_transport_ssl_skip_common_name_check(esp_transport_handle_t t); */ void esp_transport_ssl_use_secure_element(esp_transport_handle_t t); + +/** + * @brief Set the ds_data handle in ssl context.(used for the digital signature operation) + * + * @param t ssl transport + * ds_data the handle for ds data params + */ + +void esp_transport_ssl_set_ds_data(esp_transport_handle_t t, void *ds_data); + /** * @brief Set PSK key and hint for PSK server/client verification in esp-tls component. * Important notes: diff --git a/tools/sdk/esp32s2/include/ulp/include/esp32s3/ulp.h b/tools/sdk/esp32s2/include/ulp/include/esp32s3/ulp.h new file mode 100644 index 00000000..9207a00e --- /dev/null +++ b/tools/sdk/esp32s2/include/ulp/include/esp32s3/ulp.h @@ -0,0 +1,840 @@ +// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include +#include "esp_err.h" +#include "soc/soc.h" +#include "ulp_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ULP_FSM_PREPARE_SLEEP_CYCLES 2 /*!< Cycles spent by FSM preparing ULP for sleep */ +#define ULP_FSM_WAKEUP_SLEEP_CYCLES 2 /*!< Cycles spent by FSM waking up ULP from sleep */ + +/** + * @defgroup ulp_registers ULP coprocessor registers + * @{ + */ + + +#define R0 0 /*!< general purpose register 0 */ +#define R1 1 /*!< general purpose register 1 */ +#define R2 2 /*!< general purpose register 2 */ +#define R3 3 /*!< general purpose register 3 */ +/**@}*/ + +/** @defgroup ulp_opcodes ULP coprocessor opcodes, sub opcodes, and various modifiers/flags + * + * These definitions are not intended to be used directly. + * They are used in definitions of instructions later on. + * + * @{ + */ + +#define OPCODE_WR_REG 1 /*!< Instruction: write peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define OPCODE_RD_REG 2 /*!< Instruction: read peripheral register (RTC_CNTL/RTC_IO/SARADC) (not implemented yet) */ + +#define RD_REG_PERIPH_RTC_CNTL 0 /*!< Identifier of RTC_CNTL peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_IO 1 /*!< Identifier of RTC_IO peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_SENS 2 /*!< Identifier of SARADC peripheral for RD_REG and WR_REG instructions */ +#define RD_REG_PERIPH_RTC_I2C 3 /*!< Identifier of RTC_I2C peripheral for RD_REG and WR_REG instructions */ + +#define OPCODE_I2C 3 /*!< Instruction: read/write I2C (not implemented yet) */ + +#define OPCODE_DELAY 4 /*!< Instruction: delay (nop) for a given number of cycles */ + +#define OPCODE_ADC 5 /*!< Instruction: SAR ADC measurement (not implemented yet) */ + +#define OPCODE_ST 6 /*!< Instruction: store indirect to RTC memory */ +#define SUB_OPCODE_ST 4 /*!< Store 32 bits, 16 MSBs contain PC, 16 LSBs contain value from source register */ + +#define OPCODE_ALU 7 /*!< Arithmetic instructions */ +#define SUB_OPCODE_ALU_REG 0 /*!< Arithmetic instruction, both source values are in register */ +#define SUB_OPCODE_ALU_IMM 1 /*!< Arithmetic instruction, one source value is an immediate */ +#define SUB_OPCODE_ALU_CNT 2 /*!< Arithmetic instruction between counter register and an immediate (not implemented yet)*/ +#define ALU_SEL_ADD 0 /*!< Addition */ +#define ALU_SEL_SUB 1 /*!< Subtraction */ +#define ALU_SEL_AND 2 /*!< Logical AND */ +#define ALU_SEL_OR 3 /*!< Logical OR */ +#define ALU_SEL_MOV 4 /*!< Copy value (immediate to destination register or source register to destination register */ +#define ALU_SEL_LSH 5 /*!< Shift left by given number of bits */ +#define ALU_SEL_RSH 6 /*!< Shift right by given number of bits */ + +#define OPCODE_BRANCH 8 /*!< Branch instructions */ +#define SUB_OPCODE_BX 0 /*!< Branch to absolute PC (immediate or in register) */ +#define BX_JUMP_TYPE_DIRECT 0 /*!< Unconditional jump */ +#define BX_JUMP_TYPE_ZERO 1 /*!< Branch if last ALU result is zero */ +#define BX_JUMP_TYPE_OVF 2 /*!< Branch if last ALU operation caused and overflow */ +#define SUB_OPCODE_B 1 /*!< Branch to a relative offset */ +#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */ +#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */ + +#define OPCODE_END 9 /*!< Stop executing the program */ +#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */ +#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */ + +#define OPCODE_TSENS 10 /*!< Instruction: temperature sensor measurement (not implemented yet) */ + +#define OPCODE_HALT 11 /*!< Halt the coprocessor */ + +#define OPCODE_LD 13 /*!< Indirect load lower 16 bits from RTC memory */ + +#define OPCODE_MACRO 15 /*!< Not a real opcode. Used to identify labels and branches in the program */ +#define SUB_OPCODE_MACRO_LABEL 0 /*!< Label macro */ +#define SUB_OPCODE_MACRO_BRANCH 1 /*!< Branch macro */ +/**@}*/ + +/** + * @brief Instruction format structure + * + * All ULP instructions are 32 bit long. + * This union contains field layouts used by all of the supported instructions. + * This union also includes a special "macro" instruction layout. + * This is not a real instruction which can be executed by the CPU. It acts + * as a token which is removed from the program by the + * ulp_process_macros_and_load function. + * + * These structures are not intended to be used directly. + * Preprocessor definitions provided below fill the fields of these structure with + * the right arguments. + */ +union ulp_insn { + + struct { + uint32_t cycles : 16; /*!< Number of cycles to sleep */ + uint32_t unused : 12; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_DELAY) */ + } delay; /*!< Format of DELAY instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains data to store */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ST) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ST) */ + } st; /*!< Format of ST instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where the data should be loaded to */ + uint32_t sreg : 2; /*!< Register which contains address in RTC memory (expressed in words) */ + uint32_t unused1 : 6; /*!< Unused */ + uint32_t offset : 11; /*!< Offset to add to sreg */ + uint32_t unused2 : 7; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_LD) */ + } ld; /*!< Format of LD instruction */ + + struct { + uint32_t unused : 28; /*!< Unused */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_HALT) */ + } halt; /*!< Format of HALT instruction */ + + struct { + uint32_t dreg : 2; /*!< Register which contains target PC, expressed in words (used if .reg == 1) */ + uint32_t addr : 11; /*!< Target PC, expressed in words (used if .reg == 0) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t reg : 1; /*!< Target PC in register (1) or immediate (0) */ + uint32_t type : 3; /*!< Jump condition (BX_JUMP_TYPE_xxx) */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_BX) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } bx; /*!< Format of BRANCH instruction (absolute address) */ + + struct { + uint32_t imm : 16; /*!< Immediate value to compare against */ + uint32_t cmp : 1; /*!< Comparison to perform: B_CMP_L or B_CMP_GE */ + uint32_t offset : 7; /*!< Absolute value of target PC offset w.r.t. current PC, expressed in words */ + uint32_t sign : 1; /*!< Sign of target PC offset: 0: positive, 1: negative */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_B) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_BRANCH) */ + } b; /*!< Format of BRANCH instruction (relative address) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t treg : 2; /*!< Register with operand B */ + uint32_t unused : 15; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_REG) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_reg; /*!< Format of ALU instruction (both sources are registers) */ + + struct { + uint32_t dreg : 2; /*!< Destination register */ + uint32_t sreg : 2; /*!< Register with operand A */ + uint32_t imm : 16; /*!< Immediate value of operand B */ + uint32_t unused : 1; /*!< Unused */ + uint32_t sel : 4; /*!< Operation to perform, one of ALU_SEL_xxx */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_ALU_IMM) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_ALU) */ + } alu_imm; /*!< Format of ALU instruction (one source is an immediate) */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t data : 8; /*!< 8 bits of data to write */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } wr_reg; /*!< Format of WR_REG instruction */ + + struct { + uint32_t addr : 8; /*!< Address within either RTC_CNTL, RTC_IO, or SARADC */ + uint32_t periph_sel : 2; /*!< Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2) */ + uint32_t unused : 8; /*!< Unused */ + uint32_t low : 5; /*!< Low bit */ + uint32_t high : 5; /*!< High bit */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_WR_REG) */ + } rd_reg; /*!< Format of RD_REG instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store ADC result */ + uint32_t mux : 4; /*!< Select SARADC pad (mux + 1) */ + uint32_t sar_sel : 1; /*!< Select SARADC0 (0) or SARADC1 (1) */ + uint32_t unused1 : 1; /*!< Unused */ + uint32_t cycles : 16; /*!< TBD, cycles used for measurement */ + uint32_t unused2 : 4; /*!< Unused */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_ADC) */ + } adc; /*!< Format of ADC instruction */ + + struct { + uint32_t dreg : 2; /*!< Register where to store temperature measurement result */ + uint32_t wait_delay: 14; /*!< Cycles to wait after measurement is done */ + uint32_t reserved: 12; /*!< Reserved, set to 0 */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_TSENS) */ + } tsens; /*!< Format of TSENS instruction */ + + struct { + uint32_t i2c_addr : 8; /*!< I2C slave address */ + uint32_t data : 8; /*!< Data to read or write */ + uint32_t low_bits : 3; /*!< TBD */ + uint32_t high_bits : 3; /*!< TBD */ + uint32_t i2c_sel : 4; /*!< TBD, select reg_i2c_slave_address[7:0] */ + uint32_t unused : 1; /*!< Unused */ + uint32_t rw : 1; /*!< Write (1) or read (0) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_I2C) */ + } i2c; /*!< Format of I2C instruction */ + + struct { + uint32_t wakeup : 1; /*!< Set to 1 to wake up chip */ + uint32_t unused : 24; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_WAKEUP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } end; /*!< Format of END instruction with wakeup */ + + struct { + uint32_t cycle_sel : 4; /*!< Select which one of SARADC_ULP_CP_SLEEP_CYCx_REG to get the sleep duration from */ + uint32_t unused : 21; /*!< Unused */ + uint32_t sub_opcode : 3; /*!< Sub opcode (SUB_OPCODE_SLEEP) */ + uint32_t opcode : 4; /*!< Opcode (OPCODE_END) */ + } sleep; /*!< Format of END instruction with sleep */ + + struct { + uint32_t label : 16; /*!< Label number */ + uint32_t unused : 8; /*!< Unused */ + uint32_t sub_opcode : 4; /*!< SUB_OPCODE_MACRO_LABEL or SUB_OPCODE_MACRO_BRANCH */ + uint32_t opcode: 4; /*!< Opcode (OPCODE_MACRO) */ + } macro; /*!< Format of tokens used by LABEL and BRANCH macros */ + +}; + +typedef union ulp_insn ulp_insn_t; + +_Static_assert(sizeof(ulp_insn_t) == 4, "ULP coprocessor instruction size should be 4 bytes"); + +/** + * Delay (nop) for a given number of cycles + */ +#define I_DELAY(cycles_) { .delay = {\ + .cycles = cycles_, \ + .unused = 0, \ + .opcode = OPCODE_DELAY } } + +/** + * Halt the coprocessor. + * + * This instruction halts the coprocessor, but keeps ULP timer active. + * As such, ULP program will be restarted again by timer. + * To stop the program and prevent the timer from restarting the program, + * use I_END(0) instruction. + */ +#define I_HALT() { .halt = {\ + .unused = 0, \ + .opcode = OPCODE_HALT } } + +/** + * Map SoC peripheral register to periph_sel field of RD_REG and WR_REG + * instructions. + * + * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. + * @return periph_sel value for the peripheral to which this register belongs. + */ +static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) +{ + uint32_t ret = 3; + if (reg < DR_REG_RTCCNTL_BASE) { + assert(0 && "invalid register base"); + } else if (reg < DR_REG_RTCIO_BASE) { + ret = RD_REG_PERIPH_RTC_CNTL; + } else if (reg < DR_REG_SENS_BASE) { + ret = RD_REG_PERIPH_RTC_IO; + } else if (reg < DR_REG_RTC_I2C_BASE) { + ret = RD_REG_PERIPH_SENS; + } else if (reg < DR_REG_IO_MUX_BASE) { + ret = RD_REG_PERIPH_RTC_I2C; + } else { + assert(0 && "invalid register base"); + } + return ret; +} + +/** + * Write literal value to a peripheral register + * + * reg[high_bit : low_bit] = val + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .data = val, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_WR_REG } } + +/** + * Read from peripheral register into R0 + * + * R0 = reg[high_bit : low_bit] + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\ + .addr = (reg & 0xff) / sizeof(uint32_t), \ + .periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \ + .unused = 0, \ + .low = low_bit, \ + .high = high_bit, \ + .opcode = OPCODE_RD_REG } } + +/** + * Set or clear a bit in the peripheral register. + * + * Sets bit (1 << shift) of register reg to value val. + * This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers. + */ +#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val) + +/** + * Wake the SoC from deep sleep. + * + * This instruction initiates wake up from deep sleep. + * Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup + * triggered by the ULP before going into deep sleep. + * Note that ULP program will still keep running until the I_HALT + * instruction, and it will still be restarted by timer at regular + * intervals, even when the SoC is woken up. + * + * To stop the ULP program, use I_HALT instruction. + * + * To disable the timer which start ULP program, use I_END() + * instruction. I_END instruction clears the + * RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG + * register, which controls the ULP timer. + */ +#define I_WAKE() { .end = { \ + .wakeup = 1, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_END, \ + .opcode = OPCODE_END } } + +/** + * Stop ULP program timer. + * + * This is a convenience macro which disables the ULP program timer. + * Once this instruction is used, ULP program will not be restarted + * anymore until ulp_run function is called. + * + * ULP program will continue running after this instruction. To stop + * the currently running program, use I_HALT(). + */ +#define I_END() \ + I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0) +/** + * Select the time interval used to run ULP program. + * + * This instructions selects which of the SENS_SLEEP_CYCLES_Sx + * registers' value is used by the ULP program timer. + * When the ULP program stops at I_HALT instruction, ULP program + * timer start counting. When the counter reaches the value of + * the selected SENS_SLEEP_CYCLES_Sx register, ULP program + * start running again from the start address (passed to the ulp_run + * function). + * There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5. + * + * By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP + * program timer. + */ +#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \ + .cycle_sel = timer_idx, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_SLEEP, \ + .opcode = OPCODE_END } } + +/** + * Perform temperature sensor measurement and store it into reg_dest. + * + * Delay can be set between 1 and ((1 << 14) - 1). Higher values give + * higher measurement resolution. + */ +#define I_TSENS(reg_dest, delay) { .tsens = { \ + .dreg = reg_dest, \ + .wait_delay = delay, \ + .reserved = 0, \ + .opcode = OPCODE_TSENS } } + +/** + * Perform ADC measurement and store result in reg_dest. + * + * adc_idx selects ADC (0 or 1). + * pad_idx selects ADC pad (0 - 7). + */ +#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\ + .dreg = reg_dest, \ + .mux = pad_idx + 1, \ + .sar_sel = adc_idx, \ + .unused1 = 0, \ + .cycles = 0, \ + .unused2 = 0, \ + .opcode = OPCODE_ADC } } + +/** + * Store value from register reg_val into RTC memory. + * + * The value is written to an offset calculated by adding value of + * reg_addr register and offset_ field (this offset is expressed in 32-bit words). + * 32 bits written to RTC memory are built as follows: + * - bits [31:21] hold the PC of current instruction, expressed in 32-bit words + * - bits [20:16] = 5'b1 + * - bits [15:0] are assigned the contents of reg_val + * + * RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] } + */ +#define I_ST(reg_val, reg_addr, offset_) { .st = { \ + .dreg = reg_val, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .sub_opcode = SUB_OPCODE_ST, \ + .opcode = OPCODE_ST } } + + +/** + * Load value from RTC memory into reg_dest register. + * + * Loads 16 LSBs from RTC memory word given by the sum of value in reg_addr and + * value of offset_. + */ +#define I_LD(reg_dest, reg_addr, offset_) { .ld = { \ + .dreg = reg_dest, \ + .sreg = reg_addr, \ + .unused1 = 0, \ + .offset = offset_, \ + .unused2 = 0, \ + .opcode = OPCODE_LD } } + + +/** + * Branch relative if R0 less than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BL(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_L, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch relative if R0 greater or equal than immediate value. + * + * pc_offset is expressed in words, and can be from -127 to 127 + * imm_value is a 16-bit value to compare R0 against + */ +#define I_BGE(pc_offset, imm_value) { .b = { \ + .imm = imm_value, \ + .cmp = B_CMP_GE, \ + .offset = abs(pc_offset), \ + .sign = (pc_offset >= 0) ? 0 : 1, \ + .sub_opcode = SUB_OPCODE_B, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Unconditional branch to absolute PC, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_DIRECT, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, address in register. + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXZR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU result is zero, immediate address. + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXZI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_ZERO, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, address in register + * + * reg_pc is the register which contains address to jump to. + * Address is expressed in 32-bit words. + */ +#define I_BXFR(reg_pc) { .bx = { \ + .dreg = reg_pc, \ + .addr = 0, \ + .unused = 0, \ + .reg = 1, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + +/** + * Branch to absolute PC if ALU overflow, immediate address + * + * Address imm_pc is expressed in 32-bit words. + */ +#define I_BXFI(imm_pc) { .bx = { \ + .dreg = 0, \ + .addr = imm_pc, \ + .unused = 0, \ + .reg = 0, \ + .type = BX_JUMP_TYPE_OVF, \ + .sub_opcode = SUB_OPCODE_BX, \ + .opcode = OPCODE_BRANCH } } + + +/** + * Addition: dest = src1 + src2 + */ +#define I_ADDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Subtraction: dest = src1 - src2 + */ +#define I_SUBR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND: dest = src1 & src2 + */ +#define I_ANDR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR: dest = src1 | src2 + */ +#define I_ORR(reg_dest, reg_src1, reg_src2) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src1, \ + .treg = reg_src2, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Copy: dest = src + */ +#define I_MOVR(reg_dest, reg_src) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = 0, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left: dest = src << shift + */ +#define I_LSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right: dest = src >> shift + */ +#define I_RSHR(reg_dest, reg_src, reg_shift) { .alu_reg = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .treg = reg_shift, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_REG, \ + .opcode = OPCODE_ALU } } + +/** + * Add register and an immediate value: dest = src1 + imm + */ +#define I_ADDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_ADD, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Subtract register and an immediate value: dest = src - imm + */ +#define I_SUBI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_SUB, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical AND register and an immediate value: dest = src & imm + */ +#define I_ANDI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_AND, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical OR register and an immediate value: dest = src | imm + */ +#define I_ORI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_OR, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Copy an immediate value into register: dest = imm + */ +#define I_MOVI(reg_dest, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = 0, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_MOV, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Logical shift left register value by an immediate: dest = src << imm + */ +#define I_LSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_LSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + + +/** + * Logical shift right register value by an immediate: dest = val >> imm + */ +#define I_RSHI(reg_dest, reg_src, imm_) { .alu_imm = { \ + .dreg = reg_dest, \ + .sreg = reg_src, \ + .imm = imm_, \ + .unused = 0, \ + .sel = ALU_SEL_RSH, \ + .sub_opcode = SUB_OPCODE_ALU_IMM, \ + .opcode = OPCODE_ALU } } + +/** + * Define a label with number label_num. + * + * This is a macro which doesn't generate a real instruction. + * The token generated by this macro is removed by ulp_process_macros_and_load + * function. Label defined using this macro can be used in branch macros defined + * below. + */ +#define M_LABEL(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_LABEL, \ + .opcode = OPCODE_MACRO } } + +/** + * Token macro used by M_B and M_BX macros. Not to be used directly. + */ +#define M_BRANCH(label_num) { .macro = { \ + .label = label_num, \ + .unused = 0, \ + .sub_opcode = SUB_OPCODE_MACRO_BRANCH, \ + .opcode = OPCODE_MACRO } } + +/** + * Macro: branch to label label_num if R0 is less than immediate value. + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BL(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BL(0, imm_value) + +/** + * Macro: branch to label label_num if R0 is greater or equal than immediate value + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BGE(label_num, imm_value) \ + M_BRANCH(label_num), \ + I_BGE(0, imm_value) + +/** + * Macro: unconditional branch to label + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BX(label_num) \ + M_BRANCH(label_num), \ + I_BXI(0) + +/** + * Macro: branch to label if ALU result is zero + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXZ(label_num) \ + M_BRANCH(label_num), \ + I_BXZI(0) + +/** + * Macro: branch to label if ALU overflow + * + * This macro generates two ulp_insn_t values separated by a comma, and should + * be used when defining contents of ulp_insn_t arrays. First value is not a + * real instruction; it is a token which is removed by ulp_process_macros_and_load + * function. + */ +#define M_BXF(label_num) \ + M_BRANCH(label_num), \ + I_BXFI(0) + + + +#define RTC_SLOW_MEM ((uint32_t*) 0x50000000) /*!< RTC slow memory, 8k size */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h b/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h index 2b59f16e..27db5cbf 100644 --- a/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h +++ b/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h @@ -14,6 +14,7 @@ #ifndef __ESP_ATTR_H__ #define __ESP_ATTR_H__ +#include #include "sdkconfig.h" #define ROMFN_ATTR diff --git a/tools/sdk/esp32s2/include/xtensa/include/xtensa/xtensa_api.h b/tools/sdk/esp32s2/include/xtensa/include/xtensa/xtensa_api.h new file mode 100644 index 00000000..7f263b83 --- /dev/null +++ b/tools/sdk/esp32s2/include/xtensa/include/xtensa/xtensa_api.h @@ -0,0 +1,181 @@ +/******************************************************************************* +Copyright (c) 2006-2015 Cadence Design Systems Inc. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +******************************************************************************/ + +/****************************************************************************** + Xtensa-specific API for RTOS ports. +******************************************************************************/ + +#ifndef __XTENSA_API_H__ +#define __XTENSA_API_H__ + +#include +#include +#include "xtensa_context.h" + + +/* Typedef for C-callable interrupt handler function */ +typedef void (*xt_handler)(void *); + +/* Typedef for C-callable exception handler function */ +typedef void (*xt_exc_handler)(XtExcFrame *); + + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified exception. The handler + will be installed on the core that calls this function. + + n - Exception number (type) + f - Handler function address, NULL to uninstall handler. + + The handler will be passed a pointer to the exception frame, which is created + on the stack of the thread that caused the exception. + + If the handler returns, the thread context will be restored and the faulting + instruction will be retried. Any values in the exception frame that are + modified by the handler will be restored as part of the context. For details + of the exception frame structure see xtensa_context.h. +------------------------------------------------------------------------------- +*/ +extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f); + + +/* +------------------------------------------------------------------------------- + Call this function to set a handler for the specified interrupt. The handler + will be installed on the core that calls this function. + + n - Interrupt number. + f - Handler function address, NULL to uninstall handler. + arg - Argument to be passed to handler. +------------------------------------------------------------------------------- +*/ +extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg); + + +/* +------------------------------------------------------------------------------- + Call this function to enable the specified interrupts on the core that runs + this code. + + mask - Bit mask of interrupts to be enabled. +------------------------------------------------------------------------------- +*/ +extern void xt_ints_on(unsigned int mask); + + +/* +------------------------------------------------------------------------------- + Call this function to disable the specified interrupts on the core that runs + this code. + + mask - Bit mask of interrupts to be disabled. +------------------------------------------------------------------------------- +*/ +extern void xt_ints_off(unsigned int mask); + + +/* +------------------------------------------------------------------------------- + Call this function to set the specified (s/w) interrupt. +------------------------------------------------------------------------------- +*/ +static inline void xt_set_intset(unsigned int arg) +{ + xthal_set_intset(arg); +} + + +/* +------------------------------------------------------------------------------- + Call this function to clear the specified (s/w or edge-triggered) + interrupt. +------------------------------------------------------------------------------- +*/ +static inline void xt_set_intclear(unsigned int arg) +{ + xthal_set_intclear(arg); +} + +/* +------------------------------------------------------------------------------- + Call this function to get handler's argument for the specified interrupt. + + n - Interrupt number. +------------------------------------------------------------------------------- +*/ +extern void * xt_get_interrupt_handler_arg(int n); + +/* +------------------------------------------------------------------------------- + Call this function to check if the specified interrupt is free to use. + + intr - Interrupt number. + cpu - cpu number. +------------------------------------------------------------------------------- +*/ +bool xt_int_has_handler(int intr, int cpu); + +/* +------------------------------------------------------------------------------- + Call this function to disable non iram located interrupts. + + newmask - mask containing the interrupts to disable. +------------------------------------------------------------------------------- +*/ +static inline uint32_t xt_int_disable_mask(uint32_t newmask) +{ + uint32_t oldint; + asm volatile ( + "movi %0,0\n" + "xsr %0,INTENABLE\n" //disable all ints first + "rsync\n" + "and a3,%0,%1\n" //mask ints that need disabling + "wsr a3,INTENABLE\n" //write back + "rsync\n" + :"=&r"(oldint):"r"(newmask):"a3"); + + return oldint; +} + +/* +------------------------------------------------------------------------------- + Call this function to enable non iram located interrupts. + + newmask - mask containing the interrupts to enable. +------------------------------------------------------------------------------- +*/ +static inline void xt_int_enable_mask(uint32_t newmask) +{ + asm volatile ( + "movi a3,0\n" + "xsr a3,INTENABLE\n" + "rsync\n" + "or a3,a3,%0\n" + "wsr a3,INTENABLE\n" + "rsync\n" + ::"r"(newmask):"a3"); +} + +#endif /* __XTENSA_API_H__ */ + diff --git a/tools/sdk/esp32s2/include/xtensa/include/xtensa/xtensa_context.h b/tools/sdk/esp32s2/include/xtensa/include/xtensa/xtensa_context.h new file mode 100644 index 00000000..120676da --- /dev/null +++ b/tools/sdk/esp32s2/include/xtensa/include/xtensa/xtensa_context.h @@ -0,0 +1,387 @@ +/******************************************************************************* +Copyright (c) 2006-2015 Cadence Design Systems Inc. + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + + XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES + +This header contains definitions and macros for use primarily by Xtensa +RTOS assembly coded source files. It includes and uses the Xtensa hardware +abstraction layer (HAL) to deal with config specifics. It may also be +included in C source files. + +!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !! + +NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes. + +*******************************************************************************/ + +#ifndef XTENSA_CONTEXT_H +#define XTENSA_CONTEXT_H + +#ifdef __ASSEMBLER__ +#include +#endif + +#include +#include +#include +#include + + +/* Align a value up to nearest n-byte boundary, where n is a power of 2. */ +#define ALIGNUP(n, val) (((val) + (n)-1) & -(n)) + + +/* +------------------------------------------------------------------------------- + Macros that help define structures for both C and assembler. +------------------------------------------------------------------------------- +*/ + +#ifdef STRUCT_BEGIN +#undef STRUCT_BEGIN +#undef STRUCT_FIELD +#undef STRUCT_AFIELD +#undef STRUCT_END +#endif + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + +#define STRUCT_BEGIN .pushsection .text; .struct 0 +#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size +#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n) +#define STRUCT_END(sname) sname##Size:; .popsection + +#else + +#define STRUCT_BEGIN typedef struct { +#define STRUCT_FIELD(ctype,size,asname,name) ctype name; +#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n]; +#define STRUCT_END(sname) } sname; + +#endif //_ASMLANGUAGE || __ASSEMBLER__ + + +/* +------------------------------------------------------------------------------- + INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT + + A stack frame of this structure is allocated for any interrupt or exception. + It goes on the current stack. If the RTOS has a system stack for handling + interrupts, every thread stack must allow space for just one interrupt stack + frame, then nested interrupt stack frames go on the system stack. + + The frame includes basic registers (explicit) and "extra" registers introduced + by user TIE or the use of the MAC16 option in the user's Xtensa config. + The frame size is minimized by omitting regs not applicable to user's config. + + For Windowed ABI, this stack frame includes the interruptee's base save area, + another base save area to manage gcc nested functions, and a little temporary + space to help manage the spilling of the register windows. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */ +STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */ +STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */ +STRUCT_FIELD (long, 4, XT_STK_A0, a0) +STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */ +STRUCT_FIELD (long, 4, XT_STK_A2, a2) +STRUCT_FIELD (long, 4, XT_STK_A3, a3) +STRUCT_FIELD (long, 4, XT_STK_A4, a4) +STRUCT_FIELD (long, 4, XT_STK_A5, a5) +STRUCT_FIELD (long, 4, XT_STK_A6, a6) +STRUCT_FIELD (long, 4, XT_STK_A7, a7) +STRUCT_FIELD (long, 4, XT_STK_A8, a8) +STRUCT_FIELD (long, 4, XT_STK_A9, a9) +STRUCT_FIELD (long, 4, XT_STK_A10, a10) +STRUCT_FIELD (long, 4, XT_STK_A11, a11) +STRUCT_FIELD (long, 4, XT_STK_A12, a12) +STRUCT_FIELD (long, 4, XT_STK_A13, a13) +STRUCT_FIELD (long, 4, XT_STK_A14, a14) +STRUCT_FIELD (long, 4, XT_STK_A15, a15) +STRUCT_FIELD (long, 4, XT_STK_SAR, sar) +STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause) +STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr) +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg) +STRUCT_FIELD (long, 4, XT_STK_LEND, lend) +STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount) +#endif +#ifndef __XTENSA_CALL0_ABI__ +/* Temporary space for saving stuff during window spill */ +STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0) +STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1) +STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2) +#endif +#ifdef XT_USE_SWPRI +/* Storage for virtual priority mask */ +STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri) +#endif +#ifdef XT_USE_OVLY +/* Storage for overlay state */ +STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly) +#endif +STRUCT_END(XtExcFrame) + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) +#define XT_STK_NEXT1 XtExcFrameSize +#else +#define XT_STK_NEXT1 sizeof(XtExcFrame) +#endif + +/* Allocate extra storage if needed */ +#if XCHAL_EXTRA_SA_SIZE != 0 + +#if XCHAL_EXTRA_SA_ALIGN <= 16 +#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) +#else +/* If need more alignment than stack, add space for dynamic alignment */ +#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN) +#endif +#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE) + +#else + +#define XT_STK_NEXT2 XT_STK_NEXT1 + +#endif + +/* +------------------------------------------------------------------------------- + This is the frame size. Add space for 4 registers (interruptee's base save + area) and some space for gcc nested functions if any. +------------------------------------------------------------------------------- +*/ +#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20) + + +/* +------------------------------------------------------------------------------- + SOLICITED STACK FRAME FOR A THREAD + + A stack frame of this structure is allocated whenever a thread enters the + RTOS kernel intentionally (and synchronously) to submit to thread scheduling. + It goes on the current thread's stack. + + The solicited frame only includes registers that are required to be preserved + by the callee according to the compiler's ABI conventions, some space to save + the return address for returning to the caller, and the caller's PS register. + + For Windowed ABI, this stack frame includes the caller's base save area. + + Note on XT_SOL_EXIT field: + It is necessary to distinguish a solicited from an interrupt stack frame. + This field corresponds to XT_STK_EXIT in the interrupt stack frame and is + always at the same offset (0). It can be written with a code (usually 0) + to distinguish a solicted frame from an interrupt frame. An RTOS port may + opt to ignore this field if it has another way of distinguishing frames. +------------------------------------------------------------------------------- +*/ + +STRUCT_BEGIN +#ifdef __XTENSA_CALL0_ABI__ +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A13, a13) +STRUCT_FIELD (long, 4, XT_SOL_A14, a14) +STRUCT_FIELD (long, 4, XT_SOL_A15, a15) +#else +STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit) +STRUCT_FIELD (long, 4, XT_SOL_PC, pc) +STRUCT_FIELD (long, 4, XT_SOL_PS, ps) +STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) +STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */ +STRUCT_FIELD (long, 4, XT_SOL_A1, a1) +STRUCT_FIELD (long, 4, XT_SOL_A2, a2) +STRUCT_FIELD (long, 4, XT_SOL_A3, a3) +#endif +STRUCT_END(XtSolFrame) + +/* Size of solicited stack frame */ +#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize) + + +/* +------------------------------------------------------------------------------- + CO-PROCESSOR STATE SAVE AREA FOR A THREAD + + The RTOS must provide an area per thread to save the state of co-processors + when that thread does not have control. Co-processors are context-switched + lazily (on demand) only when a new thread uses a co-processor instruction, + otherwise a thread retains ownership of the co-processor even when it loses + control of the processor. An Xtensa co-processor exception is triggered when + any co-processor instruction is executed by a thread that is not the owner, + and the context switch of that co-processor is then peformed by the handler. + Ownership represents which thread's state is currently in the co-processor. + + Co-processors may not be used by interrupt or exception handlers. If an + co-processor instruction is executed by an interrupt or exception handler, + the co-processor exception handler will trigger a kernel panic and freeze. + This restriction is introduced to reduce the overhead of saving and restoring + co-processor state (which can be quite large) and in particular remove that + overhead from interrupt handlers. + + The co-processor state save area may be in any convenient per-thread location + such as in the thread control block or above the thread stack area. It need + not be in the interrupt stack frame since interrupts don't use co-processors. + + Along with the save area for each co-processor, two bitmasks with flags per + co-processor (laid out as in the CPENABLE reg) help manage context-switching + co-processors as efficiently as possible: + + XT_CPENABLE + The contents of a non-running thread's CPENABLE register. + It represents the co-processors owned (and whose state is still needed) + by the thread. When a thread is preempted, its CPENABLE is saved here. + When a thread solicits a context-swtich, its CPENABLE is cleared - the + compiler has saved the (caller-saved) co-proc state if it needs to. + When a non-running thread loses ownership of a CP, its bit is cleared. + When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg. + Avoids co-processor exceptions when no change of ownership is needed. + + XT_CPSTORED + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether the state of each co-processor is saved in the state + save area. When a thread enters the kernel, only the state of co-procs + still enabled in CPENABLE is saved. When the co-processor exception + handler assigns ownership of a co-processor to a thread, it restores + the saved state only if this bit is set, and clears this bit. + + XT_CP_CS_ST + A bitmask with the same layout as CPENABLE, a bit per co-processor. + Indicates whether callee-saved state is saved in the state save area. + Callee-saved state is saved by itself on a solicited context switch, + and restored when needed by the coprocessor exception handler. + Unsolicited switches will cause the entire coprocessor to be saved + when necessary. + + XT_CP_ASA + Pointer to the aligned save area. Allows it to be aligned more than + the overall save area (which might only be stack-aligned or TCB-aligned). + Especially relevant for Xtensa cores configured with a very large data + path that requires alignment greater than 16 bytes (ABI stack alignment). +------------------------------------------------------------------------------- +*/ + +#if XCHAL_CP_NUM > 0 + +/* Offsets of each coprocessor save area within the 'aligned save area': */ +#define XT_CP0_SA 0 +#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE) +#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE) + +/* Offsets within the overall save area: */ +#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ +#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ +#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ +#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */ +/* Overall size allows for dynamic alignment: */ +#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN) +#else +#define XT_CP_SIZE 0 +#endif + + +/* + Macro to get the current core ID. Only uses the reg given as an argument. + Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0) + and 0xABAB on the APP CPU (1). We can distinguish between the two by checking + bit 13: it's 1 on the APP and 0 on the PRO processor. +*/ +#ifdef __ASSEMBLER__ + .macro getcoreid reg + rsr.prid \reg + extui \reg,\reg,13,1 + .endm +#endif + +/* Note: These are different to xCoreID used in ESP-IDF FreeRTOS, most places use + 0 and 1 which are determined by checking bit 13 (see previous comment) +*/ +#define CORE_ID_REGVAL_PRO 0xCDCD +#define CORE_ID_REGVAL_APP 0xABAB + +/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */ +#define CORE_ID_PRO CORE_ID_REGVAL_PRO + +/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */ +#define CORE_ID_APP CORE_ID_REGVAL_APP + +/* +------------------------------------------------------------------------------- + MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN + + Convenient where the frame size requirements are the same for both ABIs. + ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + ENTRY0, RET0 are for frameless functions (no locals, no calls). + + where size = size of stack frame in bytes (must be >0 and aligned to 16). + For framed functions the frame is created and the return address saved at + base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + For frameless functions, there is no frame and return address remains in a0. + Note: Because CPP macros expand to a single line, macros requiring multi-line + expansions are implemented as assembler macros. +------------------------------------------------------------------------------- +*/ + +#ifdef __ASSEMBLER__ +#ifdef __XTENSA_CALL0_ABI__ + /* Call0 */ + #define ENTRY(sz) entry1 sz + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + #define ENTRY0 + #define RET(sz) ret1 sz + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + #define RET0 ret +#else + /* Windowed */ + #define ENTRY(sz) entry sp, sz + #define ENTRY0 entry sp, 0x10 + #define RET(sz) retw + #define RET0 retw +#endif +#endif + + + + + +#endif /* XTENSA_CONTEXT_H */ + diff --git a/tools/sdk/esp32s2/ld/esp32s2.project.ld b/tools/sdk/esp32s2/ld/esp32s2.project.ld index 49518637..41c6c295 100644 --- a/tools/sdk/esp32s2/ld/esp32s2.project.ld +++ b/tools/sdk/esp32s2/ld/esp32s2.project.ld @@ -12,14 +12,27 @@ SECTIONS */ .rtc.text : { + _rtc_text_start = ABSOLUTE(.); . = ALIGN(4); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.literal EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.text EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.text.*) + _rtc_code_start = .; + + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.literal EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.text EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.text.*) + *libfreertos.a:port.*( .rtc.text.*) *libfreertos.a:queue.*( .rtc.text.*) + *libfreertos.a:port.*(.rtc.text.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.text.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.text.main_task) *libfreertos.a:queue.*(.rtc.text.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.literal .rtc.text .rtc.text.*) *libhal.a:uart_hal_iram.*( .rtc.literal .rtc.text .rtc.text.*) *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_code_end = .; + + /* possibly align + add 16B for CPU dummy speculative instr. fetch */ + . = ((_rtc_code_end - _rtc_code_start) == 0) ? ALIGN(0) : ALIGN(4) + 16; + _rtc_text_end = ABSOLUTE(.); } > rtc_iram_seg @@ -45,9 +58,14 @@ SECTIONS _rtc_force_fast_start = ABSOLUTE(.); _coredump_rtc_fast_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.fast.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.fast.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.fast.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.fast.coredump.*) + *libfreertos.a:port.*( .rtc.fast.coredump.*) *libfreertos.a:queue.*( .rtc.fast.coredump.*) + *libfreertos.a:port.*(.rtc.fast.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.fast.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.fast.coredump.main_task) *libfreertos.a:queue.*(.rtc.fast.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.fast.coredump .rtc.fast.coredump.*) *libhal.a:uart_hal_iram.*( .rtc.fast.coredump .rtc.fast.coredump.*) _coredump_rtc_fast_end = ABSOLUTE(.); @@ -69,16 +87,26 @@ SECTIONS /* coredump mapping */ _coredump_rtc_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .rtc.coredump.*) + *libfreertos.a:port.*( .rtc.coredump.*) *libfreertos.a:queue.*( .rtc.coredump.*) + *libfreertos.a:port.*(.rtc.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.coredump.main_task) *libfreertos.a:queue.*(.rtc.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.coredump .rtc.coredump.*) *libhal.a:uart_hal_iram.*( .rtc.coredump .rtc.coredump.*) _coredump_rtc_end = ABSOLUTE(.); /* should be placed after coredump mapping */ - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.rodata EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.rodata.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.rodata EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .rtc.rodata.*) + *libfreertos.a:port.*( .rtc.data.* .rtc.rodata.*) *libfreertos.a:queue.*( .rtc.data.* .rtc.rodata.*) + *libfreertos.a:port.*(.rtc.data.esp_startup_start_app .rtc.rodata.esp_startup_start_app) + *libfreertos.a:port.*(.rtc.data.esp_startup_start_app_other_cores .rtc.rodata.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rtc.data.main_task .rtc.rodata.main_task) *libfreertos.a:queue.*(.rtc.data.xQueueGenericCreateStatic .rtc.rodata.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rtc.data .rtc.data.* .rtc.rodata .rtc.rodata.*) *libhal.a:uart_hal_iram.*( .rtc.data .rtc.data.* .rtc.rodata .rtc.rodata.*) *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*) @@ -92,7 +120,8 @@ SECTIONS *rtc_wake_stub*.*(.bss .bss.*) *rtc_wake_stub*.*(COMMON) - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .rtc.bss) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .rtc.bss) + *libhal.a:twai_hal_iram.*( .rtc.bss) *libhal.a:uart_hal_iram.*( .rtc.bss) _rtc_bss_end = ABSOLUTE(.); @@ -187,7 +216,7 @@ SECTIONS /* Code marked as runnning out of IRAM */ _iram_text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .iram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram1.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .iram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .iram1.*) *libapp_trace.a:SEGGER_RTT_esp32.*( .literal .literal.* .text .text.*) *libapp_trace.a:SEGGER_SYSVIEW.*( .literal .literal.* .text .text.*) *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.*( .literal .literal.* .text .text.*) @@ -202,8 +231,12 @@ SECTIONS *libesp_system.a:panic_handler.*( .literal .literal.* .text .text.*) *libesp_system.a:reset_reason.*( .literal .literal.* .text .text.*) *libesp_system.a:system_api.*(.literal.esp_system_abort .text.esp_system_abort) - *libfreertos.a:( .literal EXCLUDE_FILE(*libfreertos.a:queue.*) .literal.* .text EXCLUDE_FILE(*libfreertos.a:queue.*) .text.*) + *libfreertos.a:( .literal EXCLUDE_FILE(*libfreertos.a:port.* *libfreertos.a:queue.*) .literal.* .text EXCLUDE_FILE(*libfreertos.a:port.* *libfreertos.a:queue.*) .text.*) + *libfreertos.a:port.*(.iram1.24.literal .iram1.25.literal .iram1.24 .iram1.25 .literal.pxPortInitialiseStack .literal.xPortStartScheduler .literal.vPortYieldOtherCore .literal.xPortInIsrContext .literal.xPortSysTickHandler .literal.vPortAssertIfInISR .literal.vPortSetStackWatchpoint .literal.vPortEnterCritical .literal.vPortExitCritical .literal.vApplicationStackOverflowHook .text.pxPortInitialiseStack .text.vPortEndScheduler .text.xPortStartScheduler .text.vPortYieldOtherCore .text.xPortInIsrContext .text.xPortSysTickHandler .text.vPortAssertIfInISR .text.vPortSetStackWatchpoint .text.xPortGetTickRateHz .text.vPortEnterCritical .text.vPortExitCritical .text.vApplicationStackOverflowHook) *libfreertos.a:queue.*( .iram1.* .literal.prvCopyDataToQueue .literal.prvCopyDataFromQueue .literal.prvNotifyQueueSetContainer .literal.xQueueGenericReset .literal.xQueueGenericCreate .literal.xQueueGetMutexHolder .literal.xQueueCreateCountingSemaphoreStatic .literal.xQueueCreateCountingSemaphore .literal.xQueueGenericSend .literal.xQueueCreateMutexStatic .literal.xQueueGiveMutexRecursive .literal.xQueueCreateMutex .literal.xQueueGenericSendFromISR .literal.xQueueGiveFromISR .literal.xQueueGenericReceive .literal.xQueueTakeMutexRecursive .literal.xQueueReceiveFromISR .literal.xQueuePeekFromISR .literal.uxQueueMessagesWaiting .literal.uxQueueSpacesAvailable .literal.uxQueueMessagesWaitingFromISR .literal.vQueueDelete .literal.xQueueIsQueueEmptyFromISR .literal.xQueueIsQueueFullFromISR .literal.vQueueWaitForMessageRestricted .literal.xQueueCreateSet .literal.xQueueAddToSet .literal.xQueueRemoveFromSet .literal.xQueueSelectFromSet .literal.xQueueSelectFromSetFromISR .text.prvCopyDataToQueue .text.prvCopyDataFromQueue .text.prvNotifyQueueSetContainer .text.xQueueGenericReset .text.xQueueGenericCreate .text.xQueueGetMutexHolder .text.xQueueCreateCountingSemaphoreStatic .text.xQueueCreateCountingSemaphore .text.xQueueGenericSend .text.xQueueCreateMutexStatic .text.xQueueGiveMutexRecursive .text.xQueueCreateMutex .text.xQueueGenericSendFromISR .text.xQueueGiveFromISR .text.xQueueGenericReceive .text.xQueueTakeMutexRecursive .text.xQueueReceiveFromISR .text.xQueuePeekFromISR .text.uxQueueMessagesWaiting .text.uxQueueSpacesAvailable .text.uxQueueMessagesWaitingFromISR .text.vQueueDelete .text.xQueueIsQueueEmptyFromISR .text.xQueueIsQueueFullFromISR .text.vQueueWaitForMessageRestricted .text.xQueueCreateSet .text.xQueueAddToSet .text.xQueueRemoveFromSet .text.xQueueSelectFromSet .text.xQueueSelectFromSetFromISR) + *libfreertos.a:port.*(.iram1.esp_startup_start_app) + *libfreertos.a:port.*(.iram1.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.iram1.main_task) *libfreertos.a:queue.*(.iram1.xQueueGenericCreateStatic) *libgcc.a:lib2funcs.*( .literal .literal.* .text .text.*) *libgcov.a:( .literal .literal.* .text .text.*) @@ -216,6 +249,7 @@ SECTIONS *libhal.a:spi_hal_iram.*( .literal .literal.* .text .text.*) *libhal.a:spi_slave_hal_iram.*( .literal .literal.* .text .text.*) *libhal.a:systimer_hal.*( .literal .literal.* .text .text.*) + *libhal.a:twai_hal_iram.*( .iram1 .iram1.*) *libhal.a:uart_hal_iram.*( .iram1 .iram1.*) *libhal.a:wdt_hal_iram.*( .literal .literal.* .text .text.*) *libheap.a:multi_heap.*( .literal .literal.* .text .text.*) @@ -254,7 +288,7 @@ SECTIONS _coredump_iram_start = 0; _coredump_iram_end = 0; - /* align + add 16B for the possibly overlapping instructions */ + /* align + add 16B for CPU dummy speculative instr. fetch */ . = ALIGN(4) + 16; _iram_text_end = ABSOLUTE(.); _iram_end = ABSOLUTE(.); @@ -280,9 +314,14 @@ SECTIONS /* coredump mapping */ _coredump_dram_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .dram1.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.coredump.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .dram1.coredump EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .dram1.coredump.*) + *libfreertos.a:port.*( .dram1.coredump.*) *libfreertos.a:queue.*( .dram1.coredump.*) + *libfreertos.a:port.*(.dram1.coredump.esp_startup_start_app) + *libfreertos.a:port.*(.dram1.coredump.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.dram1.coredump.main_task) *libfreertos.a:queue.*(.dram1.coredump.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .dram1.coredump .dram1.coredump.*) *libhal.a:uart_hal_iram.*( .dram1.coredump .dram1.coredump.*) _coredump_dram_end = ABSOLUTE(.); @@ -291,7 +330,7 @@ SECTIONS KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*))) _esp_system_init_fn_array_end = ABSOLUTE(.); - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .dram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.*) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .data EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .data.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .dram1 EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .dram1.*) *libapp_trace.a:SEGGER_RTT_esp32.*( .rodata .rodata.*) *libapp_trace.a:SEGGER_SYSVIEW.*( .rodata .rodata.*) *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.*( .rodata .rodata.*) @@ -305,7 +344,11 @@ SECTIONS *libesp_system.a:panic_handler.*( .rodata .rodata.*) *libesp_system.a:reset_reason.*( .rodata .rodata.*) *libesp_system.a:system_api.*(.rodata.esp_system_abort) + *libfreertos.a:port.*( .data.* .dram1.*) *libfreertos.a:queue.*( .data.* .dram1.*) + *libfreertos.a:port.*(.data.esp_startup_start_app .dram1.esp_startup_start_app) + *libfreertos.a:port.*(.data.esp_startup_start_app_other_cores .dram1.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.data.main_task .dram1.main_task) *libfreertos.a:queue.*(.data.xQueueGenericCreateStatic .dram1.xQueueGenericCreateStatic) *libgcov.a:( .rodata .rodata.*) *libhal.a:cpu_hal.*( .rodata .rodata.*) @@ -317,6 +360,7 @@ SECTIONS *libhal.a:spi_hal_iram.*( .rodata .rodata.*) *libhal.a:spi_slave_hal_iram.*( .rodata .rodata.*) *libhal.a:systimer_hal.*( .rodata .rodata.*) + *libhal.a:twai_hal_iram.*( .data .data.* .dram1 .dram1.*) *libhal.a:uart_hal_iram.*( .data .data.* .dram1 .dram1.*) *libhal.a:wdt_hal_iram.*( .rodata .rodata.*) *libheap.a:multi_heap.*( .rodata .rodata.*) @@ -366,9 +410,14 @@ SECTIONS _bss_start = ABSOLUTE(.); *(.ext_ram.bss*) - *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .bss EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .bss.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) COMMON) + *(EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .bss EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.*) .bss.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) COMMON) + *libfreertos.a:port.*(.bss.port_uxOldInterruptState .bss.port_uxCriticalNesting .bss.port_interruptNesting .bss.port_xSchedulerRunning) *libfreertos.a:queue.*( .bss.*) + *libfreertos.a:port.*(.bss.esp_startup_start_app) + *libfreertos.a:port.*(.bss.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.bss.main_task) *libfreertos.a:queue.*(.bss.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .bss .bss.* COMMON) *libhal.a:uart_hal_iram.*( .bss .bss.* COMMON) *(.dynsbss) @@ -396,12 +445,17 @@ SECTIONS *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log_freertos.* *liblog.a:log.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a:queue.* *libphy.a) .rodata.*) + *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log_freertos.* *liblog.a:log.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a:queue.* *libfreertos.a:port.* *libphy.a) .rodata.*) *libesp_event.a:default_event_loop.*(.rodata.esp_event_loop_create_default.str1.4 .rodata.esp_event_send_to_default_loop) - *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$9843 .rodata.__func__$9830 .rodata.__func__$9797 .rodata.__func__$9765 .rodata.__func__$9740 .rodata.__func__$9699 .rodata.__func__$9690) + *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$9877 .rodata.__func__$9864 .rodata.__func__$9831 .rodata.__func__$9799 .rodata.__func__$9774 .rodata.__func__$9733 .rodata.__func__$9724) *libesp_system.a:system_api.*(.rodata.esp_get_idf_version.str1.4) - *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.__FUNCTION__$5272 .rodata.__FUNCTION__$5262 .rodata.__FUNCTION__$5242 .rodata.__FUNCTION__$5237 .rodata.__FUNCTION__$5231 .rodata.__FUNCTION__$5225 .rodata.__FUNCTION__$5219 .rodata.__FUNCTION__$5210 .rodata.__FUNCTION__$5200 .rodata.__FUNCTION__$5189 .rodata.__FUNCTION__$5181 .rodata.__FUNCTION__$5308 .rodata.__FUNCTION__$5170 .rodata.__FUNCTION__$5159 .rodata.__FUNCTION__$5153 .rodata.__FUNCTION__$5146 .rodata.__FUNCTION__$5139 .rodata.__FUNCTION__$5105 .rodata.__FUNCTION__$5095 .rodata.__FUNCTION__$5086) + *libfreertos.a:port.*(.rodata.main_task.str1.4 .rodata.vPortAssertIfInISR.str1.4 .rodata.vApplicationStackOverflowHook.str1.4 .rodata.esp_startup_start_app.str1.4 .rodata.__func__$5361 .rodata.__func__$5366 .rodata.__FUNCTION__$5326) + *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.__FUNCTION__$5305 .rodata.__FUNCTION__$5295 .rodata.__FUNCTION__$5275 .rodata.__FUNCTION__$5270 .rodata.__FUNCTION__$5264 .rodata.__FUNCTION__$5258 .rodata.__FUNCTION__$5252 .rodata.__FUNCTION__$5243 .rodata.__FUNCTION__$5233 .rodata.__FUNCTION__$5222 .rodata.__FUNCTION__$5214 .rodata.__FUNCTION__$5341 .rodata.__FUNCTION__$5203 .rodata.__FUNCTION__$5192 .rodata.__FUNCTION__$5186 .rodata.__FUNCTION__$5179 .rodata.__FUNCTION__$5172 .rodata.__FUNCTION__$5138 .rodata.__FUNCTION__$5128 .rodata.__FUNCTION__$5119) + *libfreertos.a:port.*(.rodata.esp_startup_start_app) + *libfreertos.a:port.*(.rodata.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.rodata.main_task) *libfreertos.a:queue.*(.rodata.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .rodata .rodata.*) *libhal.a:uart_hal_iram.*( .rodata .rodata.*) *liblog.a:log.*(.rodata.esp_log_level_set.str1.4 .rodata.__func__$3542 .rodata.__func__$3513) *liblog.a:log_freertos.*(.rodata.esp_log_system_timestamp.str1.4) @@ -467,12 +521,17 @@ SECTIONS _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifirxiram.*) + *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libxt_hal.a *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:cpu_util.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:lldesc.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a:spi_flash_hal_iram.* *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libhal.a:i2c_hal_iram.* *libhal.a:soc_hal.* *libhal.a:spi_flash_hal_gpspi.* *libhal.a:cpu_hal.* *libhal.a:ledc_hal_iram.* *libhal.a:spi_slave_hal_iram.* *libhal.a:systimer_hal.* *libhal.a:wdt_hal_iram.* *libhal.a:spi_hal_iram.* *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libhal.a:uart_hal_iram.* *libhal.a:twai_hal_iram.* *libfreertos.a:port.* *libfreertos.a:queue.*) .wifirxiram.*) *libesp_event.a:default_event_loop.*(.literal.esp_event_handler_register .literal.esp_event_handler_instance_register .literal.esp_event_handler_unregister .literal.esp_event_handler_instance_unregister .literal.esp_event_post .literal.esp_event_loop_create_default .literal.esp_event_loop_delete_default .literal.esp_event_send_to_default_loop .text.esp_event_handler_register .text.esp_event_handler_instance_register .text.esp_event_handler_unregister .text.esp_event_handler_instance_unregister .text.esp_event_post .text.esp_event_loop_create_default .text.esp_event_loop_delete_default .text.esp_event_send_to_default_loop) *libesp_event.a:esp_event.*(.literal.handler_instances_add .literal.base_node_add_handler .literal.loop_node_add_handler .literal.handler_instances_remove .literal.handler_instances_remove_all$isra$1 .literal.esp_event_loop_create .literal.esp_event_loop_run .literal.esp_event_loop_run_task .literal.esp_event_loop_delete .literal.esp_event_handler_register_with_internal .literal.esp_event_handler_register_with .literal.esp_event_handler_instance_register_with .literal.esp_event_handler_unregister_with_internal .literal.esp_event_handler_unregister_with .literal.esp_event_handler_instance_unregister_with .literal.esp_event_post_to .text.handler_instances_add .text.base_node_add_handler .text.loop_node_add_handler .text.handler_instances_remove .text.handler_instances_remove_all$isra$1 .text.esp_event_loop_create .text.esp_event_loop_run .text.esp_event_loop_run_task .text.esp_event_loop_delete .text.esp_event_handler_register_with_internal .text.esp_event_handler_register_with .text.esp_event_handler_instance_register_with .text.esp_event_handler_unregister_with_internal .text.esp_event_handler_unregister_with .text.esp_event_handler_instance_unregister_with .text.esp_event_post_to .text.esp_event_dump) *libesp_system.a:system_api.*(.literal.esp_register_shutdown_handler .literal.esp_unregister_shutdown_handler .literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_minimum_free_heap_size .literal.esp_get_idf_version .text.esp_register_shutdown_handler .text.esp_unregister_shutdown_handler .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_minimum_free_heap_size .text.esp_get_idf_version) + *libfreertos.a:port.*( .wifi0iram.* .wifirxiram.*) *libfreertos.a:queue.*( .wifi0iram.* .wifirxiram.*) + *libfreertos.a:port.*(.literal.esp_startup_start_app .text.esp_startup_start_app .wifi0iram.esp_startup_start_app .wifirxiram.esp_startup_start_app) + *libfreertos.a:port.*(.literal.esp_startup_start_app_other_cores .text.esp_startup_start_app_other_cores .wifi0iram.esp_startup_start_app_other_cores .wifirxiram.esp_startup_start_app_other_cores) + *libfreertos.a:port.*(.literal.main_task .text.main_task .wifi0iram.main_task .wifirxiram.main_task) *libfreertos.a:queue.*(.literal.xQueueGenericCreateStatic .text.xQueueGenericCreateStatic .wifi0iram.xQueueGenericCreateStatic .wifirxiram.xQueueGenericCreateStatic) + *libhal.a:twai_hal_iram.*( .literal .literal.* .text .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *libhal.a:uart_hal_iram.*( .literal .literal.* .text .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *liblog.a:log.*(.literal.heap_bubble_down .literal.esp_log_set_vprintf .literal.esp_log_level_set .literal.esp_log_writev .text.heap_bubble_down .text.esp_log_set_vprintf .text.esp_log_level_set .text.esp_log_writev) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text.esp_log_system_timestamp) diff --git a/tools/sdk/esp32s2/ld/libesp32s2.a b/tools/sdk/esp32s2/ld/libesp32s2.a new file mode 100644 index 00000000..af3355e1 Binary files /dev/null and b/tools/sdk/esp32s2/ld/libesp32s2.a differ diff --git a/tools/sdk/esp32s2/lib/libapp_trace.a b/tools/sdk/esp32s2/lib/libapp_trace.a index 3ac06497..c8d55cae 100644 Binary files a/tools/sdk/esp32s2/lib/libapp_trace.a and b/tools/sdk/esp32s2/lib/libapp_trace.a differ diff --git a/tools/sdk/esp32s2/lib/libapp_update.a b/tools/sdk/esp32s2/lib/libapp_update.a index b3b23d12..e8b01613 100644 Binary files a/tools/sdk/esp32s2/lib/libapp_update.a and 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a/tools/sdk/esp32s2/lib/libxtensa.a and b/tools/sdk/esp32s2/lib/libxtensa.a differ diff --git a/tools/sdk/esp32s2/sdkconfig b/tools/sdk/esp32s2/sdkconfig index 47fab72a..8c2a7626 100644 --- a/tools/sdk/esp32s2/sdkconfig +++ b/tools/sdk/esp32s2/sdkconfig @@ -76,7 +76,7 @@ CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y # Serial flasher config # CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 -CONFIG_ESPTOOLPY_WITH_STUB=y +# CONFIG_ESPTOOLPY_NO_STUB is not set CONFIG_ESPTOOLPY_FLASHMODE_QIO=y # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set # CONFIG_ESPTOOLPY_FLASHMODE_DIO is not set @@ -248,6 +248,12 @@ CONFIG_ADC_DISABLE_DAC=y # CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set # end of SPI configuration +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI configuration + # # UART configuration # @@ -267,6 +273,7 @@ CONFIG_EFUSE_MAX_BLK_LEN=256 # ESP-TLS # CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y CONFIG_ESP_TLS_SERVER=y # CONFIG_ESP_TLS_PSK_VERIFICATION is not set # end of ESP-TLS @@ -367,14 +374,9 @@ CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 CONFIG_ESP32S2_KEEP_USB_ALIVE=y # CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set # CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set +CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y # end of ESP32S2-specific -# -# Power Management -# -# CONFIG_PM_ENABLE is not set -# end of Power Management - # # ADC-Calibration # @@ -404,6 +406,7 @@ CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT_OFFSET=1 # end of Common ESP-related # @@ -467,6 +470,12 @@ CONFIG_ESP_NETIF_TCPIP_LWIP=y CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y # end of ESP NETIF Adapter +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +# end of Power Management + # # ESP System Settings # @@ -481,6 +490,7 @@ CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y # High resolution timer (esp_timer) # # CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIMER_RTC_USE=y CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP_TIMER_IMPL_SYSTIMER=y # end of High resolution timer (esp_timer) @@ -519,9 +529,9 @@ CONFIG_ESP32_PHY_MAX_TX_POWER=20 # # Core dump # -# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set -# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set -CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y # end of Core dump # @@ -988,6 +998,7 @@ CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 # CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set # # Auto-detect flash chips @@ -1267,6 +1278,9 @@ CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y # CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set # CONFIG_ESP32S2_PANIC_GDBSTUB is not set CONFIG_TIMER_TASK_STACK_SIZE=4096 +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 CONFIG_MB_QUEUE_LENGTH=20