diff --git a/boards.txt b/boards.txt index 52583d81..50540911 100644 --- a/boards.txt +++ b/boards.txt @@ -1,5 +1,4 @@ menu.UploadSpeed=Upload Speed -menu.UploadMode=Upload Mode menu.SerialMode=Serial Connected To menu.CPUFreq=CPU Frequency menu.FlashFreq=Flash Frequency @@ -47,22 +46,6 @@ esp32s2.menu.SerialMode.default.build.serial=0 esp32s2.menu.SerialMode.cdc=USB CDC esp32s2.menu.SerialMode.cdc.build.serial=1 -esp32s2.menu.UploadMode.default=Default Uart -esp32s2.menu.UploadMode.default.upload.flags= -esp32s2.menu.UploadMode.default.upload.tool=esptool_py -esp32s2.menu.UploadMode.default.serial.disableDTR=true -esp32s2.menu.UploadMode.default.serial.disableRTS=true -esp32s2.menu.UploadMode.cdc=USB CDC -esp32s2.menu.UploadMode.cdc.upload.flags=--no-stub -esp32s2.menu.UploadMode.cdc.upload.tool=esptool_py -esp32s2.menu.UploadMode.cdc.serial.disableDTR=false -esp32s2.menu.UploadMode.cdc.serial.disableRTS=false -#esp32s2.menu.UploadMode.dfu=USB DFU -#esp32s2.menu.UploadMode.dfu.upload.flags= -#esp32s2.menu.UploadMode.dfu.upload.tool=dfu_util -#esp32s2.menu.UploadMode.dfu.serial.disableDTR=false -#esp32s2.menu.UploadMode.dfu.serial.disableRTS=false - esp32s2.menu.PSRAM.disabled=Disabled esp32s2.menu.PSRAM.disabled.build.defines= esp32s2.menu.PSRAM.enabled=Enabled @@ -598,17 +581,6 @@ feathers2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM feathers2.menu.PSRAM.disabled=Disabled feathers2.menu.PSRAM.disabled.build.defines= -feathers2.menu.UploadMode.cdc=USB CDC -feathers2.menu.UploadMode.cdc.upload.flags=--no-stub -feathers2.menu.UploadMode.cdc.upload.tool=esptool_py -feathers2.menu.UploadMode.cdc.serial.disableDTR=false -feathers2.menu.UploadMode.cdc.serial.disableRTS=false -feathers2.menu.UploadMode.default=Default Uart - External -feathers2.menu.UploadMode.default.upload.flags= -feathers2.menu.UploadMode.default.upload.tool=esptool_py -feathers2.menu.UploadMode.default.serial.disableDTR=true -feathers2.menu.UploadMode.default.serial.disableRTS=true - feathers2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) feathers2.menu.PartitionScheme.fatflash.build.partitions=ffat feathers2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 @@ -730,17 +702,6 @@ pros2.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM pros2.menu.PSRAM.disabled=Disabled pros2.menu.PSRAM.disabled.build.defines= -pros2.menu.UploadMode.cdc=USB CDC -pros2.menu.UploadMode.cdc.upload.flags=--no-stub -pros2.menu.UploadMode.cdc.upload.tool=esptool_py -pros2.menu.UploadMode.cdc.serial.disableDTR=false -pros2.menu.UploadMode.cdc.serial.disableRTS=false -pros2.menu.UploadMode.default=Default Uart - External -pros2.menu.UploadMode.default.upload.flags= -pros2.menu.UploadMode.default.upload.tool=esptool_py -pros2.menu.UploadMode.default.serial.disableDTR=true -pros2.menu.UploadMode.default.serial.disableRTS=true - pros2.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT) pros2.menu.PartitionScheme.fatflash.build.partitions=ffat pros2.menu.PartitionScheme.fatflash.upload.maximum_size=2097152 diff --git a/cores/esp32/esp32-hal-tinyusb.c b/cores/esp32/esp32-hal-tinyusb.c index 1ea0b8b1..1b645bfa 100644 --- a/cores/esp32/esp32-hal-tinyusb.c +++ b/cores/esp32/esp32-hal-tinyusb.c @@ -544,7 +544,7 @@ esp_err_t tinyusb_init(tinyusb_device_config_t *config) { initialized = false; return err; } - xTaskCreate(usb_device_task, "usbd", 4096, NULL, 24, NULL); + xTaskCreate(usb_device_task, "usbd", 4096, NULL, configMAX_PRIORITIES - 1, NULL); return err; } diff --git a/package/package_esp32_index.template.json b/package/package_esp32_index.template.json index 64aba2d3..cf64babb 100644 --- a/package/package_esp32_index.template.json +++ b/package/package_esp32_index.template.json @@ -54,83 +54,83 @@ "tools": [ { "name": "xtensa-esp32-elf-gcc", - "version": "gcc8_2_0-esp-2020r1", + "version": "gcc8_2_0-esp-2020r2", "systems": [ { "host": "i686-mingw32", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32-elf-gcc8_2_0-esp-2020r1-win32.zip", - "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r1-win32.zip", - "checksum": "SHA-256:5fbabd2b7c75f56ebe207061f56beb21aca32ef867b64e14e735065cf812cce4", - "size": "103877946" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32-elf-gcc8_2_0-esp-2020r2-win32.zip", + "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r2-win32.zip", + "checksum": "SHA-256:f2ba6bdb1c4b2178955e5e7a204552bb754709e02eaf9d8febe770d46629db8f", + "size": "103885422" }, { "host": "x86_64-apple-darwin", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32-elf-gcc8_2_0-esp-2020r1-macos.tar.gz", - "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r1-macos.tar.gz", - "checksum": "SHA-256:a3ee69bbe23acb77242086d2445c62d6bf13dbd9abcdfd4b56acef0937051a12", - "size": "92170881" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32-elf-gcc8_2_0-esp-2020r2-macos.tar.gz", + "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r2-macos.tar.gz", + "checksum": "SHA-256:48b288e3e5c60623851616bf545b8e4fc5382dc980d6b9682373f11013fe5776", + "size": "92201363" }, { "host": "x86_64-pc-linux-gnu", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32-elf-gcc8_2_0-esp-2020r1-linux-amd64.tar.gz", - "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r1-linux-amd64.tar.gz", - "checksum": "SHA-256:b65ae41a675c866f5e11e3c452fc4b9cee3f39038d88435faa45308f50388c54", - "size": "85490835" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32-elf-gcc8_2_0-esp-2020r2-linux-amd64.tar.gz", + "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r2-linux-amd64.tar.gz", + "checksum": "SHA-256:6c73b9e9d252810a63ca5e94b497c6c09fb8c903fe9c477f385bdc2ab4d2187e", + "size": "85520229" }, { "host": "i686-pc-linux-gnu", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32-elf-gcc8_2_0-esp-2020r1-linux-i686.tar.gz", - "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r1-linux-i686.tar.gz", - "checksum": "SHA-256:19273eb069efb29cc1df129f667fc09571c8e6e0ffa1fc536fb8b5d14bd59d4b", - "size": "87449664" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32-elf-gcc8_2_0-esp-2020r2-linux-i686.tar.gz", + "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r2-linux-i686.tar.gz", + "checksum": "SHA-256:a003c7bc9b9f0dd82170480aadd62c0586fc6e3d69119c637c957125164f40e5", + "size": "87467927" }, { "host": "arm-linux-gnueabihf", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32-elf-gcc8_2_0-esp-2020r1-linux-armel.tar.gz", - "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r1-linux-armel.tar.gz", - "checksum": "SHA-256:7cd03edf067b5da6acf333ddaf18ce8070db98876c01b1d8979702e63587fcb5", - "size": "83653607" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32-elf-gcc8_2_0-esp-2020r2-linux-armel.tar.gz", + "archiveFileName": "xtensa-esp32-elf-gcc8_2_0-esp-2020r2-linux-armel.tar.gz", + "checksum": "SHA-256:51dd318c4f2ac1fe2b206d029e1d2080c922107cc56e4a3802b1acafd7b436db", + "size": "83672167" } ] }, { "name": "xtensa-esp32s2-elf-gcc", - "version": "gcc8_2_0-esp-2020r1", + "version": "gcc8_2_0-esp-2020r2", "systems": [ { "host": "i686-mingw32", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-win32.zip", - "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-win32.zip", - "checksum": "SHA-256:a73a5b61510e730d7d0e46584f146a190b19627117e7657c92dccbedbf55ad68", - "size": "104292272" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-win32.zip", + "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-win32.zip", + "checksum": "SHA-256:e7fe06fc37f1046765653ec1ed571f06a86a5b5cde7b3a0ab71c44232c5b6a2f", + "size": "104302935" }, { "host": "x86_64-apple-darwin", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-macos.tar.gz", - "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-macos.tar.gz", - "checksum": "SHA-256:f6ec427699930ccd17d730fb5bcb0daa2283bee83e0987cade45d8f0e1f6f544", - "size": "92539826" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-macos.tar.gz", + "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-macos.tar.gz", + "checksum": "SHA-256:76d17b170e667b73dbb013e8efa8032b18d9e68f6e364745639e851d99ad68a3", + "size": "92562690" }, { "host": "x86_64-pc-linux-gnu", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-linux-amd64.tar.gz", - "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-linux-amd64.tar.gz", - "checksum": "SHA-256:f435159a654dbfd8ccc9f89a16d5ce523ebd9e04ae48d95bf4935d15ac7bd058", - "size": "85781628" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-linux-amd64.tar.gz", + "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-linux-amd64.tar.gz", + "checksum": "SHA-256:f5efd18a96f773b73bd6bcdee4476b5e4fbccea6befe0cb62c08675e4c68a65f", + "size": "85796525" }, { "host": "i686-pc-linux-gnu", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-linux-i686.tar.gz", - "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-linux-i686.tar.gz", - "checksum": "SHA-256:38b685c3243ab991dd9112ef330ba1fa1a176ab68a6aca832a0fc76975b8916f", - "size": "87764133" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-linux-i686.tar.gz", + "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-linux-i686.tar.gz", + "checksum": "SHA-256:53e8b9d38c409a207685b615924eada2ee9719ac4fe8c79caa7a89c788a65a7d", + "size": "87773410" }, { "host": "arm-linux-gnueabihf", - "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r1/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-linux-armel.tar.gz", - "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r1-linux-armel.tar.gz", - "checksum": "SHA-256:38081688e3d6d21b436adca9c790d8cdc9dd4dbd9e1a9c98262ea6b04639f8c1", - "size": "84055798" + "url": "https://github.com/espressif/crosstool-NG/releases/download/esp-2020r2/xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-linux-armel.tar.gz", + "archiveFileName": "xtensa-esp32s2-elf-gcc8_2_0-esp-2020r2-linux-armel.tar.gz", + "checksum": "SHA-256:40ed8c365a3e32643c7fc9cf44908fb166d3acc52754ebf0b03e82122a0ecd2c", + "size": "84041933" } ] }, @@ -140,45 +140,45 @@ "systems": [ { "host": "i686-mingw32", - "url": "https://dl.espressif.com/dl/esptool-3.0.0-windows.zip", - "archiveFileName": "esptool-3.0.0-windows.zip", - "checksum": "SHA-256:65e2da7ca5f1da175ac7ae1ea776d3259ff01989a734d4f5fe1c1a12f19495c8", - "size": "3430930" + "url": "https://dl.espressif.com/dl/esptool-3.0.0.1-windows.zip", + "archiveFileName": "esptool-3.0.0.1-windows.zip", + "checksum": "SHA-256:6d95564d6b2786966b28155d5f066341b04a00f2f168082272c264db5c48f8fe", + "size": "3434601" }, { "host": "x86_64-apple-darwin", - "url": "https://dl.espressif.com/dl/esptool-3.0.0-macos.tar.gz", - "archiveFileName": "esptool-3.0.0-macos.tar.gz", - "checksum": "SHA-256:33dce4abffcf3d04da02cd0fd4dd9b78d71828d26f535ac5de7913dd5e5133a6", - "size": "3845775" + "url": "https://dl.espressif.com/dl/esptool-3.0.0.1-macos.tar.gz", + "archiveFileName": "esptool-3.0.0.1-macos.tar.gz", + "checksum": "SHA-256:f382920c176a6143ccdb39efedda514214b9804d1932b1f86a591bd3b5c7ac8f", + "size": "3849476" }, { "host": "x86_64-pc-linux-gnu", - "url": "https://dl.espressif.com/dl/esptool-3.0.0-linux.tar.gz", - "archiveFileName": "esptool-3.0.0-linux.tar.gz", - "checksum": "SHA-256:a3ba4d8d49f4f03b63eb103de2572c82e3963be8e748d6923ec79fe40f358722", - "size": "53912" + "url": "https://dl.espressif.com/dl/esptool-3.0.0.1-linux.tar.gz", + "archiveFileName": "esptool-3.0.0.1-linux.tar.gz", + "checksum": "SHA-256:0af60bb12037266a19e086f0873143b1217e9dd508c9b864c2efc2250de812ff", + "size": "57123" }, { "host": "i686-pc-linux-gnu", - "url": "https://dl.espressif.com/dl/esptool-3.0.0-linux.tar.gz", - "archiveFileName": "esptool-3.0.0-linux.tar.gz", - "checksum": "SHA-256:a3ba4d8d49f4f03b63eb103de2572c82e3963be8e748d6923ec79fe40f358722", - "size": "53912" + "url": "https://dl.espressif.com/dl/esptool-3.0.0.1-linux.tar.gz", + "archiveFileName": "esptool-3.0.0.1-linux.tar.gz", + "checksum": "SHA-256:0af60bb12037266a19e086f0873143b1217e9dd508c9b864c2efc2250de812ff", + "size": "57123" }, { "host": "arm-linux-gnueabihf", - "url": "https://dl.espressif.com/dl/esptool-3.0.0-linux.tar.gz", - "archiveFileName": "esptool-3.0.0-linux.tar.gz", - "checksum": "SHA-256:a3ba4d8d49f4f03b63eb103de2572c82e3963be8e748d6923ec79fe40f358722", - "size": "53912" + "url": "https://dl.espressif.com/dl/esptool-3.0.0.1-linux.tar.gz", + "archiveFileName": "esptool-3.0.0.1-linux.tar.gz", + "checksum": "SHA-256:0af60bb12037266a19e086f0873143b1217e9dd508c9b864c2efc2250de812ff", + "size": "57123" }, { "host": "aarch64-linux-gnu", - "url": "https://dl.espressif.com/dl/esptool-3.0.0-linux.tar.gz", - "archiveFileName": "esptool-3.0.0-linux.tar.gz", - "checksum": "SHA-256:a3ba4d8d49f4f03b63eb103de2572c82e3963be8e748d6923ec79fe40f358722", - "size": "53912" + "url": "https://dl.espressif.com/dl/esptool-3.0.0.1-linux.tar.gz", + "archiveFileName": "esptool-3.0.0.1-linux.tar.gz", + "checksum": "SHA-256:0af60bb12037266a19e086f0873143b1217e9dd508c9b864c2efc2250de812ff", + "size": "57123" } ] }, diff --git a/platform.txt b/platform.txt index 8607c693..7dbeaed0 100644 --- a/platform.txt +++ b/platform.txt @@ -22,12 +22,12 @@ compiler.prefix=xtensa-{build.mcu}-elf- # # ESP32 Support Start # -compiler.cpreprocessor.flags.esp32=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.2-dev-1905-g625bd5eb1-dirty" -DESP_PLATFORM "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/src/esp32" "-I{compiler.sdk.path}/include/soc/src/esp32/include" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32/include" "-I{compiler.sdk.path}/include/esp32/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/soc/soc/esp32" "-I{compiler.sdk.path}/include/soc/soc/esp32/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/bt/include" "-I{compiler.sdk.path}/include/bt/common/osi/include" "-I{compiler.sdk.path}/include/bt/host/bluedroid/api/include/api" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/fb_gfx/include" -compiler.c.elf.libs.esp32=-lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lbt -lcbor -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lspiffs -lulp -lunity -lwifi_provisioning -lfb_gfx -lasio -lcbor -lcoap -lesp_gdbstub -lesp_hid -lesp_https_ota -lesp_local_ctrl -lesp_serial_slave_link -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lunity -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lfb_gfx -lbt -lbtdm_app -lesp_adc_cal -lmdns -lconsole -lfatfs -lsdmmc -lwear_levelling -lopenssl -lspiffs -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lhal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc +compiler.cpreprocessor.flags.esp32=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.3-dev-907-g6c17e3a64-dirty" -DESP_PLATFORM -DESP32 "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/src/esp32" "-I{compiler.sdk.path}/include/soc/src/esp32/include" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32/include" "-I{compiler.sdk.path}/include/esp32/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/soc/soc/esp32" "-I{compiler.sdk.path}/include/soc/soc/esp32/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/bt/include" "-I{compiler.sdk.path}/include/bt/common/osi/include" "-I{compiler.sdk.path}/include/bt/host/bluedroid/api/include/api" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/fb_gfx/include" +compiler.c.elf.libs.esp32=-lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lbt -lcbor -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lspiffs -lulp -lunity -lwifi_provisioning -lfb_gfx -lasio -lcbor -lcoap -lesp_gdbstub -lesp_hid -lesp_https_ota -lesp_local_ctrl -lesp_serial_slave_link -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lunity -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lfb_gfx -lbt -lbtdm_app -lesp_adc_cal -lmdns -lconsole -lfatfs -lsdmmc -lwear_levelling -lopenssl -lspiffs -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lperfmon -lesp32 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lhal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc compiler.c.flags.esp32=-mlongcalls -Wno-frame-address -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -Og -fstack-protector -std=gnu99 -Wno-old-style-declaration -MMD -c compiler.cpp.flags.esp32=-mlongcalls -Wno-frame-address -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -Og -fstack-protector -std=gnu++11 -fexceptions -fno-rtti -MMD -c compiler.S.flags.esp32=-ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -Og -fstack-protector -x assembler-with-cpp -MMD -c -compiler.c.elf.flags.esp32=-mlongcalls -T esp32.rom.ld -T esp32.rom.libgcc.ld -T esp32.rom.newlib-data.ld -T esp32.rom.syscalls.ld -T esp32_out.ld -T esp32.project.ld -T esp32.peripherals.ld -Wl,--cref -fno-rtti -fno-lto -u esp_app_desc -u vfs_include_syscalls_impl -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u app_main -u call_user_start_cpu0 -u ld_include_panic_highint_hdl -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -Wl,--gc-sections -Wl,--undefined=uxTopUsedPriority -u newlib_include_locks_impl -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u __cxa_guard_dummy +compiler.c.elf.flags.esp32=-mlongcalls -T esp32.rom.api.ld -T esp32.rom.ld -T esp32.rom.libgcc.ld -T esp32.rom.newlib-data.ld -T esp32.rom.syscalls.ld -T esp32_out.ld -T esp32.project.ld -T esp32.peripherals.ld -Wl,--cref -fno-rtti -fno-lto -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u ld_include_panic_highint_hdl -u start_app -u start_app_other_cores -u vfs_include_syscalls_impl -u call_user_start_cpu0 -mfix-esp32-psram-cache-issue -mfix-esp32-psram-cache-strategy=memw -Wl,--gc-sections -Wl,--undefined=uxTopUsedPriority -u app_main -u newlib_include_locks_impl -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u __cxa_guard_dummy compiler.ar.flags.esp32=cru build.extra_flags.esp32=-DARDUINO_SERIAL_PORT=0 # @@ -37,12 +37,12 @@ build.extra_flags.esp32=-DARDUINO_SERIAL_PORT=0 # # ESP32S2 Support Start # -compiler.cpreprocessor.flags.esp32s2=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.2-dev-1905-g625bd5eb1-dirty" -DESP_PLATFORM -DCFG_TUSB_MCU=OPT_MCU_ESP32_S2 "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/src/esp32s2" "-I{compiler.sdk.path}/include/soc/src/esp32s2/include" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32s2/include" "-I{compiler.sdk.path}/include/esp32s2/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32s2/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32s2/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/soc/soc/esp32s2" "-I{compiler.sdk.path}/include/soc/soc/esp32s2/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32s2/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/esp_https_server/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32s2" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/tinyusb/port/esp32s2/include" "-I{compiler.sdk.path}/include/tinyusb/port/common/include" "-I{compiler.sdk.path}/include/tinyusb/tinyusb/hw/bsp" "-I{compiler.sdk.path}/include/tinyusb/tinyusb/src" "-I{compiler.sdk.path}/include/tinyusb/tinyusb/src/device" "-I{compiler.sdk.path}/include/freertos/include/freertos" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/fb_gfx/include" -compiler.c.elf.libs.esp32s2=-lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lcbor -lcoap -lconsole -lnghttp -lesp-tls -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lperfmon -lspiffs -ltinyusb -lulp -lunity -lwifi_provisioning -lfb_gfx -lasio -lcbor -lcoap -lesp_gdbstub -lesp_hid -lesp_https_ota -lesp_local_ctrl -lesp_https_server -lesp_serial_slave_link -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lperfmon -lunity -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lfb_gfx -lmdns -lconsole -lfatfs -lsdmmc -lwear_levelling -lopenssl -lspiffs -ltinyusb -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lesp_system -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lnvs_flash -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lpthread -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lhal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc +compiler.cpreprocessor.flags.esp32s2=-DHAVE_CONFIG_H -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h" -DUNITY_INCLUDE_CONFIG_H -DWITH_POSIX -D_GNU_SOURCE -DIDF_VER="v4.3-dev-907-g6c17e3a64-dirty" -DESP_PLATFORM -DESP32 "-I{compiler.sdk.path}/include/config" "-I{compiler.sdk.path}/include/newlib/platform_include" "-I{compiler.sdk.path}/include/freertos/include" "-I{compiler.sdk.path}/include/freertos/xtensa/include" "-I{compiler.sdk.path}/include/heap/include" "-I{compiler.sdk.path}/include/log/include" "-I{compiler.sdk.path}/include/lwip/include/apps" "-I{compiler.sdk.path}/include/lwip/include/apps/sntp" "-I{compiler.sdk.path}/include/lwip/lwip/src/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include" "-I{compiler.sdk.path}/include/lwip/port/esp32/include/arch" "-I{compiler.sdk.path}/include/soc/src/esp32s2" "-I{compiler.sdk.path}/include/soc/src/esp32s2/include" "-I{compiler.sdk.path}/include/soc/include" "-I{compiler.sdk.path}/include/esp_rom/include" "-I{compiler.sdk.path}/include/esp_common/include" "-I{compiler.sdk.path}/include/esp_system/include" "-I{compiler.sdk.path}/include/xtensa/include" "-I{compiler.sdk.path}/include/xtensa/esp32s2/include" "-I{compiler.sdk.path}/include/esp32s2/include" "-I{compiler.sdk.path}/include/driver/include" "-I{compiler.sdk.path}/include/driver/esp32s2/include" "-I{compiler.sdk.path}/include/esp_ringbuf/include" "-I{compiler.sdk.path}/include/efuse/include" "-I{compiler.sdk.path}/include/efuse/esp32s2/include" "-I{compiler.sdk.path}/include/espcoredump/include" "-I{compiler.sdk.path}/include/esp_timer/include" "-I{compiler.sdk.path}/include/esp_ipc/include" "-I{compiler.sdk.path}/include/soc/soc/esp32s2" "-I{compiler.sdk.path}/include/soc/soc/esp32s2/include" "-I{compiler.sdk.path}/include/soc/soc/include" "-I{compiler.sdk.path}/include/vfs/include" "-I{compiler.sdk.path}/include/esp_wifi/include" "-I{compiler.sdk.path}/include/esp_wifi/esp32s2/include" "-I{compiler.sdk.path}/include/esp_event/include" "-I{compiler.sdk.path}/include/esp_netif/include" "-I{compiler.sdk.path}/include/esp_eth/include" "-I{compiler.sdk.path}/include/tcpip_adapter/include" "-I{compiler.sdk.path}/include/app_trace/include" "-I{compiler.sdk.path}/include/mbedtls/port/include" "-I{compiler.sdk.path}/include/mbedtls/mbedtls/include" "-I{compiler.sdk.path}/include/mbedtls/esp_crt_bundle/include" "-I{compiler.sdk.path}/include/bootloader_support/include" "-I{compiler.sdk.path}/include/app_update/include" "-I{compiler.sdk.path}/include/spi_flash/include" "-I{compiler.sdk.path}/include/nvs_flash/include" "-I{compiler.sdk.path}/include/pthread/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include" "-I{compiler.sdk.path}/include/wpa_supplicant/port/include" "-I{compiler.sdk.path}/include/wpa_supplicant/include/esp_supplicant" "-I{compiler.sdk.path}/include/asio/asio/asio/include" "-I{compiler.sdk.path}/include/asio/port/include" "-I{compiler.sdk.path}/include/cbor/port/include" "-I{compiler.sdk.path}/include/coap/port/include" "-I{compiler.sdk.path}/include/coap/port/include/coap" "-I{compiler.sdk.path}/include/coap/libcoap/include" "-I{compiler.sdk.path}/include/coap/libcoap/include/coap2" "-I{compiler.sdk.path}/include/console" "-I{compiler.sdk.path}/include/nghttp/port/include" "-I{compiler.sdk.path}/include/nghttp/nghttp2/lib/includes" "-I{compiler.sdk.path}/include/esp-tls" "-I{compiler.sdk.path}/include/esp_adc_cal/include" "-I{compiler.sdk.path}/include/esp_gdbstub/include" "-I{compiler.sdk.path}/include/esp_hid/include" "-I{compiler.sdk.path}/include/tcp_transport/include" "-I{compiler.sdk.path}/include/esp_http_client/include" "-I{compiler.sdk.path}/include/esp_http_server/include" "-I{compiler.sdk.path}/include/esp_https_ota/include" "-I{compiler.sdk.path}/include/esp_https_server/include" "-I{compiler.sdk.path}/include/protobuf-c/protobuf-c" "-I{compiler.sdk.path}/include/protocomm/include/common" "-I{compiler.sdk.path}/include/protocomm/include/security" "-I{compiler.sdk.path}/include/protocomm/include/transports" "-I{compiler.sdk.path}/include/mdns/include" "-I{compiler.sdk.path}/include/esp_local_ctrl/include" "-I{compiler.sdk.path}/include/sdmmc/include" "-I{compiler.sdk.path}/include/esp_serial_slave_link/include" "-I{compiler.sdk.path}/include/esp_websocket_client/include" "-I{compiler.sdk.path}/include/expat/expat/expat/lib" "-I{compiler.sdk.path}/include/expat/port/include" "-I{compiler.sdk.path}/include/wear_levelling/include" "-I{compiler.sdk.path}/include/fatfs/diskio" "-I{compiler.sdk.path}/include/fatfs/vfs" "-I{compiler.sdk.path}/include/fatfs/src" "-I{compiler.sdk.path}/include/freemodbus/common/include" "-I{compiler.sdk.path}/include/idf_test/include" "-I{compiler.sdk.path}/include/idf_test/include/esp32s2" "-I{compiler.sdk.path}/include/jsmn/include" "-I{compiler.sdk.path}/include/json/cJSON" "-I{compiler.sdk.path}/include/libsodium/libsodium/src/libsodium/include" "-I{compiler.sdk.path}/include/libsodium/port_include" "-I{compiler.sdk.path}/include/mqtt/esp-mqtt/include" "-I{compiler.sdk.path}/include/openssl/include" "-I{compiler.sdk.path}/include/perfmon/include" "-I{compiler.sdk.path}/include/spiffs/include" "-I{compiler.sdk.path}/include/freertos/include/freertos" "-I{compiler.sdk.path}/include/tinyusb/tinyusb/src" "-I{compiler.sdk.path}/include/tinyusb/additions/include" "-I{compiler.sdk.path}/include/ulp/include" "-I{compiler.sdk.path}/include/unity/include" "-I{compiler.sdk.path}/include/unity/unity/src" "-I{compiler.sdk.path}/include/wifi_provisioning/include" "-I{compiler.sdk.path}/include/fb_gfx/include" +compiler.c.elf.libs.esp32s2=-lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lasio -lcbor -lcoap -lconsole -lnghttp -lesp-tls -lesp_adc_cal -lesp_gdbstub -lesp_hid -ltcp_transport -lesp_http_client -lesp_http_server -lesp_https_ota -lesp_https_server -lprotobuf-c -lprotocomm -lmdns -lesp_local_ctrl -lsdmmc -lesp_serial_slave_link -lesp_websocket_client -lexpat -lwear_levelling -lfatfs -lfreemodbus -ljsmn -ljson -llibsodium -lmqtt -lopenssl -lperfmon -lspiffs -lulp -lunity -lwifi_provisioning -lfb_gfx -lasio -lcbor -lcoap -lesp_gdbstub -lesp_hid -lesp_https_ota -lesp_local_ctrl -lesp_https_server -lesp_serial_slave_link -lesp_websocket_client -lexpat -lfreemodbus -ljsmn -llibsodium -lmqtt -lperfmon -lunity -lwifi_provisioning -lprotocomm -lprotobuf-c -ljson -lfb_gfx -lesp_adc_cal -lmdns -lconsole -lfatfs -lsdmmc -lwear_levelling -lopenssl -lspiffs -ltinyusb -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lxtensa -lmbedtls -lefuse -lbootloader_support -lapp_update -lesp_ipc -lspi_flash -lnvs_flash -lpthread -lesp_system -lesp_rom -lsoc -lvfs -lesp_eth -ltcpip_adapter -lesp_netif -lesp_event -lwpa_supplicant -lesp_wifi -llwip -llog -lheap -lesp_ringbuf -ldriver -lespcoredump -lesp32s2 -lesp_common -lesp_timer -lfreertos -lnewlib -lcxx -lapp_trace -lnghttp -lesp-tls -ltcp_transport -lesp_http_client -lesp_http_server -lulp -lmbedtls -lmbedcrypto -lmbedx509 -lsoc_esp32s2 -lcoexist -lcore -lespnow -lmesh -lnet80211 -lpp -lrtc -lsmartconfig -lphy -lhal -lm -lnewlib -lgcc -lstdc++ -lpthread -lapp_trace -lgcov -lapp_trace -lgcov -lc compiler.c.flags.esp32s2=-mlongcalls -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -Og -fstack-protector -std=gnu99 -Wno-old-style-declaration -MMD -c compiler.cpp.flags.esp32s2=-mlongcalls -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -Og -fstack-protector -std=gnu++11 -fexceptions -fno-rtti -MMD -c compiler.S.flags.esp32s2=-ffunction-sections -fdata-sections -fstrict-volatile-bitfields -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wno-unused-parameter -Wno-sign-compare -ggdb -Og -fstack-protector -x assembler-with-cpp -MMD -c -compiler.c.elf.flags.esp32s2=-mlongcalls -T esp32s2.rom.ld -T esp32s2.rom.libgcc.ld -T esp32s2.rom.newlib-data.ld -T esp32s2.rom.newlib-funcs.ld -T esp32s2.rom.spiflash.ld -T esp32s2_out.ld -T esp32s2.project.ld -T esp32s2.peripherals.ld -Wl,--cref -fno-rtti -fno-lto -u esp_app_desc -u vfs_include_syscalls_impl -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u app_main -u call_user_start_cpu0 -u ld_include_panic_highint_hdl -Wl,--gc-sections -Wl,--undefined=uxTopUsedPriority -u newlib_include_locks_impl -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u __cxa_guard_dummy +compiler.c.elf.flags.esp32s2=-mlongcalls -T esp32s2.rom.api.ld -T esp32s2.rom.ld -T esp32s2.rom.libgcc.ld -T esp32s2.rom.newlib-data.ld -T esp32s2.rom.newlib-funcs.ld -T esp32s2.rom.spiflash.ld -T esp32s2_out.ld -T esp32s2.project.ld -T esp32s2.peripherals.ld -Wl,--cref -fno-rtti -fno-lto -u esp_app_desc -u pthread_include_pthread_impl -u pthread_include_pthread_cond_impl -u pthread_include_pthread_local_storage_impl -u ld_include_panic_highint_hdl -u start_app -u vfs_include_syscalls_impl -u call_user_start_cpu0 -Wl,--gc-sections -Wl,--undefined=uxTopUsedPriority -u app_main -u newlib_include_locks_impl -u newlib_include_heap_impl -u newlib_include_syscalls_impl -u newlib_include_pthread_impl -u __cxa_guard_dummy compiler.ar.flags.esp32s2=cru build.extra_flags.esp32s2=-DARDUINO_SERIAL_PORT={build.serial} # diff --git a/tools/esptool.py b/tools/esptool.py index 4637cc72..ec92c03c 100755 --- a/tools/esptool.py +++ b/tools/esptool.py @@ -309,6 +309,7 @@ class ESPLoader(object): if date_reg == cls.DATE_REG_VALUE and (cls.DATE_REG2_VALUE is None or date_reg2 == cls.DATE_REG2_VALUE): # don't connect a second time inst = cls(detect_port._port, baud, trace_enabled=trace_enabled) + inst._post_connect() print(' %s' % inst.CHIP_NAME, end='') return inst except UnsupportedCommandError: @@ -538,6 +539,14 @@ class ESPLoader(object): raise FatalError("This chip is %s not %s. Wrong --chip argument?" % (actually.CHIP_NAME, self.CHIP_NAME)) except UnsupportedCommandError: self.secure_download_mode = True + self._post_connect() + + def _post_connect(self): + """ + Additional initialization hook, may be overridden by the chip-specific class. + Gets called after connect, and after auto-detection. + """ + pass def read_reg(self, addr): """ Read memory address in target """ @@ -1185,6 +1194,7 @@ class ESP8266StubLoader(ESP8266ROM): IS_STUB = True def __init__(self, rom_loader): + self.secure_download_mode = rom_loader.secure_download_mode self._port = rom_loader._port self._trace_enabled = rom_loader._trace_enabled self.flush_input() # resets _slip_reader @@ -1247,12 +1257,12 @@ class ESP32ROM(ESPLoader): OVERRIDE_VDDSDIO_CHOICES = ["1.8V", "1.9V", "OFF"] - MEMORY_MAP = [[0x3F400000, 0x3F800000, "DROM"], + MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"], + [0x3F400000, 0x3F800000, "DROM"], [0x3F800000, 0x3FC00000, "EXTRAM_DATA"], [0x3FF80000, 0x3FF82000, "RTC_DRAM"], [0x3FF90000, 0x40000000, "BYTE_ACCESSIBLE"], [0x3FFAE000, 0x40000000, "DRAM"], - [0x3FFAE000, 0x40000000, "DMA"], [0x3FFE0000, 0x3FFFFFFC, "DIRAM_DRAM"], [0x40000000, 0x40070000, "IROM"], [0x40070000, 0x40078000, "CACHE_PRO"], @@ -1318,6 +1328,12 @@ class ESP32ROM(ESPLoader): else: return False + def get_pkg_version(self): + word3 = self.read_efuse(3) + pkg_version = (word3 >> 9) & 0x07 + pkg_version += ((word3 >> 2) & 0x1) << 3 + return pkg_version + def get_chip_description(self): word3 = self.read_efuse(3) word5 = self.read_efuse(5) @@ -1325,13 +1341,15 @@ class ESP32ROM(ESPLoader): rev_bit0 = (word3 >> 15) & 0x1 rev_bit1 = (word5 >> 20) & 0x1 rev_bit2 = (apb_ctl_date >> 31) & 0x1 - pkg_version = (word3 >> 9) & 0x07 + pkg_version = self.get_pkg_version() chip_name = { 0: "ESP32D0WDQ6", 1: "ESP32D0WDQ5", 2: "ESP32D2WDQ5", - 5: "ESP32-PICO-D4", + 4: "ESP32-U4WDH", + 5: "ESP32-PICO", + 6: "ESP32-PICO-V3-02", }.get(pkg_version, "unknown ESP32") chip_revision = 0 @@ -1343,6 +1361,13 @@ class ESP32ROM(ESPLoader): chip_revision = 2 else: chip_revision = 1 + + if chip_name == "ESP32-PICO": + if chip_revision == 1: + chip_name += "-D4" + elif chip_revision == 3: + chip_name += "-V3" + return "%s (revision %d)" % (chip_name, chip_revision) def get_chip_features(self): @@ -1371,8 +1396,8 @@ class ESP32ROM(ESPLoader): else: features += ["240MHz"] - pkg_version = (word3 >> 9) & 0x07 - if pkg_version in [2, 4, 5]: + pkg_version = self.get_pkg_version() + if pkg_version in [2, 4, 5, 6]: features += ["Embedded Flash"] word4 = self.read_efuse(4) @@ -1502,16 +1527,68 @@ class ESP32S2ROM(ESP32ROM): PURPOSE_VAL_XTS_AES256_KEY_2 = 3 PURPOSE_VAL_XTS_AES128_KEY = 4 + UARTDEV_BUF_NO = 0x3ffffd14 # Variable in ROM .bss which indicates the port in use + UARTDEV_BUF_NO_USB = 2 # Value of the above variable indicating that USB is in use + + USB_RAM_BLOCK = 0x800 # Max block size USB CDC is used + + GPIO_STRAP_REG = 0x3f404038 + GPIO_STRAP_SPI_BOOT_MASK = 0x8 # Not download mode + RTC_CNTL_OPTION1_REG = 0x3f408128 + RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1 # Is download mode forced over USB? + + MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"], + [0x3F000000, 0x3FF80000, "DROM"], + [0x3F500000, 0x3FF80000, "EXTRAM_DATA"], + [0x3FF9E000, 0x3FFA0000, "RTC_DRAM"], + [0x3FF9E000, 0x40000000, "BYTE_ACCESSIBLE"], + [0x3FF9E000, 0x40072000, "MEM_INTERNAL"], + [0x3FFB0000, 0x40000000, "DRAM"], + [0x40000000, 0x4001A100, "IROM_MASK"], + [0x40020000, 0x40070000, "IRAM"], + [0x40070000, 0x40072000, "RTC_IRAM"], + [0x40080000, 0x40800000, "IROM"], + [0x50000000, 0x50002000, "RTC_DATA"]] + + def get_pkg_version(self): + num_word = 3 + block1_addr = self.EFUSE_BASE + 0x044 + word3 = self.read_reg(block1_addr + (4 * num_word)) + pkg_version = (word3 >> 21) & 0x0F + return pkg_version + def get_chip_description(self): - return "ESP32-S2" + chip_name = { + 0: "ESP32-S2", + 1: "ESP32-S2FH16", + 2: "ESP32-S2FH32", + }.get(self.get_pkg_version(), "unknown ESP32-S2") + + return "%s" % (chip_name) def get_chip_features(self): - result = ["WiFi"] + features = ["WiFi"] if self.secure_download_mode: - result.append("Secure Download Mode Enabled") + features += ["Secure Download Mode Enabled"] - return result + pkg_version = self.get_pkg_version() + + if pkg_version in [1, 2]: + if pkg_version == 1: + features += ["Embedded 2MB Flash"] + elif pkg_version == 2: + features += ["Embedded 4MB Flash"] + features += ["105C temp rating"] + + num_word = 4 + block2_addr = self.EFUSE_BASE + 0x05C + word4 = self.read_reg(block2_addr + (4 * num_word)) + block2_version = (word4 >> 4) & 0x07 + + if block2_version == 1: + features += ["ADC and temperature sensor calibration in BLK2 of efuse"] + return features def get_crystal_freq(self): # ESP32-S2 XTAL is fixed to 40MHz @@ -1554,6 +1631,46 @@ class ESP32S2ROM(ESP32ROM): return any(p == self.PURPOSE_VAL_XTS_AES256_KEY_1 for p in purposes) \ and any(p == self.PURPOSE_VAL_XTS_AES256_KEY_2 for p in purposes) + def uses_usb(self, _cache=[]): + if not _cache: + buf_no = self.read_reg(self.UARTDEV_BUF_NO) & 0xff + _cache.append(buf_no == self.UARTDEV_BUF_NO_USB) + return _cache[0] + + def _post_connect(self): + if self.uses_usb(): + self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK + + def _check_if_can_reset(self): + """ + Check the strapping register to see if we can reset out of download mode. + """ + if os.getenv("ESPTOOL_TESTING") is not None: + print("ESPTOOL_TESTING is set, ignoring strapping mode check") + # Esptool tests over USB CDC run with GPIO0 strapped low, don't complain in this case. + return + strap_reg = self.read_reg(self.GPIO_STRAP_REG) + force_dl_reg = self.read_reg(self.RTC_CNTL_OPTION1_REG) + if strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0 and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0: + print("ERROR: {} chip was placed into download mode using GPIO0.\n" + "esptool.py can not exit the download mode over USB. " + "To run the app, reset the chip manually.\n" + "To suppress this error, set --after option to 'no_reset'.".format(self.get_chip_description())) + raise SystemExit(1) + + def hard_reset(self): + if self.uses_usb(): + self._check_if_can_reset() + + self._setRTS(True) # EN->LOW + if self.uses_usb(): + # Give the chip some time to come out of reset, to be able to handle further DTR/RTS transitions + time.sleep(0.2) + self._setRTS(False) + time.sleep(0.2) + else: + self._setRTS(False) + class ESP32StubLoader(ESP32ROM): """ Access class for ESP32 stub loader, runs on top of ROM. @@ -1588,6 +1705,10 @@ class ESP32S2StubLoader(ESP32S2ROM): self._trace_enabled = rom_loader._trace_enabled self.flush_input() # resets _slip_reader + if rom_loader.uses_usb(): + self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK + self.FLASH_WRITE_SIZE = self.USB_RAM_BLOCK + ESP32S2ROM.STUB_CLASS = ESP32S2StubLoader @@ -2225,7 +2346,7 @@ class ELFFile(object): if machine != 0x5e: raise FatalError("%s does not appear to be an Xtensa ELF file. e_machine=%04x" % (self.name, machine)) if shentsize != self.LEN_SEC_HEADER: - raise FatalError("%s has unexpected section header entry size 0x%x (not 0x28)" % (self.name, shentsize, self.LEN_SEC_HEADER)) + raise FatalError("%s has unexpected section header entry size 0x%x (not 0x%x)" % (self.name, shentsize, self.LEN_SEC_HEADER)) if shnum == 0: raise FatalError("%s has 0 section headers" % (self.name)) self._read_sections(f, shoff, shnum, shstrndx) @@ -3399,137 +3520,142 @@ class AddrFilenamePairAction(argparse.Action): # Binary stub code (see flasher_stub dir for source & details) ESP8266ROM.STUB_CODE = eval(zlib.decompress(base64.b64decode(b""" -eNq9PHt/2zaSX4WkHT8UuwFIigLTuJFlW82zTZyNm97PvTX4Sptt2kTxXdxucp/9OC8QpBTbabf9Q7YAgcBgZjBv8N+b5/XF+ebtoNg8vbDm9EKr0wulpu0ffXrRNPCZn17kBXUoRZ+mHali+H7Gj0hDLTXkY8L2\ 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+hK/vTs6ZJECEkAHl5jNrfZbT1SRQ4CrleAyy8be8Nmj2TNW2Mj6wxnMiSVtELml38iHm5N7J2bLjUiDwAVJ38Ts6I7lWqR9GN6hDNwgd/PoZ142g4oBASy7CFLMVzEvFWw5lZa0Qrli34fsjNn1+hmdbIjGffkJl\ +a1SsQ0FupMHVNKwCXhRuBbF96GCYH0F63UENbH3N5rmK6mz66yr0gtETNTrToyUSPgML77JSweJAOuAEUn9Mi3Ft8u8dQrseGvPaGbXk9i3z3UvtCb5BVTrBA7mp+F5M8ic76F05hGDGmJ1Sschj6rgcyYIjMjO8\ +yGN/G3ZYcI1ZsV3hzTVYXq6wlfgSs7eCSOrkNllKKYyML+/Ky6CqhHlZWU6Y4pIVj6m3rj5j4IsmX3850wRuVpzxJWMwmBtdAYYOjFMN4xF4SglrGVkQaiZWaPf6V2TAo9V4TJmEWyU1nWtuclVC0p0EAcMm3c0C\ +z1hX649Gjn9pJIjCp5OweRb35/XqBtr0++4cCs+Bf4Zz4Ow3PAfOtrJTvET2DlixP4zHjqIzCxFlrMJ4xHiY0MCHSSkEXXHN0oRrKSZd07ZhuMYJXq7By7h4dnFVkMuvsSxlsPSabq1302zSuQKlyXkQs2A1OK7z\ +VqRH+GwNRiFzfFOmsNJS8slNzofKjRQNHOXohkWMbQAGrFuVU45RvIRLNIW71IkUKa/Ha2vwVXKHUu4OF1jV5CNF6As+Hhw+Jg2ArcpcXTMGdzibhFk9F1iBRLwVI/Kuwq0bPK/mexbGdidk4mjy9gWgy+xooKYo\ +Oqg+uq2ETiDAjSNSa2w4kodlqnSLz5dAJRuOXVRaYDDqs3evOcHvUqMj7oM3XQFzNtMA0MLVCWnMt18vbkUbt6ZHDFSr9W/UwX9KIBATozvKpTYdU/WroQPfirhWlvv6iQptnUMkWxjOhO8C4CBHGYYFLK5FlFj6\ +9B11oFOp7rq3FPS6UMpFOid5AaBkH4XLEyitTEE8vIEaf6K6K36tOSm0iL83pqpC+qV7Vmb7nqyLl3GmMnGDYDlTO1Rh+i23Zog07P2IzzXVWt0alVzqFtbS3tBpIKV/crf5cIL/j+DX35fFFfxvAmuyODezNE3a\ +L/X58uq2a8xmcLl9syqWxeC/HTTV7iZ/6U2URpExyef/AWm6JiM=\ """))) diff --git a/tools/platformio-build-esp32.py b/tools/platformio-build-esp32.py index 12dac67e..5e716cef 100644 --- a/tools/platformio-build-esp32.py +++ b/tools/platformio-build-esp32.py @@ -80,6 +80,7 @@ env.Append( "-mfix-esp32-psram-cache-strategy=memw", "-Wl,--gc-sections", "-Wl,--undefined=uxTopUsedPriority", + "-T", "esp32.rom.api.ld", "-T", "esp32.rom.ld", "-T", "esp32.rom.libgcc.ld", "-T", "esp32.rom.newlib-data.ld", @@ -88,13 +89,15 @@ env.Append( "-T", "esp32.project.ld", "-T", "esp32.peripherals.ld", "-u", "esp_app_desc", - "-u", "vfs_include_syscalls_impl", "-u", "pthread_include_pthread_impl", "-u", "pthread_include_pthread_cond_impl", "-u", "pthread_include_pthread_local_storage_impl", - "-u", "app_main", - "-u", "call_user_start_cpu0", "-u", "ld_include_panic_highint_hdl", + "-u", "start_app", + "-u", "start_app_other_cores", + "-u", "vfs_include_syscalls_impl", + "-u", "call_user_start_cpu0", + "-u", "app_main", "-u", "newlib_include_locks_impl", "-u", "newlib_include_heap_impl", "-u", "newlib_include_syscalls_impl", @@ -149,11 +152,11 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "bootloader_support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "app_update", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "spi_flash", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "nvs_flash", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "pthread", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "wpa_supplicant", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "wpa_supplicant", "port", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "wpa_supplicant", "include", "esp_supplicant"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "nvs_flash", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "pthread", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "perfmon", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "asio", "asio", "asio", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "asio", "port", "include"), @@ -215,7 +218,7 @@ env.Append( ], LIBS=[ - "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lbt", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lspiffs", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lbt", "-lbtdm_app", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" + "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lbt", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lspiffs", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lbt", "-lbtdm_app", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" ], CPPDEFINES=[ @@ -224,8 +227,14 @@ env.Append( "UNITY_INCLUDE_CONFIG_H", "WITH_POSIX", "_GNU_SOURCE", - ("IDF_VER", '\\"v4.2-dev-1905-g625bd5eb1-dirty\\"'), + ("IDF_VER", '\\"v4.3-dev-907-g6c17e3a64-dirty\\"'), "ESP_PLATFORM", + ("ARDUINO", 10812), + "ARDUINO_ESP32_DEV", + "ARDUINO_ARCH_ESP32", + ("ARDUINO_BOARD", '\\"ESP32_DEV\\"'), + ("ARDUINO_VARIANT", '\\"esp32\\"'), + "ESP32", "ARDUINO_ARCH_ESP32", "ESP32", ("F_CPU", "$BOARD_F_CPU"), diff --git a/tools/platformio-build-esp32s2.py b/tools/platformio-build-esp32s2.py index 4057af1a..ca92ef91 100644 --- a/tools/platformio-build-esp32s2.py +++ b/tools/platformio-build-esp32s2.py @@ -74,6 +74,7 @@ env.Append( "-fno-lto", "-Wl,--gc-sections", "-Wl,--undefined=uxTopUsedPriority", + "-T", "esp32s2.rom.api.ld", "-T", "esp32s2.rom.ld", "-T", "esp32s2.rom.libgcc.ld", "-T", "esp32s2.rom.newlib-data.ld", @@ -83,13 +84,14 @@ env.Append( "-T", "esp32s2.project.ld", "-T", "esp32s2.peripherals.ld", "-u", "esp_app_desc", - "-u", "vfs_include_syscalls_impl", "-u", "pthread_include_pthread_impl", "-u", "pthread_include_pthread_cond_impl", "-u", "pthread_include_pthread_local_storage_impl", - "-u", "app_main", - "-u", "call_user_start_cpu0", "-u", "ld_include_panic_highint_hdl", + "-u", "start_app", + "-u", "vfs_include_syscalls_impl", + "-u", "call_user_start_cpu0", + "-u", "app_main", "-u", "newlib_include_locks_impl", "-u", "newlib_include_heap_impl", "-u", "newlib_include_syscalls_impl", @@ -144,11 +146,11 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "bootloader_support", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "app_update", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "spi_flash", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "nvs_flash", "include"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "pthread", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "wpa_supplicant", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "wpa_supplicant", "port", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "wpa_supplicant", "include", "esp_supplicant"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "nvs_flash", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "pthread", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "asio", "asio", "asio", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "asio", "port", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "cbor", "port", "include"), @@ -160,6 +162,7 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "nghttp", "port", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "nghttp", "nghttp2", "lib", "includes"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp-tls"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_adc_cal", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_gdbstub", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_hid", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tcp_transport", "include"), @@ -193,12 +196,9 @@ env.Append( join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "openssl", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "perfmon", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "spiffs", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "port", "esp32s2", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "port", "common", "include"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "tinyusb", "hw", "bsp"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "tinyusb", "src"), - join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "tinyusb", "src", "device"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "freertos", "include", "freertos"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "tinyusb", "src"), + join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "tinyusb", "additions", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "ulp", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "unity", "include"), join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "unity", "unity", "src"), @@ -213,7 +213,7 @@ env.Append( ], LIBS=[ - "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lperfmon", "-lspiffs", "-ltinyusb", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_https_server", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lperfmon", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-ltinyusb", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" + "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lperfmon", "-lspiffs", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_https_server", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lperfmon", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-ltinyusb", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lnvs_flash", "-lpthread", "-lesp_system", "-lesp_rom", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc" ], CPPDEFINES=[ @@ -222,9 +222,14 @@ env.Append( "UNITY_INCLUDE_CONFIG_H", "WITH_POSIX", "_GNU_SOURCE", - ("IDF_VER", '\\"v4.2-dev-1905-g625bd5eb1-dirty\\"'), + ("IDF_VER", '\\"v4.3-dev-907-g6c17e3a64-dirty\\"'), "ESP_PLATFORM", - ("CFG_TUSB_MCU", 'OPT_MCU_ESP32_S2'), + ("ARDUINO", 10812), + "ARDUINO_ESP32S2_DEV", + "ARDUINO_ARCH_ESP32", + ("ARDUINO_BOARD", '\\"ESP32S2_DEV\\"'), + ("ARDUINO_VARIANT", '\\"esp32s2\\"'), + "ESP32", "ARDUINO_ARCH_ESP32", "ESP32", ("F_CPU", "$BOARD_F_CPU"), diff --git a/tools/sdk/esp32/bin/bootloader_dio_40m.bin b/tools/sdk/esp32/bin/bootloader_dio_40m.bin index 09236fa3..b164910a 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dio_40m.bin and b/tools/sdk/esp32/bin/bootloader_dio_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_dio_80m.bin b/tools/sdk/esp32/bin/bootloader_dio_80m.bin index acf317e8..d298d2a1 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dio_80m.bin and b/tools/sdk/esp32/bin/bootloader_dio_80m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_dout_40m.bin b/tools/sdk/esp32/bin/bootloader_dout_40m.bin index 09236fa3..b164910a 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dout_40m.bin and b/tools/sdk/esp32/bin/bootloader_dout_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_dout_80m.bin b/tools/sdk/esp32/bin/bootloader_dout_80m.bin index acf317e8..d298d2a1 100644 Binary files a/tools/sdk/esp32/bin/bootloader_dout_80m.bin and b/tools/sdk/esp32/bin/bootloader_dout_80m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qio_40m.bin b/tools/sdk/esp32/bin/bootloader_qio_40m.bin index 09236fa3..b164910a 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qio_40m.bin and b/tools/sdk/esp32/bin/bootloader_qio_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qio_80m.bin b/tools/sdk/esp32/bin/bootloader_qio_80m.bin index acf317e8..d298d2a1 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qio_80m.bin and b/tools/sdk/esp32/bin/bootloader_qio_80m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qout_40m.bin b/tools/sdk/esp32/bin/bootloader_qout_40m.bin index 09236fa3..b164910a 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qout_40m.bin and b/tools/sdk/esp32/bin/bootloader_qout_40m.bin differ diff --git a/tools/sdk/esp32/bin/bootloader_qout_80m.bin b/tools/sdk/esp32/bin/bootloader_qout_80m.bin index acf317e8..d298d2a1 100644 Binary files a/tools/sdk/esp32/bin/bootloader_qout_80m.bin and b/tools/sdk/esp32/bin/bootloader_qout_80m.bin differ diff --git a/tools/sdk/esp32/include/app_update/include/esp_ota_ops.h b/tools/sdk/esp32/include/app_update/include/esp_ota_ops.h index 3bb063d3..ac0ae656 100644 --- a/tools/sdk/esp32/include/app_update/include/esp_ota_ops.h +++ b/tools/sdk/esp32/include/app_update/include/esp_ota_ops.h @@ -299,6 +299,34 @@ esp_err_t esp_ota_erase_last_boot_app_partition(void); */ bool esp_ota_check_rollback_is_possible(void); +#if CONFIG_IDF_TARGET_ESP32S2 && (CONFIG_SECURE_BOOT_V2_ENABLED || __DOXYGEN__) + +/** + * Secure Boot V2 public key indexes. + */ +typedef enum { + SECURE_BOOT_PUBLIC_KEY_INDEX_0, /*!< Points to the 0th index of the Secure Boot v2 public key */ + SECURE_BOOT_PUBLIC_KEY_INDEX_1, /*!< Points to the 1st index of the Secure Boot v2 public key */ + SECURE_BOOT_PUBLIC_KEY_INDEX_2 /*!< Points to the 2nd index of the Secure Boot v2 public key */ +} esp_ota_secure_boot_public_key_index_t; + +/** + * @brief Revokes the old signature digest. To be called in the application after the rollback logic. + * + * Relevant for Secure boot v2 on ESP32-S2 where upto 3 key digests can be stored (Key #N-1, Key #N, Key #N+1). + * When key #N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key #N-1 & Key #N. + * After successfully booting the OTA app should call this function to revoke Key #N-1. + * + * @param index - The index of the signature block to be revoked + * + * @return + * - ESP_OK: If revocation is successful. + * - ESP_ERR_INVALID_ARG: If the index of the public key to be revoked is incorrect. + * - ESP_FAIL: If secure boot v2 has not been enabled. + */ +esp_err_t esp_ota_revoke_secure_boot_public_key(esp_ota_secure_boot_public_key_index_t index); +#endif /* CONFIG_IDF_TARGET_ESP32S2 */ + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/asio/asio/asio/include/asio/ssl/error.hpp b/tools/sdk/esp32/include/asio/asio/asio/include/asio/ssl/error.hpp index bbb5ef82..71599e7b 100644 --- a/tools/sdk/esp32/include/asio/asio/asio/include/asio/ssl/error.hpp +++ b/tools/sdk/esp32/include/asio/asio/asio/include/asio/ssl/error.hpp @@ -56,7 +56,8 @@ enum stream_errors #else // defined(GENERATING_DOCUMENTATION) # if (OPENSSL_VERSION_NUMBER < 0x10100000L) \ && !defined(OPENSSL_IS_BORINGSSL) \ - && !defined(ASIO_USE_WOLFSSL) + && !defined(ASIO_USE_WOLFSSL) \ + && !defined(ASIO_USE_ESP_OPENSSL) stream_truncated = ERR_PACK(ERR_LIB_SSL, 0, SSL_R_SHORT_READ), # else stream_truncated = 1, diff --git a/tools/sdk/esp32/include/asio/port/include/esp_asio_config.h b/tools/sdk/esp32/include/asio/port/include/esp_asio_config.h index 750f4cbe..bcf8c38d 100644 --- a/tools/sdk/esp32/include/asio/port/include/esp_asio_config.h +++ b/tools/sdk/esp32/include/asio/port/include/esp_asio_config.h @@ -40,4 +40,11 @@ # define ASIO_STANDALONE # define ASIO_HAS_PTHREADS +# ifdef CONFIG_ASIO_USE_ESP_OPENSSL +# define ASIO_USE_ESP_OPENSSL +# define OPENSSL_NO_ENGINE +# elif CONFIG_ASIO_USE_ESP_WOLFSSL +# define ASIO_USE_WOLFSSL +# endif // CONFIG_ASIO_USE_ESP_OPENSSL + #endif // _ESP_ASIO_CONFIG_H_ diff --git a/tools/sdk/esp32/include/asio/port/include/openssl/conf.h b/tools/sdk/esp32/include/asio/port/include/openssl/conf.h new file mode 100644 index 00000000..f125c3e6 --- /dev/null +++ b/tools/sdk/esp32/include/asio/port/include/openssl/conf.h @@ -0,0 +1,26 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_CONF_H +#define _ESP_ASIO_OPENSSL_CONF_H +#include "esp_asio_config.h" +#include "openssl/esp_asio_openssl_stubs.h" + +#if defined(ASIO_USE_WOLFSSL) +// SSLv3 Methods not present in current wolfSSL library +#define OPENSSL_NO_SSL3 +#include_next "openssl/conf.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_CONF_H diff --git a/tools/sdk/esp32/include/asio/port/include/openssl/dh.h b/tools/sdk/esp32/include/asio/port/include/openssl/dh.h new file mode 100644 index 00000000..def713cf --- /dev/null +++ b/tools/sdk/esp32/include/asio/port/include/openssl/dh.h @@ -0,0 +1,23 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_DH_STUB_H +#define _ESP_ASIO_OPENSSL_DH_STUB_H +// Dummy header needed for ASIO compilation with esp-openssl + +#if defined(ASIO_USE_WOLFSSL) +#include_next "openssl/dh.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_DH_STUB_H diff --git a/tools/sdk/esp32/include/asio/port/include/openssl/esp_asio_openssl_stubs.h b/tools/sdk/esp32/include/asio/port/include/openssl/esp_asio_openssl_stubs.h new file mode 100644 index 00000000..fde52317 --- /dev/null +++ b/tools/sdk/esp32/include/asio/port/include/openssl/esp_asio_openssl_stubs.h @@ -0,0 +1,209 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_STUBS_H +#define _ESP_ASIO_OPENSSL_STUBS_H + +/** + * @note This header contains openssl API which are NOT implemented, and are only provided + * as stubs or no-operations to get the ASIO library compiled and working with most + * practical use cases as an embedded application on ESP platform + */ + +#if defined(ASIO_USE_WOLFSSL) + +#include "wolfssl/ssl.h" +// esp-wolfssl disables filesystem by default, but the ssl filesystem functions are needed for the ASIO to compile +// - so we could either configure wolfSSL to use filesystem +// - or use the default wolfSSL and declare the filesystem functions -- preferred option, as whenever +// the filesystem functions are used from app code (potential security impact if private keys in a filesystem) +// compilation fails with linking errors. + +#if defined(NO_FILESYSTEM) +// WolfSSL methods that are not included in standard esp-wolfssl config, must be defined here +// as function stubs, so ASIO compiles, but would get link errors, if these functions were used. + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct WOLFSSL_CTX WOLFSSL_CTX; + +void wolfSSL_CTX_set_verify_depth(WOLFSSL_CTX *ctx,int depth); +int SSL_CTX_load_verify_locations(WOLFSSL_CTX*, const char*, const char*); +int SSL_CTX_use_certificate_file(WOLFSSL_CTX*, const char*, int); +int SSL_CTX_use_certificate_chain_file(WOLFSSL_CTX*, const char*); +int SSL_CTX_use_PrivateKey_file(WOLFSSL_CTX*, const char*, int); +int SSL_CTX_use_RSAPrivateKey_file(WOLFSSL_CTX*, const char*, int); + +#if defined(__cplusplus) +} /* extern C */ +#endif + +#endif // NO_FILESYSTEM + +#elif defined(ASIO_USE_ESP_OPENSSL) + +#include "internal/ssl_x509.h" +#include "internal/ssl_pkey.h" +#include "mbedtls/pem.h" +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +// The most applicable OpenSSL version wrtt ASIO usage +#define OPENSSL_VERSION_NUMBER 0x10100001L +// SSLv2 methods not supported +// OpenSSL port supports: TLS_ANY, TLS_1, TLS_1_1, TLS_1_2, SSL_3 +#define OPENSSL_NO_SSL2 +#define SSL2_VERSION 0x0002 + +#define SSL_R_SHORT_READ 219 +#define SSL_OP_ALL 0 +#define SSL_OP_SINGLE_DH_USE 0 +#define SSL_OP_NO_COMPRESSION 0 +// Translates mbedTLS PEM parse error, used by ASIO +#define PEM_R_NO_START_LINE -MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT + +#define SSL_OP_NO_SSLv2 0x01000000L +#define SSL_OP_NO_SSLv3 0x02000000L +#define SSL_OP_NO_TLSv1 0x04000000L + +#define X509_FILETYPE_PEM 1 +#define X509_FILETYPE_ASN1 2 +#define SSL_FILETYPE_ASN1 X509_FILETYPE_ASN1 +#define SSL_FILETYPE_PEM X509_FILETYPE_PEM + +#define NID_subject_alt_name 85 + + +#define GEN_DNS 2 +#define GEN_IPADD 7 +#define V_ASN1_OCTET_STRING 4 +#define V_ASN1_IA5STRING 22 +#define NID_commonName 13 + +#define SSL_CTX_get_app_data(ctx) ((void*)SSL_CTX_get_ex_data(ctx, 0)) + +/** +* @brief Frees DH object -- not implemented +* +* Current implementation calls SSL_ASSERT +* +* @param r DH object +*/ +void DH_free(DH *r); + +/** + * @brief Frees GENERAL_NAMES -- not implemented + * + * Current implementation calls SSL_ASSERT + * + * @param r GENERAL_NAMES object + */ +void GENERAL_NAMES_free(GENERAL_NAMES * gens); + +/** + * @brief Returns subject name from X509 -- not implemented + * + * Current implementation calls SSL_ASSERT + * + * @param r X509 object + */ +X509_NAME *X509_get_subject_name(X509 *a); + +/** + * @brief API provaded as declaration only + * + */ +int X509_STORE_CTX_get_error_depth(X509_STORE_CTX *ctx); + +/** + * @brief API provaded as declaration only + * + */ +int X509_NAME_get_index_by_NID(X509_NAME *name, int nid, int lastpos); + +/** + * @brief API provaded as declaration only + * + */ +X509_NAME_ENTRY *X509_NAME_get_entry(X509_NAME *name, int loc); + +/** + * @brief API provaded as declaration only + * + */ +ASN1_STRING *X509_NAME_ENTRY_get_data(X509_NAME_ENTRY *ne); + +/** + * @brief API provaded as declaration only + * + */ +void *X509_get_ext_d2i(X509 *x, int nid, int *crit, int *idx); + +/** + * @brief API provaded as declaration only + * + */ +X509 * X509_STORE_CTX_get_current_cert(X509_STORE_CTX *ctx); + +/** + * @brief Reads DH params from a bio object -- not implemented + * + * Current implementation calls SSL_ASSERT + */ +DH *PEM_read_bio_DHparams(BIO *bp, DH **x, pem_password_cb *cb, void *u); + +/** + * @brief API provaded as declaration only + * + */ +void * X509_STORE_CTX_get_ex_data(X509_STORE_CTX *ctx,int idx); + +/** + * @brief Sets DH params to ssl ctx -- not implemented + * + * Current implementation calls SSL_ASSERT + */ +int SSL_CTX_set_tmp_dh(SSL_CTX *ctx, const DH *dh); + +/** + * @brief API provaded as declaration only + * + */ +void SSL_CTX_set_default_passwd_cb_userdata(SSL_CTX *ctx, void *data); + +/** + * @brief API provaded as declaration only + * + */ +void SSL_CTX_set_default_passwd_cb(SSL_CTX *ctx, pem_password_cb *cb); + +/** + * @brief Clears any existing chain associated with the current certificate of ctx. + * + */ +int SSL_CTX_clear_chain_certs(SSL_CTX *ctx); + +#if defined(__cplusplus) +} /* extern C */ +#endif + +#endif /* ASIO_USE_ESP_OPENSSL, ASIO_USE_WOLFSSL */ +#endif /* _ESP_ASIO_OPENSSL_STUBS_H */ diff --git a/tools/sdk/esp32/include/asio/port/include/openssl/rsa.h b/tools/sdk/esp32/include/asio/port/include/openssl/rsa.h new file mode 100644 index 00000000..5d9d10e8 --- /dev/null +++ b/tools/sdk/esp32/include/asio/port/include/openssl/rsa.h @@ -0,0 +1,23 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_RSA_STUB_H +#define _ESP_ASIO_OPENSSL_RSA_STUB_H +// Dummy header needed for ASIO compilation with esp-openssl + +#if defined(ASIO_USE_WOLFSSL) +#include_next "openssl/rsa.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_RSA_STUB_H diff --git a/tools/sdk/esp32/include/asio/port/include/openssl/x509v3.h b/tools/sdk/esp32/include/asio/port/include/openssl/x509v3.h new file mode 100644 index 00000000..5ae8e784 --- /dev/null +++ b/tools/sdk/esp32/include/asio/port/include/openssl/x509v3.h @@ -0,0 +1,23 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_X509V3_STUB_H +#define _ESP_ASIO_OPENSSL_X509V3_STUB_H +// Dummy header needed for ASIO compilation with esp-openssl + +#if defined(ASIO_USE_WOLFSSL) +#include_next "openssl/x509v3.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_X509V3_STUB_H diff --git a/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash_config.h b/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash_config.h index 98c169f4..45367730 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash_config.h +++ b/tools/sdk/esp32/include/bootloader_support/include/bootloader_flash_config.h @@ -14,6 +14,7 @@ #pragma once +#include "sdkconfig.h" #include "esp_image_format.h" #ifdef __cplusplus @@ -66,6 +67,22 @@ void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr); */ void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr); +#ifdef CONFIG_IDF_TARGET_ESP32 +/** + * @brief Return the pin number used for custom SPI flash and/or SPIRAM WP pin + * + * Can be determined by eFuse values in most cases, or overriden in configuration + * + * This value is only meaningful if the other SPI flash pins are overriden via eFuse. + * + * This value is only meaningful if flash is set to QIO or QOUT mode, or if + * SPIRAM is enabled. + * + * @return Pin number to use, or -1 if the default should be kept + */ +int bootloader_flash_get_wp_pin(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/bootloader_support/include/esp_app_format.h b/tools/sdk/esp32/include/bootloader_support/include/esp_app_format.h index 0f0a6038..a67c38ee 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/esp_app_format.h +++ b/tools/sdk/esp32/include/bootloader_support/include/esp_app_format.h @@ -19,7 +19,8 @@ */ typedef enum { ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */ - ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32S2 */ + ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */ + ESP_CHIP_ID_ESP32S3 = 0x0004, /*!< chip ID: ESP32-S3 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/tools/sdk/esp32/include/bootloader_support/include/esp_flash_partitions.h b/tools/sdk/esp32/include/bootloader_support/include/esp_flash_partitions.h index 004bbeb2..1fc9d4f6 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/esp_flash_partitions.h +++ b/tools/sdk/esp32/include/bootloader_support/include/esp_flash_partitions.h @@ -44,7 +44,7 @@ extern "C" { /* Pre-partition table fixed flash offsets */ #define ESP_BOOTLOADER_DIGEST_OFFSET 0x0 -#define ESP_BOOTLOADER_OFFSET 0x1000 /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */ +#define ESP_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */ #define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/ #define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */ diff --git a/tools/sdk/esp32/include/bootloader_support/include/esp_secure_boot.h b/tools/sdk/esp32/include/bootloader_support/include/esp_secure_boot.h index 551a7370..f15c240d 100644 --- a/tools/sdk/esp32/include/bootloader_support/include/esp_secure_boot.h +++ b/tools/sdk/esp32/include/bootloader_support/include/esp_secure_boot.h @@ -17,11 +17,10 @@ #include #include "soc/efuse_periph.h" #include "esp_image_format.h" - +#include "esp_rom_efuse.h" #include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/efuse.h" -#else + +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/secure_boot.h" #endif @@ -57,8 +56,8 @@ static inline bool esp_secure_boot_enabled(void) #elif CONFIG_SECURE_BOOT_V2_ENABLED return ets_use_secure_boot_v2(); #endif -#elif CONFIG_IDF_TARGET_ESP32S2 - return ets_efuse_secure_boot_enabled(); +#else + return esp_rom_efuse_is_secure_boot_enabled(); #endif return false; /* Secure Boot not enabled in menuconfig */ } diff --git a/tools/sdk/esp32/include/bt/common/osi/include/osi/list.h b/tools/sdk/esp32/include/bt/common/osi/include/osi/list.h index c0abd106..d3373fcc 100644 --- a/tools/sdk/esp32/include/bt/common/osi/include/osi/list.h +++ b/tools/sdk/esp32/include/bt/common/osi/include/osi/list.h @@ -34,6 +34,10 @@ bool list_is_empty(const list_t *list); // |list| may not be NULL. bool list_contains(const list_t *list, const void *data); +// Returns list_node which contains |data|, NULL otherwise. +// |list| may not be NULL. +list_node_t *list_get_node(const list_t *list, const void *data); + // Returns the length of the |list|. |list| may not be NULL. size_t list_length(const list_t *list); diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h index 37b9b2f9..4ecc64a3 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_bt_api.h @@ -155,6 +155,16 @@ typedef enum { #define ESP_BT_IO_CAP_NONE 3 /*!< NoInputNoOutput */ /* relate to BTM_IO_CAP_NONE in stack/btm_api.h */ typedef uint8_t esp_bt_io_cap_t; /*!< combination of the io capability */ + +/* BTM Power manager modes */ +#define ESP_BT_PM_MD_ACTIVE 0x00 /*!< Active mode */ +#define ESP_BT_PM_MD_HOLD 0x01 /*!< Hold mode */ +#define ESP_BT_PM_MD_SNIFF 0x02 /*!< Sniff mode */ +#define ESP_BT_PM_MD_PARK 0x03 /*!< Park state */ +typedef uint8_t esp_bt_pm_mode_t; + + + /// Bits of major service class field #define ESP_BT_COD_SRVC_BIT_MASK (0xffe000) /*!< Major service bit mask */ #define ESP_BT_COD_SRVC_BIT_OFFSET (13) /*!< Major service bit offset */ @@ -210,6 +220,7 @@ typedef enum { ESP_BT_GAP_CONFIG_EIR_DATA_EVT, /*!< config EIR data event */ ESP_BT_GAP_SET_AFH_CHANNELS_EVT, /*!< set AFH channels event */ ESP_BT_GAP_READ_REMOTE_NAME_EVT, /*!< read Remote Name event */ + ESP_BT_GAP_MODE_CHG_EVT, ESP_BT_GAP_EVT_MAX, } esp_bt_gap_cb_event_t; @@ -336,6 +347,14 @@ typedef union { uint8_t rmt_name[ESP_BT_GAP_MAX_BDNAME_LEN + 1]; /*!< Remote device name */ } read_rmt_name; /*!< read Remote Name parameter struct */ + /** + * @brief ESP_BT_GAP_MODE_CHG_EVT + */ + struct mode_chg_param { + esp_bd_addr_t bda; /*!< remote bluetooth device address*/ + esp_bt_pm_mode_t mode; /*!< PM mode*/ + } mode_chg; /*!< mode change event parameter struct */ + } esp_bt_gap_cb_param_t; /** @@ -427,13 +446,15 @@ esp_err_t esp_bt_gap_register_callback(esp_bt_gap_cb_t callback); esp_err_t esp_bt_gap_set_scan_mode(esp_bt_connection_mode_t c_mode, esp_bt_discovery_mode_t d_mode); /** - * @brief Start device discovery. This function should be called after esp_bluedroid_enable() completes successfully. - * esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_STATE_CHANGED_EVT if discovery is started or halted. - * esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_RES_EVT if discovery result is got. + * @brief This function starts Inquiry and Name Discovery. It should be called after esp_bluedroid_enable() completes successfully. + * When Inquiry is halted and cached results do not contain device name, then Name Discovery will connect to the peer target to get the device name. + * esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_STATE_CHANGED_EVT when Inquriry is started or Name Discovery is completed. + * esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_RES_EVT each time the two types of discovery results are got. * - * @param[in] mode - inquiry mode - * @param[in] inq_len - inquiry duration in 1.28 sec units, ranging from 0x01 to 0x30 - * @param[in] num_rsps - number of inquiry responses that can be received, value 0 indicates an unlimited number of responses + * @param[in] mode - Inquiry mode + * @param[in] inq_len - Inquiry duration in 1.28 sec units, ranging from 0x01 to 0x30. This parameter only specifies the total duration of the Inquiry process, + * - when this time expires, Inquiry will be halted. + * @param[in] num_rsps - Number of responses that can be received before the Inquiry is halted, value 0 indicates an unlimited number of responses. * * @return * - ESP_OK : Succeed @@ -444,8 +465,9 @@ esp_err_t esp_bt_gap_set_scan_mode(esp_bt_connection_mode_t c_mode, esp_bt_disco esp_err_t esp_bt_gap_start_discovery(esp_bt_inq_mode_t mode, uint8_t inq_len, uint8_t num_rsps); /** - * @brief Cancel device discovery. This function should be called after esp_bluedroid_enable() completes successfully - * esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_STATE_CHANGED_EVT if discovery is stopped. + * @brief Cancel Inquiry and Name Discovery. This function should be called after esp_bluedroid_enable() completes successfully. + * esp_bt_gap_cb_t will be called with ESP_BT_GAP_DISC_STATE_CHANGED_EVT if Inquiry or Name Discovery is cancelled by + * calling this function. * * @return * - ESP_OK : Succeed diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatt_common_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatt_common_api.h index bee2c28f..447a26bd 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatt_common_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatt_common_api.h @@ -46,6 +46,7 @@ extern esp_err_t esp_ble_gatt_set_local_mtu (uint16_t mtu); #if (BLE_INCLUDED == TRUE) extern uint16_t esp_ble_get_sendable_packets_num (void); +extern uint16_t esp_ble_get_cur_sendable_packets_num (uint16_t connid); #endif #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatts_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatts_api.h index 341e71b7..42dfeb26 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatts_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gatts_api.h @@ -326,7 +326,7 @@ esp_err_t esp_ble_gatts_app_unregister(esp_gatt_if_t gatts_if); /** * @brief Create a service. When service creation is done, a callback - * event BTA_GATTS_CREATE_SRVC_EVT is called to report status + * event ESP_GATTS_CREATE_EVT is called to report status * and service ID to the profile. The service ID obtained in * the callback function needs to be used when adding included * service and characteristics/descriptors into the service. @@ -363,7 +363,7 @@ esp_err_t esp_ble_gatts_create_attr_tab(const esp_gatts_attr_db_t *gatts_attr_db /** * @brief This function is called to add an included service. This function have to be called between * 'esp_ble_gatts_create_service' and 'esp_ble_gatts_add_char'. After included - * service is included, a callback event BTA_GATTS_ADD_INCL_SRVC_EVT + * service is included, a callback event ESP_GATTS_ADD_INCL_SRVC_EVT * is reported the included service ID. * * @param[in] service_handle: service handle to which this included service is to @@ -402,7 +402,7 @@ esp_err_t esp_ble_gatts_add_char(uint16_t service_handle, esp_bt_uuid_t *char_ /** * @brief This function is called to add characteristic descriptor. When - * it's done, a callback event BTA_GATTS_ADD_DESCR_EVT is called + * it's done, a callback event ESP_GATTS_ADD_DESCR_EVT is called * to report the status and an ID number for this descriptor. * * @param[in] service_handle: service handle to which this characteristic descriptor is to @@ -425,7 +425,7 @@ esp_err_t esp_ble_gatts_add_char_descr (uint16_t service_handle, /** * @brief This function is called to delete a service. When this is done, - * a callback event BTA_GATTS_DELETE_EVT is report with the status. + * a callback event ESP_GATTS_DELETE_EVT is report with the status. * * @param[in] service_handle: service_handle to be deleted. * diff --git a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_spp_api.h b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_spp_api.h index 9163fea8..8f1c0608 100644 --- a/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_spp_api.h +++ b/tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_spp_api.h @@ -57,6 +57,7 @@ typedef enum { */ typedef enum { ESP_SPP_INIT_EVT = 0, /*!< When SPP is inited, the event comes */ + ESP_SPP_UNINIT_EVT = 1, /*!< When SPP is uninited, the event comes */ ESP_SPP_DISCOVERY_COMP_EVT = 8, /*!< When SDP discovery complete, the event comes */ ESP_SPP_OPEN_EVT = 26, /*!< When SPP Client connection open, the event comes */ ESP_SPP_CLOSE_EVT = 27, /*!< When SPP connection closed, the event comes */ @@ -66,6 +67,7 @@ typedef enum { ESP_SPP_CONG_EVT = 31, /*!< When SPP connection congestion status changed, the event comes, only for ESP_SPP_MODE_CB */ ESP_SPP_WRITE_EVT = 33, /*!< When SPP write operation completes, the event comes, only for ESP_SPP_MODE_CB */ ESP_SPP_SRV_OPEN_EVT = 34, /*!< When SPP Server connection open, the event comes */ + ESP_SPP_SRV_STOP_EVT = 35, /*!< When SPP server stopped, the event comes */ } esp_spp_cb_event_t; @@ -80,6 +82,13 @@ typedef union { esp_spp_status_t status; /*!< status */ } init; /*!< SPP callback param of SPP_INIT_EVT */ + /** + * @brief SPP_UNINIT_EVT + */ + struct spp_uninit_evt_param { + esp_spp_status_t status; /*!< status */ + } uninit; /*!< SPP callback param of SPP_UNINIT_EVT */ + /** * @brief SPP_DISCOVERY_COMP_EVT */ @@ -128,6 +137,14 @@ typedef union { uint8_t sec_id; /*!< security ID used by this server */ bool use_co; /*!< TRUE to use co_rfc_data */ } start; /*!< SPP callback param of ESP_SPP_START_EVT */ + + /** + * @brief ESP_SPP_SRV_STOP_EVT + */ + struct spp_srv_stop_evt_param { + esp_spp_status_t status; /*!< status */ + } srv_stop; /*!< SPP callback param of ESP_SPP_SRV_STOP_EVT */ + /** * @brief ESP_SPP_CL_INIT_EVT */ @@ -273,6 +290,16 @@ esp_err_t esp_spp_disconnect(uint32_t handle); esp_err_t esp_spp_start_srv(esp_spp_sec_t sec_mask, esp_spp_role_t role, uint8_t local_scn, const char *name); +/** + * @brief This function stops a SPP server + * When the server is stopped successfully, the callback is called + * with ESP_SPP_SRV_STOP_EVT. + * + * @return + * - ESP_OK: success + * - other: failed + */ +esp_err_t esp_spp_stop_srv(void); /** * @brief This function is used to write data, only for ESP_SPP_MODE_CB. diff --git a/tools/sdk/esp32/include/bt/include/esp_bt.h b/tools/sdk/esp32/include/bt/include/esp_bt.h index 6435e954..de8b0423 100644 --- a/tools/sdk/esp32/include/bt/include/esp_bt.h +++ b/tools/sdk/esp32/include/bt/include/esp_bt.h @@ -25,7 +25,7 @@ extern "C" { #endif -#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL 0x20200106 +#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL 0x20200622 /** * @brief Bluetooth mode for controller enable/disable @@ -117,6 +117,12 @@ the adv packet will be discarded until the memory is restored. */ #define BTDM_CTRL_AUTO_LATENCY_EFF false #endif +#ifdef CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF +#define BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF +#else +#define BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF false +#endif + #define BTDM_CONTROLLER_BLE_MAX_CONN_LIMIT 9 //Maximum BLE connection limitation #define BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_LIMIT 7 //Maximum ACL connection limitation #define BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_LIMIT 3 //Maximum SCO/eSCO connection limitation @@ -140,8 +146,11 @@ the adv packet will be discarded until the memory is restored. */ .bt_max_acl_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF, \ .bt_sco_datapath = CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF, \ .auto_latency = BTDM_CTRL_AUTO_LATENCY_EFF, \ + .bt_legacy_auth_vs_evt = BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF, \ .bt_max_sync_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF, \ .ble_sca = CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF, \ + .pcm_role = CONFIG_BTDM_CTRL_PCM_ROLE_EFF, \ + .pcm_polar = CONFIG_BTDM_CTRL_PCM_POLAR_EFF, \ .magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL, \ }; @@ -173,6 +182,7 @@ typedef struct { uint8_t bt_max_acl_conn; /*!< BR/EDR maximum ACL connection numbers */ uint8_t bt_sco_datapath; /*!< SCO data path, i.e. HCI or PCM module */ bool auto_latency; /*!< BLE auto latency, used to enhance classic BT performance */ + bool bt_legacy_auth_vs_evt; /*!< BR/EDR Legacy auth complete event required to protect from BIAS attack */ /* * Following parameters can not be configured runtime when call esp_bt_controller_init() * It will be overwrite with a constant value which in menuconfig or from a macro. @@ -180,6 +190,8 @@ typedef struct { */ uint8_t bt_max_sync_conn; /*!< BR/EDR maximum ACL connection numbers. Effective in menuconfig */ uint8_t ble_sca; /*!< BLE low power crystal accuracy index */ + uint8_t pcm_role; /*!< PCM role (master & slave)*/ + uint8_t pcm_polar; /*!< PCM polar trig (falling clk edge & rising clk edge) */ uint32_t magic; /*!< Magic number */ } esp_bt_controller_config_t; diff --git a/tools/sdk/esp32/include/config/sdkconfig.h b/tools/sdk/esp32/include/config/sdkconfig.h index 79949888..61b14a24 100644 --- a/tools/sdk/esp32/include/config/sdkconfig.h +++ b/tools/sdk/esp32/include/config/sdkconfig.h @@ -14,6 +14,7 @@ #define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 #define CONFIG_APP_COMPILE_TIME_DATE 1 #define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000 #define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 #define CONFIG_BOOTLOADER_LOG_LEVEL_NONE 1 #define CONFIG_BOOTLOADER_LOG_LEVEL 0 @@ -22,7 +23,6 @@ #define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0 #define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 -#define CONFIG_ESPTOOLPY_WITH_STUB 1 #define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1 #define CONFIG_ESPTOOLPY_FLASHMODE "dio" #define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1 @@ -71,6 +71,13 @@ #define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN 0 #define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM 1 #define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 1 +#define CONFIG_BTDM_CTRL_PCM_ROLE_EDGE_CONFIG 1 +#define CONFIG_BTDM_CTRL_PCM_ROLE_MASTER 1 +#define CONFIG_BTDM_CTRL_PCM_POLAR_FALLING_EDGE 1 +#define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0 +#define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0 +#define CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT 1 +#define CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF 1 #define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 3 #define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 2 #define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0 @@ -123,6 +130,7 @@ #define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1 #define CONFIG_EFUSE_MAX_BLK_LEN 192 #define CONFIG_ESP_TLS_USING_MBEDTLS 1 +#define CONFIG_ESP32_ECO3_CACHE_LOCK_FIX 1 #define CONFIG_ESP32_REV_MIN_0 1 #define CONFIG_ESP32_REV_MIN 0 #define CONFIG_ESP32_DPORT_WORKAROUND 1 @@ -174,9 +182,8 @@ #define CONFIG_ESP_IPC_USES_CALLERS_PRIORITY 1 #define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048 #define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_UART 1 #define CONFIG_ESP_CONSOLE_UART_NUM 0 -#define CONFIG_ESP_CONSOLE_UART_TX_GPIO 1 -#define CONFIG_ESP_CONSOLE_UART_RX_GPIO 3 #define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200 #define CONFIG_ESP_INT_WDT 1 #define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300 @@ -219,6 +226,7 @@ #define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER 1 #define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 0 #define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM 16 +#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 #define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 #define CONFIG_ESP32_WIFI_TX_BA_WIN 6 #define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 @@ -241,16 +249,20 @@ #define CONFIG_FATFS_TIMEOUT_MS 10000 #define CONFIG_FATFS_PER_FILE_CACHE 1 #define CONFIG_FATFS_ALLOC_PREFER_EXTRAM 1 +#define CONFIG_FMB_COMM_MODE_TCP_EN 1 +#define CONFIG_FMB_TCP_PORT_DEFAULT 502 +#define CONFIG_FMB_TCP_PORT_MAX_CONN 5 +#define CONFIG_FMB_TCP_CONNECTION_TOUT_SEC 20 #define CONFIG_FMB_COMM_MODE_RTU_EN 1 #define CONFIG_FMB_COMM_MODE_ASCII_EN 1 #define CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND 150 #define CONFIG_FMB_MASTER_DELAY_MS_CONVERT 200 #define CONFIG_FMB_QUEUE_LENGTH 20 -#define CONFIG_FMB_SERIAL_TASK_STACK_SIZE 2048 +#define CONFIG_FMB_PORT_TASK_STACK_SIZE 4096 #define CONFIG_FMB_SERIAL_BUF_SIZE 256 #define CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB 8 #define CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS 1000 -#define CONFIG_FMB_SERIAL_TASK_PRIO 10 +#define CONFIG_FMB_PORT_TASK_PRIO 10 #define CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT 20 #define CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE 20 #define CONFIG_FMB_CONTROLLER_STACK_SIZE 4096 @@ -290,6 +302,8 @@ #define CONFIG_LWIP_SO_REUSE 1 #define CONFIG_LWIP_SO_REUSE_RXTOALL 1 #define CONFIG_LWIP_SO_RCVBUF 1 +#define CONFIG_LWIP_IP4_FRAG 1 +#define CONFIG_LWIP_IP6_FRAG 1 #define CONFIG_LWIP_ETHARP_TRUST_IP_MAC 1 #define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1 #define CONFIG_LWIP_GARP_TMR_INTERVAL 60 @@ -311,6 +325,7 @@ #define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6 #define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1 #define CONFIG_LWIP_TCP_OVERSIZE_MSS 1 +#define CONFIG_LWIP_TCP_RTO_TIME 3000 #define CONFIG_LWIP_MAX_UDP_PCBS 16 #define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6 #define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 2560 @@ -318,6 +333,8 @@ #define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x0 #define CONFIG_LWIP_PPP_SUPPORT 1 #define CONFIG_LWIP_PPP_ENABLE_IPV6 1 +#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3 +#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5 #define CONFIG_LWIP_PPP_PAP_SUPPORT 1 #define CONFIG_LWIP_PPP_CHAP_SUPPORT 1 #define CONFIG_LWIP_PPP_MSCHAP_SUPPORT 1 @@ -395,6 +412,7 @@ #define CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE 1 #define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 #define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_OPENSSL_ERROR_STACK 1 #define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1 #define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5 #define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 2048 @@ -407,6 +425,7 @@ #define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 #define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 #define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192 #define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1 #define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 #define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 @@ -421,8 +440,7 @@ #define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 #define CONFIG_SPIFFS_META_LENGTH 4 #define CONFIG_SPIFFS_USE_MTIME 1 -#define CONFIG_USB_DESC_CUSTOM_VID 0x1234 -#define CONFIG_USB_DESC_CUSTOM_PID 0x5678 +#define CONFIG_WS_BUFFER_SIZE 1024 #define CONFIG_UNITY_ENABLE_FLOAT 1 #define CONFIG_UNITY_ENABLE_DOUBLE 1 #define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1 @@ -463,10 +481,7 @@ #define CONFIG_BTU_TASK_STACK_SIZE CONFIG_BT_BTU_TASK_STACK_SIZE #define CONFIG_CLASSIC_BT_ENABLED CONFIG_BT_CLASSIC_ENABLED #define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT -#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE #define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT -#define CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO -#define CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO #define CONFIG_CXX_EXCEPTIONS CONFIG_COMPILER_CXX_EXCEPTIONS #define CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE #define CONFIG_DUPLICATE_SCAN_CACHE_SIZE CONFIG_BTDM_SCAN_DUPL_CACHE_SIZE @@ -503,8 +518,8 @@ #define CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND #define CONFIG_MB_QUEUE_LENGTH CONFIG_FMB_QUEUE_LENGTH #define CONFIG_MB_SERIAL_BUF_SIZE CONFIG_FMB_SERIAL_BUF_SIZE -#define CONFIG_MB_SERIAL_TASK_PRIO CONFIG_FMB_SERIAL_TASK_PRIO -#define CONFIG_MB_SERIAL_TASK_STACK_SIZE CONFIG_FMB_SERIAL_TASK_STACK_SIZE +#define CONFIG_MB_SERIAL_TASK_PRIO CONFIG_FMB_PORT_TASK_PRIO +#define CONFIG_MB_SERIAL_TASK_STACK_SIZE CONFIG_FMB_PORT_TASK_STACK_SIZE #define CONFIG_MB_TIMER_GROUP CONFIG_FMB_TIMER_GROUP #define CONFIG_MB_TIMER_INDEX CONFIG_FMB_TIMER_INDEX #define CONFIG_MB_TIMER_PORT_ENABLED CONFIG_FMB_TIMER_PORT_ENABLED diff --git a/tools/sdk/esp32/include/console/esp_console.h b/tools/sdk/esp32/include/console/esp_console.h index 1409bfe5..98201cdb 100644 --- a/tools/sdk/esp32/include/console/esp_console.h +++ b/tools/sdk/esp32/include/console/esp_console.h @@ -56,60 +56,49 @@ typedef struct { uint32_t task_stack_size; //!< repl task stack size uint32_t task_priority; //!< repl task priority const char *prompt; //!< prompt (NULL represents default: "esp> ") - union { - struct { - int channel; //!< UART channel - uint32_t baud_rate; //!< Comunication baud rate - int tx_gpio; //!< GPIO number for TX path, -1 means using the default - int rx_gpio; //!< GPIO number for RX path, -1 means using the default - } uart; //!< UART specific configuration - } device; //!< device configuration } esp_console_repl_config_t; -#ifdef CONFIG_ESP_CONSOLE_UART_NUM -#define CONSOLE_DEFAULT_UART_CHANNEL CONFIG_ESP_CONSOLE_UART_NUM -#else -#define CONSOLE_DEFAULT_UART_CHANNEL 0 -#endif - -#ifdef CONFIG_ESP_CONSOLE_UART_BAUDRATE -#define CONSOLE_DEFAULT_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE -#else -#define CONSOLE_DEFAULT_UART_BAUDRATE 115200 -#endif - -#ifdef CONFIG_ESP_CONSOLE_UART_TX_GPIO -#define CONSOLE_DEFAULT_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO -#else -#define CONSOLE_DEFAULT_UART_TX_GPIO 1 -#endif - -#ifdef CONFIG_ESP_CONSOLE_UART_RX_GPIO -#define CONSOLE_DEFAULT_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO -#else -#define CONSOLE_DEFAULT_UART_RX_GPIO 3 -#endif - /** * @brief Default console repl configuration value * */ -#define ESP_CONSOLE_REPL_CONFIG_DEFAULT() \ - { \ - .max_history_len = 32, \ - .history_save_path = NULL, \ - .task_stack_size = 4096, \ - .task_priority = 2, \ - .prompt = NULL, \ - .device = { \ - .uart = { \ - .channel = CONSOLE_DEFAULT_UART_CHANNEL, \ - .baud_rate = CONSOLE_DEFAULT_UART_BAUDRATE, \ - .tx_gpio = CONSOLE_DEFAULT_UART_TX_GPIO, \ - .rx_gpio = CONSOLE_DEFAULT_UART_RX_GPIO, \ - } \ - } \ - } +#define ESP_CONSOLE_REPL_CONFIG_DEFAULT() \ +{ \ + .max_history_len = 32, \ + .history_save_path = NULL, \ + .task_stack_size = 4096, \ + .task_priority = 2, \ + .prompt = NULL, \ +} + +/** + * @brief Parameters for console device: UART + * + */ +typedef struct { + int channel; //!< UART channel number (count from zero) + int baud_rate; //!< Comunication baud rate + int tx_gpio_num; //!< GPIO number for TX path, -1 means using default one + int rx_gpio_num; //!< GPIO number for RX path, -1 means using default one +} esp_console_dev_uart_config_t; + +#ifdef CONFIG_ESP_CONSOLE_UART_CUSTOM +#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \ +{ \ + .channel = CONFIG_ESP_CONSOLE_UART_NUM, \ + .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \ + .tx_gpio_num = CONFIG_ESP_CONSOLE_UART_TX_GPIO, \ + .rx_gpio_num = CONFIG_ESP_CONSOLE_UART_RX_GPIO, \ +} +#else +#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \ +{ \ + .channel = CONFIG_ESP_CONSOLE_UART_NUM, \ + .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \ + .tx_gpio_num = -1, \ + .rx_gpio_num = -1, \ +} +#endif /** * @brief initialize console module @@ -270,10 +259,34 @@ esp_err_t esp_console_register_help_command(void); /****************************************************************************** * Console REPL ******************************************************************************/ + /** - * @brief Initialize console REPL environment + * @brief Type defined for console REPL * - * @param config REPL configuration + */ +typedef struct esp_console_repl_s esp_console_repl_t; + +/** + * @brief Console REPL base structure + * + */ +struct esp_console_repl_s { + /** + * @brief Delete console REPL environment + * @param[in] repl REPL handle returned from esp_console_new_repl_xxx + * @return + * - ESP_OK on success + * - ESP_FAIL on errors + */ + esp_err_t (*del)(esp_console_repl_t *repl); +}; + +/** + * @brief Establish a console REPL environment over UART driver + * + * @param[in] dev_config UART device configuration + * @param[in] repl_config REPL configuration + * @param[out] ret_repl return REPL handle after initialization succeed, return NULL otherwise * * @note This is a all-in-one function to establish the environment needed for REPL, includes: * - Install the UART driver on the console UART (8n1, 115200, REF_TICK clock source) @@ -289,27 +302,17 @@ esp_err_t esp_console_register_help_command(void); * - ESP_OK on success * - ESP_FAIL Parameter error */ -esp_err_t esp_console_repl_init(const esp_console_repl_config_t *config); +esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl); /** - * @brief Start REPL task - * + * @brief Start REPL environment + * @param[in] repl REPL handle returned from esp_console_new_repl_xxx + * @note Once the REPL got started, it won't be stopped until user call repl->del(repl) to destory the REPL environment. * @return * - ESP_OK on success * - ESP_ERR_INVALID_STATE, if repl has started already */ -esp_err_t esp_console_repl_start(void); - -/** - * @brief Register a 'quit' command - * - * Default 'quit' command will destory resources and exit REPL environment. - * - * @return - * - ESP_OK on success - * - others on failed - */ -esp_err_t esp_console_register_quit_command(void); +esp_err_t esp_console_start_repl(esp_console_repl_t *repl); #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/driver/esp32/include/driver/adc.h b/tools/sdk/esp32/include/driver/esp32/include/driver/adc.h index 4f07a6b5..2ee228b3 100644 --- a/tools/sdk/esp32/include/driver/esp32/include/driver/adc.h +++ b/tools/sdk/esp32/include/driver/esp32/include/driver/adc.h @@ -46,22 +46,6 @@ esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel); RTC controller setting ---------------------------------------------------------------*/ -/** - * @brief Output ADC2 reference voltage to GPIO 25 or 26 or 27 - * - * This function utilizes the testing mux exclusive to ADC 2 to route the - * reference voltage one of ADC2's channels. Supported GPIOs are GPIOs - * 25, 26, and 27. This refernce voltage can be manually read from the pin - * and used in the esp_adc_cal component. - * - * @param[in] gpio GPIO number (GPIOs 25, 26 and 27 are supported) - * - * @return - * - ESP_OK: v_ref successfully routed to selected GPIO - * - ESP_ERR_INVALID_ARG: Unsupported GPIO - */ -esp_err_t adc2_vref_to_gpio(gpio_num_t gpio); - /** * @brief Read Hall Sensor * diff --git a/tools/sdk/esp32/include/driver/include/driver/adc_common.h b/tools/sdk/esp32/include/driver/include/driver/adc_common.h index 9f896a55..2c426b71 100644 --- a/tools/sdk/esp32/include/driver/include/driver/adc_common.h +++ b/tools/sdk/esp32/include/driver/include/driver/adc_common.h @@ -312,6 +312,40 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten); */ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out); +/** + * @brief Output ADC1 or ADC2's reference voltage to ``adc2_channe_t``'s IO. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @note ESP32 only supports output of ADC2's internal reference voltage. + * @param[in] adc_unit ADC unit index + * @param[in] gpio GPIO number (Only ADC2's channels IO are supported) + * + * @return + * - ESP_OK: v_ref successfully routed to selected GPIO + * - ESP_ERR_INVALID_ARG: Unsupported GPIO + */ +esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio); + +/** + * @brief Output ADC2 reference voltage to ``adc2_channe_t``'s IO. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @deprecated Use ``adc_vref_to_gpio`` instead. + * + * @param[in] gpio GPIO number (ADC2's channels are supported) + * + * @return + * - ESP_OK: v_ref successfully routed to selected GPIO + * - ESP_ERR_INVALID_ARG: Unsupported GPIO + */ +esp_err_t adc2_vref_to_gpio(gpio_num_t gpio) __attribute__((deprecated)); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/driver/include/driver/can.h b/tools/sdk/esp32/include/driver/include/driver/can.h index 16b88f98..7b42ce1d 100644 --- a/tools/sdk/esp32/include/driver/include/driver/can.h +++ b/tools/sdk/esp32/include/driver/include/driver/can.h @@ -18,330 +18,57 @@ extern "C" { #endif -#include "soc/soc_caps.h" -#ifndef SOC_CAN_SUPPORTED -#error CAN is not supported in this chip target -#endif +#warning driver/can.h is deprecated, please use driver/twai.h instead -#include "freertos/FreeRTOS.h" -#include "esp_types.h" -#include "esp_intr_alloc.h" -#include "esp_err.h" -#include "gpio.h" -#include "soc/can_caps.h" #include "hal/can_types.h" +#include "driver/twai.h" -/* -------------------- Default initializers and flags ---------------------- */ -/** @cond */ //Doxy command to hide preprocessor definitions from docs -/** - * @brief Initializer macro for general configuration structure. - * - * This initializer macros allows the TX GPIO, RX GPIO, and operating mode to be - * configured. The other members of the general configuration structure are - * assigned default values. - */ -#define CAN_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ - .clkout_io = CAN_IO_UNUSED, .bus_off_io = CAN_IO_UNUSED, \ - .tx_queue_len = 5, .rx_queue_len = 5, \ - .alerts_enabled = CAN_ALERT_NONE, .clkout_divider = 0, } +/* ---------------------------- Compatibility ------------------------------- */ -/** - * @brief Alert flags - * - * The following flags represents the various kind of alerts available in - * the CAN driver. These flags can be used when configuring/reconfiguring - * alerts, or when calling can_read_alerts(). - * - * @note The CAN_ALERT_AND_LOG flag is not an actual alert, but will configure - * the CAN driver to log to UART when an enabled alert occurs. - */ -#define CAN_ALERT_TX_IDLE 0x0001 /**< Alert(1): No more messages to transmit */ -#define CAN_ALERT_TX_SUCCESS 0x0002 /**< Alert(2): The previous transmission was successful */ -#define CAN_ALERT_BELOW_ERR_WARN 0x0004 /**< Alert(4): Both error counters have dropped below error warning limit */ -#define CAN_ALERT_ERR_ACTIVE 0x0008 /**< Alert(8): CAN controller has become error active */ -#define CAN_ALERT_RECOVERY_IN_PROGRESS 0x0010 /**< Alert(16): CAN controller is undergoing bus recovery */ -#define CAN_ALERT_BUS_RECOVERED 0x0020 /**< Alert(32): CAN controller has successfully completed bus recovery */ -#define CAN_ALERT_ARB_LOST 0x0040 /**< Alert(64): The previous transmission lost arbitration */ -#define CAN_ALERT_ABOVE_ERR_WARN 0x0080 /**< Alert(128): One of the error counters have exceeded the error warning limit */ -#define CAN_ALERT_BUS_ERROR 0x0100 /**< Alert(256): A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus */ -#define CAN_ALERT_TX_FAILED 0x0200 /**< Alert(512): The previous transmission has failed (for single shot transmission) */ -#define CAN_ALERT_RX_QUEUE_FULL 0x0400 /**< Alert(1024): The RX queue is full causing a frame to be lost */ -#define CAN_ALERT_ERR_PASS 0x0800 /**< Alert(2048): CAN controller has become error passive */ -#define CAN_ALERT_BUS_OFF 0x1000 /**< Alert(4096): Bus-off condition occurred. CAN controller can no longer influence bus */ -#define CAN_ALERT_ALL 0x1FFF /**< Bit mask to enable all alerts during configuration */ -#define CAN_ALERT_NONE 0x0000 /**< Bit mask to disable all alerts during configuration */ -#define CAN_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur */ +#define CAN_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) -/** @endcond */ +#define CAN_ALERT_TX_IDLE TWAI_ALERT_TX_IDLE +#define CAN_ALERT_TX_SUCCESS TWAI_ALERT_TX_SUCCESS +#define CAN_ALERT_BELOW_ERR_WARN TWAI_ALERT_BELOW_ERR_WARN +#define CAN_ALERT_ERR_ACTIVE TWAI_ALERT_ERR_ACTIVE +#define CAN_ALERT_RECOVERY_IN_PROGRESS TWAI_ALERT_RECOVERY_IN_PROGRESS +#define CAN_ALERT_BUS_RECOVERED TWAI_ALERT_BUS_RECOVERED +#define CAN_ALERT_ARB_LOST TWAI_ALERT_ARB_LOST +#define CAN_ALERT_ABOVE_ERR_WARN TWAI_ALERT_ABOVE_ERR_WARN +#define CAN_ALERT_BUS_ERROR TWAI_ALERT_BUS_ERROR +#define CAN_ALERT_TX_FAILED TWAI_ALERT_TX_FAILED +#define CAN_ALERT_RX_QUEUE_FULL TWAI_ALERT_RX_QUEUE_FULL +#define CAN_ALERT_ERR_PASS TWAI_ALERT_ERR_PASS +#define CAN_ALERT_BUS_OFF TWAI_ALERT_BUS_OFF +#define CAN_ALERT_ALL TWAI_ALERT_ALL +#define CAN_ALERT_NONE TWAI_ALERT_NONE +#define CAN_ALERT_AND_LOG TWAI_ALERT_AND_LOG -#define CAN_IO_UNUSED ((gpio_num_t) -1) /**< Marks GPIO as unused in CAN configuration */ +#define CAN_IO_UNUSED TWAI_IO_UNUSED -/* ----------------------- Enum and Struct Definitions ---------------------- */ +#define CAN_STATE_STOPPED TWAI_STATE_STOPPED +#define CAN_STATE_RUNNING TWAI_STATE_RUNNING +#define CAN_STATE_BUS_OFF TWAI_STATE_BUS_OFF +#define CAN_STATE_RECOVERING TWAI_STATE_RECOVERING -/** - * @brief CAN driver states - */ -typedef enum { - CAN_STATE_STOPPED, /**< Stopped state. The CAN controller will not participate in any CAN bus activities */ - CAN_STATE_RUNNING, /**< Running state. The CAN controller can transmit and receive messages */ - CAN_STATE_BUS_OFF, /**< Bus-off state. The CAN controller cannot participate in bus activities until it has recovered */ - CAN_STATE_RECOVERING, /**< Recovering state. The CAN controller is undergoing bus recovery */ -} can_state_t; +typedef twai_state_t can_state_t; +typedef twai_general_config_t can_general_config_t; +typedef twai_status_info_t can_status_info_t; -/** - * @brief Structure for general configuration of the CAN driver - * - * @note Macro initializers are available for this structure - */ -typedef struct { - can_mode_t mode; /**< Mode of CAN controller */ - gpio_num_t tx_io; /**< Transmit GPIO number */ - gpio_num_t rx_io; /**< Receive GPIO number */ - gpio_num_t clkout_io; /**< CLKOUT GPIO number (optional, set to -1 if unused) */ - gpio_num_t bus_off_io; /**< Bus off indicator GPIO number (optional, set to -1 if unused) */ - uint32_t tx_queue_len; /**< Number of messages TX queue can hold (set to 0 to disable TX Queue) */ - uint32_t rx_queue_len; /**< Number of messages RX queue can hold */ - uint32_t alerts_enabled; /**< Bit field of alerts to enable (see documentation) */ - uint32_t clkout_divider; /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */ -} can_general_config_t; -/** - * @brief Structure to store status information of CAN driver - */ -typedef struct { - can_state_t state; /**< Current state of CAN controller (Stopped/Running/Bus-Off/Recovery) */ - uint32_t msgs_to_tx; /**< Number of messages queued for transmission or awaiting transmission completion */ - uint32_t msgs_to_rx; /**< Number of messages in RX queue waiting to be read */ - uint32_t tx_error_counter; /**< Current value of Transmit Error Counter */ - uint32_t rx_error_counter; /**< Current value of Receive Error Counter */ - uint32_t tx_failed_count; /**< Number of messages that failed transmissions */ - uint32_t rx_missed_count; /**< Number of messages that were lost due to a full RX queue */ - uint32_t arb_lost_count; /**< Number of instances arbitration was lost */ - uint32_t bus_error_count; /**< Number of instances a bus error has occurred */ -} can_status_info_t; - -/* ----------------------------- Public API -------------------------------- */ - -/** - * @brief Install CAN driver - * - * This function installs the CAN driver using three configuration structures. - * The required memory is allocated and the CAN driver is placed in the stopped - * state after running this function. - * - * @param[in] g_config General configuration structure - * @param[in] t_config Timing configuration structure - * @param[in] f_config Filter configuration structure - * - * @note Macro initializers are available for the configuration structures (see documentation) - * - * @note To reinstall the CAN driver, call can_driver_uninstall() first - * - * @return - * - ESP_OK: Successfully installed CAN driver - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_NO_MEM: Insufficient memory - * - ESP_ERR_INVALID_STATE: Driver is already installed - */ -esp_err_t can_driver_install(const can_general_config_t *g_config, const can_timing_config_t *t_config, const can_filter_config_t *f_config); - -/** - * @brief Uninstall the CAN driver - * - * This function uninstalls the CAN driver, freeing the memory utilized by the - * driver. This function can only be called when the driver is in the stopped - * state or the bus-off state. - * - * @warning The application must ensure that no tasks are blocked on TX/RX - * queues or alerts when this function is called. - * - * @return - * - ESP_OK: Successfully uninstalled CAN driver - * - ESP_ERR_INVALID_STATE: Driver is not in stopped/bus-off state, or is not installed - */ -esp_err_t can_driver_uninstall(void); - -/** - * @brief Start the CAN driver - * - * This function starts the CAN driver, putting the CAN driver into the running - * state. This allows the CAN driver to participate in CAN bus activities such - * as transmitting/receiving messages. The RX queue is reset in this function, - * clearing any unread messages. This function can only be called when the CAN - * driver is in the stopped state. - * - * @return - * - ESP_OK: CAN driver is now running - * - ESP_ERR_INVALID_STATE: Driver is not in stopped state, or is not installed - */ -esp_err_t can_start(void); - -/** - * @brief Stop the CAN driver - * - * This function stops the CAN driver, preventing any further message from being - * transmitted or received until can_start() is called. Any messages in the TX - * queue are cleared. Any messages in the RX queue should be read by the - * application after this function is called. This function can only be called - * when the CAN driver is in the running state. - * - * @warning A message currently being transmitted/received on the CAN bus will - * be ceased immediately. This may lead to other CAN nodes interpreting - * the unfinished message as an error. - * - * @return - * - ESP_OK: CAN driver is now Stopped - * - ESP_ERR_INVALID_STATE: Driver is not in running state, or is not installed - */ -esp_err_t can_stop(void); - -/** - * @brief Transmit a CAN message - * - * This function queues a CAN message for transmission. Transmission will start - * immediately if no other messages are queued for transmission. If the TX queue - * is full, this function will block until more space becomes available or until - * it timesout. If the TX queue is disabled (TX queue length = 0 in configuration), - * this function will return immediately if another message is undergoing - * transmission. This function can only be called when the CAN driver is in the - * running state and cannot be called under Listen Only Mode. - * - * @param[in] message Message to transmit - * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on the TX queue - * - * @note This function does not guarantee that the transmission is successful. - * The TX_SUCCESS/TX_FAILED alert can be enabled to alert the application - * upon the success/failure of a transmission. - * - * @note The TX_IDLE alert can be used to alert the application when no other - * messages are awaiting transmission. - * - * @return - * - ESP_OK: Transmission successfully queued/initiated - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_TIMEOUT: Timed out waiting for space on TX queue - * - ESP_FAIL: TX queue is disabled and another message is currently transmitting - * - ESP_ERR_INVALID_STATE: CAN driver is not in running state, or is not installed - * - ESP_ERR_NOT_SUPPORTED: Listen Only Mode does not support transmissions - */ -esp_err_t can_transmit(const can_message_t *message, TickType_t ticks_to_wait); - -/** - * @brief Receive a CAN message - * - * This function receives a message from the RX queue. The flags field of the - * message structure will indicate the type of message received. This function - * will block if there are no messages in the RX queue - * - * @param[out] message Received message - * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on RX queue - * - * @warning The flags field of the received message should be checked to determine - * if the received message contains any data bytes. - * - * @return - * - ESP_OK: Message successfully received from RX queue - * - ESP_ERR_TIMEOUT: Timed out waiting for message - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_receive(can_message_t *message, TickType_t ticks_to_wait); - -/** - * @brief Read CAN driver alerts - * - * This function will read the alerts raised by the CAN driver. If no alert has - * been when this function is called, this function will block until an alert - * occurs or until it timeouts. - * - * @param[out] alerts Bit field of raised alerts (see documentation for alert flags) - * @param[in] ticks_to_wait Number of FreeRTOS ticks to block for alert - * - * @note Multiple alerts can be raised simultaneously. The application should - * check for all alerts that have been enabled. - * - * @return - * - ESP_OK: Alerts read - * - ESP_ERR_TIMEOUT: Timed out waiting for alerts - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_read_alerts(uint32_t *alerts, TickType_t ticks_to_wait); - -/** - * @brief Reconfigure which alerts are enabled - * - * This function reconfigures which alerts are enabled. If there are alerts - * which have not been read whilst reconfiguring, this function can read those - * alerts. - * - * @param[in] alerts_enabled Bit field of alerts to enable (see documentation for alert flags) - * @param[out] current_alerts Bit field of currently raised alerts. Set to NULL if unused - * - * @return - * - ESP_OK: Alerts reconfigured - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_reconfigure_alerts(uint32_t alerts_enabled, uint32_t *current_alerts); - -/** - * @brief Start the bus recovery process - * - * This function initiates the bus recovery process when the CAN driver is in - * the bus-off state. Once initiated, the CAN driver will enter the recovering - * state and wait for 128 occurrences of the bus-free signal on the CAN bus - * before returning to the stopped state. This function will reset the TX queue, - * clearing any messages pending transmission. - * - * @note The BUS_RECOVERED alert can be enabled to alert the application when - * the bus recovery process completes. - * - * @return - * - ESP_OK: Bus recovery started - * - ESP_ERR_INVALID_STATE: CAN driver is not in the bus-off state, or is not installed - */ -esp_err_t can_initiate_recovery(void); - -/** - * @brief Get current status information of the CAN driver - * - * @param[out] status_info Status information - * - * @return - * - ESP_OK: Status information retrieved - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_get_status_info(can_status_info_t *status_info); - -/** - * @brief Clear the transmit queue - * - * This function will clear the transmit queue of all messages. - * - * @note The transmit queue is automatically cleared when can_stop() or - * can_initiate_recovery() is called. - * - * @return - * - ESP_OK: Transmit queue cleared - * - ESP_ERR_INVALID_STATE: CAN driver is not installed or TX queue is disabled - */ -esp_err_t can_clear_transmit_queue(void); - -/** - * @brief Clear the receive queue - * - * This function will clear the receive queue of all messages. - * - * @note The receive queue is automatically cleared when can_start() is - * called. - * - * @return - * - ESP_OK: Transmit queue cleared - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_clear_receive_queue(void); +#define can_driver_install(g_config, t_config, f_config) twai_driver_install(g_config, t_config, f_config) +#define can_driver_uninstall() twai_driver_uninstall() +#define can_start() twai_start() +#define can_stop() twai_stop() +#define can_transmit(message, ticks_to_wait) twai_transmit(message, ticks_to_wait) +#define can_receive(message, ticks_to_wait) twai_receive(message, ticks_to_wait) +#define can_read_alerts(alerts, ticks_to_wait) twai_read_alerts(alerts, ticks_to_wait) +#define can_reconfigure_alerts(alerts_enabled, current_alerts) twai_reconfigure_alerts(alerts_enabled, current_alerts) +#define can_initiate_recovery() twai_initiate_recovery() +#define can_get_status_info(status_info) twai_get_status_info(status_info) +#define can_clear_transmit_queue() twai_clear_transmit_queue() +#define can_clear_receive_queue() twai_clear_receive_queue() #ifdef __cplusplus } -#endif +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/driver/include/driver/gpio.h b/tools/sdk/esp32/include/driver/include/driver/gpio.h index 270d738a..bc3c56cd 100644 --- a/tools/sdk/esp32/include/driver/include/driver/gpio.h +++ b/tools/sdk/esp32/include/driver/include/driver/gpio.h @@ -22,6 +22,10 @@ #include "soc/gpio_periph.h" #include "hal/gpio_types.h" +// |================================= WARNING ====================================================== | +// | Including ROM header file in a PUBLIC API file will be REMOVED in the next major release (5.x). | +// | User should include "esp_rom_gpio.h" in their code if they have to use those ROM API. | +// |================================================================================================ | #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/gpio.h" #elif CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32/include/driver/include/driver/i2c.h b/tools/sdk/esp32/include/driver/include/driver/i2c.h index 197bca29..8a1084c2 100644 --- a/tools/sdk/esp32/include/driver/include/driver/i2c.h +++ b/tools/sdk/esp32/include/driver/include/driver/i2c.h @@ -225,7 +225,7 @@ esp_err_t i2c_master_write_byte(i2c_cmd_handle_t cmd_handle, uint8_t data, bool * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error */ -esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, uint8_t *data, size_t data_len, bool ack_en); +esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, const uint8_t *data, size_t data_len, bool ack_en); /** * @brief Queue command for I2C master to read one byte from I2C bus diff --git a/tools/sdk/esp32/include/driver/include/driver/periph_ctrl.h b/tools/sdk/esp32/include/driver/include/driver/periph_ctrl.h index b6147722..b6c6a9d7 100644 --- a/tools/sdk/esp32/include/driver/include/driver/periph_ctrl.h +++ b/tools/sdk/esp32/include/driver/include/driver/periph_ctrl.h @@ -67,6 +67,29 @@ void periph_module_disable(periph_module_t periph); */ void periph_module_reset(periph_module_t periph); +/** + * @brief enable wifi bt common module + * + * @note If wifi_bt_common_module_enable is called a number of times, + * wifi_bt_common_module_disable has to be called the same number of times + * in order to put the peripheral into disabled state. + * + * @return NULL + * + */ +void wifi_bt_common_module_enable(void); + +/** + * @brief disable wifi bt common module + * + * @note If wifi_bt_common_module_enable is called a number of times, + * wifi_bt_common_module_disable has to be called the same number of times + * in order to put the peripheral into disabled state. + * + * @return NULL + * + */ +void wifi_bt_common_module_disable(void); #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/driver/include/driver/spi_common.h b/tools/sdk/esp32/include/driver/include/driver/spi_common.h index 89160b9e..da12bb36 100644 --- a/tools/sdk/esp32/include/driver/include/driver/spi_common.h +++ b/tools/sdk/esp32/include/driver/include/driver/spi_common.h @@ -62,11 +62,12 @@ extern "C" #define SPICOMMON_BUSFLAG_SLAVE 0 ///< Initialize I/O in slave mode #define SPICOMMON_BUSFLAG_MASTER (1<<0) ///< Initialize I/O in master mode #define SPICOMMON_BUSFLAG_IOMUX_PINS (1<<1) ///< Check using iomux pins. Or indicates the pins are configured through the IO mux rather than GPIO matrix. -#define SPICOMMON_BUSFLAG_SCLK (1<<2) ///< Check existing of SCLK pin. Or indicates CLK line initialized. -#define SPICOMMON_BUSFLAG_MISO (1<<3) ///< Check existing of MISO pin. Or indicates MISO line initialized. -#define SPICOMMON_BUSFLAG_MOSI (1<<4) ///< Check existing of MOSI pin. Or indicates CLK line initialized. -#define SPICOMMON_BUSFLAG_DUAL (1<<5) ///< Check MOSI and MISO pins can output. Or indicates bus able to work under DIO mode. -#define SPICOMMON_BUSFLAG_WPHD (1<<6) ///< Check existing of WP and HD pins. Or indicates WP & HD pins initialized. +#define SPICOMMON_BUSFLAG_GPIO_PINS (1<<2) ///< Force the signals to be routed through GPIO matrix. Or indicates the pins are routed through the GPIO matrix. +#define SPICOMMON_BUSFLAG_SCLK (1<<3) ///< Check existing of SCLK pin. Or indicates CLK line initialized. +#define SPICOMMON_BUSFLAG_MISO (1<<4) ///< Check existing of MISO pin. Or indicates MISO line initialized. +#define SPICOMMON_BUSFLAG_MOSI (1<<5) ///< Check existing of MOSI pin. Or indicates MOSI line initialized. +#define SPICOMMON_BUSFLAG_DUAL (1<<6) ///< Check MOSI and MISO pins can output. Or indicates bus able to work under DIO mode. +#define SPICOMMON_BUSFLAG_WPHD (1<<7) ///< Check existing of WP and HD pins. Or indicates WP & HD pins initialized. #define SPICOMMON_BUSFLAG_QUAD (SPICOMMON_BUSFLAG_DUAL|SPICOMMON_BUSFLAG_WPHD) ///< Check existing of MOSI/MISO/WP/HD pins as output. Or indicates bus able to work under QIO mode. #define SPICOMMON_BUSFLAG_NATIVE_PINS SPICOMMON_BUSFLAG_IOMUX_PINS diff --git a/tools/sdk/esp32/include/driver/include/driver/spi_slave_hd.h b/tools/sdk/esp32/include/driver/include/driver/spi_slave_hd.h new file mode 100644 index 00000000..f096f34c --- /dev/null +++ b/tools/sdk/esp32/include/driver/include/driver/spi_slave_hd.h @@ -0,0 +1,168 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_types.h" +#include "soc/spi_caps.h" +#include "freertos/FreeRTOS.h" + +#include "hal/spi_types.h" +#include "driver/spi_common.h" +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !SOC_SPI_SUPPORT_SLAVE_HD_VER2 && !CI_HEADER_CHECK +#error The SPI peripheral does not support this feature +#endif + +/// Descriptor of data to send/receive +typedef struct { + uint8_t* data; ///< Buffer to send, must be DMA capable + size_t len; ///< Len of data to send/receive. For receiving the buffer length should be multiples of 4 bytes, otherwise the extra part will be truncated. + size_t trans_len; ///< Data actually received + void* arg; ///< Extra argument indiciating this data +} spi_slave_hd_data_t; + +/// Information of SPI Slave HD event +typedef struct { + spi_event_t event; ///< Event type + spi_slave_hd_data_t* trans; ///< Corresponding transaction for SPI_EV_SEND and SPI_EV_RECV events +} spi_slave_hd_event_t; + +/// Callback for SPI Slave HD +typedef bool (*slave_cb_t)(void* arg, spi_slave_hd_event_t* event, BaseType_t* awoken); + +/// Channel of SPI Slave HD to do data transaction +typedef enum { + SPI_SLAVE_CHAN_TX = 0, ///< The output channel (RDDMA) + SPI_SLAVE_CHAN_RX = 1, ///< The input channel (WRDMA) +} spi_slave_chan_t; + +/// Callback configuration structure for SPI Slave HD +typedef struct { + slave_cb_t cb_recv; ///< Callback when receive data + slave_cb_t cb_sent; ///< Callback when data sent + slave_cb_t cb_buffer_tx; ///< Callback when master reads from shared buffer + slave_cb_t cb_buffer_rx; ///< Callback when master writes to shared buffer + slave_cb_t cb_cmd9; ///< Callback when CMD9 received + slave_cb_t cb_cmdA; ///< Callback when CMDA received + void* arg; ///< Argument indicating this SPI Slave HD peripheral instance +} spi_slave_hd_callback_config_t; + +/// Configuration structure for the SPI Slave HD driver +typedef struct { + int spics_io_num; ///< CS GPIO pin for this device + uint32_t flags; ///< Bitwise OR of SPI_SLAVE_HD_* flags +#define SPI_SLAVE_HD_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first +#define SPI_SLAVE_HD_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first +#define SPI_SLAVE_HD_BIT_LSBFIRST (SPI_SLAVE_HD_TXBIT_LSBFIRST|SPI_SLAVE_HD_RXBIT_LSBFIRST) ///< Transmit and receive LSB first + + uint8_t mode; ///< SPI mode (0-3) + int command_bits; ///< command field bits, multiples of 8 and at least 8. + int address_bits; ///< address field bits, multiples of 8 and at least 8. + int dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. + + int queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_hd_queue_trans but not yet finished using spi_slave_hd_get_trans_result) at the same time + + int dma_chan; ///< DMA channel used + spi_slave_hd_callback_config_t cb_config; ///< Callback configuration +} spi_slave_hd_slot_config_t; + +/** + * @brief Initialize the SPI Slave HD driver. + * + * @param host_id The host to use + * @param bus_config Bus configuration for the bus used + * @param config Configuration for the SPI Slave HD driver + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: invalid argument given + * - ESP_ERR_INVALID_STATE: function called in invalid state, may be some resources are already in use + * - ESP_ERR_NO_MEM: memory allocation failed + * - or other return value from `esp_intr_alloc` + */ +esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, + const spi_slave_hd_slot_config_t *config); + +/** + * @brief Deinitialize the SPI Slave HD driver + * + * @param host_id The host to deinitialize the driver + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: if the host_id is not correct + */ +esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id); + +/** + * @brief Queue data transaction + * + * @param host_id Host to queue the transaction + * @param chan Channel to queue the data, SPI_SLAVE_CHAN_TX or SPI_SLAVE_CHAN_RX + * @param trans Descriptor of data to queue + * @param timeout Timeout before the data is queued + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: The input argument is invalid. Can be the following reason: + * - The buffer given is not DMA capable + * - The length of data is invalid (not larger than 0, or exceed the max transfer length) + * - The function is invalid + * - ESP_ERR_TIMEOUT: Cannot queue the data before timeout. This is quite possible if the master + * doesn't read/write the slave on time. + */ +esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t* trans, TickType_t timeout); + +/** + * @brief Get the result of a data transaction + * + * @param host_id Host to queue the transaction + * @param chan Channel to get the result, SPI_SLAVE_CHAN_TX or SPI_SLAVE_CHAN_RX + * @param[out] out_trans Output descriptor of the returned transaction + * @param timeout Timeout before the result is got + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: Function is not valid + * - ESP_ERR_TIMEOUT: There's no transaction done before timeout + */ +esp_err_t spi_slave_hd_get_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t** out_trans, TickType_t timeout); + +/** + * @brief Read the shared registers + * + * @param host_id Host to read the shared registers + * @param addr Address of register to read, 0 to ``SOC_SPI_MAXIMUM_BUFFER_SIZE-1`` + * @param[out] out_data Output buffer to store the read data + * @param len Length to read, not larger than ``SOC_SPI_MAXIMUM_BUFFER_SIZE-addr`` + */ +void spi_slave_hd_read_buffer(spi_host_device_t host_id, int addr, uint8_t *out_data, size_t len); + +/** + * @brief Write the shared registers + * + * @param host_id Host to write the shared registers + * @param addr Address of register to write, 0 to ``SOC_SPI_MAXIMUM_BUFFER_SIZE-1`` + * @param data Buffer holding the data to write + * @param len Length to write, ``SOC_SPI_MAXIMUM_BUFFER_SIZE-addr`` + */ +void spi_slave_hd_write_buffer(spi_host_device_t host_id, int addr, uint8_t *data, size_t len); + + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/driver/include/driver/timer.h b/tools/sdk/esp32/include/driver/include/driver/timer.h index a4888fb0..1a4c074a 100644 --- a/tools/sdk/esp32/include/driver/include/driver/timer.h +++ b/tools/sdk/esp32/include/driver/include/driver/timer.h @@ -27,7 +27,20 @@ extern "C" { #define TIMER_BASE_CLK (APB_CLK_FREQ) /*!< Frequency of the clock on the input of the timer groups */ -typedef void (*timer_isr_t)(void *); +/** + * @brief Interrupt handle callback function. User need to retrun a bool value + * in callback. + * + * @return + * - True Do task yield at the end of ISR + * - False Not do task yield at the end of ISR + * + * @note If you called FreeRTOS functions in callback, you need to return true or false based on + * the retrun value of argument `pxHigherPriorityTaskWoken`. + * For example, `xQueueSendFromISR` is called in callback, if the return value `pxHigherPriorityTaskWoken` + * of any FreeRTOS calls is pdTRUE, return true; otherwise return false. + */ +typedef bool (*timer_isr_t)(void *); /** * @brief Interrupt handle, used in order to free the isr after use. @@ -191,6 +204,9 @@ esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_ * If you want to realize some specific applications or write the whole ISR, you can * call timer_isr_register(...) to register ISR. * + * The callback should return a bool value to determine whether need to do YIELD at + * the end of the ISR. + * * If the intr_alloc_flags value ESP_INTR_FLAG_IRAM is set, * the handler function must be declared with IRAM_ATTR attribute * and can only call functions in IRAM or ROM. It cannot call other timer APIs. diff --git a/tools/sdk/esp32/include/driver/include/driver/twai.h b/tools/sdk/esp32/include/driver/include/driver/twai.h new file mode 100644 index 00000000..5313d953 --- /dev/null +++ b/tools/sdk/esp32/include/driver/include/driver/twai.h @@ -0,0 +1,347 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#ifndef SOC_TWAI_SUPPORTED +#error TWAI is not supported in this chip target +#endif + +#include "freertos/FreeRTOS.h" +#include "esp_types.h" +#include "esp_intr_alloc.h" +#include "esp_err.h" +#include "gpio.h" +#include "soc/twai_caps.h" +#include "hal/twai_types.h" + +/* -------------------- Default initializers and flags ---------------------- */ +/** @cond */ //Doxy command to hide preprocessor definitions from docs +/** + * @brief Initializer macro for general configuration structure. + * + * This initializer macros allows the TX GPIO, RX GPIO, and operating mode to be + * configured. The other members of the general configuration structure are + * assigned default values. + */ +#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ + .clkout_io = TWAI_IO_UNUSED, .bus_off_io = TWAI_IO_UNUSED, \ + .tx_queue_len = 5, .rx_queue_len = 5, \ + .alerts_enabled = TWAI_ALERT_NONE, .clkout_divider = 0, } + +/** + * @brief Alert flags + * + * The following flags represents the various kind of alerts available in + * the TWAI driver. These flags can be used when configuring/reconfiguring + * alerts, or when calling twai_read_alerts(). + * + * @note The TWAI_ALERT_AND_LOG flag is not an actual alert, but will configure + * the TWAI driver to log to UART when an enabled alert occurs. + */ +#define TWAI_ALERT_TX_IDLE 0x0001 /**< Alert(1): No more messages to transmit */ +#define TWAI_ALERT_TX_SUCCESS 0x0002 /**< Alert(2): The previous transmission was successful */ +#define TWAI_ALERT_BELOW_ERR_WARN 0x0004 /**< Alert(4): Both error counters have dropped below error warning limit */ +#define TWAI_ALERT_ERR_ACTIVE 0x0008 /**< Alert(8): TWAI controller has become error active */ +#define TWAI_ALERT_RECOVERY_IN_PROGRESS 0x0010 /**< Alert(16): TWAI controller is undergoing bus recovery */ +#define TWAI_ALERT_BUS_RECOVERED 0x0020 /**< Alert(32): TWAI controller has successfully completed bus recovery */ +#define TWAI_ALERT_ARB_LOST 0x0040 /**< Alert(64): The previous transmission lost arbitration */ +#define TWAI_ALERT_ABOVE_ERR_WARN 0x0080 /**< Alert(128): One of the error counters have exceeded the error warning limit */ +#define TWAI_ALERT_BUS_ERROR 0x0100 /**< Alert(256): A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus */ +#define TWAI_ALERT_TX_FAILED 0x0200 /**< Alert(512): The previous transmission has failed (for single shot transmission) */ +#define TWAI_ALERT_RX_QUEUE_FULL 0x0400 /**< Alert(1024): The RX queue is full causing a frame to be lost */ +#define TWAI_ALERT_ERR_PASS 0x0800 /**< Alert(2048): TWAI controller has become error passive */ +#define TWAI_ALERT_BUS_OFF 0x1000 /**< Alert(4096): Bus-off condition occurred. TWAI controller can no longer influence bus */ +#define TWAI_ALERT_ALL 0x1FFF /**< Bit mask to enable all alerts during configuration */ +#define TWAI_ALERT_NONE 0x0000 /**< Bit mask to disable all alerts during configuration */ +#define TWAI_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur */ + +/** @endcond */ + +#define TWAI_IO_UNUSED ((gpio_num_t) -1) /**< Marks GPIO as unused in TWAI configuration */ + +/* ----------------------- Enum and Struct Definitions ---------------------- */ + +/** + * @brief TWAI driver states + */ +typedef enum { + TWAI_STATE_STOPPED, /**< Stopped state. The TWAI controller will not participate in any TWAI bus activities */ + TWAI_STATE_RUNNING, /**< Running state. The TWAI controller can transmit and receive messages */ + TWAI_STATE_BUS_OFF, /**< Bus-off state. The TWAI controller cannot participate in bus activities until it has recovered */ + TWAI_STATE_RECOVERING, /**< Recovering state. The TWAI controller is undergoing bus recovery */ +} twai_state_t; + +/** + * @brief Structure for general configuration of the TWAI driver + * + * @note Macro initializers are available for this structure + */ +typedef struct { + twai_mode_t mode; /**< Mode of TWAI controller */ + gpio_num_t tx_io; /**< Transmit GPIO number */ + gpio_num_t rx_io; /**< Receive GPIO number */ + gpio_num_t clkout_io; /**< CLKOUT GPIO number (optional, set to -1 if unused) */ + gpio_num_t bus_off_io; /**< Bus off indicator GPIO number (optional, set to -1 if unused) */ + uint32_t tx_queue_len; /**< Number of messages TX queue can hold (set to 0 to disable TX Queue) */ + uint32_t rx_queue_len; /**< Number of messages RX queue can hold */ + uint32_t alerts_enabled; /**< Bit field of alerts to enable (see documentation) */ + uint32_t clkout_divider; /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */ +} twai_general_config_t; + +/** + * @brief Structure to store status information of TWAI driver + */ +typedef struct { + twai_state_t state; /**< Current state of TWAI controller (Stopped/Running/Bus-Off/Recovery) */ + uint32_t msgs_to_tx; /**< Number of messages queued for transmission or awaiting transmission completion */ + uint32_t msgs_to_rx; /**< Number of messages in RX queue waiting to be read */ + uint32_t tx_error_counter; /**< Current value of Transmit Error Counter */ + uint32_t rx_error_counter; /**< Current value of Receive Error Counter */ + uint32_t tx_failed_count; /**< Number of messages that failed transmissions */ + uint32_t rx_missed_count; /**< Number of messages that were lost due to a full RX queue */ + uint32_t arb_lost_count; /**< Number of instances arbitration was lost */ + uint32_t bus_error_count; /**< Number of instances a bus error has occurred */ +} twai_status_info_t; + +/* ------------------------------ Public API -------------------------------- */ + +/** + * @brief Install TWAI driver + * + * This function installs the TWAI driver using three configuration structures. + * The required memory is allocated and the TWAI driver is placed in the stopped + * state after running this function. + * + * @param[in] g_config General configuration structure + * @param[in] t_config Timing configuration structure + * @param[in] f_config Filter configuration structure + * + * @note Macro initializers are available for the configuration structures (see documentation) + * + * @note To reinstall the TWAI driver, call twai_driver_uninstall() first + * + * @return + * - ESP_OK: Successfully installed TWAI driver + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_NO_MEM: Insufficient memory + * - ESP_ERR_INVALID_STATE: Driver is already installed + */ +esp_err_t twai_driver_install(const twai_general_config_t *g_config, const twai_timing_config_t *t_config, const twai_filter_config_t *f_config); + +/** + * @brief Uninstall the TWAI driver + * + * This function uninstalls the TWAI driver, freeing the memory utilized by the + * driver. This function can only be called when the driver is in the stopped + * state or the bus-off state. + * + * @warning The application must ensure that no tasks are blocked on TX/RX + * queues or alerts when this function is called. + * + * @return + * - ESP_OK: Successfully uninstalled TWAI driver + * - ESP_ERR_INVALID_STATE: Driver is not in stopped/bus-off state, or is not installed + */ +esp_err_t twai_driver_uninstall(void); + +/** + * @brief Start the TWAI driver + * + * This function starts the TWAI driver, putting the TWAI driver into the running + * state. This allows the TWAI driver to participate in TWAI bus activities such + * as transmitting/receiving messages. The RX queue is reset in this function, + * clearing any unread messages. This function can only be called when the TWAI + * driver is in the stopped state. + * + * @return + * - ESP_OK: TWAI driver is now running + * - ESP_ERR_INVALID_STATE: Driver is not in stopped state, or is not installed + */ +esp_err_t twai_start(void); + +/** + * @brief Stop the TWAI driver + * + * This function stops the TWAI driver, preventing any further message from being + * transmitted or received until twai_start() is called. Any messages in the TX + * queue are cleared. Any messages in the RX queue should be read by the + * application after this function is called. This function can only be called + * when the TWAI driver is in the running state. + * + * @warning A message currently being transmitted/received on the TWAI bus will + * be ceased immediately. This may lead to other TWAI nodes interpreting + * the unfinished message as an error. + * + * @return + * - ESP_OK: TWAI driver is now Stopped + * - ESP_ERR_INVALID_STATE: Driver is not in running state, or is not installed + */ +esp_err_t twai_stop(void); + +/** + * @brief Transmit a TWAI message + * + * This function queues a TWAI message for transmission. Transmission will start + * immediately if no other messages are queued for transmission. If the TX queue + * is full, this function will block until more space becomes available or until + * it times out. If the TX queue is disabled (TX queue length = 0 in configuration), + * this function will return immediately if another message is undergoing + * transmission. This function can only be called when the TWAI driver is in the + * running state and cannot be called under Listen Only Mode. + * + * @param[in] message Message to transmit + * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on the TX queue + * + * @note This function does not guarantee that the transmission is successful. + * The TX_SUCCESS/TX_FAILED alert can be enabled to alert the application + * upon the success/failure of a transmission. + * + * @note The TX_IDLE alert can be used to alert the application when no other + * messages are awaiting transmission. + * + * @return + * - ESP_OK: Transmission successfully queued/initiated + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_TIMEOUT: Timed out waiting for space on TX queue + * - ESP_FAIL: TX queue is disabled and another message is currently transmitting + * - ESP_ERR_INVALID_STATE: TWAI driver is not in running state, or is not installed + * - ESP_ERR_NOT_SUPPORTED: Listen Only Mode does not support transmissions + */ +esp_err_t twai_transmit(const twai_message_t *message, TickType_t ticks_to_wait); + +/** + * @brief Receive a TWAI message + * + * This function receives a message from the RX queue. The flags field of the + * message structure will indicate the type of message received. This function + * will block if there are no messages in the RX queue + * + * @param[out] message Received message + * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on RX queue + * + * @warning The flags field of the received message should be checked to determine + * if the received message contains any data bytes. + * + * @return + * - ESP_OK: Message successfully received from RX queue + * - ESP_ERR_TIMEOUT: Timed out waiting for message + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_receive(twai_message_t *message, TickType_t ticks_to_wait); + +/** + * @brief Read TWAI driver alerts + * + * This function will read the alerts raised by the TWAI driver. If no alert has + * been issued when this function is called, this function will block until an alert + * occurs or until it timeouts. + * + * @param[out] alerts Bit field of raised alerts (see documentation for alert flags) + * @param[in] ticks_to_wait Number of FreeRTOS ticks to block for alert + * + * @note Multiple alerts can be raised simultaneously. The application should + * check for all alerts that have been enabled. + * + * @return + * - ESP_OK: Alerts read + * - ESP_ERR_TIMEOUT: Timed out waiting for alerts + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_read_alerts(uint32_t *alerts, TickType_t ticks_to_wait); + +/** + * @brief Reconfigure which alerts are enabled + * + * This function reconfigures which alerts are enabled. If there are alerts + * which have not been read whilst reconfiguring, this function can read those + * alerts. + * + * @param[in] alerts_enabled Bit field of alerts to enable (see documentation for alert flags) + * @param[out] current_alerts Bit field of currently raised alerts. Set to NULL if unused + * + * @return + * - ESP_OK: Alerts reconfigured + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_reconfigure_alerts(uint32_t alerts_enabled, uint32_t *current_alerts); + +/** + * @brief Start the bus recovery process + * + * This function initiates the bus recovery process when the TWAI driver is in + * the bus-off state. Once initiated, the TWAI driver will enter the recovering + * state and wait for 128 occurrences of the bus-free signal on the TWAI bus + * before returning to the stopped state. This function will reset the TX queue, + * clearing any messages pending transmission. + * + * @note The BUS_RECOVERED alert can be enabled to alert the application when + * the bus recovery process completes. + * + * @return + * - ESP_OK: Bus recovery started + * - ESP_ERR_INVALID_STATE: TWAI driver is not in the bus-off state, or is not installed + */ +esp_err_t twai_initiate_recovery(void); + +/** + * @brief Get current status information of the TWAI driver + * + * @param[out] status_info Status information + * + * @return + * - ESP_OK: Status information retrieved + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_get_status_info(twai_status_info_t *status_info); + +/** + * @brief Clear the transmit queue + * + * This function will clear the transmit queue of all messages. + * + * @note The transmit queue is automatically cleared when twai_stop() or + * twai_initiate_recovery() is called. + * + * @return + * - ESP_OK: Transmit queue cleared + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed or TX queue is disabled + */ +esp_err_t twai_clear_transmit_queue(void); + +/** + * @brief Clear the receive queue + * + * This function will clear the receive queue of all messages. + * + * @note The receive queue is automatically cleared when twai_start() is + * called. + * + * @return + * - ESP_OK: Transmit queue cleared + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_clear_receive_queue(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/driver/include/driver/uart.h b/tools/sdk/esp32/include/driver/include/driver/uart.h index ef750873..7be0fb02 100644 --- a/tools/sdk/esp32/include/driver/include/driver/uart.h +++ b/tools/sdk/esp32/include/driver/include/driver/uart.h @@ -514,7 +514,7 @@ int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len); * - (-1) Parameter error * - OTHERS (>=0) The number of bytes pushed to the TX FIFO */ -int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size); +int uart_write_bytes(uart_port_t uart_num, const void* src, size_t size); /** * @brief Send data to the UART port from a given buffer and length, @@ -536,7 +536,7 @@ int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size); * - (-1) Parameter error * - OTHERS (>=0) The number of bytes pushed to the TX FIFO */ -int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len); +int uart_write_bytes_with_break(uart_port_t uart_num, const void* src, size_t size, int brk_len); /** * @brief UART read bytes from UART buffer @@ -550,7 +550,7 @@ int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t si * - (-1) Error * - OTHERS (>=0) The number of bytes read from UART FIFO */ -int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait); +int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t ticks_to_wait); /** * @brief Alias of uart_flush_input. @@ -858,7 +858,6 @@ esp_err_t uart_set_loop_back(uart_port_t uart_num, bool loop_back_en); * @param always_rx_timeout_en Set to false enable the default behavior of timeout interrupt, * set it to true to always trigger timeout interrupt. * - * * @return None */ void uart_set_always_rx_timeout(uart_port_t uart_num, bool always_rx_timeout_en); diff --git a/tools/sdk/esp32/include/esp32/include/esp32/rtc.h b/tools/sdk/esp32/include/esp32/include/esp32/rtc.h new file mode 100644 index 00000000..9b3e343d --- /dev/null +++ b/tools/sdk/esp32/include/esp32/include/esp32/rtc.h @@ -0,0 +1,39 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp32/rtc.h + * + * This file contains declarations of rtc related functions. + */ + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +uint64_t esp_rtc_get_time_us(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_adc_cal/include/esp_adc_cal.h b/tools/sdk/esp32/include/esp_adc_cal/include/esp_adc_cal.h index b1798847..7d8f1278 100644 --- a/tools/sdk/esp32/include/esp_adc_cal/include/esp_adc_cal.h +++ b/tools/sdk/esp32/include/esp_adc_cal/include/esp_adc_cal.h @@ -30,6 +30,7 @@ typedef enum { ESP_ADC_CAL_VAL_EFUSE_VREF = 0, /**< Characterization based on reference voltage stored in eFuse*/ ESP_ADC_CAL_VAL_EFUSE_TP = 1, /**< Characterization based on Two Point values stored in eFuse*/ ESP_ADC_CAL_VAL_DEFAULT_VREF = 2, /**< Characterization based on default reference voltage*/ + ESP_ADC_CAL_VAL_MAX } esp_adc_cal_value_t; /** @@ -71,12 +72,15 @@ esp_err_t esp_adc_cal_check_efuse(esp_adc_cal_value_t value_type); * Characterization can be based on Two Point values, eFuse Vref, or default Vref * and the calibration values will be prioritized in that order. * - * @note Two Point values and eFuse Vref can be enabled/disabled using menuconfig. + * @note + * For ESP32, Two Point values and eFuse Vref calibration can be enabled/disabled using menuconfig. + * For ESP32s2, only Two Point values calibration and only ADC_WIDTH_BIT_13 is supported. The parameter default_vref is unused. + * * * @param[in] adc_num ADC to characterize (ADC_UNIT_1 or ADC_UNIT_2) * @param[in] atten Attenuation to characterize * @param[in] bit_width Bit width configuration of ADC - * @param[in] default_vref Default ADC reference voltage in mV (used if eFuse values is not available) + * @param[in] default_vref Default ADC reference voltage in mV (Only in ESP32, used if eFuse values is not available) * @param[out] chars Pointer to empty structure used to store ADC characteristics * * @return diff --git a/tools/sdk/esp32/include/esp_common/include/esp_crc.h b/tools/sdk/esp32/include/esp_common/include/esp_crc.h index cc14c6ac..6294a7b6 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_crc.h +++ b/tools/sdk/esp32/include/esp_common/include/esp_crc.h @@ -18,21 +18,9 @@ extern "C" { #endif #include -#include "sdkconfig.h" -#if defined(CONFIG_IDF_TARGET_ESP32) -#include "esp32/rom/crc.h" -#endif - -#if defined(CONFIG_IDF_TARGET_ESP32S2) -#include "esp32s2/rom/crc.h" -#endif - -/******************* Polynomials Used in the CRC APIs **************************** -* CRC-8 x8+x2+x1+1 0x07 -* CRC16-CCITT x16+x12+x5+1 0x1021 -* CRC32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1 0x04c11db7 -********************************************************************************/ +// This header is only a wrapper on ROM CRC API +#include "esp_rom_crc.h" /** * @brief CRC32 value in little endian. @@ -44,10 +32,9 @@ extern "C" { */ static inline uint32_t esp_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len) { - return crc32_le(crc, buf, len); + return esp_rom_crc32_le(crc, buf, len); } -#if defined(CONFIG_IDF_TARGET_ESP32) /** * @brief CRC32 value in big endian. * @@ -58,9 +45,8 @@ static inline uint32_t esp_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t l */ static inline uint32_t esp_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len) { - return crc32_be(crc, buf, len); + return esp_rom_crc32_be(crc, buf, len); } -#endif /** * @brief CRC16 value in little endian. @@ -72,10 +58,9 @@ static inline uint32_t esp_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t l */ static inline uint16_t esp_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len) { - return crc16_le(crc, buf, len); + return esp_rom_crc16_le(crc, buf, len); } -#if defined(CONFIG_IDF_TARGET_ESP32) /** * @brief CRC16 value in big endian. * @@ -86,9 +71,8 @@ static inline uint16_t esp_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t l */ static inline uint16_t esp_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len) { - return crc16_be(crc, buf, len); + return esp_rom_crc16_be(crc, buf, len); } -#endif /** * @brief CRC8 value in little endian. @@ -100,10 +84,9 @@ static inline uint16_t esp_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t l */ static inline uint8_t esp_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len) { - return crc8_le(crc, buf, len); + return esp_rom_crc8_le(crc, buf, len); } -#if defined(CONFIG_IDF_TARGET_ESP32) /** * @brief CRC8 value in big endian. * @@ -114,9 +97,8 @@ static inline uint8_t esp_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len) */ static inline uint8_t esp_crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len) { - return crc8_be(crc, buf, len); + return esp_rom_crc8_be(crc, buf, len); } -#endif #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/esp_common/include/esp_expression_with_stack.h b/tools/sdk/esp32/include/esp_common/include/esp_expression_with_stack.h index 3c94f9d3..096b4575 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_expression_with_stack.h +++ b/tools/sdk/esp32/include/esp_common/include/esp_expression_with_stack.h @@ -13,6 +13,7 @@ // limitations under the License. #pragma once +#include #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/task.h" @@ -23,56 +24,25 @@ extern "C" { #endif +typedef void (*shared_stack_function)(void); + +#define ESP_EXECUTE_EXPRESSION_WITH_STACK(lock, stack, stack_size, expression) \ + esp_execute_shared_stack_function(lock, stack, stack_size, expression) + /** - * @brief Executes a 1-line expression with a application alocated stack + * @brief Calls user defined shared stack space function * @param lock Mutex object to protect in case of shared stack * @param stack Pointer to user alocated stack * @param stack_size Size of current stack in bytes - * @param expression Expression or function to be executed using the stack + * @param function pointer to the shared stack function to be executed * @note if either lock, stack or stack size is invalid, the expression will * be called using the current stack. */ -#define ESP_EXECUTE_EXPRESSION_WITH_STACK(lock, stack, stack_size, expression) \ -({ \ - assert(lock && stack && (stack_size >= CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE)); \ - uint32_t backup; \ - xSemaphoreTake(lock, portMAX_DELAY); \ - StackType_t *top_of_stack = esp_switch_stack_setup(stack, stack_size); \ - esp_switch_stack_enter(top_of_stack, &backup); \ - { \ - expression; \ - } \ - esp_switch_stack_exit(&backup); \ - StaticTask_t *current = (StaticTask_t *)xTaskGetCurrentTaskHandle(); \ - /* pxDummy6 is the stack base of current thread defined in TCB_t */ \ - /* place the watchpoint on current task stack after function execution*/ \ - vPortSetStackWatchpoint(current->pxDummy6); \ - xSemaphoreGive(lock); \ -}) +void esp_execute_shared_stack_function(SemaphoreHandle_t lock, + void *stack, + size_t stack_size, + shared_stack_function function); -/** - * @brief Fill stack frame with CPU-specifics value before use - * @param stack Caller allocated stack pointer - * @param stack_size Size of stack in bytes - * @return New pointer to the top of stack - * @note Application must not call this function directly - */ -StackType_t * esp_switch_stack_setup(StackType_t *stack, size_t stack_size); - -/** - * @brief Changes CPU sp-register to use another stack space and save the previous one - * @param stack Caller allocated stack pointer - * @param backup_stack Pointer to a place to save the current stack - * @note Application must not call this function directly - */ -extern void esp_switch_stack_enter(StackType_t *stack, uint32_t *backup_stack); - -/** - * @brief Restores the previous CPU sp-register - * @param backup_stack Pointer to the place where stack was saved - * @note Application must not call this function directly - */ -extern void esp_switch_stack_exit(uint32_t *backup_stack); #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/esp_common/include/esp_fault.h b/tools/sdk/esp32/include/esp_common/include/esp_fault.h index 0eb7ebb6..4ccb259c 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_fault.h +++ b/tools/sdk/esp32/include/esp_common/include/esp_fault.h @@ -13,6 +13,7 @@ // limitations under the License. #include "sdkconfig.h" #include "soc/rtc_cntl_reg.h" +#include "esp_rom_sys.h" #pragma once @@ -81,9 +82,9 @@ extern "C" { #warning "Enabling ESP_FAULT_ASSERT_DEBUG makes ESP_FAULT_ASSERT() less effective" -#define _ESP_FAULT_RESET() do { \ - ets_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \ - asm volatile("ill;"); \ +#define _ESP_FAULT_RESET() do { \ + esp_rom_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \ + asm volatile("ill;"); \ } while(0) #endif // ESP_FAULT_ASSERT_DEBUG diff --git a/tools/sdk/esp32/include/esp_common/include/esp_idf_version.h b/tools/sdk/esp32/include/esp_common/include/esp_idf_version.h index cb9a8b45..bf910010 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_idf_version.h +++ b/tools/sdk/esp32/include/esp_common/include/esp_idf_version.h @@ -21,7 +21,7 @@ extern "C" { /** Major version number (X.x.x) */ #define ESP_IDF_VERSION_MAJOR 4 /** Minor version number (x.X.x) */ -#define ESP_IDF_VERSION_MINOR 2 +#define ESP_IDF_VERSION_MINOR 3 /** Patch version number (x.x.X) */ #define ESP_IDF_VERSION_PATCH 0 diff --git a/tools/sdk/esp32/include/esp_common/include/esp_private/system_internal.h b/tools/sdk/esp32/include/esp_common/include/esp_private/system_internal.h index 9b383cd6..4f5c90e8 100644 --- a/tools/sdk/esp32/include/esp_common/include/esp_private/system_internal.h +++ b/tools/sdk/esp32/include/esp_common/include/esp_private/system_internal.h @@ -61,6 +61,21 @@ void esp_reset_reason_set_hint(esp_reset_reason_t hint); */ esp_reset_reason_t esp_reset_reason_get_hint(void); + +/** + * @brief Get the time in microseconds since startup + * + * @returns time since startup in microseconds + */ +int64_t esp_system_get_time(void); + +/** + * @brief Get the resolution of the time returned by `esp_system_get_time`. + * + * @returns the resolution in microseconds + */ +uint32_t esp_system_get_time_resolution(void); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_eth/include/esp_eth_phy.h b/tools/sdk/esp32/include/esp_eth/include/esp_eth_phy.h index 4aedff11..b3aa39b4 100644 --- a/tools/sdk/esp32/include/esp_eth/include/esp_eth_phy.h +++ b/tools/sdk/esp32/include/esp_eth/include/esp_eth_phy.h @@ -240,6 +240,17 @@ esp_eth_phy_t *esp_eth_phy_new_lan8720(const eth_phy_config_t *config); */ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config); +/** +* @brief Create a PHY instance of KSZ8041 +* +* @param[in] config: configuration of PHY +* +* @return +* - instance: create PHY instance successfully +* - NULL: create PHY instance failed because some error occurred +*/ +esp_eth_phy_t *esp_eth_phy_new_ksz8041(const eth_phy_config_t *config); + #if CONFIG_ETH_SPI_ETHERNET_DM9051 /** * @brief Create a PHY instance of DM9051 @@ -252,6 +263,7 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config); */ esp_eth_phy_t *esp_eth_phy_new_dm9051(const eth_phy_config_t *config); #endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_event/include/esp_event_legacy.h b/tools/sdk/esp32/include/esp_event/include/esp_event_legacy.h index 00d402c4..ba74ec77 100644 --- a/tools/sdk/esp32/include/esp_event/include/esp_event_legacy.h +++ b/tools/sdk/esp32/include/esp_event/include/esp_event_legacy.h @@ -80,6 +80,9 @@ typedef wifi_event_sta_authmode_change_t system_event_sta_authmode_change_t; /** Argument structure of SYSTEM_EVENT_STA_WPS_ER_PIN event */ typedef wifi_event_sta_wps_er_pin_t system_event_sta_wps_er_pin_t; +/** Argument structure of SYSTEM_EVENT_STA_WPS_ER_PIN event */ +typedef wifi_event_sta_wps_er_success_t system_event_sta_wps_er_success_t; + /** Argument structure of event */ typedef wifi_event_ap_staconnected_t system_event_ap_staconnected_t; @@ -107,6 +110,7 @@ typedef union { system_event_sta_got_ip_t got_ip; /*!< ESP32 station got IP, first time got IP or when IP is changed */ system_event_sta_wps_er_pin_t sta_er_pin; /*!< ESP32 station WPS enrollee mode PIN code received */ system_event_sta_wps_fail_reason_t sta_er_fail_reason; /*!< ESP32 station WPS enrollee mode failed reason code received */ + system_event_sta_wps_er_success_t sta_er_success; /*!< ESP32 station WPS enrollee success */ system_event_ap_staconnected_t sta_connected; /*!< a station connected to ESP32 soft-AP */ system_event_ap_stadisconnected_t sta_disconnected; /*!< a station disconnected to ESP32 soft-AP */ system_event_ap_probe_req_rx_t ap_probereqrecved; /*!< ESP32 soft-AP receive probe request packet */ diff --git a/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h index 15c64dcc..3ad04b49 100644 --- a/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h @@ -83,6 +83,13 @@ typedef enum { HTTP_METHOD_SUBSCRIBE, /*!< HTTP SUBSCRIBE Method */ HTTP_METHOD_UNSUBSCRIBE,/*!< HTTP UNSUBSCRIBE Method */ HTTP_METHOD_OPTIONS, /*!< HTTP OPTIONS Method */ + HTTP_METHOD_COPY, /*!< HTTP COPY Method */ + HTTP_METHOD_MOVE, /*!< HTTP MOVE Method */ + HTTP_METHOD_LOCK, /*!< HTTP LOCK Method */ + HTTP_METHOD_UNLOCK, /*!< HTTP UNLOCK Method */ + HTTP_METHOD_PROPFIND, /*!< HTTP PROPFIND Method */ + HTTP_METHOD_PROPPATCH, /*!< HTTP PROPPATCH Method */ + HTTP_METHOD_MKCOL, /*!< HTTP MKCOL Method */ HTTP_METHOD_MAX, } esp_http_client_method_t; @@ -113,7 +120,8 @@ typedef struct { esp_http_client_method_t method; /*!< HTTP Method */ int timeout_ms; /*!< Network timeout in milliseconds */ bool disable_auto_redirect; /*!< Disable HTTP automatic redirects */ - int max_redirection_count; /*!< Max redirection number, using default value if zero*/ + int max_redirection_count; /*!< Max number of redirections on receiving HTTP redirect status code, using default value if zero*/ + int max_authorization_retries; /*!< Max connection retries on receiving HTTP unauthorized status code, using default value if zero. Disables authorization retry if -1*/ http_event_handle_cb event_handler; /*!< HTTP Event Handle */ esp_http_client_transport_t transport_type; /*!< HTTP transport type, see `esp_http_client_transport_t` */ int buffer_size; /*!< HTTP receive buffer size */ @@ -134,7 +142,12 @@ typedef enum { HttpStatus_TemporaryRedirect = 307, /* 4xx - Client Error */ - HttpStatus_Unauthorized = 401 + HttpStatus_Unauthorized = 401, + HttpStatus_Forbidden = 403, + HttpStatus_NotFound = 404, + + /* 5xx - Server Error */ + HttpStatus_InternalError = 500 } HttpStatus_Code; #define ESP_ERR_HTTP_BASE (0x7000) /*!< Starting number of HTTP error codes */ diff --git a/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h b/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h index e1e5c288..0d936de8 100644 --- a/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h +++ b/tools/sdk/esp32/include/esp_http_server/include/esp_http_server.h @@ -1047,7 +1047,7 @@ esp_err_t httpd_resp_send_chunk(httpd_req_t *r, const char *buf, ssize_t buf_len * - ESP_ERR_HTTPD_INVALID_REQ : Invalid request */ static inline esp_err_t httpd_resp_sendstr(httpd_req_t *r, const char *str) { - return httpd_resp_send(r, str, (str == NULL) ? 0 : strlen(str)); + return httpd_resp_send(r, str, (str == NULL) ? 0 : HTTPD_RESP_USE_STRLEN); } /** @@ -1068,7 +1068,7 @@ static inline esp_err_t httpd_resp_sendstr(httpd_req_t *r, const char *str) { * - ESP_ERR_HTTPD_INVALID_REQ : Invalid request */ static inline esp_err_t httpd_resp_sendstr_chunk(httpd_req_t *r, const char *str) { - return httpd_resp_send_chunk(r, str, (str == NULL) ? 0 : strlen(str)); + return httpd_resp_send_chunk(r, str, (str == NULL) ? 0 : HTTPD_RESP_USE_STRLEN); } /* Some commonly used status codes */ @@ -1292,6 +1292,53 @@ static inline esp_err_t httpd_resp_send_500(httpd_req_t *r) { */ int httpd_send(httpd_req_t *r, const char *buf, size_t buf_len); +/** + * A low level API to send data on a given socket + * + * @note This API is not recommended to be used in any request handler. + * Use this only for advanced use cases, wherein some asynchronous + * data is to be sent over a socket. + * + * This internally calls the default send function, or the function registered by + * httpd_sess_set_send_override(). + * + * @param[in] hd server instance + * @param[in] sockfd session socket file descriptor + * @param[in] buf buffer with bytes to send + * @param[in] buf_len data size + * @param[in] flags flags for the send() function + * @return + * - Bytes : The number of bytes sent successfully + * - HTTPD_SOCK_ERR_INVALID : Invalid arguments + * - HTTPD_SOCK_ERR_TIMEOUT : Timeout/interrupted while calling socket send() + * - HTTPD_SOCK_ERR_FAIL : Unrecoverable error while calling socket send() + */ +int httpd_socket_send(httpd_handle_t hd, int sockfd, const char *buf, size_t buf_len, int flags); + +/** + * A low level API to receive data from a given socket + * + * @note This API is not recommended to be used in any request handler. + * Use this only for advanced use cases, wherein some asynchronous + * communication is required. + * + * This internally calls the default recv function, or the function registered by + * httpd_sess_set_recv_override(). + * + * @param[in] hd server instance + * @param[in] sockfd session socket file descriptor + * @param[in] buf buffer with bytes to send + * @param[in] buf_len data size + * @param[in] flags flags for the send() function + * @return + * - Bytes : The number of bytes received successfully + * - 0 : Buffer length parameter is zero / connection closed by peer + * - HTTPD_SOCK_ERR_INVALID : Invalid arguments + * - HTTPD_SOCK_ERR_TIMEOUT : Timeout/interrupted while calling socket recv() + * - HTTPD_SOCK_ERR_FAIL : Unrecoverable error while calling socket recv() + */ +int httpd_socket_recv(httpd_handle_t hd, int sockfd, char *buf, size_t buf_len, int flags); + /** End of Request / Response * @} */ @@ -1483,7 +1530,15 @@ typedef enum { * @brief WebSocket frame format */ typedef struct httpd_ws_frame { - bool final; /*!< Final frame */ + bool final; /*!< Final frame: + For received frames this field indicates whether the `FIN` flag was set. + For frames to be transmitted, this field is only used if the `fragmented` + option is set as well. If `fragmented` is false, the `FIN` flag is set + by default, marking the ws_frame as a complete/unfragmented message + (esp_http_server doesn't automatically fragment messages) */ + bool fragmented; /*!< Indication that the frame allocated for transmission is a message fragment, + so the `FIN` flag is set manually according to the `final` option. + This flag is never set for received messages */ httpd_ws_type_t type; /*!< WebSocket frame type */ uint8_t *payload; /*!< Pre-allocated data buffer */ size_t len; /*!< Length of the WebSocket data */ diff --git a/tools/sdk/esp32/include/esp_netif/include/esp_netif.h b/tools/sdk/esp32/include/esp_netif/include/esp_netif.h index a8df60e6..5cb6e802 100644 --- a/tools/sdk/esp32/include/esp_netif/include/esp_netif.h +++ b/tools/sdk/esp32/include/esp_netif/include/esp_netif.h @@ -815,6 +815,22 @@ esp_netif_t *esp_netif_next(esp_netif_t *esp_netif); */ size_t esp_netif_get_nr_of_ifs(void); +/** + * @brief increase the reference counter of net stack buffer + * + * @param[in] netstack_buf the net stack buffer + * + */ +void esp_netif_netstack_buf_ref(void *netstack_buf); + +/** + * @brief free the netstack buffer + * + * @param[in] netstack_buf the net stack buffer + * + */ +void esp_netif_netstack_buf_free(void *netstack_buf); + /** * @} */ diff --git a/tools/sdk/esp32/include/esp_netif/include/esp_netif_defaults.h b/tools/sdk/esp32/include/esp_netif/include/esp_netif_defaults.h index 3c41d9c2..f61d7294 100644 --- a/tools/sdk/esp32/include/esp_netif/include/esp_netif_defaults.h +++ b/tools/sdk/esp32/include/esp_netif/include/esp_netif_defaults.h @@ -70,7 +70,19 @@ extern "C" { .lost_ip_event = IP_EVENT_PPP_LOST_IP, \ .if_key = "PPP_DEF", \ .if_desc = "ppp", \ - .route_prio = 128 \ + .route_prio = 20 \ +}; + +#define ESP_NETIF_INHERENT_DEFAULT_SLIP() \ + { \ + .flags = ESP_NETIF_FLAG_IS_SLIP, \ + ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(mac) \ + ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(ip_info) \ + .get_ip_event = 0, \ + .lost_ip_event = 0, \ + .if_key = "SLP_DEF", \ + .if_desc = "slip", \ + .route_prio = 16 \ }; /** @@ -112,6 +124,18 @@ extern "C" { .driver = NULL, \ .stack = ESP_NETIF_NETSTACK_DEFAULT_PPP, \ } + +/** +* @brief Default configuration reference of SLIP client +*/ +#define ESP_NETIF_DEFAULT_SLIP() \ + { \ + .base = ESP_NETIF_BASE_DEFAULT_SLIP, \ + .driver = NULL, \ + .stack = ESP_NETIF_NETSTACK_DEFAULT_SLIP, \ + } + + /** * @brief Default base config (esp-netif inherent) of WIFI STA */ @@ -132,11 +156,18 @@ extern "C" { */ #define ESP_NETIF_BASE_DEFAULT_PPP &_g_esp_netif_inherent_ppp_config +/** + * @brief Default base config (esp-netif inherent) of slip interface + */ +#define ESP_NETIF_BASE_DEFAULT_SLIP &_g_esp_netif_inherent_slip_config + + #define ESP_NETIF_NETSTACK_DEFAULT_ETH _g_esp_netif_netstack_default_eth #define ESP_NETIF_NETSTACK_DEFAULT_WIFI_STA _g_esp_netif_netstack_default_wifi_sta #define ESP_NETIF_NETSTACK_DEFAULT_WIFI_AP _g_esp_netif_netstack_default_wifi_ap #define ESP_NETIF_NETSTACK_DEFAULT_PPP _g_esp_netif_netstack_default_ppp +#define ESP_NETIF_NETSTACK_DEFAULT_SLIP _g_esp_netif_netstack_default_slip // // Include default network stacks configs @@ -148,6 +179,7 @@ extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_eth; extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_wifi_sta; extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_wifi_ap; extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_ppp; +extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_slip; // // Include default common configs inherent to esp-netif @@ -158,6 +190,7 @@ extern const esp_netif_inherent_config_t _g_esp_netif_inherent_sta_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_ap_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_eth_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_ppp_config; +extern const esp_netif_inherent_config_t _g_esp_netif_inherent_slip_config; extern const esp_netif_ip_info_t _g_esp_netif_soft_ap_ip; diff --git a/tools/sdk/esp32/include/esp_netif/include/esp_netif_net_stack.h b/tools/sdk/esp32/include/esp_netif/include/esp_netif_net_stack.h index c38297a9..ab6d6a07 100644 --- a/tools/sdk/esp32/include/esp_netif/include/esp_netif_net_stack.h +++ b/tools/sdk/esp32/include/esp_netif/include/esp_netif_net_stack.h @@ -69,6 +69,20 @@ void* esp_netif_get_netif_impl(esp_netif_t *esp_netif); */ esp_err_t esp_netif_transmit(esp_netif_t *esp_netif, void* data, size_t len); +/** + * @brief Outputs packets from the TCP/IP stack to the media to be transmitted + * + * This function gets called from network stack to output packets to IO driver. + * + * @param[in] esp_netif Handle to esp-netif instance + * @param[in] data Data to be transmitted + * @param[in] len Length of the data frame + * @param[in] netstack_buf net stack buffer + * + * @return ESP_OK on success, an error passed from the I/O driver otherwise + */ +esp_err_t esp_netif_transmit_wrap(esp_netif_t *esp_netif, void *data, size_t len, void *netstack_buf); + /** * @brief Free the rx buffer allocated by the media driver * diff --git a/tools/sdk/esp32/include/esp_netif/include/esp_netif_slip.h b/tools/sdk/esp32/include/esp_netif/include/esp_netif_slip.h new file mode 100644 index 00000000..9cfafb97 --- /dev/null +++ b/tools/sdk/esp32/include/esp_netif/include/esp_netif_slip.h @@ -0,0 +1,77 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +#ifndef _ESP_NETIF_SLIP_H_ +#define _ESP_NETIF_SLIP_H_ + +#include "esp_netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Configuration structure for SLIP network interface + * + */ +typedef struct esp_netif_slip_config { + esp_ip6_addr_t ip6_addr; /* Local IP6 address */ + +} esp_netif_slip_config_t; + + +/** @brief Sets common parameters for the supplied esp-netif. + * + * @param[in] esp_netif handle to slip esp-netif instance + * @param[in] config Pointer to SLIP netif configuration structure + * + * @return ESP_OK on success, ESP_ERR_ESP_NETIF_INVALID_PARAMS if netif null or not SLIP + */ +esp_err_t esp_netif_slip_set_params(esp_netif_t *netif, const esp_netif_slip_config_t *config); + +/** @brief Sets IPV6 address for the supplied esp-netif. + * + * @param[in] netif handle to slip esp-netif instance + * @param[in] ipv6 IPv6 address of the SLIP interface + * + * @return ESP_OK on success, ESP_ERR_ESP_NETIF_INVALID_PARAMS if netif null or not SLIP + */ +esp_err_t esp_netif_slip_set_ipv6(esp_netif_t *netif, const esp_ip6_addr_t *ipv6); + +/** + * @brief Data path API to write raw packet ous the SLIP interface + * + * This API is typically used when implementing user defined methods + * + * @param[in] esp_netif handle to slip esp-netif instance + * @param[in] buffer pointer to the outgoing data + * @param[in] len length of the data + * + * @return + * - ESP_OK on success + */ +void esp_netif_lwip_slip_raw_output(esp_netif_t *netif, void *buffer, size_t len); + +/** + * @brief Fetch IP6 address attached to the SLIP interface + * + * @param[in] esp_netif handle to slip esp-netif instance + * @param[in] address index (unused) + * + * @return + * - pointer to the internal ip6 address object + */ +const esp_ip6_addr_t *esp_slip_get_ip6(esp_netif_t *slip_netif); + +#endif diff --git a/tools/sdk/esp32/include/esp_netif/include/esp_netif_types.h b/tools/sdk/esp32/include/esp_netif/include/esp_netif_types.h index 0e361393..470839d1 100644 --- a/tools/sdk/esp32/include/esp_netif/include/esp_netif_types.h +++ b/tools/sdk/esp32/include/esp_netif/include/esp_netif_types.h @@ -138,7 +138,8 @@ typedef enum esp_netif_flags { ESP_NETIF_FLAG_AUTOUP = 1 << 2, ESP_NETIF_FLAG_GARP = 1 << 3, ESP_NETIF_FLAG_EVENT_IP_MODIFIED = 1 << 4, - ESP_NETIF_FLAG_IS_PPP = 1 << 5 + ESP_NETIF_FLAG_IS_PPP = 1 << 5, + ESP_NETIF_FLAG_IS_SLIP = 1 << 6, } esp_netif_flags_t; typedef enum esp_netif_ip_event_type { @@ -163,7 +164,9 @@ typedef struct esp_netif_inherent_config { const char * if_key; /*!< string identifier of the interface */ const char * if_desc; /*!< textual description of the interface */ int route_prio; /*!< numeric priority of this interface to become a default - routing if (if other netifs are up) */ + routing if (if other netifs are up). + A higher value of route_prio indicates + a higher priority */ } esp_netif_inherent_config_t; typedef struct esp_netif_config esp_netif_config_t; @@ -184,6 +187,7 @@ typedef struct esp_netif_driver_base_s { struct esp_netif_driver_ifconfig { esp_netif_iodriver_handle handle; esp_err_t (*transmit)(void *h, void *buffer, size_t len); + esp_err_t (*transmit_wrap)(void *h, void *buffer, size_t len, void *netstack_buffer); void (*driver_free_rx_buffer)(void *h, void* buffer); }; diff --git a/tools/sdk/esp32/include/esp_ringbuf/include/freertos/ringbuf.h b/tools/sdk/esp32/include/esp_ringbuf/include/freertos/ringbuf.h index 1312723a..ef9c5322 100644 --- a/tools/sdk/esp32/include/esp_ringbuf/include/freertos/ringbuf.h +++ b/tools/sdk/esp32/include/esp_ringbuf/include/freertos/ringbuf.h @@ -255,6 +255,7 @@ void *xRingbufferReceive(RingbufHandle_t xRingbuffer, size_t *pxItemSize, TickTy * * @note A call to vRingbufferReturnItemFromISR() is required after this to free the item retrieved. * @note Byte buffers do not allow multiple retrievals before returning an item + * @note Two calls to RingbufferReceiveFromISR() are required if the bytes wrap around the end of the ring buffer. * * @return * - Pointer to the retrieved item on success; *pxItemSize filled with the length of the item. @@ -333,6 +334,7 @@ BaseType_t xRingbufferReceiveSplitFromISR(RingbufHandle_t xRingbuffer, * @note A call to vRingbufferReturnItem() is required after this to free up the data retrieved. * @note This function should only be called on byte buffers * @note Byte buffers do not allow multiple retrievals before returning an item + * @note Two calls to RingbufferReceiveUpTo() are required if the bytes wrap around the end of the ring buffer. * * @return * - Pointer to the retrieved item on success; *pxItemSize filled with diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/crc.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/crc.h index a940b638..a5703611 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/crc.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/crc.h @@ -17,13 +17,6 @@ #include -#define ESP_ROM_HAS_CRC8LE 1 -#define ESP_ROM_HAS_CRC16LE 1 -#define ESP_ROM_HAS_CRC32LE 1 -#define ESP_ROM_HAS_CRC8BE 1 -#define ESP_ROM_HAS_CRC16BE 1 -#define ESP_ROM_HAS_CRC32BE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h index 04ffec0a..1ec326ca 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32/rom/secure_boot.h @@ -107,7 +107,7 @@ void ets_secure_boot_verify_boot_bootloader(void); * @return true if is Secure boot v2 has been enabled * False if Secure boot v2 has not been enabled. */ -bool ets_use_secure_boot_v2(); +bool ets_use_secure_boot_v2(void); #endif /* CONFIG_ESP32_REV_MIN_3 */ diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/cache.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/cache.h index 76ede22b..cc85512f 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/cache.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/cache.h @@ -50,10 +50,10 @@ typedef enum { typedef enum { CACHE_MEMORY_INVALID = 0, - CACHE_MEMORY_ICACHE_LOW = BIT(0), - CACHE_MEMORY_ICACHE_HIGH = BIT(1), - CACHE_MEMORY_DCACHE_LOW = BIT(2), - CACHE_MEMORY_DCACHE_HIGH = BIT(3), + CACHE_MEMORY_ICACHE_LOW = 1<<0, + CACHE_MEMORY_ICACHE_HIGH = 1<<1, + CACHE_MEMORY_DCACHE_LOW = 1<<2, + CACHE_MEMORY_DCACHE_HIGH = 1<<3, } cache_layout_t; #define CACHE_SIZE_8KB CACHE_SIZE_HALF diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/crc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/crc.h index f6a06871..0d139795 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/crc.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/crc.h @@ -17,10 +17,6 @@ #include -#define ESP_ROM_HAS_CRC8LE 1 -#define ESP_ROM_HAS_CRC16LE 1 -#define ESP_ROM_HAS_CRC32LE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/queue.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/queue.h deleted file mode 100644 index 29ee6706..00000000 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/queue.h +++ /dev/null @@ -1,645 +0,0 @@ -/*- - * Copyright (c) 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)queue.h 8.5 (Berkeley) 8/20/94 - * $FreeBSD$ - */ - -#ifndef _SYS_QUEUE_H_ -#define _SYS_QUEUE_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file defines four types of data structures: singly-linked lists, - * singly-linked tail queues, lists and tail queues. - * - * A singly-linked list is headed by a single forward pointer. The elements - * are singly linked for minimum space and pointer manipulation overhead at - * the expense of O(n) removal for arbitrary elements. New elements can be - * added to the list after an existing element or at the head of the list. - * Elements being removed from the head of the list should use the explicit - * macro for this purpose for optimum efficiency. A singly-linked list may - * only be traversed in the forward direction. Singly-linked lists are ideal - * for applications with large datasets and few or no removals or for - * implementing a LIFO queue. - * - * A singly-linked tail queue is headed by a pair of pointers, one to the - * head of the list and the other to the tail of the list. The elements are - * singly linked for minimum space and pointer manipulation overhead at the - * expense of O(n) removal for arbitrary elements. New elements can be added - * to the list after an existing element, at the head of the list, or at the - * end of the list. Elements being removed from the head of the tail queue - * should use the explicit macro for this purpose for optimum efficiency. - * A singly-linked tail queue may only be traversed in the forward direction. - * Singly-linked tail queues are ideal for applications with large datasets - * and few or no removals or for implementing a FIFO queue. - * - * A list is headed by a single forward pointer (or an array of forward - * pointers for a hash table header). The elements are doubly linked - * so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before - * or after an existing element or at the head of the list. A list - * may only be traversed in the forward direction. - * - * A tail queue is headed by a pair of pointers, one to the head of the - * list and the other to the tail of the list. The elements are doubly - * linked so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before or - * after an existing element, at the head of the list, or at the end of - * the list. A tail queue may be traversed in either direction. - * - * For details on the use of these macros, see the queue(3) manual page. - * - * - * SLIST LIST STAILQ TAILQ - * _HEAD + + + + - * _HEAD_INITIALIZER + + + + - * _ENTRY + + + + - * _INIT + + + + - * _EMPTY + + + + - * _FIRST + + + + - * _NEXT + + + + - * _PREV - - - + - * _LAST - - + + - * _FOREACH + + + + - * _FOREACH_SAFE + + + + - * _FOREACH_REVERSE - - - + - * _FOREACH_REVERSE_SAFE - - - + - * _INSERT_HEAD + + + + - * _INSERT_BEFORE - + - + - * _INSERT_AFTER + + + + - * _INSERT_TAIL - - + + - * _CONCAT - - + + - * _REMOVE_AFTER + - + - - * _REMOVE_HEAD + - + - - * _REMOVE + + + + - * - */ -#ifdef QUEUE_MACRO_DEBUG -/* Store the last 2 places the queue element or head was altered */ -struct qm_trace { - char * lastfile; - int lastline; - char * prevfile; - int prevline; -}; - -#define TRACEBUF struct qm_trace trace; -#define TRASHIT(x) do {(x) = (void *)-1;} while (0) -#define QMD_SAVELINK(name, link) void **name = (void *)&(link) - -#define QMD_TRACE_HEAD(head) do { \ - (head)->trace.prevline = (head)->trace.lastline; \ - (head)->trace.prevfile = (head)->trace.lastfile; \ - (head)->trace.lastline = __LINE__; \ - (head)->trace.lastfile = __FILE__; \ -} while (0) - -#define QMD_TRACE_ELEM(elem) do { \ - (elem)->trace.prevline = (elem)->trace.lastline; \ - (elem)->trace.prevfile = (elem)->trace.lastfile; \ - (elem)->trace.lastline = __LINE__; \ - (elem)->trace.lastfile = __FILE__; \ -} while (0) - -#else -#define QMD_TRACE_ELEM(elem) -#define QMD_TRACE_HEAD(head) -#define QMD_SAVELINK(name, link) -#define TRACEBUF -#define TRASHIT(x) -#endif /* QUEUE_MACRO_DEBUG */ - -/* - * Singly-linked List declarations. - */ -#define SLIST_HEAD(name, type) \ -struct name { \ - struct type *slh_first; /* first element */ \ -} - -#define SLIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define SLIST_ENTRY(type) \ -struct { \ - struct type *sle_next; /* next element */ \ -} - -/* - * Singly-linked List functions. - */ -#define SLIST_EMPTY(head) ((head)->slh_first == NULL) - -#define SLIST_FIRST(head) ((head)->slh_first) - -#define SLIST_FOREACH(var, head, field) \ - for ((var) = SLIST_FIRST((head)); \ - (var); \ - (var) = SLIST_NEXT((var), field)) - -#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = SLIST_FIRST((head)); \ - (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ - for ((varp) = &SLIST_FIRST((head)); \ - ((var) = *(varp)) != NULL; \ - (varp) = &SLIST_NEXT((var), field)) - -#define SLIST_INIT(head) do { \ - SLIST_FIRST((head)) = NULL; \ -} while (0) - -#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ - SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ - SLIST_NEXT((slistelm), field) = (elm); \ -} while (0) - -#define SLIST_INSERT_HEAD(head, elm, field) do { \ - SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ - SLIST_FIRST((head)) = (elm); \ -} while (0) - -#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) - -#define SLIST_REMOVE(head, elm, type, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.sle_next); \ - if (SLIST_FIRST((head)) == (elm)) { \ - SLIST_REMOVE_HEAD((head), field); \ - } \ - else { \ - struct type *curelm = SLIST_FIRST((head)); \ - while (SLIST_NEXT(curelm, field) != (elm)) \ - curelm = SLIST_NEXT(curelm, field); \ - SLIST_REMOVE_AFTER(curelm, field); \ - } \ - TRASHIT(*oldnext); \ -} while (0) - -#define SLIST_REMOVE_AFTER(elm, field) do { \ - SLIST_NEXT(elm, field) = \ - SLIST_NEXT(SLIST_NEXT(elm, field), field); \ -} while (0) - -#define SLIST_REMOVE_HEAD(head, field) do { \ - SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ -} while (0) - -/* - * Singly-linked Tail queue declarations. - */ -#define STAILQ_HEAD(name, type) \ -struct name { \ - struct type *stqh_first;/* first element */ \ - struct type **stqh_last;/* addr of last next element */ \ -} - -#define STAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).stqh_first } - -#define STAILQ_ENTRY(type) \ -struct { \ - struct type *stqe_next; /* next element */ \ -} - -/* - * Singly-linked Tail queue functions. - */ -#define STAILQ_CONCAT(head1, head2) do { \ - if (!STAILQ_EMPTY((head2))) { \ - *(head1)->stqh_last = (head2)->stqh_first; \ - (head1)->stqh_last = (head2)->stqh_last; \ - STAILQ_INIT((head2)); \ - } \ -} while (0) - -#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) - -#define STAILQ_FIRST(head) ((head)->stqh_first) - -#define STAILQ_FOREACH(var, head, field) \ - for((var) = STAILQ_FIRST((head)); \ - (var); \ - (var) = STAILQ_NEXT((var), field)) - - -#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = STAILQ_FIRST((head)); \ - (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define STAILQ_INIT(head) do { \ - STAILQ_FIRST((head)) = NULL; \ - (head)->stqh_last = &STAILQ_FIRST((head)); \ -} while (0) - -#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ - if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ - STAILQ_NEXT((tqelm), field) = (elm); \ -} while (0) - -#define STAILQ_INSERT_HEAD(head, elm, field) do { \ - if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ - STAILQ_FIRST((head)) = (elm); \ -} while (0) - -#define STAILQ_INSERT_TAIL(head, elm, field) do { \ - STAILQ_NEXT((elm), field) = NULL; \ - *(head)->stqh_last = (elm); \ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ -} while (0) - -#define STAILQ_LAST(head, type, field) \ - (STAILQ_EMPTY((head)) ? \ - NULL : \ - ((struct type *)(void *) \ - ((char *)((head)->stqh_last) - __offsetof(struct type, field)))) - -#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) - -#define STAILQ_REMOVE(head, elm, type, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \ - if (STAILQ_FIRST((head)) == (elm)) { \ - STAILQ_REMOVE_HEAD((head), field); \ - } \ - else { \ - struct type *curelm = STAILQ_FIRST((head)); \ - while (STAILQ_NEXT(curelm, field) != (elm)) \ - curelm = STAILQ_NEXT(curelm, field); \ - STAILQ_REMOVE_AFTER(head, curelm, field); \ - } \ - TRASHIT(*oldnext); \ -} while (0) - -#define STAILQ_REMOVE_HEAD(head, field) do { \ - if ((STAILQ_FIRST((head)) = \ - STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ - (head)->stqh_last = &STAILQ_FIRST((head)); \ -} while (0) - -#define STAILQ_REMOVE_AFTER(head, elm, field) do { \ - if ((STAILQ_NEXT(elm, field) = \ - STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ -} while (0) - -#define STAILQ_SWAP(head1, head2, type) do { \ - struct type *swap_first = STAILQ_FIRST(head1); \ - struct type **swap_last = (head1)->stqh_last; \ - STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \ - (head1)->stqh_last = (head2)->stqh_last; \ - STAILQ_FIRST(head2) = swap_first; \ - (head2)->stqh_last = swap_last; \ - if (STAILQ_EMPTY(head1)) \ - (head1)->stqh_last = &STAILQ_FIRST(head1); \ - if (STAILQ_EMPTY(head2)) \ - (head2)->stqh_last = &STAILQ_FIRST(head2); \ -} while (0) - -#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do { \ - if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \ - (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field); \ - } \ - STAILQ_FIRST(head) = (elm_chead); \ -} while (0) - - -/* - * List declarations. - */ -#define LIST_HEAD(name, type) \ -struct name { \ - struct type *lh_first; /* first element */ \ -} - -#define LIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define LIST_ENTRY(type) \ -struct { \ - struct type *le_next; /* next element */ \ - struct type **le_prev; /* address of previous next element */ \ -} - -/* - * List functions. - */ - -#if (defined(_KERNEL) && defined(INVARIANTS)) -#define QMD_LIST_CHECK_HEAD(head, field) do { \ - if (LIST_FIRST((head)) != NULL && \ - LIST_FIRST((head))->field.le_prev != \ - &LIST_FIRST((head))) \ - panic("Bad list head %p first->prev != head", (head)); \ -} while (0) - -#define QMD_LIST_CHECK_NEXT(elm, field) do { \ - if (LIST_NEXT((elm), field) != NULL && \ - LIST_NEXT((elm), field)->field.le_prev != \ - &((elm)->field.le_next)) \ - panic("Bad link elm %p next->prev != elm", (elm)); \ -} while (0) - -#define QMD_LIST_CHECK_PREV(elm, field) do { \ - if (*(elm)->field.le_prev != (elm)) \ - panic("Bad link elm %p prev->next != elm", (elm)); \ -} while (0) -#else -#define QMD_LIST_CHECK_HEAD(head, field) -#define QMD_LIST_CHECK_NEXT(elm, field) -#define QMD_LIST_CHECK_PREV(elm, field) -#endif /* (_KERNEL && INVARIANTS) */ - -#define LIST_EMPTY(head) ((head)->lh_first == NULL) - -#define LIST_FIRST(head) ((head)->lh_first) - -#define LIST_FOREACH(var, head, field) \ - for ((var) = LIST_FIRST((head)); \ - (var); \ - (var) = LIST_NEXT((var), field)) - -#define LIST_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = LIST_FIRST((head)); \ - (var) && ((tvar) = LIST_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define LIST_INIT(head) do { \ - LIST_FIRST((head)) = NULL; \ -} while (0) - -#define LIST_INSERT_AFTER(listelm, elm, field) do { \ - QMD_LIST_CHECK_NEXT(listelm, field); \ - if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ - LIST_NEXT((listelm), field)->field.le_prev = \ - &LIST_NEXT((elm), field); \ - LIST_NEXT((listelm), field) = (elm); \ - (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ -} while (0) - -#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ - QMD_LIST_CHECK_PREV(listelm, field); \ - (elm)->field.le_prev = (listelm)->field.le_prev; \ - LIST_NEXT((elm), field) = (listelm); \ - *(listelm)->field.le_prev = (elm); \ - (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ -} while (0) - -#define LIST_INSERT_HEAD(head, elm, field) do { \ - QMD_LIST_CHECK_HEAD((head), field); \ - if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ - LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ - LIST_FIRST((head)) = (elm); \ - (elm)->field.le_prev = &LIST_FIRST((head)); \ -} while (0) - -#define LIST_NEXT(elm, field) ((elm)->field.le_next) - -#define LIST_REMOVE(elm, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.le_next); \ - QMD_SAVELINK(oldprev, (elm)->field.le_prev); \ - QMD_LIST_CHECK_NEXT(elm, field); \ - QMD_LIST_CHECK_PREV(elm, field); \ - if (LIST_NEXT((elm), field) != NULL) \ - LIST_NEXT((elm), field)->field.le_prev = \ - (elm)->field.le_prev; \ - *(elm)->field.le_prev = LIST_NEXT((elm), field); \ - TRASHIT(*oldnext); \ - TRASHIT(*oldprev); \ -} while (0) - -#define LIST_SWAP(head1, head2, type, field) do { \ - struct type *swap_tmp = LIST_FIRST((head1)); \ - LIST_FIRST((head1)) = LIST_FIRST((head2)); \ - LIST_FIRST((head2)) = swap_tmp; \ - if ((swap_tmp = LIST_FIRST((head1))) != NULL) \ - swap_tmp->field.le_prev = &LIST_FIRST((head1)); \ - if ((swap_tmp = LIST_FIRST((head2))) != NULL) \ - swap_tmp->field.le_prev = &LIST_FIRST((head2)); \ -} while (0) - -/* - * Tail queue declarations. - */ -#define TAILQ_HEAD(name, type) \ -struct name { \ - struct type *tqh_first; /* first element */ \ - struct type **tqh_last; /* addr of last next element */ \ - TRACEBUF \ -} - -#define TAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).tqh_first } - -#define TAILQ_ENTRY(type) \ -struct { \ - struct type *tqe_next; /* next element */ \ - struct type **tqe_prev; /* address of previous next element */ \ - TRACEBUF \ -} - -/* - * Tail queue functions. - */ -#if (defined(_KERNEL) && defined(INVARIANTS)) -#define QMD_TAILQ_CHECK_HEAD(head, field) do { \ - if (!TAILQ_EMPTY(head) && \ - TAILQ_FIRST((head))->field.tqe_prev != \ - &TAILQ_FIRST((head))) \ - panic("Bad tailq head %p first->prev != head", (head)); \ -} while (0) - -#define QMD_TAILQ_CHECK_TAIL(head, field) do { \ - if (*(head)->tqh_last != NULL) \ - panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \ -} while (0) - -#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \ - if (TAILQ_NEXT((elm), field) != NULL && \ - TAILQ_NEXT((elm), field)->field.tqe_prev != \ - &((elm)->field.tqe_next)) \ - panic("Bad link elm %p next->prev != elm", (elm)); \ -} while (0) - -#define QMD_TAILQ_CHECK_PREV(elm, field) do { \ - if (*(elm)->field.tqe_prev != (elm)) \ - panic("Bad link elm %p prev->next != elm", (elm)); \ -} while (0) -#else -#define QMD_TAILQ_CHECK_HEAD(head, field) -#define QMD_TAILQ_CHECK_TAIL(head, headname) -#define QMD_TAILQ_CHECK_NEXT(elm, field) -#define QMD_TAILQ_CHECK_PREV(elm, field) -#endif /* (_KERNEL && INVARIANTS) */ - -#define TAILQ_CONCAT(head1, head2, field) do { \ - if (!TAILQ_EMPTY(head2)) { \ - *(head1)->tqh_last = (head2)->tqh_first; \ - (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ - (head1)->tqh_last = (head2)->tqh_last; \ - TAILQ_INIT((head2)); \ - QMD_TRACE_HEAD(head1); \ - QMD_TRACE_HEAD(head2); \ - } \ -} while (0) - -#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) - -#define TAILQ_FIRST(head) ((head)->tqh_first) - -#define TAILQ_FOREACH(var, head, field) \ - for ((var) = TAILQ_FIRST((head)); \ - (var); \ - (var) = TAILQ_NEXT((var), field)) - -#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = TAILQ_FIRST((head)); \ - (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ - for ((var) = TAILQ_LAST((head), headname); \ - (var); \ - (var) = TAILQ_PREV((var), headname, field)) - -#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ - for ((var) = TAILQ_LAST((head), headname); \ - (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ - (var) = (tvar)) - -#define TAILQ_INIT(head) do { \ - TAILQ_FIRST((head)) = NULL; \ - (head)->tqh_last = &TAILQ_FIRST((head)); \ - QMD_TRACE_HEAD(head); \ -} while (0) - -#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ - QMD_TAILQ_CHECK_NEXT(listelm, field); \ - if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ - TAILQ_NEXT((elm), field)->field.tqe_prev = \ - &TAILQ_NEXT((elm), field); \ - else { \ - (head)->tqh_last = &TAILQ_NEXT((elm), field); \ - QMD_TRACE_HEAD(head); \ - } \ - TAILQ_NEXT((listelm), field) = (elm); \ - (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ - QMD_TRACE_ELEM(&(elm)->field); \ - QMD_TRACE_ELEM(&listelm->field); \ -} while (0) - -#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ - QMD_TAILQ_CHECK_PREV(listelm, field); \ - (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ - TAILQ_NEXT((elm), field) = (listelm); \ - *(listelm)->field.tqe_prev = (elm); \ - (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ - QMD_TRACE_ELEM(&(elm)->field); \ - QMD_TRACE_ELEM(&listelm->field); \ -} while (0) - -#define TAILQ_INSERT_HEAD(head, elm, field) do { \ - QMD_TAILQ_CHECK_HEAD(head, field); \ - if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ - TAILQ_FIRST((head))->field.tqe_prev = \ - &TAILQ_NEXT((elm), field); \ - else \ - (head)->tqh_last = &TAILQ_NEXT((elm), field); \ - TAILQ_FIRST((head)) = (elm); \ - (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ - QMD_TRACE_HEAD(head); \ - QMD_TRACE_ELEM(&(elm)->field); \ -} while (0) - -#define TAILQ_INSERT_TAIL(head, elm, field) do { \ - QMD_TAILQ_CHECK_TAIL(head, field); \ - TAILQ_NEXT((elm), field) = NULL; \ - (elm)->field.tqe_prev = (head)->tqh_last; \ - *(head)->tqh_last = (elm); \ - (head)->tqh_last = &TAILQ_NEXT((elm), field); \ - QMD_TRACE_HEAD(head); \ - QMD_TRACE_ELEM(&(elm)->field); \ -} while (0) - -#define TAILQ_LAST(head, headname) \ - (*(((struct headname *)((head)->tqh_last))->tqh_last)) - -#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) - -#define TAILQ_PREV(elm, headname, field) \ - (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) - -#define TAILQ_REMOVE(head, elm, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \ - QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \ - QMD_TAILQ_CHECK_NEXT(elm, field); \ - QMD_TAILQ_CHECK_PREV(elm, field); \ - if ((TAILQ_NEXT((elm), field)) != NULL) \ - TAILQ_NEXT((elm), field)->field.tqe_prev = \ - (elm)->field.tqe_prev; \ - else { \ - (head)->tqh_last = (elm)->field.tqe_prev; \ - QMD_TRACE_HEAD(head); \ - } \ - *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ - TRASHIT(*oldnext); \ - TRASHIT(*oldprev); \ - QMD_TRACE_ELEM(&(elm)->field); \ -} while (0) - -#define TAILQ_SWAP(head1, head2, type, field) do { \ - struct type *swap_first = (head1)->tqh_first; \ - struct type **swap_last = (head1)->tqh_last; \ - (head1)->tqh_first = (head2)->tqh_first; \ - (head1)->tqh_last = (head2)->tqh_last; \ - (head2)->tqh_first = swap_first; \ - (head2)->tqh_last = swap_last; \ - if ((swap_first = (head1)->tqh_first) != NULL) \ - swap_first->field.tqe_prev = &(head1)->tqh_first; \ - else \ - (head1)->tqh_last = &(head1)->tqh_first; \ - if ((swap_first = (head2)->tqh_first) != NULL) \ - swap_first->field.tqe_prev = &(head2)->tqh_first; \ - else \ - (head2)->tqh_last = &(head2)->tqh_first; \ -} while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* !_SYS_QUEUE_H_ */ diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rsa_pss.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rsa_pss.h index 6a70c578..bfbaeb6a 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rsa_pss.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rsa_pss.h @@ -16,7 +16,11 @@ #define _ROM_RSA_PSS_H_ #include -#include "rsa_pss.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif #define ETS_SIG_LEN 384 /* Bytes */ #define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ @@ -28,10 +32,14 @@ typedef struct { uint32_t mdash; } ets_rsa_pubkey_t; -bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest); +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); +#ifdef __cplusplus +} +#endif + #endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rtc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rtc.h index 593e8854..c91916fa 100644 --- a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rtc.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/rtc.h @@ -71,7 +71,6 @@ extern "C" { #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG - typedef enum { AWAKE = 0, // + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void cdc_acm_device; +extern cdc_acm_device *uart_acm_dev; + +#define ACM_BYTES_PER_TX 64 + +//ACM statuses are negative to distinguish from USB_DC_* status codes +#define ACM_STATUS_LINESTATE_CHANGED -1 +#define ACM_STATUS_LINECODING_CHANGED -2 +#define ACM_STATUS_TX -3 +#define ACM_STATUS_RX -4 + +typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status); + +/** + * @brief Get amount of received characters in buffer + * + * @returns character count + */ + +int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev); + + +/* + * @brief Poll the device for input. + * + * @return -ENOTSUP Since underlying USB device controller always uses + * interrupts, polled mode UART APIs are not implemented for the UART interface + * exported by CDC ACM driver. Apps should use fifo_read API instead. + */ + +int cdc_acm_poll_in(cdc_acm_device *dev, unsigned char *c); + +/* + * @brief Output a character in polled mode. + * + * The UART poll method for USB UART is simulated by waiting till + * we get the next BULK In upcall from the USB device controller or 100 ms. + * + * @return the same character which is sent + */ +unsigned char cdc_acm_poll_out(cdc_acm_device *dev, unsigned char c); + +/** + * @brief Fill FIFO with data + * + * @param dev CDC ACM device struct. + * @param tx_data Data to transmit. + * @param len Number of bytes to send. + * + * @return Number of bytes sent. + */ +int cdc_acm_fifo_fill(cdc_acm_device *dev, const uint8_t *tx_data, int len); + +/** + * @brief Read data from FIFO + * + * @param dev CDC ACM device struct. + * @param rx_data Pointer to data container. + * @param size Container size. + * + * @return Number of bytes read. + */ +int cdc_acm_fifo_read(cdc_acm_device *dev, uint8_t *rx_data, const int size); + +/** + * @brief Enable TX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_tx_enable(cdc_acm_device *dev); + +/** + * @brief Disable TX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_tx_disable(cdc_acm_device *dev); + +/** + * @brief Check if Tx IRQ has been raised + * + * @param dev CDC ACM device struct. + * + * @return 1 if a Tx IRQ is pending, 0 otherwise. + */ +int cdc_acm_irq_tx_ready(cdc_acm_device *dev); + +/** + * @brief Enable RX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A + */ +void cdc_acm_irq_rx_enable(cdc_acm_device *dev); + +/** + * @brief Disable RX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_rx_disable(cdc_acm_device *dev); + +/** + * @brief Enable line state interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_state_enable(cdc_acm_device *dev); + +/** + * @brief Disable line state interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_state_disable(cdc_acm_device *dev); + + +/** + * @brief Check if Rx IRQ has been raised + * + * @param dev CDC ACM device struct. + * + * @return 1 if an IRQ is ready, 0 otherwise. + */ +int cdc_acm_irq_rx_ready(cdc_acm_device *dev); + +/** + * @brief Check if Tx or Rx IRQ is pending + * + * @param dev CDC ACM device struct. + * + * @return 1 if a Tx or Rx IRQ is pending, 0 otherwise. + */ +int cdc_acm_irq_is_pending(cdc_acm_device *dev); + +/** + * @brief Set the callback function pointer for IRQ. + * + * @param dev CDC ACM device struct. + * @param cb Callback function pointer. + * + * @return N/A + */ +void cdc_acm_irq_callback_set(cdc_acm_device *dev, uart_irq_callback_t cb); + +/** + * @brief Manipulate line control for UART. + * + * @param dev CDC ACM device struct + * @param ctrl The line control to be manipulated + * @param val Value to set the line control + * + * @return 0 if successful, failed otherwise. + */ +int cdc_acm_line_ctrl_set(cdc_acm_device *dev, uint32_t ctrl, uint32_t val); + +/** + * @brief Manipulate line control for UART. + * + * @param dev CDC ACM device struct + * @param ctrl The line control to be manipulated + * @param val Value to set the line control + * + * @return 0 if successful, failed otherwise. + */ +int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val); + + +/** + * @brief Initialize UART channel + * + * This routine is called to reset the chip in a quiescent state. + * It is assumed that this function is called only once per UART. + * + * @param mem_chunk Memory chunk to use for internal use + * @param mem_chunk_size Size of the memory chunk in bytes + * + * @return dev or NULL + */ +cdc_acm_device *cdc_acm_init(void *mem_chunk, int mem_chunk_size); + + +/** Common line controls for UART.*/ +#define LINE_CTRL_BAUD_RATE (1 << 0) +#define LINE_CTRL_RTS (1 << 1) +#define LINE_CTRL_DTR (1 << 2) +#define LINE_CTRL_DCD (1 << 3) +#define LINE_CTRL_DSR (1 << 4) + +/* Common communication errors for UART.*/ + +/** @brief Overrun error */ +#define UART_ERROR_OVERRUN (1 << 0) + +/** @brief Parity error */ +#define UART_ERROR_PARITY (1 << 1) + +/** @brief Framing error */ +#define UART_ERROR_FRAMING (1 << 2) + +/** + * @brief Break interrupt error: + * + * A break interrupt was received. This happens when the serial input is + * held at a logic '0' state for longer than the sum of start time + data bits + * + parity + stop bits. + */ +#define UART_ERROR_BREAK (1 << 3) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h new file mode 100644 index 00000000..a7c50643 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h @@ -0,0 +1,30 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int chip_usb_dw_init(void); +int chip_usb_dw_did_persist(void); +void chip_usb_dw_prepare_persist(void); +uint32_t chip_usb_get_persist_flags(void); +void chip_usb_set_persist_flags(uint32_t flags); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/cpio.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/cpio.h new file mode 100644 index 00000000..5603b3f5 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/cpio.h @@ -0,0 +1,180 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +/** + * Archive to parse cpio data in the newc and crc formats. Generate a cpio archive like that by e.g. + * find . | cpio -o -H newc > archive.cpio + */ + +#pragma once + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CPIO_MODE_FILETYPE_MASK 0xF000 +#define CPIO_MODE_FILETYPE_SOCKET 0xC000 +#define CPIO_MODE_FILETYPE_SYMLINK 0xA000 +#define CPIO_MODE_FILETYPE_REGULAR 0x8000 +#define CPIO_MODE_FILETYPE_BLOCKDEV 0x6000 +#define CPIO_MODE_FILETYPE_DIR 0x4000 +#define CPIO_MODE_FILETYPE_CHARDEV 0x2000 +#define CPIO_MODE_FILETYPE_FIFO 0x1000 +#define CPIO_MODE_SUID 0x0800 +#define CPIO_MODE_SGID 0x0400 +#define CPIO_MODE_STICKY 0x0200 + +typedef struct { + size_t filesize; + char *name; + uint32_t mode; + uint32_t check; +} cpio_file_t; + +typedef enum { + CPIO_RET_MORE = 0, + CPIO_RET_DONE, + CPIO_RET_ERR +} cpio_ret_t; + +typedef struct cpio_handle_data_t cpio_handle_data_t; +typedef cpio_handle_data_t *cpio_handle_t; + +typedef enum { + CPIO_RSN_FILE_ALL = 0, + CPIO_RSN_FILE_INITIAL, + CPIO_RSN_FILE_MORE, + CPIO_RSN_FILE_END +} cpio_callback_reason_t; + + +/** + * Callback for cpio file data. + * + * This callback will be called by the library to indicate data for a file is available. + * + * For files in the cpio archive that fit entirely in the internal buffer, or when no internal + * buffer is available, are entirely contained in the buffer fed to cpio_feed(), this callback + * is only called once, with reason=CPIO_RNS_FILE_ALL. fileinfo will contain the information + * for that specific file (name, size, ...), buff_offset will be 0, buff_len is the file + * size and buff contains all the information for the file. + * + * For files that do not fit in the buffer, this callback will be called multiple times. + * The initial time with reason=CPIO_RSN_FILE_INITIAL, when more data is available with + * CPIO_RSN_FILE_MORE and finally with CPIO_RSN_FILE_END. For these calls, fileinfo + * will again contain file information. buff will be the information contained in the + * file at offset buff_offset, and the lenght of this buffer will be in buff_len. + * + * The library guarantees to feed all file data to the callback consequitively, so + * within the same file, the buff_offset from a call will always be (buff_offset+buff_len) + * from the call before that. If cpio_start is + * + * The library also guarantees every file in the cpio archive will either generate a single + * callback call with CPIO_RSN_ALL, or multiple with in sequence CPIO_RSN_FILE_INITIAL, 0 or + * more CPIO_RSN_FILE_MORE and finally a CPIO_RSN_FILE_END. + * + * When a non-zero buffer size is passed to cpio_start, the library guarantees that all callback + * calls with a reason of CPIO_RSN_FILE_INITIAL and CPIO_RSN_FILE_MORE will have a buffer + * filled with exactly this amount of bytes. + * + */ +typedef void (*cpio_callback_t)(cpio_callback_reason_t reason, cpio_file_t *fileinfo, size_t buff_offset, size_t buff_len, char *buff, void *arg); + + +/** + * @brief Initialize a cpio handle. + * + * Call this to start parsing a cpio archive. You can set the callback that handles the + * files/data here. + * + * @param callback The callback that will handle the data of the files inside the cpio archive + * + * @param cbarg User-supplied argument. The callback will be called with this as an argument. + * + * @param buflen Length of internal buffer used. + * If this is zero, the callback will be called with data that lives in the data buffer + * supplied to the cpio library by whomever called cpio_feed(). Because this library has + * no power over that buffer, the callback can be passed as little as 1 and as many as + * INT_MAX bytes at a time. + * If this is non-zero, the library will allocate an internal buffer of this size. All + * cpio_feed()-calls will be rebuffered, and the callback is guaranteed to only be called + * with this many bytes in the buffer, given there's enough data in the file to fill it. + * + * @param memchunk Chunk of memory to allocate everything (handle, I/O buffer, filename buffer) in. Minimum size + * (estimate) is 160+buflen+sizeof(largest filename/path). + * @param memchunklen Size of the mem chunk + * + * @return + * - Success: A pointer to a cpio handle + * - Error: NULL + * + */ +cpio_handle_t cpio_start(cpio_callback_t callback, void *cbarg, size_t buflen, void *memchunk, int memchunklen); + +/** + * @brief Feed data from a cpio archive into the library + * + * This routine is used to feed consecutive data of the cpio archive into the library. While processing, + * the library can call the callback function one or more times if needed. + * + * @param cpio Handle obtained by calling cpio_start() + * + * @param buffer Pointer to buffer containing cpio archive data + * + * @param len Length of the buffer, in bytes + * + * @return + * - CPIO_RET_MORE: CPIO archive isn't done yet, please feed more data. + * - CPIO_RET_DONE: CPUI archive is finished. + * - CPIO_RET_ERR: Invalid CPIO archive data; decoding aborted. + * + */ +cpio_ret_t cpio_feed(cpio_handle_t cpio, char *buffer, int len); + +/** + * @brief Indicate there is no more cpio data to be fed into the archive + * + * This call is to be called when the source data is exhausted. Normally, the library can find the end of the + * cpio archive by looking for the end marker, + * + * @param timer_conf Pointer of LEDC timer configure struct + * + * + * @return + * - CPIO_RET_DONE on success + * - CPIO_RET_ERR when cpio archive is invalid + * + */ +cpio_ret_t cpio_done(cpio_handle_t cpio); + + +/** + * @brief Free the memory allocated for a cpio handle. + * + * @param cpio Handle obtained by calling cpio_start() + * + * @return + * - CPIO_RET_DONE on success + * + */ +cpio_ret_t cpio_destroy(cpio_handle_t cpio); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_cdc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_cdc.h new file mode 100644 index 00000000..c241bcfe --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_cdc.h @@ -0,0 +1,174 @@ +/* usb_cdc.h - USB CDC-ACM and CDC-ECM public header */ + +/* + * Copyright (c) 2017 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/** + * @file + * @brief USB Communications Device Class (CDC) public header + * + * Header follows the Class Definitions for + * Communications Devices Specification (CDC120-20101103-track.pdf), + * PSTN Devices Specification (PSTN120.pdf) and + * Ethernet Control Model Devices Specification (ECM120.pdf). + * Header is limited to ACM and ECM Subclasses. + */ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** CDC Specification release number in BCD format */ +#define CDC_SRN_1_20 0x0120 + +/** Communications Class Subclass Codes */ +#define ACM_SUBCLASS 0x02 +#define ECM_SUBCLASS 0x06 +#define EEM_SUBCLASS 0x0c + +/** Communications Class Protocol Codes */ +#define AT_CMD_V250_PROTOCOL 0x01 +#define EEM_PROTOCOL 0x07 + +/** + * @brief Data Class Interface Codes + * @note CDC120-20101103-track.pdf, 4.5, Table 6 + */ +#define DATA_INTERFACE_CLASS 0x0A + +/** + * @brief Values for the bDescriptorType Field + * @note CDC120-20101103-track.pdf, 5.2.3, Table 12 + */ +#define CS_INTERFACE 0x24 +#define CS_ENDPOINT 0x25 + +/** + * @brief bDescriptor SubType for Communications + * Class Functional Descriptors + * @note CDC120-20101103-track.pdf, 5.2.3, Table 13 + */ +#define HEADER_FUNC_DESC 0x00 +#define CALL_MANAGEMENT_FUNC_DESC 0x01 +#define ACM_FUNC_DESC 0x02 +#define UNION_FUNC_DESC 0x06 +#define ETHERNET_FUNC_DESC 0x0F + +/** + * @brief PSTN Subclass Specific Requests + * for ACM devices + * @note PSTN120.pdf, 6.3, Table 13 + */ +#define CDC_SEND_ENC_CMD 0x00 +#define CDC_GET_ENC_RSP 0x01 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/** UART State Bitmap Values */ +#define SERIAL_STATE_OVERRUN 0x40 +#define SERIAL_STATE_PARITY 0x20 +#define SERIAL_STATE_FRAMING 0x10 +#define SERIAL_STATE_RING 0x08 +#define SERIAL_STATE_BREAK 0x04 +#define SERIAL_STATE_TX_CARRIER 0x02 +#define SERIAL_STATE_RX_CARRIER 0x01 + +/** + * @brief Class-Specific Request Codes for Ethernet subclass + * @note ECM120.pdf, 6.2, Table 6 + */ +#define SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define SET_ETHERNET_PM_FILTER 0x41 +#define GET_ETHERNET_PM_FILTER 0x42 +#define SET_ETHERNET_PACKET_FILTER 0x43 +#define GET_ETHERNET_STATISTIC 0x44 + +/** Ethernet Packet Filter Bitmap */ +#define PACKET_TYPE_MULTICAST 0x10 +#define PACKET_TYPE_BROADCAST 0x08 +#define PACKET_TYPE_DIRECTED 0x04 +#define PACKET_TYPE_ALL_MULTICAST 0x02 +#define PACKET_TYPE_PROMISCUOUS 0x01 + +/** Header Functional Descriptor */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdCDC; +} __packed; + +/** Union Interface Functional Descriptor */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __packed; + +/** Call Management Functional Descriptor */ +struct cdc_cm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} __packed; + +/** Abstract Control Management Functional Descriptor */ +struct cdc_acm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} __packed; + + +/** Data structure for GET_LINE_CODING / SET_LINE_CODING class requests */ +struct cdc_acm_line_coding { + uint32_t dwDTERate; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} __packed; + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __packed; + +/** Ethernet Networking Functional Descriptor */ +struct cdc_ecm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __packed; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_common.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_common.h new file mode 100644 index 00000000..796a77bc --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_common.h @@ -0,0 +1,249 @@ +/*************************************************************************** + * + * + * Copyright(c) 2015,2016 Intel Corporation. + * Copyright(c) 2017 PHYTEC Messtechnik GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/** + * @file + * @brief useful constants and macros for the USB application + * + * This file contains useful constants and macros for the USB applications. + */ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BCD(x) ((((x) / 10) << 4) | ((x) / 10)) + +/* Descriptor size in bytes */ +#define USB_DEVICE_DESC_SIZE 18 +#define USB_CONFIGURATION_DESC_SIZE 9 +#define USB_INTERFACE_DESC_SIZE 9 +#define USB_ENDPOINT_DESC_SIZE 7 +#define USB_STRING_DESC_SIZE 4 +#define USB_HID_DESC_SIZE 9 +#define USB_DFU_DESC_SIZE 9 +#define USB_DEVICE_QUAL_DESC_SIZE 10 +#define USB_INTERFACE_ASSOC_DESC_SIZE 8 + +/* Descriptor type */ +#define USB_DEVICE_DESC 0x01 +#define USB_CONFIGURATION_DESC 0x02 +#define USB_STRING_DESC 0x03 +#define USB_INTERFACE_DESC 0x04 +#define USB_ENDPOINT_DESC 0x05 +#define USB_DEVICE_QUAL_DESC 0x06 +#define USB_INTERFACE_ASSOC_DESC 0x0B +#define USB_DEVICE_CAPABILITY_DESC 0x10 +#define USB_HID_DESC 0x21 +#define USB_HID_REPORT_DESC 0x22 +#define USB_DFU_FUNCTIONAL_DESC 0x21 +#define USB_ASSOCIATION_DESC 0x0B +#define USB_BINARY_OBJECT_STORE_DESC 0x0F + +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 + +#define BCDDEVICE_RELNUM (BCD(KERNEL_VERSION_MAJOR) << 8 | \ + BCD(KERNEL_VERSION_MINOR)) + +/* 100mA max power, per 2mA units */ +/* USB 1.1 spec indicates 100mA(max) per unit load, up to 5 loads */ +#define MAX_LOW_POWER 0x32 +#define MAX_HIGH_POWER 0xFA + +/* bmAttributes: + * D7:Reserved, always 1, + * D6:Self-Powered -> 1, + * D5:Remote Wakeup -> 0, + * D4...0:Reserved -> 0 + */ +#define USB_CONFIGURATION_ATTRIBUTES 0xC0 + +/* Classes */ +#define COMMUNICATION_DEVICE_CLASS 0x02 +#define COMMUNICATION_DEVICE_CLASS_DATA 0x0A +#define HID_CLASS 0x03 +#define MASS_STORAGE_CLASS 0x08 +#define WIRELESS_DEVICE_CLASS 0xE0 +#define MISC_CLASS 0xEF +#define CUSTOM_CLASS 0xFF +#define DFU_DEVICE_CLASS 0xFE + +/* Sub-classes */ +#define CDC_NCM_SUBCLASS 0x0d +#define BOOT_INTERFACE_SUBCLASS 0x01 +#define SCSI_TRANSPARENT_SUBCLASS 0x06 +#define DFU_INTERFACE_SUBCLASS 0x01 +#define RF_SUBCLASS 0x01 +#define CUSTOM_SUBCLASS 0xFF +#define COMMON_SUBCLASS 0x02 +/* Misc subclasses */ +#define MISC_RNDIS_SUBCLASS 0x04 +#define CDC_ABSTRACT_CONTROL_MODEL 0x02 + +/* Protocols */ +#define V25TER_PROTOCOL 0x01 +#define MOUSE_PROTOCOL 0x02 +#define BULK_ONLY_PROTOCOL 0x50 +#define DFU_RUNTIME_PROTOCOL 0x01 +#define DFU_MODE_PROTOCOL 0x02 +#define BLUETOOTH_PROTOCOL 0x01 +/* CDC ACM protocols */ +#define ACM_VENDOR_PROTOCOL 0xFF +/* Misc protocols */ +#define MISC_ETHERNET_PROTOCOL 0x01 +#define IAD_PROTOCOL 0x01 + +/** Standard Device Descriptor */ +struct usb_device_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __packed; + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __packed; + +/** Association Descriptor */ +struct usb_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __packed; + +/** Standard Configuration Descriptor */ +struct usb_cfg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __packed; + +/** Standard Interface Descriptor */ +struct usb_if_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} __packed; + +/** Standard Endpoint Descriptor */ +struct usb_ep_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} __packed; + +struct string_descriptor_zero { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wBcdLang[]; +} __packed; + +struct string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString[]; +} __packed; + +#define ROM_MAX_CFG_DESC_CNT 1 + +struct rom_usb_descriptors { + const struct usb_device_descriptor *device_descr; + const void *config_descr[ROM_MAX_CFG_DESC_CNT]; + int string_count; // including string_descriptor_zero + const struct string_descriptor_zero *string0_descr; + const struct string_descriptor *string_descrs[]; +}; + +/* Descriptors defined in the ROM */ +extern struct usb_device_descriptor general_device_descr; +extern const void* acm_config_descr; +extern const void* dfu_config_descr; +extern const struct string_descriptor str_manu_descr; +extern const struct string_descriptor str_prod_descr; +extern const struct string_descriptor_zero string0_descr; +extern const struct rom_usb_descriptors acm_usb_descriptors; +extern const struct rom_usb_descriptors dfu_usb_descriptors; +extern const struct rom_usb_descriptors *rom_usb_curr_desc; + +/* ROM patch: set the ACM descriptor with the correct serial number. + * Only needed on ESP32-S2, on later chips the ROM descriptor is correct. + */ +void rom_usb_cdc_set_descriptor_patch(void); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_dc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_dc.h new file mode 100644 index 00000000..f20e897c --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_dc.h @@ -0,0 +1,392 @@ +/* usb_dc.h - USB device controller driver interface */ + +/* + * Copyright (c) 2016 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief USB device controller APIs + * + * This file contains the USB device controller APIs. All device controller + * drivers should implement the APIs described in this file. + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * USB endpoint direction and number. + */ + +#define USB_EP_DIR_MASK 0x80 +#define USB_EP_DIR_IN 0x80 +#define USB_EP_DIR_OUT 0x00 + +/** + * USB Driver Status Codes + */ +enum usb_dc_status_code { + USB_DC_ERROR, /* USB error reported by the controller */ + USB_DC_RESET, /* USB reset */ + /* USB connection established, hardware enumeration is completed */ + USB_DC_CONNECTED, + USB_DC_CONFIGURED, /* USB configuration done */ + USB_DC_DISCONNECTED, /* USB connection lost */ + USB_DC_SUSPEND, /* USB connection suspended by the HOST */ + USB_DC_RESUME, /* USB connection resumed by the HOST */ + USB_DC_INTERFACE, /* USB interface selected */ + USB_DC_SET_HALT, /* Set Feature ENDPOINT_HALT received */ + USB_DC_CLEAR_HALT, /* Clear Feature ENDPOINT_HALT received */ + USB_DC_UNKNOWN /* Initial USB connection status */ +}; + +/** + * USB Endpoint Callback Status Codes + */ +enum usb_dc_ep_cb_status_code { + USB_DC_EP_SETUP, /* SETUP received */ + /* Out transaction on this EP, data is available for read */ + USB_DC_EP_DATA_OUT, + USB_DC_EP_DATA_IN, /* In transaction done on this EP */ +}; + +/** + * USB Endpoint type + */ +enum usb_dc_ep_type { + USB_DC_EP_CONTROL = 0, /* Control type endpoint */ + USB_DC_EP_ISOCHRONOUS, /* Isochronous type endpoint */ + USB_DC_EP_BULK, /* Bulk type endpoint */ + USB_DC_EP_INTERRUPT /* Interrupt type endpoint */ +}; + +/** + * USB Endpoint Configuration. + */ +struct usb_dc_ep_cfg_data { + /** The number associated with the EP in the device + * configuration structure + * IN EP = 0x80 | \ + * OUT EP = 0x00 | \ + */ + uint8_t ep_addr; + uint16_t ep_mps; /** Endpoint max packet size */ + enum usb_dc_ep_type ep_type; /** Endpoint type */ +}; + +/** + * Callback function signature for the USB Endpoint status + */ +typedef void (*usb_dc_ep_callback)(uint8_t ep, + enum usb_dc_ep_cb_status_code cb_status); + +/** + * Callback function signature for the device + */ +typedef void (*usb_dc_status_callback)(enum usb_dc_status_code cb_status, + uint8_t *param); + +/** + * @brief attach USB for device connection + * + * Function to attach USB for device connection. Upon success, the USB PLL + * is enabled, and the USB device is now capable of transmitting and receiving + * on the USB bus and of generating interrupts. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_attach(void); + +/** + * @brief detach the USB device + * + * Function to detach the USB device. Upon success, the USB hardware PLL + * is powered down and USB communication is disabled. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_detach(void); + +/** + * @brief reset the USB device + * + * This function returns the USB device and firmware back to it's initial state. + * N.B. the USB PLL is handled by the usb_detach function + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_reset(void); + +/** + * @brief set USB device address + * + * @param[in] addr device address + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_set_address(const uint8_t addr); + +/** + * @brief set USB device controller status callback + * + * Function to set USB device controller status callback. The registered + * callback is used to report changes in the status of the device controller. + * + * @param[in] cb callback function + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_set_status_callback(const usb_dc_status_callback cb); + +/** + * @brief check endpoint capabilities + * + * Function to check capabilities of an endpoint. usb_dc_ep_cfg_data structure + * provides the endpoint configuration parameters: endpoint address, + * endpoint maximum packet size and endpoint type. + * The driver should check endpoint capabilities and return 0 if the + * endpoint configuration is possible. + * + * @param[in] cfg Endpoint config + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data *const cfg); + +/** + * @brief configure endpoint + * + * Function to configure an endpoint. usb_dc_ep_cfg_data structure provides + * the endpoint configuration parameters: endpoint address, endpoint maximum + * packet size and endpoint type. + * + * @param[in] cfg Endpoint config + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg); + +/** + * @brief set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_set_stall(const uint8_t ep); + +/** + * @brief clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_clear_stall(const uint8_t ep); + +/** + * @brief check if selected endpoint is stalled + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[out] stalled Endpoint stall status + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled); + +/** + * @brief halt the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_halt(const uint8_t ep); + +/** + * @brief enable the selected endpoint + * + * Function to enable the selected endpoint. Upon success interrupts are + * enabled for the corresponding endpoint and the endpoint is ready for + * transmitting/receiving data. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_enable(const uint8_t ep); + +/** + * @brief disable the selected endpoint + * + * Function to disable the selected endpoint. Upon success interrupts are + * disabled for the corresponding endpoint and the endpoint is no longer able + * for transmitting/receiving data. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_disable(const uint8_t ep); + +/** + * @brief flush the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_flush(const uint8_t ep); + +/** + * @brief write data to the specified endpoint + * + * This function is called to write data to the specified endpoint. The supplied + * usb_ep_callback function will be called when data is transmitted out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data to write + * @param[in] data_len length of data requested to write. This may + * be zero for a zero length status packet. + * @param[out] ret_bytes bytes scheduled for transmission. This value + * may be NULL if the application expects all + * bytes to be written + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data, + const uint32_t data_len, uint32_t *const ret_bytes); + + + +/** + * @brief Indicate if the write to an IN endpoint (using usb_dc_ep_write) would block + * to wait until the endpoint has enoug space + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 when writable, 0 when not, negative errno code on fail. + */ +int usb_dc_ep_write_would_block(const uint8_t ep); + + +/** + * @brief read data from the specified endpoint + * + * This function is called by the Endpoint handler function, after an OUT + * interrupt has been received for that EP. The application must only call this + * function through the supplied usb_ep_callback function. This function clears + * the ENDPOINT NAK, if all data in the endpoint FIFO has been read, + * so as to accept more data from host. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read(const uint8_t ep, uint8_t *const data, + const uint32_t max_data_len, uint32_t *const read_bytes); + +/** + * @brief set callback function for the specified endpoint + * + * Function to set callback function for notification of data received and + * available to application or transmit done on the selected endpoint, + * NULL if callback not required by application code. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] cb callback function + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb); + +/** + * @brief read data from the specified endpoint + * + * This is similar to usb_dc_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_dc_ep_read_continue() do so. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len, + uint32_t *read_bytes); + + +/** + * @brief Continue reading data from the endpoint + * + * Clear the endpoint NAK and enable the endpoint to accept more data + * from the host. Usually called after usb_dc_ep_read_wait() when the consumer + * is fine to accept more data. Thus these calls together acts as flow control + * mechanism. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read_continue(uint8_t ep); + +/** + * @brief Get endpoint max packet size + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return enpoint max packet size (mps) + */ +int usb_dc_ep_mps(uint8_t ep); + + + +//Hack - fake interrupts by pollinfg +void usb_dc_check_poll_for_interrupts(void); + + +//Prepare for USB persist. You should reboot after this. +int usb_dc_prepare_persist(void); + + +void usb_dw_isr_handler(void); + + +int usb_dc_ep_write_would_block(const uint8_t ep); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_descriptor.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_descriptor.h new file mode 100644 index 00000000..942a1968 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_descriptor.h @@ -0,0 +1,34 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define USB_DESCRIPTOR_TYPE_ACM 0 +#define USB_DESCRIPTOR_TYPE_DFU 1 + +void usb_set_current_descriptor(int descriptor_type); + +bool usb_get_descriptor(uint16_t type_index, uint16_t lang_id, + int32_t *len, uint8_t **data); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_device.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_device.h new file mode 100644 index 00000000..51801b5d --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_device.h @@ -0,0 +1,402 @@ +/* + * LPCUSB, an USB device driver for LPC microcontrollers + * Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl) + * Copyright (c) 2016 Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file + * @brief USB device core layer APIs and structures + * + * This file contains the USB device core layer APIs and structures. + */ + +#pragma once + +#include +#include +#include "usb_dc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************************************************************* + * USB configuration + **************************************************************************/ + +#define MAX_PACKET_SIZE0 64 /**< maximum packet size for EP 0 */ +//Note: for FS this should be 8, 16, 32, 64 bytes. HS can go up to 512. + +/************************************************************************* + * USB application interface + **************************************************************************/ + +/** setup packet definitions */ +struct usb_setup_packet { + uint8_t bmRequestType; /**< characteristics of the specific request */ + uint8_t bRequest; /**< specific request */ + uint16_t wValue; /**< request specific parameter */ + uint16_t wIndex; /**< request specific parameter */ + uint16_t wLength; /**< length of data transferred in data phase */ +} __packed; + + +_Static_assert(sizeof(struct usb_setup_packet) == 8, "USB setup packet struct size error"); + +/** + * Callback function signature for the device + */ +typedef void (*usb_status_callback)(enum usb_dc_status_code status_code, + uint8_t *param); + +/** + * Callback function signature for the USB Endpoint status + */ +typedef void (*usb_ep_callback)(uint8_t ep, + enum usb_dc_ep_cb_status_code cb_status); + +/** + * Function which handles Class specific requests corresponding to an + * interface number specified in the device descriptor table + */ +typedef int (*usb_request_handler) (struct usb_setup_packet *detup, + int32_t *transfer_len, uint8_t **payload_data); + +/** + * Function for interface runtime configuration + */ +typedef void (*usb_interface_config)(uint8_t bInterfaceNumber); + +/* + * USB Endpoint Configuration + */ +struct usb_ep_cfg_data { + /** + * Callback function for notification of data received and + * available to application or transmit done, NULL if callback + * not required by application code + */ + usb_ep_callback ep_cb; + /** + * The number associated with the EP in the device configuration + * structure + * IN EP = 0x80 | \ + * OUT EP = 0x00 | \ + */ + uint8_t ep_addr; +}; + +/** + * USB Interface Configuration + */ +struct usb_interface_cfg_data { + /** Handler for USB Class specific Control (EP 0) communications */ + usb_request_handler class_handler; + /** Handler for USB Vendor specific commands */ + usb_request_handler vendor_handler; + /** + * The custom request handler gets a first chance at handling + * the request before it is handed over to the 'chapter 9' request + * handler + */ + usb_request_handler custom_handler; + /** + * This data area, allocated by the application, is used to store + * Class specific command data and must be large enough to store the + * largest payload associated with the largest supported Class' + * command set. This data area may be used for USB IN or OUT + * communications + */ + uint8_t *payload_data; + /** + * This data area, allocated by the application, is used to store + * Vendor specific payload + */ + uint8_t *vendor_data; +}; + +/* + * @brief USB device configuration + * + * The Application instantiates this with given parameters added + * using the "usb_set_config" function. Once this function is called + * changes to this structure will result in undefined behaviour. This structure + * may only be updated after calls to usb_deconfig + */ +struct usb_cfg_data { + /** + * USB device description, see + * http://www.beyondlogic.org/usbnutshell/usb5.shtml#DeviceDescriptors + */ + const uint8_t *usb_device_description; + /** Pointer to interface descriptor */ + const void *interface_descriptor; + /** Function for interface runtime configuration */ + usb_interface_config interface_config; + /** Callback to be notified on USB connection status change */ + usb_status_callback cb_usb_status; + /** USB interface (Class) handler and storage space */ + struct usb_interface_cfg_data interface; + /** Number of individual endpoints in the device configuration */ + uint8_t num_endpoints; + /** + * Pointer to an array of endpoint structs of length equal to the + * number of EP associated with the device description, + * not including control endpoints + */ + struct usb_ep_cfg_data *endpoint; +}; + +/* + * @brief configure USB controller + * + * Function to configure USB controller. + * Configuration parameters must be valid or an error is returned + * + * @param[in] config Pointer to configuration structure + * + * @return 0 on success, negative errno code on fail + */ +int usb_set_config(struct usb_cfg_data *config); + +/* + * @brief return the USB device to it's initial state + * + * @return 0 on success, negative errno code on fail + */ +int usb_deconfig(void); + +/* + * @brief enable USB for host/device connection + * + * Function to enable USB for host/device connection. + * Upon success, the USB module is no longer clock gated in hardware, + * it is now capable of transmitting and receiving on the USB bus and + * of generating interrupts. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_enable(struct usb_cfg_data *config); + +/* + * @brief disable the USB device. + * + * Function to disable the USB device. + * Upon success, the specified USB interface is clock gated in hardware, + * it is no longer capable of generating interrupts. + * + * @return 0 on success, negative errno code on fail + */ +int usb_disable(void); + +/* + * @brief Check if a write to an in ep would block until there is enough space + * in the fifo + * + * @param[in] ep Endpoint address corresponding to the one listed in the + * device configuration table + * + * @return 0 if free to write, 1 if a write would block, negative errno code on fail + */ +int usb_write_would_block(uint8_t ep); + +/* + * @brief write data to the specified endpoint + * + * Function to write data to the specified endpoint. The supplied + * usb_ep_callback will be called when transmission is done. + * + * @param[in] ep Endpoint address corresponding to the one listed in the + * device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of data requested to write. This may be zero for + * a zero length status packet. + * @param[out] bytes_ret Bytes written to the EP FIFO. This value may be NULL if + * the application expects all bytes to be written + * + * @return 0 on success, negative errno code on fail + */ +int usb_write(uint8_t ep, const uint8_t *data, uint32_t data_len, + uint32_t *bytes_ret); + +/* + * @brief read data from the specified endpoint + * + * This function is called by the Endpoint handler function, after an + * OUT interrupt has been received for that EP. The application must + * only call this function through the supplied usb_ep_callback function. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * @param[in] data Pointer to data buffer to write to + * @param[in] max_data_len Max length of data to read + * @param[out] ret_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes available + * for read is returned. + * + * @return 0 on success, negative errno code on fail + */ +int usb_read(uint8_t ep, uint8_t *data, uint32_t max_data_len, + uint32_t *ret_bytes); + +/* + * @brief set STALL condition on the specified endpoint + * + * This function is called by USB device class handler code to set stall + * conditionin on endpoint. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * + * @return 0 on success, negative errno code on fail + */ +int usb_ep_set_stall(uint8_t ep); + + +/* + * @brief clears STALL condition on the specified endpoint + * + * This function is called by USB device class handler code to clear stall + * conditionin on endpoint. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * + * @return 0 on success, negative errno code on fail + */ +int usb_ep_clear_stall(uint8_t ep); + +/** + * @brief read data from the specified endpoint + * + * This is similar to usb_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_ep_read_continue() do so. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len, + uint32_t *read_bytes); + + +/** + * @brief Continue reading data from the endpoint + * + * Clear the endpoint NAK and enable the endpoint to accept more data + * from the host. Usually called after usb_ep_read_wait() when the consumer + * is fine to accept more data. Thus these calls together acts as flow control + * mechanism. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_ep_read_continue(uint8_t ep); + +/** + * Callback function signature for transfer completion. + */ +typedef void (*usb_transfer_callback)(uint8_t ep, int tsize, void *priv); + +/* USB transfer flags */ +#define USB_TRANS_READ BIT(0) /** Read transfer flag */ +#define USB_TRANS_WRITE BIT(1) /** Write transfer flag */ +#define USB_TRANS_NO_ZLP BIT(2) /** No zero-length packet flag */ + +/** + * @brief Transfer management endpoint callback + * + * If a USB class driver wants to use high-level transfer functions, driver + * needs to register this callback as usb endpoint callback. + */ +void usb_transfer_ep_callback(uint8_t ep, enum usb_dc_ep_cb_status_code); + +/** + * @brief Start a transfer + * + * Start a usb transfer to/from the data buffer. This function is asynchronous + * and can be executed in IRQ context. The provided callback will be called + * on transfer completion (or error) in thread context. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write-to/read-from + * @param[in] dlen Size of data buffer + * @param[in] flags Transfer flags (USB_TRANS_READ, USB_TRANS_WRITE...) + * @param[in] cb Function called on transfer completion/failure + * @param[in] priv Data passed back to the transfer completion callback + * + * @return 0 on success, negative errno code on fail. + */ +int usb_transfer(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags, + usb_transfer_callback cb, void *priv); + +/** + * @brief Start a transfer and block-wait for completion + * + * Synchronous version of usb_transfer, wait for transfer completion before + * returning. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write-to/read-from + * @param[in] dlen Size of data buffer + * @param[in] flags Transfer flags + + * + * @return number of bytes transferred on success, negative errno code on fail. + */ +int usb_transfer_sync(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags); + +/** + * @brief Cancel any ongoing transfer on the specified endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +void usb_cancel_transfer(uint8_t ep); + + +void usb_dev_resume(int configuration); +int usb_dev_get_configuration(void); + + +#ifdef __cplusplus +} +#endif + diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_dfu.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_dfu.h new file mode 100644 index 00000000..dec7ea93 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_dfu.h @@ -0,0 +1,147 @@ +/*************************************************************************** + * + * Copyright(c) 2015,2016 Intel Corporation. + * Copyright(c) 2017 PHYTEC Messtechnik GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/** + * @file + * @brief USB Device Firmware Upgrade (DFU) public header + * + * Header follows the Device Class Specification for + * Device Firmware Upgrade Version 1.1 + */ + +#pragma once + +#include +#include +#include "usb_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** DFU Class Subclass */ +#define DFU_SUBCLASS 0x01 + +/** DFU Class runtime Protocol */ +#define DFU_RT_PROTOCOL 0x01 + +/** DFU Class DFU mode Protocol */ +#define DFU_MODE_PROTOCOL 0x02 + +/** + * @brief DFU Class Specific Requests + */ +#define DFU_DETACH 0x00 +#define DFU_DNLOAD 0x01 +#define DFU_UPLOAD 0x02 +#define DFU_GETSTATUS 0x03 +#define DFU_CLRSTATUS 0x04 +#define DFU_GETSTATE 0x05 +#define DFU_ABORT 0x06 + +/** DFU FUNCTIONAL descriptor type */ +#define DFU_FUNC_DESC 0x21 + +/** DFU attributes DFU Functional Descriptor */ +#define DFU_ATTR_WILL_DETACH 0x08 +#define DFU_ATTR_MANIFESTATION_TOLERANT 0x04 +#define DFU_ATTR_CAN_UPLOAD 0x02 +#define DFU_ATTR_CAN_DNLOAD 0x01 + +/** DFU Specification release */ +#define DFU_VERSION 0x0110 + +/** Run-Time Functional Descriptor */ +struct dfu_runtime_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bmAttributes; + uint16_t wDetachTimeOut; + uint16_t wTransferSize; + uint16_t bcdDFUVersion; +} __packed; + +/** bStatus values for the DFU_GETSTATUS response */ +enum dfu_status { + statusOK, + errTARGET, + errFILE, + errWRITE, + errERASE, + errCHECK_ERASED, + errPROG, + errVERIFY, + errADDRESS, + errNOTDONE, + errFIRMWARE, + errVENDOR, + errUSB, + errPOR, + errUNKNOWN, + errSTALLEDPKT +}; + +/** bState values for the DFU_GETSTATUS response */ +enum dfu_state { + appIDLE, + appDETACH, + dfuIDLE, + dfuDNLOAD_SYNC, + dfuDNBUSY, + dfuDNLOAD_IDLE, + dfuMANIFEST_SYNC, + dfuMANIFEST, + dfuMANIFEST_WAIT_RST, + dfuUPLOAD_IDLE, + dfuERROR, +}; + +/* + These callbacks are made public so the ACM driver can call them to handle the switch to DFU. +*/ + +int dfu_class_handle_req(struct usb_setup_packet *pSetup, + int32_t *data_len, uint8_t **data); +void dfu_status_cb(enum usb_dc_status_code status, uint8_t *param); +int usb_dfu_init(void); +int dfu_custom_handle_req(struct usb_setup_packet *pSetup, + int32_t *data_len, uint8_t **data); + + +typedef void(*usb_dfu_detach_routine_t)(int delay); +void usb_dfu_set_detach_cb(usb_dfu_detach_routine_t cb); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h new file mode 100644 index 00000000..74d9b2a7 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h @@ -0,0 +1,40 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef void(*usb_osglue_intdisena_routine_t)(void); +typedef int(*usb_osglue_wait_routine_t)(int delay_us); + +typedef struct { + /* Disable USB interrupt */ + usb_osglue_intdisena_routine_t int_dis_proc; + /* Enable USB interrupt */ + usb_osglue_intdisena_routine_t int_ena_proc; + /* Wait for a set amount of uS. Return the amount actually waited. If delay_us is 0, just yield.*/ + usb_osglue_wait_routine_t wait_proc; +} usb_osglue_data_t; + +extern usb_osglue_data_t rom_usb_osglue; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_persist.h b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_persist.h new file mode 100644 index 00000000..bcf11b7c --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s2/rom/usb/usb_persist.h @@ -0,0 +1,50 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// USB persistence flags. + +//This bit indicates persistence has been enabled, that is, the USB initialization routines should not +//reset the USB device as the device still is initialized and the host detected it with the same cdcacm/dfu +//descriptor as the ROM uses; we can just re-initialize the software side and have at 'er. +#define USBDC_PERSIST_ENA (1<<31) + +//This bit indicates to the ROM that we rebooted because of a request to go into DFU mode; the ROM should +//honour this request. +#define USBDC_BOOT_DFU (1<<30) + + +//This being non-0 indicates a memory location where a 'testament' is stored, aka a piece of text that should be output +//after a reboot. Can contain core dump info or something. +#define USBDC_TESTAMENT_LOC_MASK 0x7FFFF //bits 19-0; this is added to a base address of 0x3FF80000. + +//The testament is a FIFO. The ROM will output all data between textstart and textend; if textend is lower than textstart it will +//output everything from textstart to memend, then memstart to textend. +typedef struct { + char *memstart; //start of memory region + char *memend; //end of memory region + char *textstart; //start of text to output + char *textend; +} usbdc_testament_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h new file mode 100644 index 00000000..432c65ef --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/aes.h @@ -0,0 +1,55 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AES_BLOCK_SIZE (16) + +enum AES_TYPE { + AES_ENC, + AES_DEC, +}; + +enum AES_BITS { + AES128, + AES192, + AES256 +}; + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, + bool in_word_swap, bool in_byte_swap, + bool out_word_swap, bool out_byte_swap); + +int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); + +int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); + +int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); + +void ets_aes_block(const void *input, void *output); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/usb_persist.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/bigint.h similarity index 50% rename from tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/usb_persist.h rename to tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/bigint.h index 4527663c..2ab022d8 100644 --- a/tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/usb_persist.h +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/bigint.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -14,44 +14,26 @@ #pragma once +#include #include #ifdef __cplusplus extern "C" { #endif -/* - * USB Persistence API - * */ -typedef enum { - RESTART_NO_PERSIST, - RESTART_PERSIST, - RESTART_BOOTLOADER, - RESTART_BOOTLOADER_DFU, - RESTART_TYPE_MAX -} restart_type_t; +void ets_bigint_enable(void); -/* - * Init Persistence reboot system - * */ -void usb_persist_init(void); +void ets_bigint_disable(void); -/* - * Enable Persistence reboot - * - * Note: Persistence should be enabled when ONLY CDC and DFU are being used - * */ -void usb_persist_set_enable(bool enable); +int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); -/* - * Set Reboot mode. Call before esp_reboot(); - * */ -void usb_persist_restart(restart_type_t mode); +int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); -/* - * Check if last boot was persistent - * */ -bool usb_persist_this_boot(void); +int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); + +void ets_bigint_wait_finish(void); + +int ets_bigint_getz(uint32_t *z, uint32_t len_words); #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/cache.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/cache.h new file mode 100644 index 00000000..0ec6308f --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/cache.h @@ -0,0 +1,1097 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 32768 +#define MIN_DCACHE_SIZE 32768 +#define MAX_DCACHE_SIZE 65536 +#define MIN_ICACHE_WAYS 4 +#define MAX_ICACHE_WAYS 8 +#define MIN_DCACHE_WAYS 4 +#define MAX_DCACHE_WAYS 4 +#define MAX_CACHE_WAYS 8 +#define MIN_CACHE_LINE_SIZE 16 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 2 +#define MIN_DCACHE_BANK_NUM 1 +#define MAX_DCACHE_BANK_NUM 2 +#define CACHE_MEMORY_BANK_NUM 4 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 +#define CACHE_MEMORY_DBANK_SIZE 0x8000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) +#define MAX_DTAG_BANK_ITEMS (MAX_DCACHE_SIZE / MAX_DCACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_DTAG_BLOCK_ITEMS (MAX_DCACHE_SIZE / MAX_DCACHE_BANK_NUM / MAX_DCACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_DTAG_BANK_SIZE (MAX_DTAG_BANK_ITEMS * TAG_SIZE) +#define MAX_DTAG_BLOCK_SIZE (MAX_DTAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_DCACHE = 0, + CACHE_ICACHE0 = 1, + CACHE_ICACHE1 = 2, +} cache_t; + +typedef enum { + CACHE_MEMORY_INVALID = 0, + CACHE_MEMORY_IBANK0 = BIT(0), + CACHE_MEMORY_IBANK1 = BIT(1), + CACHE_MEMORY_IBANK2 = BIT(2), + CACHE_MEMORY_IBANK3 = BIT(3), + CACHE_MEMORY_DBANK0 = BIT(0), + CACHE_MEMORY_DBANK1 = BIT(1), + CACHE_MEMORY_DBANK2 = BIT(2), + CACHE_MEMORY_DBANK3 = BIT(3), +} cache_array_t; + +#define ICACHE_SIZE_16KB CACHE_SIZE_HALF +#define ICACHE_SIZE_32KB CACHE_SIZE_FULL +#define DCACHE_SIZE_32KB CACHE_SIZE_HALF +#define DCACHE_SIZE_64KB CACHE_SIZE_FULL + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid: 1; /*!< the tag item is valid or not */ + uint32_t lock: 1; /*!< the cache line is locked or not */ + uint32_t attr: 4; /*!< the attribute of the external memory physical address */ + uint32_t fifo_cnt: 3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag: 14; /*!< the tag is the high part of the cache address, however is only 64MB range, and without low part */ + uint32_t reserved: 9; +}; + +struct dcache_tag_item { + uint32_t dirty: 1; /*!< the cache line value is dirty or not */ + uint32_t valid: 1; /*!< the tag item is valid or not */ + uint32_t lock: 1; /*!< the cache line is locked or not */ + uint32_t occupy: 1; /*!< the cache line is occupied as internal sram */ + uint32_t attr: 4; /*!< the attribute of the external memory physical address */ + uint32_t fifo_cnt: 2; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag: 13; /*!< the tag is the high part of the cache address, however is only 64MB range, and without low part */ + uint32_t reserved: 9; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Count the pages in the bus room address which map to Flash. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus to count with. + * + * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. + * + * return uint32_t : the number of pages which map to Flash. + */ +uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t *page0_mapped); + +/** + * @brief Copy Instruction or rodata from Flash to SPIRAM, and remap to SPIRAM. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus which need to copy to SPIRAM. + * + * @param uint32_t bus_start_addr : the start virtual address for the bus. + * + * @param uint32_t start_page : the start (64KB) page number in SPIRAM. + * + * @param uint32_t * page0_page : the flash page0 in SPIRAM page number, 0xffff for invalid. + * + * return uint32_t : the next start page number for SPIRAM not mapped. + */ +uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus, uint32_t bus_start_addr, uint32_t start_page, uint32_t *page0_page); + +/** + * @brief allocate memory to used by ICache. + * Please do not call this function in your SDK application. + * + * @param cache_array_t icache_low : the data array bank used by icache low part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1 + * + * @param cache_array_t icache_high : the data array bank used by icache high part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1 only if icache_low and icache_high is not CACHE_MEMORY_INVALID + * + * return none + */ +void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low, cache_array_t icache_high); + +/** + * @brief allocate memory to used by DCache. + * Please do not call this function in your SDK application. + * + * @param cache_array_t dcache_low : the data array bank used by dcache low part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1 + * + * @param cache_array_t dcache1_high : the data array bank used by dcache high part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1 only if dcache_low0 and dcache_low1 is not CACHE_MEMORY_INVALID + * + * return none + */ +void Cache_Occupy_DCache_MEMORY(cache_array_t dcache_low, cache_array_t dcache_high); + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode *mode); + +/** + * @brief set ICache modes: cache size, associate ways and cache line size. + * Please do not call this function in your SDK application. + * + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL + * + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B + * + * return none + */ +void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); + +/** + * @brief set DCache modes: cache size, associate ways and cache line size. + * Please do not call this function in your SDK application. + * + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB + * + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B + * + * return none + */ +void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); + +/** + * @brief check if the address is accessed through ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through ICache, 0 if not. + */ +uint32_t Cache_Address_Through_ICache(uint32_t addr); + +/** + * @brief check if the address is accessed through DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through DCache, 0 if not. + */ +uint32_t Cache_Address_Through_DCache(uint32_t addr); + +/** + * @brief Init mmu owner register to make i/d cache use half mmu entries. + * + * @param None + * + * @return None + */ +void Cache_Owner_Init(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Clean the dirty bit of cache Items of DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to Clean + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Clean_Items(uint32_t addr, uint32_t items); + +/** + * @brief Write back the cache items of DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to write back + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_WriteBack_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Clean the dirty bit of Cache items in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : cleaned region start address. + * + * @param uint32_t size : cleaned region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Clean_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Writeback the Cache items(also clean the dirty bit) in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : writeback region start address. + * + * @param uint32_t size : writeback region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_WriteBack_Addr(uint32_t addr, uint32_t size); + + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_ICache_All(void); + +/** + * @brief Invalidate all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_DCache_All(void); + +/** + * @brief Clean the dirty bit of all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Clean_All(void); + +/** + * @brief WriteBack all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_WriteBack_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief UnMask DRam0 bus through DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_UnMask_Dram0(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_ICache_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_ICache_Autoload(uint32_t autoload); + +/** + * @brief Suspend DCache auto preload operation, then you can resume it after some DCache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for DCache not auto preload before suspend. + */ +uint32_t Cache_Suspend_DCache_Autoload(void); + +/** + * @brief Resume DCache auto preload operation after some DCache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for DCache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_DCache_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_ICache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_ICache_Preload(uint32_t autoload); + +/** + * @brief Start an DCache manual preload, will suspend auto preload of DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of DCache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for DCache not auto preload before manual preload. + */ +uint32_t Cache_Start_DCache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the DCache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for DCache manual preload not done. + */ +uint32_t Cache_DCache_Preload_Done(void); + +/** + * @brief End the DCache manual preload to resume auto preload of DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for DCache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_DCache_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_ICache_Autoload(const struct autoload_config *config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_ICache_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_ICache_Autoload(void); + +/** + * @brief Config autoload parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_DCache_Autoload(const struct autoload_config *config); + +/** + * @brief Enable auto preload for DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_DCache_Autoload(void); + +/** + * @brief Disable auto preload for DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_DCache_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_ICache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Config a group of prelock parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ +void Cache_Enable_DCache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for DCache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_DCache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_ICache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_ICache(uint32_t autoload); + +/** + * @brief Disable DCache access for the cpu. + * This operation will make all DCache tag memory invalid, CPU can't access DCache, DCache will keep idle + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_DCache(void); + +/** + * @brief Enable DCache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : DCache will preload then. + * + * @return None + */ +void Cache_Enable_DCache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_ICache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_ICache(uint32_t autoload); + +/** + * @brief Suspend DCache access for the cpu. + * The ICache tag memory is still there, CPU can't access DCache, DCache will keep idle. + × Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_DCache(void); + +/** + * @brief Resume DCache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : DCache will preload then. + * + * @return None + */ +void Cache_Resume_DCache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_ICache_Line_Size(void); + +/** + * @brief Get DCache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_DCache_Line_Size(void); + +/** + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +void Cache_Set_Default_Mode(void); + +/** + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +void Cache_Enable_Defalut_ICache_Mode(void); + +/** + * @brief Occupy the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of occupy region + * + * @param uint32_t items : cache lines to occupy, items * cache_line_size should not exceed the cache_size + * + * @return None + */ +void Cache_Occupy_Items(uint32_t addr, uint32_t items); + +/** + * @brief Occupy the cache addr for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of occupy region + * + * @param uint32_t size : size of occupy region, size should not exceed the cache_size + */ +int Cache_Occupy_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_ICache_Disable(void); + +/** + * @brief Enable freeze for DCache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for DCache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_DCache_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode *mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @brief Get cache memory block base address. + * Please do not call this function in your SDK application. + * + * @param uint32_t icache : 0 for dcache, other for icache. + * + * @param uint32_t bank_no : 0 ~ 3 bank. + * + * @return uint32_t : the cache memory block base address, 0 if the block not used. + */ +uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no); + +/** + * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); + +/** + * @brief Get the cache memory value by DRAM address. + * Please do not call this function in your SDK application. + * + * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Used by SPI flash mmap + * + */ +int flash2spiram_instruction_offset(void); +int flash2spiram_rodata_offset(void); +uint32_t flash_instr_rodata_start_page(uint32_t bus); +uint32_t flash_instr_rodata_end_page(uint32_t bus); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/crc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/crc.h new file mode 100644 index 00000000..e47a2ff5 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/crc.h @@ -0,0 +1,122 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup crc_apis, uart configuration and communication related apis + * @brief crc apis + */ + +/** @addtogroup crc_apis + * @{ + */ + +/* Standard CRC8/16/32 algorithms. */ +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/digital_signature.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/digital_signature.h new file mode 100644 index 00000000..36e71e7c --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/digital_signature.h @@ -0,0 +1,142 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ETS_DS_IV_LEN 16 + +/* Length of parameter 'C' stored in flash */ +#define ETS_DS_C_LEN (12672 / 8) + +/* Encrypted ETS data. Recommended to store in flash in this format. + */ +typedef struct { + /* RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * Max value 127 (for RSA 4096). + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + */ + unsigned rsa_length; + + /* IV value used to encrypt 'c' */ + uint8_t iv[ETS_DS_IV_LEN]; + + /* Encrypted Digital Signature parameters. Result of AES-CBC encryption + of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ETS_DS_C_LEN]; +} ets_ds_data_t; + +typedef enum { + ETS_DS_OK, + ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ + ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ + ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ + ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ +} ets_ds_result_t; + +void ets_ds_enable(void); + +void ets_ds_disable(void); + +/* + * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral + * + * - @param message Pointer to message (or padded digest) containing the message to sign. Should be + * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data + * in flash. + * + * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling + * this function, and is responsible for calling ets_ds_finish_sign() and then + * ets_hmac_invalidate_downstream() afterwards. + * + * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, + * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. + */ +ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); + + +/* + * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() + * + * A result of false indicates that a call to ets_ds_finish_sign() will not block. + * + * Only valid if ets_ds_enable() has been called. + */ +bool ets_ds_is_busy(void); + + +/* @brief Finish signing a message using the Digital Signature peripheral + * + * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until + * peripheral is no longer busy. + * + * - @param signature Pointer to buffer to contain the signature. Should be + * (data->rsa_length + 1)*4 bytes long. + * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() + * + * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, + * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the + * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a + * digest is produced anyhow.) + */ +ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); + + +/* Plaintext parameters used by Digital Signature. + + Not used for signing with DS peripheral, but can be encrypted + in-device by calling ets_ds_encrypt_params() +*/ +typedef struct { + uint32_t Y[4096 / 32]; + uint32_t M[4096 / 32]; + uint32_t Rb[4096 / 32]; + uint32_t M_prime; + uint32_t length; +} ets_ds_p_data_t; + +typedef enum { + ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ + ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ +} ets_ds_key_t; + +/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. + * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) + * + * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. + */ +ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/efuse.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/efuse.h new file mode 100644 index 00000000..cbe38e6a --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/efuse.h @@ -0,0 +1,391 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief set timing accroding the apb clock, so no read error or write error happens. + * + * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. + * + * @return : 0 if success, others if clock not accepted + */ +int ets_efuse_set_timing(uint32_t clock); + +/** + * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. + */ +void ets_efuse_start(void); + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read spi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - 1 for default HSPI pins. + * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, + * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. + */ +uint32_t ets_efuse_get_spiconfig(void); + +/** + * @brief Read spi flash wp pad from Efuse + * + * @return + * - 0x3f for invalid. + * - 0~46 is valid. + */ +uint32_t ets_efuse_get_wp_pad(void); + +/** + * @brief Read opi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: + * DQS, D4, D5, D6, D7 accordingly. + */ +uint32_t ets_efuse_get_opiconfig(void); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if legacy spi flash boot mode disabled from Efuse + * + * @return + * - true for efuse disable legacy spi flash boot mode. + * - false for efuse doesn't disable legacy spi flash boot mode. + */ +bool ets_efuse_legacy_spi_boot_mode_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO46 is low when digital reset. + * 2 for uart print when GPIO46 is high when digital reset. + * 3 for uart force slient + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read which channel will used by ROM to print + * + * @return + * - 0 for UART0. + * - 1 for UART1. + */ +uint32_t ets_efuse_get_uart_print_channel(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if tiny basic mode disabled from Efuse + * + * @return + * - true for efuse disable tiny basic mode. + * - false for efuse doesn't disable tiny basic mode. + */ +bool ets_efuse_tiny_basic_mode_disabled(void); + +/** + * @brief Read if usb module disabled from Efuse + * + * @return + * - true for efuse disable usb module. + * - false for efuse doesn't disable usb module. + */ +bool ets_efuse_usb_module_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, PSRAM, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates an external phy needs to be used for USB + */ +bool ets_efuse_usb_use_ext_phy(void); + +/** + * @brief Return true if EFuse indicates USB device persistence is disabled + */ +bool ets_efuse_usb_force_nopersist(void); + +/** + * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU + */ +bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); + +/** + * @brief Return true if EFuse indicates an opi flash is attached. + */ +bool ets_efuse_flash_opi_mode(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h new file mode 100644 index 00000000..edf9627c --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/ets_sys.h @@ -0,0 +1,654 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1 /**< return failed in ets*/ +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + +/** + * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. + * + * @param none + * + * @return none + */ +void ets_run(void); + +/** + * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. + * + * @param ets_idle_cb_t func : The callback function. + * + * @param void *arg : Argument of the callback. + * + * @return None + */ +void ets_set_idle_cb(ets_idle_cb_t func, void *arg); + +/** + * @brief Init a task with processer, priority, queue to receive Event, queue length. + * + * @param ETSTask task : The task processer. + * + * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. + * + * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. + * + * @param uint8_t qlen : Queue length. + * + * @return None + */ +void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); + +/** + * @brief Post an event to an Task. + * + * @param uint8_t prio : Priority of the Task. + * + * @param ETSSignal sig : Event signal. + * + * @param ETSParam par : Event parameter + * + * @return ETS_OK : post successful + * @return ETS_FAILED : post failed + */ +ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. + * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. + * + * @param uint32_t callback : the Startup code address value in uint32_t + * + * @return None : post successful + */ +void ets_set_startup_callback(uint32_t callback); + +/** + * @brief Set App cpu Entry code, code can be called in PRO CPU. + * When APP booting is completed, APP CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. + * + * @return None + */ +void ets_set_appcpu_boot_addr(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Set the uart channel of ets_printf(uart_tx_one_char). + * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. + * + * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2. + * + * @return None + */ +void ets_set_printf_channel(uint8_t uart_no); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * + * @note This function only sets the tick rate for the current CPU. It is located in ROM, + * so the deep sleep stub can use it even if IRAM is not initialized yet. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if stored in efuse(not 0) + * clock = ets_efuse_get_xtal_freq() * 1000000; + * else if analog_8M in efuse + * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); + * else clock = 40M. + */ +uint32_t ets_get_xtal_freq(void); + +/** + * @brief Get the apb divisor. The xtal frequency gets divided + * by this value to generate the APB clock. + * When any types of reset happens, the default value is 2. + * + * @param None + * + * @return uint32_t : 1 or 2. + */ +uint32_t ets_get_xtal_div(void); + + +/** + * @brief Modifies the apb divisor. The xtal frequency gets divided by this to + * generate the APB clock. + * + * @note The xtal frequency divisor is 2 by default as the glitch detector + * doesn't properly stop glitches when it is 1. Please do not set the + * divisor to 1 before the PLL is active without being aware that you + * may be introducing a security risk. + * + * @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq. + */ +void ets_set_xtal_div(int div); + + +/** + * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. + * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; + * else store ets_get_detected_xtal_freq() in. + */ +uint32_t ets_get_apb_freq(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + +/** + * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_waiti0(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +#define _ETSTR(v) # v +#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ + __asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \ + : "=a" (__tmp) : : "memory" ); \ + }) + +#ifdef CONFIG_NONE_OS +#define ETS_INTR_LOCK() \ + ets_intr_lock() + +#define ETS_INTR_UNLOCK() \ + ets_intr_unlock() + +#define ETS_ISR_ATTACH \ + ets_isr_attach + +#define ETS_INTR_ENABLE(inum) \ + ets_isr_unmask((1< +#include +#include "soc/gpio_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +#define GPIO_FUNC_IN_HIGH 0x38 +#define GPIO_FUNC_IN_LOW 0x3C + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEDGE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + +#define GPIO_OUTPUT_SET(gpio_no, bit_value) \ + ((gpio_no < 32) ? gpio_output_set(bit_value<>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0)) + +/* GPIO interrupt handler, registered through gpio_intr_handler_register */ +typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg); + +/** + * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet + * to initialize "output enables" and pin configurations for each gpio pin. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_init(void); + +/** + * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32. + */ +uint32_t gpio_input_get_high(void); + +/** + * @brief Register an application-specific interrupt handler for GPIO pin interrupts. + * Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack. + * Please do not call this function in SDK. + * + * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler + * + * @param void *arg : gpio application-specific interrupt handler argument. + * + * @return None + */ +void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0. + */ +uint32_t gpio_intr_pending(void); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32. + */ +uint32_t gpio_intr_pending_high(void); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0. + * + * @return None + */ +void gpio_intr_ack(uint32_t ack_mask); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32. + * + * @return None + */ +void gpio_intr_ack_high(uint32_t ack_mask); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x100, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_select_gpio(uint32_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_pullup(uint32_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_pulldown(uint32_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/hmac.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/hmac.h new file mode 100644 index 00000000..ac7ddf35 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/hmac.h @@ -0,0 +1,59 @@ +// Copyright 2018-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "efuse.h" + +void ets_hmac_enable(void); + +void ets_hmac_disable(void); + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/libc_stubs.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/libc_stubs.h new file mode 100644 index 00000000..9c9b0a21 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/libc_stubs.h @@ -0,0 +1,87 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ESP32-S3 ROM code contains implementations of some of C library functions. + * Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall + * implementation defined in the following struct. + * + * The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and + * `syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU) + * and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script. + * + * So, before using any of the C library functions (except for pure functions and memcpy/memset functions), + * application must allocate syscall table structure for each CPU being used, and populate it with pointers + * to actual implementations of corresponding syscalls. + * + */ +struct syscall_stub_table { + struct _reent *(*__getreent)(void); + void *(*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void *); + void *(*_realloc_r)(struct _reent *r, void *, size_t); + void *(*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char *); + int (*_rename_r)(struct _reent *r, const char *, const char *); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char *); + int (*_link_r)(struct _reent *r, const char *, const char *); + int (*_stat_r)(struct _reent *r, const char *, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void *(*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); + void (*_lock_init)(_lock_t *lock); + void (*_lock_init_recursive)(_lock_t *lock); + void (*_lock_close)(_lock_t *lock); + void (*_lock_close_recursive)(_lock_t *lock); + void (*_lock_acquire)(_lock_t *lock); + void (*_lock_acquire_recursive)(_lock_t *lock); + int (*_lock_try_acquire)(_lock_t *lock); + int (*_lock_try_acquire_recursive)(_lock_t *lock); + void (*_lock_release)(_lock_t *lock); + void (*_lock_release_recursive)(_lock_t *lock); + int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); +}; + +extern struct syscall_stub_table *syscall_table_ptr; +#define syscall_table_ptr_pro syscall_table_ptr +#define syscall_table_ptr_app syscall_table_ptr + +#ifdef __cplusplus +} // extern "C" +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/lldesc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/lldesc.h new file mode 100644 index 00000000..ebd02016 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/lldesc.h @@ -0,0 +1,173 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "sys/queue.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LLDESC_TX_MBLK_SIZE 268 /* */ +#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ +#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ +#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ +#ifdef ESP_MAC_5 +#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ +#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 +#else +#ifdef SBUF_RXTX +#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ +#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ +#endif +#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ + +#ifdef IEEE80211_RX_AMPDU +#define LLDESC_RX_MBLK_NUM 30 +#else +#define LLDESC_RX_MBLK_NUM 10 +#endif /*IEEE80211_RX_AMPDU*/ + +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 +#endif /* !ESP_MAC_5 */ +/* + * SLC2 DMA Desc struct, aka lldesc_t + * + * -------------------------------------------------------------- + * | own | EoF | sub_sof | 5'b0 | length [11:0] | size [11:0] | + * -------------------------------------------------------------- + * | buf_ptr [31:0] | + * -------------------------------------------------------------- + * | next_desc_ptr [31:0] | + * -------------------------------------------------------------- + */ + +/* this bitfield is start from the LSB!!! */ +typedef struct lldesc_s { + volatile uint32_t size : 12, + length: 12, + offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */ + sosf : 1, /* start of sub-frame */ + eof : 1, /* end of frame */ + owner : 1; /* hw or sw */ + volatile uint8_t *buf; /* point to buffer data */ + union { + volatile uint32_t empty; + STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */ + }; +} lldesc_t; + +typedef struct tx_ampdu_entry_s { + uint32_t sub_len : 12, + dili_num : 7, + : 1, + null_byte: 2, + data : 1, + enc : 1, + seq : 8; +} tx_ampdu_entry_t; + +typedef struct lldesc_chain_s { + lldesc_t *head; + lldesc_t *tail; +} lldesc_chain_t; + +#ifdef SBUF_RXTX +enum sbuf_mask_s { + SBUF_MOVE_NO = 0, + SBUF_MOVE_TX2RX, + SBUF_MOVE_RX2TX, +} ; + +#define SBUF_MOVE_STEP 8 +#endif +#define LLDESC_SIZE sizeof(struct lldesc_s) + +/* SLC Descriptor */ +#define LLDESC_OWNER_MASK 0x80000000 +#define LLDESC_OWNER_SHIFT 31 +#define LLDESC_SW_OWNED 0 +#define LLDESC_HW_OWNED 1 + +#define LLDESC_EOF_MASK 0x40000000 +#define LLDESC_EOF_SHIFT 30 + +#define LLDESC_SOSF_MASK 0x20000000 +#define LLDESC_SOSF_SHIFT 29 + +#define LLDESC_LENGTH_MASK 0x00fff000 +#define LLDESC_LENGTH_SHIFT 12 + +#define LLDESC_SIZE_MASK 0x00000fff +#define LLDESC_SIZE_SHIFT 0 + +#define LLDESC_ADDR_MASK 0x000fffff + +void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner, + lldesc_t **head, +#ifdef TO_HOST_RESTART + lldesc_t **one_before_tail, +#endif + lldesc_t **tail); + +lldesc_t *lldesc_num2link(lldesc_t *head, uint16_t nblks); + +lldesc_t *lldesc_set_owner(lldesc_t *head, uint16_t nblks, uint8_t owner); + +static inline uint32_t lldesc_get_chain_length(lldesc_t *head) +{ + lldesc_t *ds = head; + uint32_t len = 0; + + while (ds) { + len += ds->length; + ds = STAILQ_NEXT(ds, qe); + } + + return len; +} + +static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) +{ + ds->owner = owner; + ds->eof = eof; + ds->sosf = sosf; + ds->length = len; +} + +#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) \ + do { \ + (_desc)->owner = (_owner); \ + (_desc)->eof = (_eof); \ + (_desc)->sosf = (_sosf); \ + (_desc)->length = (_len); \ + } while(0) + +#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) + +#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/md5_hash.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/md5_hash.h new file mode 100644 index 00000000..8676ace2 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/md5_hash.h @@ -0,0 +1,35 @@ +/* + * MD5 internal definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +}; + +void MD5Init(struct MD5Context *context); +void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *context); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/miniz.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/miniz.h new file mode 100644 index 00000000..75535113 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/miniz.h @@ -0,0 +1,757 @@ +#pragma once + +#include + +// Defines to completely disable specific portions of miniz.c: +// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl. + +// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O. +#define MINIZ_NO_STDIO + +// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or +// get/set file times, and the C run-time funcs that get/set times won't be called. +// The current downside is the times written to your archives will be from 1979. +#define MINIZ_NO_TIME + +// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's. +#define MINIZ_NO_ARCHIVE_APIS + +// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's. +#define MINIZ_NO_ARCHIVE_WRITING_APIS + +// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's. +#define MINIZ_NO_ZLIB_APIS + +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib. +#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc. +// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc +// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user +// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work. +#define MINIZ_NO_MALLOC + +#if defined(__TINYC__) && (defined(__linux) || defined(__linux__)) +// TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux +#define MINIZ_NO_TIME +#endif + +#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS) +#include +#endif + +//Hardcoded options for Xtensa - JD +#define MINIZ_X86_OR_X64_CPU 0 +#define MINIZ_LITTLE_ENDIAN 1 +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0 +#define MINIZ_HAS_64BIT_REGISTERS 0 +#define TINFL_USE_64BIT_BITBUF 0 + + +#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__) +// MINIZ_X86_OR_X64_CPU is only used to help set the below macros. +#define MINIZ_X86_OR_X64_CPU 1 +#endif + +#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU +// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian. +#define MINIZ_LITTLE_ENDIAN 1 +#endif + +#if MINIZ_X86_OR_X64_CPU +// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses. +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1 +#endif + +#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__) +// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions). +#define MINIZ_HAS_64BIT_REGISTERS 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// ------------------- zlib-style API Definitions. + +// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits! +typedef unsigned long mz_ulong; + +// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap. +void mz_free(void *p); + +#define MZ_ADLER32_INIT (1) +// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL. +mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len); + +#define MZ_CRC32_INIT (0) +// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL. +mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len); + +// Compression strategies. +enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 }; + +// Method +#define MZ_DEFLATED 8 + +#ifndef MINIZ_NO_ZLIB_APIS + +// Heap allocation callbacks. +// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long. +typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size); +typedef void (*mz_free_func)(void *opaque, void *address); +typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size); + +#define MZ_VERSION "9.1.15" +#define MZ_VERNUM 0x91F0 +#define MZ_VER_MAJOR 9 +#define MZ_VER_MINOR 1 +#define MZ_VER_REVISION 15 +#define MZ_VER_SUBREVISION 0 + +// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs). +enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 }; + +// Return status codes. MZ_PARAM_ERROR is non-standard. +enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 }; + +// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL. +enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 }; + +// Window bits +#define MZ_DEFAULT_WINDOW_BITS 15 + +struct mz_internal_state; + +// Compression/decompression stream struct. +typedef struct mz_stream_s { + const unsigned char *next_in; // pointer to next byte to read + unsigned int avail_in; // number of bytes available at next_in + mz_ulong total_in; // total number of bytes consumed so far + + unsigned char *next_out; // pointer to next byte to write + unsigned int avail_out; // number of bytes that can be written to next_out + mz_ulong total_out; // total number of bytes produced so far + + char *msg; // error msg (unused) + struct mz_internal_state *state; // internal state, allocated by zalloc/zfree + + mz_alloc_func zalloc; // optional heap allocation function (defaults to malloc) + mz_free_func zfree; // optional heap free function (defaults to free) + void *opaque; // heap alloc function user pointer + + int data_type; // data_type (unused) + mz_ulong adler; // adler32 of the source or uncompressed data + mz_ulong reserved; // not used +} mz_stream; + +typedef mz_stream *mz_streamp; + +// Returns the version string of miniz.c. +const char *mz_version(void); + +// mz_deflateInit() initializes a compressor with default options: +// Parameters: +// pStream must point to an initialized mz_stream struct. +// level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION]. +// level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio. +// (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.) +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if the input parameters are bogus. +// MZ_MEM_ERROR on out of memory. +int mz_deflateInit(mz_streamp pStream, int level); + +// mz_deflateInit2() is like mz_deflate(), except with more control: +// Additional parameters: +// method must be MZ_DEFLATED +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer) +// mem_level must be between [1, 9] (it's checked but ignored by miniz.c) +int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy); + +// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2(). +int mz_deflateReset(mz_streamp pStream); + +// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH. +// Return values: +// MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full). +// MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.) +int mz_deflate(mz_streamp pStream, int flush); + +// mz_deflateEnd() deinitializes a compressor: +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +int mz_deflateEnd(mz_streamp pStream); + +// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH. +mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len); + +// Single-call compression functions mz_compress() and mz_compress2(): +// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure. +int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); +int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level); + +// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress(). +mz_ulong mz_compressBound(mz_ulong source_len); + +// Initializes a decompressor. +int mz_inflateInit(mz_streamp pStream); + +// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer: +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate). +int mz_inflateInit2(mz_streamp pStream, int window_bits); + +// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH. +// On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster). +// MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data. +// Return values: +// MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full. +// MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_DATA_ERROR if the deflate stream is invalid. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again +// with more input data, or with more room in the output buffer (except when using single call decompression, described above). +int mz_inflate(mz_streamp pStream, int flush); + +// Deinitializes a decompressor. +int mz_inflateEnd(mz_streamp pStream); + +// Single-call decompression. +// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure. +int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); + +// Returns a string description of the specified error code, or NULL if the error code is invalid. +const char *mz_error(int err); + +// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports. +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project. +#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES +typedef unsigned char Byte; +typedef unsigned int uInt; +typedef mz_ulong uLong; +typedef Byte Bytef; +typedef uInt uIntf; +typedef char charf; +typedef int intf; +typedef void *voidpf; +typedef uLong uLongf; +typedef void *voidp; +typedef void *const voidpc; +#define Z_NULL 0 +#define Z_NO_FLUSH MZ_NO_FLUSH +#define Z_PARTIAL_FLUSH MZ_PARTIAL_FLUSH +#define Z_SYNC_FLUSH MZ_SYNC_FLUSH +#define Z_FULL_FLUSH MZ_FULL_FLUSH +#define Z_FINISH MZ_FINISH +#define Z_BLOCK MZ_BLOCK +#define Z_OK MZ_OK +#define Z_STREAM_END MZ_STREAM_END +#define Z_NEED_DICT MZ_NEED_DICT +#define Z_ERRNO MZ_ERRNO +#define Z_STREAM_ERROR MZ_STREAM_ERROR +#define Z_DATA_ERROR MZ_DATA_ERROR +#define Z_MEM_ERROR MZ_MEM_ERROR +#define Z_BUF_ERROR MZ_BUF_ERROR +#define Z_VERSION_ERROR MZ_VERSION_ERROR +#define Z_PARAM_ERROR MZ_PARAM_ERROR +#define Z_NO_COMPRESSION MZ_NO_COMPRESSION +#define Z_BEST_SPEED MZ_BEST_SPEED +#define Z_BEST_COMPRESSION MZ_BEST_COMPRESSION +#define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION +#define Z_DEFAULT_STRATEGY MZ_DEFAULT_STRATEGY +#define Z_FILTERED MZ_FILTERED +#define Z_HUFFMAN_ONLY MZ_HUFFMAN_ONLY +#define Z_RLE MZ_RLE +#define Z_FIXED MZ_FIXED +#define Z_DEFLATED MZ_DEFLATED +#define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS +#define alloc_func mz_alloc_func +#define free_func mz_free_func +#define internal_state mz_internal_state +#define z_stream mz_stream +#define deflateInit mz_deflateInit +#define deflateInit2 mz_deflateInit2 +#define deflateReset mz_deflateReset +#define deflate mz_deflate +#define deflateEnd mz_deflateEnd +#define deflateBound mz_deflateBound +#define compress mz_compress +#define compress2 mz_compress2 +#define compressBound mz_compressBound +#define inflateInit mz_inflateInit +#define inflateInit2 mz_inflateInit2 +#define inflate mz_inflate +#define inflateEnd mz_inflateEnd +#define uncompress mz_uncompress +#define crc32 mz_crc32 +#define adler32 mz_adler32 +#define MAX_WBITS 15 +#define MAX_MEM_LEVEL 9 +#define zError mz_error +#define ZLIB_VERSION MZ_VERSION +#define ZLIB_VERNUM MZ_VERNUM +#define ZLIB_VER_MAJOR MZ_VER_MAJOR +#define ZLIB_VER_MINOR MZ_VER_MINOR +#define ZLIB_VER_REVISION MZ_VER_REVISION +#define ZLIB_VER_SUBREVISION MZ_VER_SUBREVISION +#define zlibVersion mz_version +#define zlib_version mz_version() +#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +#endif // MINIZ_NO_ZLIB_APIS + +// ------------------- Types and macros + +typedef unsigned char mz_uint8; +typedef signed short mz_int16; +typedef unsigned short mz_uint16; +typedef unsigned int mz_uint32; +typedef unsigned int mz_uint; +typedef long long mz_int64; +typedef unsigned long long mz_uint64; +typedef int mz_bool; + +#define MZ_FALSE (0) +#define MZ_TRUE (1) + +// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message. +#ifdef _MSC_VER +#define MZ_MACRO_END while (0, 0) +#else +#define MZ_MACRO_END while (0) +#endif + +// ------------------- ZIP archive reading/writing + +#ifndef MINIZ_NO_ARCHIVE_APIS + +enum { + MZ_ZIP_MAX_IO_BUF_SIZE = 64 * 1024, + MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260, + MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256 +}; + +typedef struct { + mz_uint32 m_file_index; + mz_uint32 m_central_dir_ofs; + mz_uint16 m_version_made_by; + mz_uint16 m_version_needed; + mz_uint16 m_bit_flag; + mz_uint16 m_method; +#ifndef MINIZ_NO_TIME + time_t m_time; +#endif + mz_uint32 m_crc32; + mz_uint64 m_comp_size; + mz_uint64 m_uncomp_size; + mz_uint16 m_internal_attr; + mz_uint32 m_external_attr; + mz_uint64 m_local_header_ofs; + mz_uint32 m_comment_size; + char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE]; + char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE]; +} mz_zip_archive_file_stat; + +typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n); +typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n); + +struct mz_zip_internal_state_tag; +typedef struct mz_zip_internal_state_tag mz_zip_internal_state; + +typedef enum { + MZ_ZIP_MODE_INVALID = 0, + MZ_ZIP_MODE_READING = 1, + MZ_ZIP_MODE_WRITING = 2, + MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3 +} mz_zip_mode; + +typedef struct mz_zip_archive_tag { + mz_uint64 m_archive_size; + mz_uint64 m_central_directory_file_ofs; + mz_uint m_total_files; + mz_zip_mode m_zip_mode; + + mz_uint m_file_offset_alignment; + + mz_alloc_func m_pAlloc; + mz_free_func m_pFree; + mz_realloc_func m_pRealloc; + void *m_pAlloc_opaque; + + mz_file_read_func m_pRead; + mz_file_write_func m_pWrite; + void *m_pIO_opaque; + + mz_zip_internal_state *m_pState; + +} mz_zip_archive; + +typedef enum { + MZ_ZIP_FLAG_CASE_SENSITIVE = 0x0100, + MZ_ZIP_FLAG_IGNORE_PATH = 0x0200, + MZ_ZIP_FLAG_COMPRESSED_DATA = 0x0400, + MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800 +} mz_zip_flags; + +// ZIP archive reading + +// Inits a ZIP archive reader. +// These functions read and validate the archive's central directory. +mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags); +mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags); +#endif + +// Returns the total number of files in the archive. +mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip); + +// Returns detailed information about an archive file entry. +mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat); + +// Determines if an archive file entry is a directory entry. +mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index); +mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index); + +// Retrieves the filename of an archive file entry. +// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename. +mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size); + +// Attempts to locates a file in the archive's central directory. +// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH +// Returns -1 if the file cannot be found. +int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags); + +// Extracts a archive file to a memory buffer using no memory allocation. +mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); +mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); + +// Extracts a archive file to a memory buffer. +mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags); + +// Extracts a archive file to a dynamically allocated heap buffer. +void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags); +void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags); + +// Extracts a archive file using a callback function to output the file's data. +mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); + +#ifndef MINIZ_NO_STDIO +// Extracts a archive file to a disk file and sets its last accessed and modified times. +// This function only extracts files, not archive directory records. +mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags); +#endif + +// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used. +mz_bool mz_zip_reader_end(mz_zip_archive *pZip); + +// ZIP archive writing + +#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +// Inits a ZIP archive writer. +mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size); +mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning); +#endif + +// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive. +// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called. +// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it). +// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL. +// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before +// the archive is finalized the file's central directory will be hosed. +mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename); + +// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive. +// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags); +mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32); + +#ifndef MINIZ_NO_STDIO +// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); +#endif + +// Adds a file to an archive by fully cloning the data from another archive. +// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields. +mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index); + +// Finalizes the archive by writing the central directory records followed by the end of central directory record. +// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end(). +// An archive must be manually finalized by calling this function for it to be valid. +mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip); +mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize); + +// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used. +// Note for the archive to be valid, it must have been finalized before ending. +mz_bool mz_zip_writer_end(mz_zip_archive *pZip); + +// Misc. high-level helper functions: + +// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); + +// Reads a single file from an archive into a heap block. +// Returns NULL on failure. +void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags); + +#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +#endif // #ifndef MINIZ_NO_ARCHIVE_APIS + +// ------------------- Low-level Decompression API Definitions + +// Decompression flags used by tinfl_decompress(). +// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream. +// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input. +// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB). +// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes. +enum { + TINFL_FLAG_PARSE_ZLIB_HEADER = 1, + TINFL_FLAG_HAS_MORE_INPUT = 2, + TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4, + TINFL_FLAG_COMPUTE_ADLER32 = 8 +}; + +// High level decompression functions: +// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress. +// On return: +// Function returns a pointer to the decompressed data, or NULL on failure. +// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must call mz_free() on the returned block when it's no longer needed. +void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory. +// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success. +#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1)) +size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer. +// Returns 1 on success or 0 on failure. +typedef int (*tinfl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser); +int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor; + +// Max size of LZ dictionary. +#define TINFL_LZ_DICT_SIZE 32768 + +// Return status. +typedef enum { + TINFL_STATUS_BAD_PARAM = -3, + TINFL_STATUS_ADLER32_MISMATCH = -2, + TINFL_STATUS_FAILED = -1, + TINFL_STATUS_DONE = 0, + TINFL_STATUS_NEEDS_MORE_INPUT = 1, + TINFL_STATUS_HAS_MORE_OUTPUT = 2 +} tinfl_status; + +// Initializes the decompressor to its initial state. +#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END +#define tinfl_get_adler32(r) (r)->m_check_adler32 + +// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability. +// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output. +tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags); + +// Internal/private bits follow. +enum { + TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19, + TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS +}; + +typedef struct { + mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0]; + mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2]; +} tinfl_huff_table; + +#if MINIZ_HAS_64BIT_REGISTERS +#define TINFL_USE_64BIT_BITBUF 1 +#endif + +#if TINFL_USE_64BIT_BITBUF +typedef mz_uint64 tinfl_bit_buf_t; +#define TINFL_BITBUF_SIZE (64) +#else +typedef mz_uint32 tinfl_bit_buf_t; +#define TINFL_BITBUF_SIZE (32) +#endif + +struct tinfl_decompressor_tag { + mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES]; + tinfl_bit_buf_t m_bit_buf; + size_t m_dist_from_out_buf_start; + tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES]; + mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137]; +}; + +// ------------------- Low-level Compression API Definitions + +// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently). +#define TDEFL_LESS_MEMORY 1 + +// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search): +// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression). +enum { + TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF +}; + +// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data. +// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers). +// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing. +// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory). +// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1) +// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled. +// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables. +// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks. +// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK). +enum { + TDEFL_WRITE_ZLIB_HEADER = 0x01000, + TDEFL_COMPUTE_ADLER32 = 0x02000, + TDEFL_GREEDY_PARSING_FLAG = 0x04000, + TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000, + TDEFL_RLE_MATCHES = 0x10000, + TDEFL_FILTER_MATCHES = 0x20000, + TDEFL_FORCE_ALL_STATIC_BLOCKS = 0x40000, + TDEFL_FORCE_ALL_RAW_BLOCKS = 0x80000 +}; + +// High level compression functions: +// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of source block to compress. +// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression. +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must free() the returned block when it's no longer needed. +void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory. +// Returns 0 on failure. +size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// Compresses an image to a compressed PNG file in memory. +// On entry: +// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. +// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory. +// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL +// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps). +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pLen_out will be set to the size of the PNG image file. +// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed. +void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip); +void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out); + +// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time. +typedef mz_bool (*tdefl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser); + +// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally. +mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 }; + +// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes). +#if TDEFL_LESS_MEMORY +enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#else +enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#endif + +// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions. +typedef enum { + TDEFL_STATUS_BAD_PARAM = -2, + TDEFL_STATUS_PUT_BUF_FAILED = -1, + TDEFL_STATUS_OKAY = 0, + TDEFL_STATUS_DONE = 1, +} tdefl_status; + +// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums +typedef enum { + TDEFL_NO_FLUSH = 0, + TDEFL_SYNC_FLUSH = 2, + TDEFL_FULL_FLUSH = 3, + TDEFL_FINISH = 4 +} tdefl_flush; + +// tdefl's compression state structure. +typedef struct { + tdefl_put_buf_func_ptr m_pPut_buf_func; + void *m_pPut_buf_user; + mz_uint m_flags, m_max_probes[2]; + int m_greedy_parsing; + mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size; + mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end; + mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer; + mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish; + tdefl_status m_prev_return_status; + const void *m_pIn_buf; + void *m_pOut_buf; + size_t *m_pIn_buf_size, *m_pOut_buf_size; + tdefl_flush m_flush; + const mz_uint8 *m_pSrc; + size_t m_src_buf_left, m_out_buf_ofs; + mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1]; + mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE]; + mz_uint16 m_next[TDEFL_LZ_DICT_SIZE]; + mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE]; + mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE]; +} tdefl_compressor; + +// Initializes the compressor. +// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. +// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// If pBut_buf_func is NULL the user should always call the tdefl_compress() API. +// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) +tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible. +tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush); + +// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr. +// tdefl_compress_buffer() always consumes the entire input buffer. +tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush); + +tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d); +mz_uint32 tdefl_get_adler32(tdefl_compressor *d); + +// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros. +#ifndef MINIZ_NO_ZLIB_APIS +// Create tdefl_compress() flags given zlib-style compression parameters. +// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files) +// window_bits may be -15 (raw deflate) or 15 (zlib) +// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED +mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy); +#endif // #ifndef MINIZ_NO_ZLIB_APIS + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rsa_pss.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rsa_pss.h new file mode 100644 index 00000000..b9ced67a --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rsa_pss.h @@ -0,0 +1,43 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_SIG_LEN 384 /* Bytes */ +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef struct { + uint8_t n[384]; /* Public key modulus */ + uint32_t e; /* Public key exponent */ + uint8_t rinv[384]; + uint32_t mdash; +} ets_rsa_pubkey_t; + +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest); + +void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); + +bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h new file mode 100644 index 00000000..15adc528 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/rtc.h @@ -0,0 +1,213 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include "ets_sys.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP + * + * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * RTC_CNTL_STORE0_REG Reserved + * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value + * RTC_CNTL_STORE2_REG Boot time, low word + * RTC_CNTL_STORE3_REG Boot time, high word + * RTC_CNTL_STORE4_REG External XTAL frequency + * RTC_CNTL_STORE5_REG APB bus frequency + * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY + * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG + + +typedef enum { + AWAKE = 0, // +#include +#include "rsa_pss.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct ets_secure_boot_sig_block; +struct ets_secure_boot_signature_t; + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Verify bootloader image (reconfigures cache to map, + loads trusted key digests from efuse) + + If allow_key_revoke is true and aggressive revoke efuse is set, + any failed signature has its associated key revoked in efuse. + + If result is ETS_OK, the "simple hash" of the bootloader + is copied into verified_hash. +*/ +int ets_secure_boot_verify_bootloader(uint8_t *verified_hash, bool allow_key_revoke); + +/* Verify bootloader image (reconfigures cache to map), with + key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If result is ETS_OK, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +int ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access. +*/ +int ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL + + Returns 0 if at least one valid digest was found. +*/ +int ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block (up to 3 can be appended) */ +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +_Static_assert(sizeof(ets_secure_boot_sig_block_t) == 1216, "ets_secure_boot_sig_block_t should occupy 1216 Bytes in memory"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +_Static_assert(sizeof(ets_secure_boot_signature_t) == 4096, "ets_secure_boot_signature_t should occupy 4096 Bytes in memory"); + +struct ets_secure_boot_key_digests { + const void *key_digests[3]; + bool allow_key_revoke; +}; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/sha.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/sha.h new file mode 100644 index 00000000..4d8fe901 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/sha.h @@ -0,0 +1,63 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include "ets_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA2_384, + SHA2_512, + SHA2_512224, + SHA2_512256, + SHA2_512T, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h new file mode 100644 index 00000000..fb060c15 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/spi_flash.h @@ -0,0 +1,554 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup spi_flash_apis, spi flash operation related apis + * @brief spi_flash apis + */ + +/** @addtogroup spi_flash_apis + * @{ + */ + +/************************************************************* + * Note + ************************************************************* + * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is + * used as an SPI master to access Flash and ext-SRAM by + * Cache module. It will support Decryto read for Flash, + * read/write for ext-SRAM. And SPI1 is also used as an + * SPI master for Flash read/write and ext-SRAM read/write. + * It will support Encrypto write for Flash. + * 2. As an SPI master, SPI support Highest clock to 80M, + * however, Flash with 80M Clock should be configured + * for different Flash chips. If you want to use 80M + * clock We should use the SPI that is certified by + * Espressif. However, the certification is not started + * at the time, so please use 40M clock at the moment. + * 3. SPI Flash can use 2 lines or 4 lines mode. If you + * use 2 lines mode, you can save two pad SPIHD and + * SPIWP for gpio. ESP32 support configured SPI pad for + * Flash, the configuration is stored in efuse and flash. + * However, the configurations of pads should be certified + * by Espressif. If you use this function, please use 40M + * clock at the moment. + * 4. ESP32 support to use Common SPI command to configure + * Flash to QIO mode, if you failed to configure with fix + * command. With Common SPI Command, ESP32 can also provide + * a way to use same Common SPI command groups on different + * Flash chips. + * 5. This functions are not protected by packeting, Please use the + ************************************************************* + */ + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +//SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_ID_GD25LQ32C 0xC86016 + +typedef enum { + ESP_ROM_SPIFLASH_QIO_MODE = 0, + ESP_ROM_SPIFLASH_QOUT_MODE, + ESP_ROM_SPIFLASH_DIO_MODE, + ESP_ROM_SPIFLASH_DOUT_MODE, + ESP_ROM_SPIFLASH_FASTRD_MODE, + ESP_ROM_SPIFLASH_SLOWRD_MODE +} esp_rom_spiflash_read_mode_t; + +typedef enum { + ESP_ROM_SPIFLASH_RESULT_OK, + ESP_ROM_SPIFLASH_RESULT_ERR, + ESP_ROM_SPIFLASH_RESULT_TIMEOUT +} esp_rom_spiflash_result_t; + +typedef struct { + uint32_t device_id; + uint32_t chip_size; // chip size in bytes + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; +} esp_rom_spiflash_chip_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from falsh by rom code, function usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t legacy: In legacy mode, more SPI command is used in line. + * + * @return None + */ +void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Falsh status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +/** + * @brief Unlock SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/* TODO: figure out how to map these to their new names */ +typedef enum { + SPI_ENCRYPT_DESTINATION_FLASH, + SPI_ENCRYPT_DESTINATION_PSRAM, +} SpiEncryptDest; + +typedef esp_rom_spiflash_result_t SpiFlashOpResult; + +SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len); +SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len); +void SPI_Write_Encrypt_Enable(void); +void SPI_Write_Encrypt_Disable(void); + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions + * + */ +extern esp_rom_spiflash_chip_t g_rom_flashchip; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/tjpgd.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/tjpgd.h new file mode 100644 index 00000000..40340dea --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/tjpgd.h @@ -0,0 +1,97 @@ +/*----------------------------------------------------------------------------/ +/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012 +/----------------------------------------------------------------------------*/ +#ifndef _TJPGDEC +#define _TJPGDEC +/*---------------------------------------------------------------------------*/ +/* System Configurations */ + +#define JD_SZBUF 512 /* Size of stream input buffer */ +#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ +#define JD_USE_SCALE 1 /* Use descaling feature for output */ +#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ + +/*---------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + + +/* Error code */ +typedef enum { + JDR_OK = 0, /* 0: Succeeded */ + JDR_INTR, /* 1: Interrupted by output function */ + JDR_INP, /* 2: Device error or wrong termination of input stream */ + JDR_MEM1, /* 3: Insufficient memory pool for the image */ + JDR_MEM2, /* 4: Insufficient stream input buffer */ + JDR_PAR, /* 5: Parameter error */ + JDR_FMT1, /* 6: Data format error (may be damaged data) */ + JDR_FMT2, /* 7: Right format but not supported */ + JDR_FMT3 /* 8: Not supported JPEG standard */ +} JRESULT; + + + +/* Rectangular structure */ +typedef struct { + WORD left, right, top, bottom; +} JRECT; + + + +/* Decompressor object structure */ +typedef struct JDEC JDEC; +struct JDEC { + UINT dctr; /* Number of bytes available in the input buffer */ + BYTE *dptr; /* Current data read ptr */ + BYTE *inbuf; /* Bit stream input buffer */ + BYTE dmsk; /* Current bit in the current read byte */ + BYTE scale; /* Output scaling ratio */ + BYTE msx, msy; /* MCU size in unit of block (width, height) */ + BYTE qtid[3]; /* Quantization table ID of each component */ + SHORT dcv[3]; /* Previous DC element of each component */ + WORD nrst; /* Restart inverval */ + UINT width, height; /* Size of the input image (pixel) */ + BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ + WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */ + BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ + LONG *qttbl[4]; /* Dequaitizer tables [id] */ + void *workbuf; /* Working buffer for IDCT and RGB output */ + BYTE *mcubuf; /* Working buffer for the MCU */ + void *pool; /* Pointer to available memory pool */ + UINT sz_pool; /* Size of momory pool (bytes available) */ + UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */ + void *device; /* Pointer to I/O device identifiler for the session */ +}; + +/* TJpgDec API functions */ +JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *); +JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE); + + +#ifdef __cplusplus +} +#endif + +#endif /* _TJPGDEC */ diff --git a/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h new file mode 100644 index 00000000..0c45e92c --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp32s3/rom/uart.h @@ -0,0 +1,436 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +#define RX_BUFF_SIZE 0x400 +#define TX_BUFF_SIZE 100 + +//uart int enalbe register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; + * 1, two UART modules, hard to detect, detect and return. + * + * @return None + */ +int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Switch message exchange channel for UART download booting. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_buff_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t DataLen : the string length. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS SendMsg(uint8_t *pData, uint16_t DataLen); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); + +/** + * @brief Check if this UART is in download connection. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return ETS_NO_BOOT = 0 for no. + * SEL_UART_BOOT = BIT(1) for yes. + */ +uint8_t UartConnCheck(uint8_t uart_no); + +/** + * @brief Initialize the USB ACM UART + * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. + * + * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code + * @param cdc_acm_work_mem_len Length of work mem + */ +void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); + + +/** + * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. + */ +void uart_usb_enable_reset_on_rts(void); + + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp_rom_crc.h b/tools/sdk/esp32/include/esp_rom/include/esp_rom_crc.h new file mode 100644 index 00000000..39787ed1 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp_rom_crc.h @@ -0,0 +1,124 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** Notes about CRC API + * The ESP32 ROM include some CRC tables and CRC APIs to speed up CRC calculation. + * The CRC APIs include CRC8, CRC16, CRC32 algorithms for both little endian and big endian modes. + * Here are the polynomials for the algorithms: + * CRC-8 x8+x2+x1+1 0x07 + * CRC16-CCITT x16+x12+x5+1 0x1021 + * CRC32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1 0x04c11db7 + * + * These group of CRC APIs are designed to calculate the data in buffers either continuous or not. + * To make it easy, we had added a `~` at the beginning and the end of the functions. + * To calculate non-continuous buffers, we can write the code like this: + * init = ~init; + * crc = crc32_le(init, buf0, length0); + * crc = crc32_le(crc, buf1, length1); + * crc = ~crc; + * + * However, it is not easy to select which API to use and give the correct parameters. + * A specific CRC algorithm will include this parameters: width, polynomials, init, refin, refout, xorout + * refin and refout show the endian of the algorithm: + * if both of them are true, please use the little endian API. + * if both of them are false, please use the big endian API. + * xorout is the value which you need to be xored to the raw result. + * However, these group of APIs need one '~' before and after the APIs. + * + * Here are some examples for CRC16: + * CRC-16/CCITT, poly = 0x1021, init = 0x0000, refin = true, refout = true, xorout = 0x0000 + * crc = ~crc16_le((uint16_t)~0x0000, buf, length); + * + * CRC-16/CCITT-FALSE, poly = 0x1021, init = 0xffff, refin = false, refout = false, xorout = 0x0000 + * crc = ~crc16_be((uint16_t)~0xffff, buf, length); + * + * CRC-16/X25, poly = 0x1021, init = 0xffff, refin = true, refout = true, xorout = 0xffff + * crc = (~crc16_le((uint16_t)~(0xffff), buf, length))^0xffff; + * + * CRC-16/XMODEM, poly= 0x1021, init = 0x0000, refin = false, refout = false, xorout = 0x0000 + * crc = ~crc16_be((uint16_t)~0x0000, buf, length); + * + */ + +/** + * @brief CRC32 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC32 value + */ +uint32_t esp_rom_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC32 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC32 value + */ +uint32_t esp_rom_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC16 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC16 value + */ +uint16_t esp_rom_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC16 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC16 value + */ +uint16_t esp_rom_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC8 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC8 value + */ +uint8_t esp_rom_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC8 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC8 value + */ +uint8_t esp_rom_crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp_rom_efuse.h b/tools/sdk/esp32/include/esp_rom/include/esp_rom_efuse.h new file mode 100644 index 00000000..907e175e --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp_rom_efuse.h @@ -0,0 +1,68 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0) +#define ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI (1) + +/** + * @brief A CRC8 algorithm used for MAC addresses stored in eFuse + * + * @param data Pointer to the original data + * @param len Data length in byte + * @return uint8_t CRC value + */ +uint8_t esp_rom_efuse_mac_address_crc8(const uint8_t *data, uint32_t len); + +/** + * @brief Get SPI Flash GPIO pin configurations from eFuse + * + * @return uint32_t + * - 0: default SPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) + * - 1: default HSPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) + * - Others: Customized pin configuration mask. Pins are encoded as per the + * EFUSE_SPICONFIG_RET_SPICLK, EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, + * EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * + * @note WP pin (for quad I/O modes) is not saved in eFuse and not returned by this function. + */ +uint32_t esp_rom_efuse_get_flash_gpio_info(void); + +/** + * @brief Get SPI Flash WP pin information from eFuse + * + * @return uint32_t + * - 0x3F: invalid GPIO number + * - 0~46: valid GPIO number + */ +uint32_t esp_rom_efuse_get_flash_wp_gpio(void); + +/** + * @brief Read eFuse to check whether secure boot has been enabled or not + * + * @return true if secure boot is enabled, otherwise false + */ +bool esp_rom_efuse_is_secure_boot_enabled(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp_rom_gpio.h b/tools/sdk/esp32/include/esp_rom/include/esp_rom_gpio.h new file mode 100644 index 00000000..fc5f0d22 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp_rom_gpio.h @@ -0,0 +1,86 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @brief Configure IO Pad as General Purpose IO, + * so that it can be connected to internal Matrix, + * then combined with one or more peripheral signals. + * + * @param iopad_num IO Pad number + */ +void esp_rom_gpio_pad_select_gpio(uint32_t iopad_num); + +/** + * @brief Enable internal pull up, and disable internal pull down. + * + * @param iopad_num IO Pad number + */ +void esp_rom_gpio_pad_pullup_only(uint32_t iopad_num); + +/** + * @brief Unhold the IO Pad. + * @note When the Pad is set to hold, the state is latched at that moment and won't get changed. + * + * @param iopad_num IP Pad number + */ +void esp_rom_gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Set IO Pad current drive capability. + * + * @param iopad_num IO Pad number + * @param drv Numeric to indicate the capability of current drive + * - 0: 5mA + * - 1: 10mA + * - 2: 20mA + * - 3: 40mA + */ +void esp_rom_gpio_pad_set_drv(uint32_t iopad_num, uint32_t drv); + +/** + * @brief Combine a GPIO input with a peripheral signal, which tagged as input attribute. + * + * @note There's no limitation on the number of signals that a GPIO can combine with. + * + * @param gpio_num GPIO number, especially, `GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to signal + * `GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to signal + * @param signal_idx Peripheral signal index (tagged as input attribute) + * @param inv Whether the GPIO input to be inverted or not + */ +void esp_rom_gpio_connect_in_signal(uint32_t gpio_num, uint32_t signal_idx, bool inv); + +/** + * @brief Combine a peripheral signal which tagged as output attribute with a GPIO. + * + * @note There's no limitation on the number of signals that a GPIO can combine with. + * + * @param gpio_num GPIO number + * @param signal_idx Peripheral signal index (tagged as output attribute) + * @param out_inv Whether to signal to be inverted or not + * @param oen_inv Whether the output enable control is inverted or not + */ +void esp_rom_gpio_connect_out_signal(uint32_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp_rom_md5.h b/tools/sdk/esp32/include/esp_rom/include/esp_rom_md5.h new file mode 100644 index 00000000..5bb71f3e --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp_rom_md5.h @@ -0,0 +1,63 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * The MD5 functions calculate a 128-bit cryptographic digest for any number of input bytes. + */ + +/** + * @brief Type defined for MD5 context + * + */ +typedef struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +} md5_context_t; + +/** + * @brief Initialize the MD5 context + * + * @param context Context object allocated by user + */ +void esp_rom_md5_init(md5_context_t *context); + +/** + * @brief Running MD5 algorithm over input data + * + * @param context MD5 context which has been initialized by `MD5Init` + * @param buf Input buffer + * @param len Buffer length + */ +void esp_rom_md5_update(md5_context_t *context, const uint8_t *buf, uint32_t len); + +/** + * @brief Extract the MD5 result, and erase the context + * + * @param digest Where to store the 128-bit digest value + * @param context MD5 context + */ +void esp_rom_md5_final(uint8_t digest[16], md5_context_t *context); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp_rom_sys.h b/tools/sdk/esp32/include/esp_rom/include/esp_rom_sys.h new file mode 100644 index 00000000..68a538b1 --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp_rom_sys.h @@ -0,0 +1,56 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Print formated string to console device + * @note float and long long data are not supported! + * + * @param fmt Format string + * @param ... Additional arguments, depending on the format string + * @return int: Total number of characters written on success; A negative number on failure. + */ +int esp_rom_printf(const char *fmt, ...); + +/** + * @brief Pauses execution for us microseconds + * + * @param us Number of microseconds to pause + */ +void esp_rom_delay_us(uint32_t us); + +/** + * @brief esp_rom_printf can print message to different channels simultaneously. + * This function can help install the low level putc function for esp_rom_printf. + * + * @param channel Channel number (startting from 1) + * @param putc Function pointer to the putc implementation. Set NULL can disconnect esp_rom_printf with putc. + */ +void esp_rom_install_channel_putc(int channel, void (*putc)(char c)); + +/** + * @brief Disable logging from the ROM code. + */ +void esp_rom_disable_logging(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_rom/include/esp_rom_uart.h b/tools/sdk/esp32/include/esp_rom/include/esp_rom_uart.h new file mode 100644 index 00000000..a944fc6b --- /dev/null +++ b/tools/sdk/esp32/include/esp_rom/include/esp_rom_uart.h @@ -0,0 +1,109 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define ESP_ROM_CDC_ACM_WORK_BUF_MIN 128 + +typedef enum { + ESP_ROM_UART_0, + ESP_ROM_UART_1, + ESP_ROM_UART_USB +} esp_rom_uart_num_t; + +/** + * @brief Wait for UART TX FIFO is empty and all data has been sent out. + * + * @param uart_no UART port number + */ +void esp_rom_uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Set clock source and baud rate for UART. + * + * @param uart_no UART port number + * @param clock_hz Source clock (in Hz) + * @param baud_rate Baud rate to set + */ +void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate); + +/** + * @brief Wait until UART TX FIFO is empty (i.e. flush TX FIFO) + * + * @param uart_no UART port number + */ +void esp_rom_uart_flush_tx(uint8_t uart_no); + +/** + * @brief Transmit one character to the console channel. + * + * @param c Character to send + * @return + * - 0 on success + * - 1 on failure + */ +int esp_rom_uart_tx_one_char(uint8_t c); + +/** + * @brief Transmit one character to the console channel. + * @note This function is a wrapper over esp_rom_uart_tx_one_char, it can help handle line ending issue by replacing '\n' with '\r\n'. + * + * @param c Character to send + */ +void esp_rom_uart_putc(char c); + +/** + * @brief Get one character from the console channel. + * + * @param c Where to store the character + * @return + * - 0 on success + * - 1 on failure or no data available + */ +int esp_rom_uart_rx_one_char(uint8_t *c); + +/** + * @brief Get one line of string from console channel (line ending won't be stored in the buffer). + * + * @param str Where to store the string + * @param max_len Maximum length of the buffer (including the NULL delimiter) + * @return always return 0 when on success or wait in a loop for rx data + */ +int esp_rom_uart_rx_string(uint8_t *str, uint8_t max_len); + +/** + * @brief Set the UART port used by ets_printf. + * + * @param uart_no UART port number + */ +void esp_rom_uart_set_as_console(uint8_t uart_no); + +/** + * @brief Initialize the USB ACM UART + * @note The ACM working memroy should be at least 128 bytes (ESP_ROM_CDC_ACM_WORK_BUF_MIN) in size. + * + * @param cdc_acm_work_mem Pointer to the work memroy used for CDC-ACM + * @param cdc_acm_work_mem_len Length of work memory + */ +void esp_rom_uart_usb_acm_init(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h b/tools/sdk/esp32/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h new file mode 100644 index 00000000..179fa555 --- /dev/null +++ b/tools/sdk/esp32/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h @@ -0,0 +1,165 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_err.h" +#include "esp_serial_slave_link/essl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Basic commands to communicate with the SPI Slave HD on ESP32-S2 +//////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Read the shared buffer from the slave. + * + * @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words + * by the DMA. When a byte is written, the remaining bytes in the same word will also be + * overwritten, even the ``len`` is shorter than a word. + * + * @param spi SPI device handle representing the slave + * @param out_data Buffer for read data, strongly suggested to be in the DRAM and align to 4 + * @param addr Address of the slave shared buffer + * @param len Length to read + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: on success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags); + +/** + * @brief Write the shared buffer of the slave. + * + * @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words + * by the DMA. When a byte is written, the remaining bytes in the same word will also be + * overwritten, even the ``len`` is shorter than a word. + * + * @param spi SPI device handle representing the slave + * @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4 + * @param addr Address of the slave shared buffer, + * @param len Length to write + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags); + +/** + * @brief Receive long buffer in segments from the slave through its DMA. + * + * @note This function combines several :cpp:func:`essl_spi_rddma_seg` and one + * :cpp:func:`essl_spi_rddma_done` at the end. Used when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param out_data Buffer to hold the received data, strongly suggested to be in the DRAM and align to 4 + * @param len Total length of data to receive. + * @param seg_len Length of each segment, which is not larger than the maximum transaction length + * allowed for the spi device. Suggested to be multiples of 4. When set < 0, means send + * all data in one segment (the ``rddma_done`` will still be sent.) + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rddma(spi_device_handle_t spi, uint8_t *out_data, int len, int seg_len, uint32_t flags); + +/** + * @brief Read one data segment from the slave through its DMA. + * + * @note To read long buffer, call :cpp:func:`essl_spi_rddma` instead. + * + * @param spi SPI device handle representing the slave + * @param out_data Buffer to hold the received data, strongly suggested to be in the DRAM and align to 4 + * @param seg_len Length of this segment + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg_len, uint32_t flags); + +/** + * @brief Send the ``rddma_done`` command to the slave. Upon receiving this command, the slave will + * stop sending the current buffer even there are data unsent, and maybe prepare the next buffer to + * send. + * + * @note This is required only when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags); + +/** + * @brief Send long buffer in segments to the slave through its DMA. + * + * @note This function combines several :cpp:func:`essl_spi_wrdma_seg` and one + * :cpp:func:`essl_spi_wrdma_done` at the end. Used when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4 + * @param len Total length of data to send. + * @param seg_len Length of each segment, which is not larger than the maximum transaction length + * allowed for the spi device. Suggested to be multiples of 4. When set < 0, means send + * all data in one segment (the ``wrdma_done`` will still be sent.) + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, int seg_len, uint32_t flags); + +/** + * @brief Send one data segment to the slave through its DMA. + * + * @note To send long buffer, call :cpp:func:`essl_spi_wrdma` instead. + * + * @param spi SPI device handle representing the slave + * @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4 + * @param seg_len Length of this segment + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int seg_len, uint32_t flags); + +/** + * @brief Send the ``wrdma_done`` command to the slave. Upon receiving this command, the slave will + * stop receiving, process the received data, and maybe prepare the next buffer to receive. + * + * @note This is required only when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h b/tools/sdk/esp32/include/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h new file mode 100644 index 00000000..d2856fd1 --- /dev/null +++ b/tools/sdk/esp32/include/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h @@ -0,0 +1,38 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once + +// NOTE: From the view of master +#define CMD_HD_WRBUF_REG 0x01 +#define CMD_HD_RDBUF_REG 0x02 +#define CMD_HD_WRDMA_REG 0x03 +#define CMD_HD_RDDMA_REG 0x04 + +#define CMD_HD_ONEBIT_MODE 0x00 +#define CMD_HD_DOUT_MODE 0x10 +#define CMD_HD_QOUT_MODE 0x20 +#define CMD_HD_DIO_MODE 0x50 +#define CMD_HD_QIO_MODE 0xA0 + +#define CMD_HD_SEG_END_REG 0x05 +#define CMD_HD_EN_QPI_REG 0x06 +#define CMD_HD_WR_END_REG 0x07 +#define CMD_HD_INT0_REG 0x08 +#define CMD_HD_INT1_REG 0x09 +#define CMD_HD_INT2_REG 0x0A +#define CMD_HD_EX_QPI_REG 0xDD + +#define SPI_SLAVE_HD_BUFFER_SIZE 72 \ No newline at end of file diff --git a/tools/sdk/esp32/include/esp_system/include/esp_private/panic_internal.h b/tools/sdk/esp32/include/esp_system/include/esp_private/panic_internal.h new file mode 100644 index 00000000..583d3eba --- /dev/null +++ b/tools/sdk/esp32/include/esp_system/include/esp_private/panic_internal.h @@ -0,0 +1,77 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern bool g_panic_abort; + +// Function to print longer amounts of information such as the details +// and backtrace field of panic_info_t. These functions should limit themselves +// to printing to the console and should do other more involved processing, +// and must be aware that the main logic in panic.c has a watchdog timer active. +typedef void (*panic_info_dump_fn_t)(const void* frame); + +// Non architecture specific exceptions (generally valid for all targets). +// Can be used to convey to the main logic what exception is being +// dealt with to perform some actions, without knowing the underlying +// architecture/chip-specific exception. +typedef enum { + PANIC_EXCEPTION_DEBUG, + PANIC_EXCEPTION_IWDT, + PANIC_EXCEPTION_TWDT, + PANIC_EXCEPTION_ABORT, + PANIC_EXCEPTION_FAULT, // catch-all for all types of faults +} panic_exception_t; + +typedef struct { + int core; // core which triggered panic + panic_exception_t exception; // non-architecture-specific exception code + const char* reason; // exception string + const char* description; // short description of the exception + panic_info_dump_fn_t details; // more details on the exception + panic_info_dump_fn_t state; // processor state, usually the contents of the registers + const void* addr; // instruction address that triggered the exception + const void* frame; // reference to the frame + bool pseudo_excause; // flag indicating that exception cause has special meaning +} panic_info_t; + +#define PANIC_INFO_DUMP(info, dump_fn) {if ((info)->dump_fn) (*(info)->dump_fn)((info->frame));} + +// Create own print functions, since printf might be broken, and can be silenced +// when CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT +#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT +void panic_print_char(char c); +void panic_print_str(const char *str); +void panic_print_dec(int d); +void panic_print_hex(int h); +#else +#define panic_print_char(c) +#define panic_print_str(str) +#define panic_print_dec(d) +#define panic_print_hex(h) +#endif + +void __attribute__((noreturn)) panic_abort(const char *details); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp_system/include/esp_private/startup_internal.h b/tools/sdk/esp32/include/esp_system/include/esp_private/startup_internal.h new file mode 100644 index 00000000..fc91b0fa --- /dev/null +++ b/tools/sdk/esp32/include/esp_system/include/esp_private/startup_internal.h @@ -0,0 +1,74 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_attr.h" + +#include "soc/soc_caps.h" +#include "hal/cpu_hal.h" + +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern bool g_spiram_ok; // [refactor-todo] better way to communicate this from port layer to common startup code + +// Port layer defines the entry point. It then transfer control to a `sys_startup_fn_t`, stored in this +// array, one per core. +typedef void (*sys_startup_fn_t)(void); + +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE +extern sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM]; +#else +extern sys_startup_fn_t g_startup_fn[1]; +#endif + +// Utility to execute `sys_startup_fn_t` for the current core. +#define SYS_STARTUP_FN() ((*g_startup_fn[(cpu_hal_get_core_id())])()) + +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE +void startup_resume_other_cores(void); +#endif + +typedef struct { + void (*fn)(void); + uint32_t cores; +} esp_system_init_fn_t; + +/* + * Declare an component initialization function that will execute on the specified cores (ex. if BIT0 == 1, will execute + * on CORE0, CORE1 if BIT1 and so on). + * + * @note Initialization functions should be placed in a compilation unit where at least one other + * symbol is referenced 'meaningfully' in another compilation unit, otherwise this gets discarded during linking. (By + * 'meaningfully' we mean the reference should not itself get optimized out by the compiler/discarded by the linker). + */ +#define ESP_SYSTEM_INIT_FN(f, c, ...) \ +static void __attribute__((used)) __VA_ARGS__ __esp_system_init_fn_##f(void); \ +static __attribute__((used)) esp_system_init_fn_t _SECTION_ATTR_IMPL(".esp_system_init_fn", f) \ + esp_system_init_fn_##f = { .fn = ( __esp_system_init_fn_##f), .cores = (c) }; \ +static __attribute__((used)) __VA_ARGS__ void __esp_system_init_fn_##f(void) // [refactor-todo] this can be made public API if we allow components to declare init functions, + // instead of calling them explicitly + +extern uint64_t g_startup_time; // Startup time that serves as the point of origin for system time. Should be set by the entry + // function in the port layer. May be 0 as well if this is not backed by a persistent counter, in which case + // startup time = system time = 0 at the point the entry function sets this variable. + +#ifdef __cplusplus +} +#endif + diff --git a/tools/sdk/esp32/include/esp_system/include/esp_private/usb_console.h b/tools/sdk/esp32/include/esp_system/include/esp_private/usb_console.h new file mode 100644 index 00000000..1e9536f4 --- /dev/null +++ b/tools/sdk/esp32/include/esp_system/include/esp_private/usb_console.h @@ -0,0 +1,73 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file usb_console.h + * This file contains definitions of low-level USB console functions. + * These functions are not considered to be a public interface and + * should not be called by applications directly. + * Application interface to the USB console is provided either by + * "cdcacm" VFS driver, or by the USB CDC driver in TinyUSB. + */ + + +/** + * RX/TX callback function type + * @param arg callback-specific context pointer + */ +typedef void (*esp_usb_console_cb_t)(void* arg); + +/** + * Initialize USB console output using ROM USB CDC driver. + * This function is called by the early startup code if USB CDC is + * selected as the console output option. + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM + * - other error codes from the interrupt allocator + */ +esp_err_t esp_usb_console_init(void); + +/** + * Write a buffer to USB CDC + * @param buf data to write + * @param size size of the data, in bytes + * @return -1 on error, otherwise the number of bytes + */ +ssize_t esp_usb_console_write_buf(const char* buf, size_t size); + +ssize_t esp_usb_console_flush(void); + +ssize_t esp_usb_console_read_buf(char* buf, size_t buf_size); + +bool esp_usb_console_read_available(void); + +bool esp_usb_console_write_available(void); + +esp_err_t esp_usb_console_set_cb(esp_usb_console_cb_t rx_cb, esp_usb_console_cb_t tx_cb, void* arg); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp32s2/include/esp_sleep.h b/tools/sdk/esp32/include/esp_system/include/esp_sleep.h similarity index 95% rename from tools/sdk/esp32s2/include/esp32s2/include/esp_sleep.h rename to tools/sdk/esp32/include/esp_system/include/esp_sleep.h index 58d3f642..e423e6df 100644 --- a/tools/sdk/esp32s2/include/esp32s2/include/esp_sleep.h +++ b/tools/sdk/esp32/include/esp_system/include/esp_sleep.h @@ -16,8 +16,9 @@ #include #include "esp_err.h" -#include "driver/gpio.h" -#include "driver/touch_pad.h" + +#include "hal/touch_sensor_types.h" +#include "hal/gpio_types.h" #ifdef __cplusplus extern "C" { @@ -64,7 +65,9 @@ typedef enum { ESP_SLEEP_WAKEUP_ULP, //!< Wakeup caused by ULP program ESP_SLEEP_WAKEUP_GPIO, //!< Wakeup caused by GPIO (light sleep only) ESP_SLEEP_WAKEUP_UART, //!< Wakeup caused by UART (light sleep only) - ESP_SLEEP_WAKEUP_WIFI, //!< Wakeup caused by WIFI (light sleep only) + ESP_SLEEP_WAKEUP_WIFI, //!< Wakeup caused by WIFI (light sleep only) + ESP_SLEEP_WAKEUP_COCPU, //!< Wakeup caused by COCPU int + ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG, //!< Wakeup caused by COCPU crash } esp_sleep_source_t; /* Leave this type define for compatibility */ @@ -90,10 +93,8 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source); /** * @brief Enable wakeup by ULP coprocessor - * @note In revisions 0 and 1 of the ESP32, ULP wakeup source - * can not be used when RTC_PERIPH power domain is forced - * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup - * source is used. + * @note On ESP32, ULP wakeup source cannot be used when RTC_PERIPH power domain is forced + * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup source is used. * @return * - ESP_OK on success * - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled. @@ -115,8 +116,6 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us); * * @note In revisions 0 and 1 of the ESP32, touch wakeup source * can not be used when RTC_PERIPH power domain is forced - * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup - * source is used. * * @note The FSM mode of the touch button should be configured * as the timer trigger mode. @@ -224,6 +223,8 @@ esp_err_t esp_sleep_enable_gpio_wakeup(void); * Wakeup from light sleep takes some time, so not every character sent * to the UART can be received by the application. * + * @note ESP32 does not support wakeup from UART2. + * * @param uart_num UART port to wake up from * @return * - ESP_OK on success @@ -231,6 +232,14 @@ esp_err_t esp_sleep_enable_gpio_wakeup(void); */ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num); +/** + * @brief Enable wakeup by WiFi MAC + * @return + * - ESP_OK on success + */ +esp_err_t esp_sleep_enable_wifi_wakeup(void); + + /** * @brief Get the bit mask of GPIOs which caused wakeup (ext1) * @@ -240,13 +249,6 @@ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num); */ uint64_t esp_sleep_get_ext1_wakeup_status(void); -/** - * @brief Enable wakeup by WiFi MAC - * @return - * - ESP_OK on success - */ -esp_err_t esp_sleep_enable_wifi_wakeup(void); - /** * @brief Set power down mode for an RTC power domain in sleep mode * @@ -357,6 +359,13 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void); */ void esp_default_wake_deep_sleep(void); +/** + * @brief Disable logging from the ROM code after deep sleep. + * + * Using LSB of RTC_STORE4. + */ +void esp_deep_sleep_disable_rom_logging(void); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_system/include/esp_system.h b/tools/sdk/esp32/include/esp_system/include/esp_system.h index 9b0abf43..9be72c3e 100644 --- a/tools/sdk/esp32/include/esp_system/include/esp_system.h +++ b/tools/sdk/esp32/include/esp_system/include/esp_system.h @@ -117,6 +117,16 @@ esp_reset_reason_t esp_reset_reason(void); */ uint32_t esp_get_free_heap_size(void); +/** + * @brief Get the size of available internal heap. + * + * Note that the returned value may be larger than the maximum contiguous block + * which can be allocated. + * + * @return Available internal heap size, in bytes. + */ +uint32_t esp_get_free_internal_heap_size(void); + /** * @brief Get the minimum heap that has ever been available * @@ -251,6 +261,7 @@ void __attribute__((noreturn)) esp_system_abort(const char* details); typedef enum { CHIP_ESP32 = 1, //!< ESP32 CHIP_ESP32S2 = 2, //!< ESP32-S2 + CHIP_ESP32S3 = 4, //!< ESP32-S3 } esp_chip_model_t; /* Chip feature flags, used in esp_chip_info_t */ @@ -275,6 +286,18 @@ typedef struct { */ void esp_chip_info(esp_chip_info_t* out_info); + +#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX +/** + * @brief Cache lock bug exists or not + * + * @return + * - ture : bug exists + * - false : bug not exists + */ +bool soc_has_cache_lock_bug(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_timer/include/esp_timer.h b/tools/sdk/esp32/include/esp_timer/include/esp_timer.h index 1a39ef0a..79766d61 100644 --- a/tools/sdk/esp32/include/esp_timer/include/esp_timer.h +++ b/tools/sdk/esp32/include/esp_timer/include/esp_timer.h @@ -178,7 +178,7 @@ esp_err_t esp_timer_stop(esp_timer_handle_t timer); * @param timer timer handle allocated using esp_timer_create * @return * - ESP_OK on success - * - ESP_ERR_INVALID_STATE if the timer is not running + * - ESP_ERR_INVALID_STATE if the timer is running */ esp_err_t esp_timer_delete(esp_timer_handle_t timer); diff --git a/tools/sdk/esp32/include/esp_websocket_client/include/esp_websocket_client.h b/tools/sdk/esp32/include/esp_websocket_client/include/esp_websocket_client.h index ae8cc8a4..5a0e52e0 100644 --- a/tools/sdk/esp32/include/esp_websocket_client/include/esp_websocket_client.h +++ b/tools/sdk/esp32/include/esp_websocket_client/include/esp_websocket_client.h @@ -85,6 +85,9 @@ typedef struct { char *subprotocol; /*!< Websocket subprotocol */ char *user_agent; /*!< Websocket user-agent */ char *headers; /*!< Websocket additional headers */ + int pingpong_timeout_sec; /*!< Period before connection is aborted due to no PONGs received */ + bool disable_pingpong_discon; /*!< Disable auto-disconnect due to no PONG received within pingpong_timeout_sec */ + } esp_websocket_client_config_t; /** @@ -185,7 +188,7 @@ int esp_websocket_client_send_bin(esp_websocket_client_handle_t client, const ch int esp_websocket_client_send_text(esp_websocket_client_handle_t client, const char *data, int len, TickType_t timeout); /** - * @brief Check the WebSocket connection status + * @brief Check the WebSocket client connection state * * @param[in] client The client handle * diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi.h b/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi.h index 8d21c64e..04a306fb 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi.h @@ -119,15 +119,6 @@ esp_err_t esp_wifi_init_internal(const wifi_init_config_t *config); */ esp_err_t esp_wifi_deinit_internal(void); -/** - * @brief get whether the wifi driver is allowed to transmit data or not - * - * @return - * - true : upper layer should stop to transmit data to wifi driver - * - false : upper layer can transmit data to wifi driver - */ -bool esp_wifi_internal_tx_is_stop(void); - /** * @brief free the rx buffer which allocated by wifi driver * @@ -138,18 +129,79 @@ void esp_wifi_internal_free_rx_buffer(void* buffer); /** * @brief transmit the buffer via wifi driver * + * This API makes a copy of the input buffer and then forwards the buffer + * copy to WiFi driver. + * * @param wifi_interface_t wifi_if : wifi interface id * @param void *buffer : the buffer to be tansmit * @param uint16_t len : the length of buffer * * @return - * - ERR_OK : Successfully transmit the buffer to wifi driver - * - ERR_MEM : Out of memory - * - ERR_IF : WiFi driver error - * - ERR_ARG : Invalid argument + * - ESP_OK : Successfully transmit the buffer to wifi driver + * - ESP_ERR_NO_MEM: out of memory + * - ESP_ERR_WIFI_ARG: invalid argument + * - ESP_ERR_WIFI_IF : WiFi interface is invalid + * - ESP_ERR_WIFI_CONN : WiFi interface is not created, e.g. send the data to STA while WiFi mode is AP mode + * - ESP_ERR_WIFI_NOT_STARTED : WiFi is not started + * - ESP_ERR_WIFI_STATE : WiFi internal state is not ready, e.g. WiFi is not started + * - ESP_ERR_WIFI_NOT_ASSOC : WiFi is not associated + * - ESP_ERR_WIFI_TX_DISALLOW : WiFi TX is disallowed, e.g. WiFi hasn't pass the authentication + * - ESP_ERR_WIFI_POST : caller fails to post event to WiFi task */ int esp_wifi_internal_tx(wifi_interface_t wifi_if, void *buffer, uint16_t len); +/** + * @brief The net stack buffer reference counter callback function + * + */ +typedef void (*wifi_netstack_buf_ref_cb_t)(void *netstack_buf); + +/** + * @brief The net stack buffer free callback function + * + */ +typedef void (*wifi_netstack_buf_free_cb_t)(void *netstack_buf); + +/** + * @brief transmit the buffer by reference via wifi driver + * + * This API firstly increases the reference counter of the input buffer and + * then forwards the buffer to WiFi driver. The WiFi driver will free the buffer + * after processing it. Use esp_wifi_internal_tx() if the uplayer buffer doesn't + * supports reference counter. + * + * @param wifi_if : wifi interface id + * @param buffer : the buffer to be tansmit + * @param len : the length of buffer + * @param netstack_buf : the netstack buffer related to bufffer + * + * @return + * - ESP_OK : Successfully transmit the buffer to wifi driver + * - ESP_ERR_NO_MEM: out of memory + * - ESP_ERR_WIFI_ARG: invalid argument + * - ESP_ERR_WIFI_IF : WiFi interface is invalid + * - ESP_ERR_WIFI_CONN : WiFi interface is not created, e.g. send the data to STA while WiFi mode is AP mode + * - ESP_ERR_WIFI_NOT_STARTED : WiFi is not started + * - ESP_ERR_WIFI_STATE : WiFi internal state is not ready, e.g. WiFi is not started + * - ESP_ERR_WIFI_NOT_ASSOC : WiFi is not associated + * - ESP_ERR_WIFI_TX_DISALLOW : WiFi TX is disallowed, e.g. WiFi hasn't pass the authentication + * - ESP_ERR_WIFI_POST : caller fails to post event to WiFi task + */ +esp_err_t esp_wifi_internal_tx_by_ref(wifi_interface_t ifx, void *buffer, size_t len, void *netstack_buf); + +/** + * @brief register the net stack buffer reference increasing and free callback + * + * @param ref : net stack buffer reference callback + * @param free: net stack buffer free callback + * + * @return + * - ESP_OK : Successfully transmit the buffer to wifi driver + * - others : failed to register the callback + */ +esp_err_t esp_wifi_internal_reg_netstack_buf_cb(wifi_netstack_buf_ref_cb_t ref, wifi_netstack_buf_free_cb_t free); + + /** * @brief The WiFi RX callback function * diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi_os_adapter.h b/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi_os_adapter.h index f005b315..ad4245b7 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi_os_adapter.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_private/wifi_os_adapter.h @@ -21,7 +21,7 @@ extern "C" { #endif -#define ESP_WIFI_OS_ADAPTER_VERSION 0x00000006 +#define ESP_WIFI_OS_ADAPTER_VERSION 0x00000007 #define ESP_WIFI_OS_ADAPTER_MAGIC 0xDEADBEAF #define OSI_FUNCS_TIME_BLOCKING 0xffffffff @@ -133,6 +133,7 @@ typedef struct { void (* _coex_condition_set)(uint32_t type, bool dissatisfy); int32_t (* _coex_wifi_request)(uint32_t event, uint32_t latency, uint32_t duration); int32_t (* _coex_wifi_release)(uint32_t event); + bool (* _is_from_isr)(void); int32_t _magic; } wifi_osi_funcs_t; diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h index 891a8de6..4dad75b9 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi.h @@ -88,6 +88,8 @@ extern "C" { #define ESP_ERR_WIFI_POST (ESP_ERR_WIFI_BASE + 18) /*!< Failed to post the event to WiFi task */ #define ESP_ERR_WIFI_INIT_STATE (ESP_ERR_WIFI_BASE + 19) /*!< Invalod WiFi state when init/deinit is called */ #define ESP_ERR_WIFI_STOP_STATE (ESP_ERR_WIFI_BASE + 20) /*!< Returned when WiFi is stopping */ +#define ESP_ERR_WIFI_NOT_ASSOC (ESP_ERR_WIFI_BASE + 21) /*!< The WiFi connection is not associated */ +#define ESP_ERR_WIFI_TX_DISALLOW (ESP_ERR_WIFI_BASE + 22) /*!< The WiFi TX is disallowed */ /** * @brief WiFi stack configuration parameters passed to esp_wifi_init call. @@ -101,12 +103,12 @@ typedef struct { int tx_buf_type; /**< WiFi TX buffer type */ int static_tx_buf_num; /**< WiFi static TX buffer number */ int dynamic_tx_buf_num; /**< WiFi dynamic TX buffer number */ + int cache_tx_buf_num; /**< WiFi TX cache buffer number */ int csi_enable; /**< WiFi channel state information enable flag */ int ampdu_rx_enable; /**< WiFi AMPDU RX feature enable flag */ int ampdu_tx_enable; /**< WiFi AMPDU TX feature enable flag */ int nvs_enable; /**< WiFi NVS flash enable flag */ int nano_enable; /**< Nano option for printf/scan family enable flag */ - int tx_ba_win; /**< WiFi Block Ack TX window size */ int rx_ba_win; /**< WiFi Block Ack RX window size */ int wifi_task_core_id; /**< WiFi Task Core ID */ int beacon_max_len; /**< WiFi softAP maximum length of the beacon */ @@ -121,6 +123,12 @@ typedef struct { #define WIFI_STATIC_TX_BUFFER_NUM 0 #endif +#if (CONFIG_ESP32_SPIRAM_SUPPORT | CONFIG_ESP32S2_SPIRAM_SUPPORT) +#define WIFI_CACHE_TX_BUFFER_NUM CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM +#else +#define WIFI_CACHE_TX_BUFFER_NUM 0 +#endif + #ifdef CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM #define WIFI_DYNAMIC_TX_BUFFER_NUM CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM #else @@ -162,12 +170,6 @@ extern uint64_t g_wifi_feature_caps; #define WIFI_INIT_CONFIG_MAGIC 0x1F2F3F4F -#ifdef CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED -#define WIFI_DEFAULT_TX_BA_WIN CONFIG_ESP32_WIFI_TX_BA_WIN -#else -#define WIFI_DEFAULT_TX_BA_WIN 0 /* unused if ampdu_tx_enable == false */ -#endif - #ifdef CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED #define WIFI_DEFAULT_RX_BA_WIN CONFIG_ESP32_WIFI_RX_BA_WIN #else @@ -193,6 +195,7 @@ extern uint64_t g_wifi_feature_caps; #endif #define CONFIG_FEATURE_WPA3_SAE_BIT (1<<0) +#define CONFIG_FEATURE_CACHE_TX_BUF_BIT (1<<1) #define WIFI_INIT_CONFIG_DEFAULT() { \ .event_handler = &esp_event_send_internal, \ @@ -203,12 +206,12 @@ extern uint64_t g_wifi_feature_caps; .tx_buf_type = CONFIG_ESP32_WIFI_TX_BUFFER_TYPE,\ .static_tx_buf_num = WIFI_STATIC_TX_BUFFER_NUM,\ .dynamic_tx_buf_num = WIFI_DYNAMIC_TX_BUFFER_NUM,\ + .cache_tx_buf_num = WIFI_CACHE_TX_BUFFER_NUM,\ .csi_enable = WIFI_CSI_ENABLED,\ .ampdu_rx_enable = WIFI_AMPDU_RX_ENABLED,\ .ampdu_tx_enable = WIFI_AMPDU_TX_ENABLED,\ .nvs_enable = WIFI_NVS_ENABLED,\ .nano_enable = WIFI_NANO_FORMAT_ENABLED,\ - .tx_ba_win = WIFI_DEFAULT_TX_BA_WIN,\ .rx_ba_win = WIFI_DEFAULT_RX_BA_WIN,\ .wifi_task_core_id = WIFI_TASK_CORE_ID,\ .beacon_max_len = WIFI_SOFTAP_BEACON_MAX_LEN, \ @@ -1093,6 +1096,63 @@ esp_err_t esp_wifi_set_ant(const wifi_ant_config_t *config); */ esp_err_t esp_wifi_get_ant(wifi_ant_config_t *config); +/** + * @brief Get the TSF time + * In Station mode or SoftAP+Station mode if station is not connected or station doesn't receive at least + * one beacon after connected, will return 0 + * + * @attention Enabling power save may cause the return value inaccurate, except WiFi modem sleep + * + * @param interface The interface whose tsf_time is to be retrieved. + * + * @return 0 or the TSF time + */ +int64_t esp_wifi_get_tsf_time(wifi_interface_t interface); + +/** + * @brief Set the inactive time of the ESP32 STA or AP + * + * @attention 1. For Station, If the station does not receive a beacon frame from the connected SoftAP during the inactive time, + * disconnect from SoftAP. Default 6s. + * @attention 2. For SoftAP, If the softAP doesn't receive any data from the connected STA during inactive time, + * the softAP will force deauth the STA. Default is 300s. + * @attention 3. The inactive time configuration is not stored into flash + * + * @param ifx interface to be configured. + * @param sec Inactive time. Unit seconds. + * + * @return + * - ESP_OK: succeed + * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start + * - ESP_ERR_WIFI_ARG: invalid argument, For Station, if sec is less than 3. For SoftAP, if sec is less than 10. + */ +esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec); + +/** + * @brief Get inactive time of specified interface + * + * @param ifx Interface to be configured. + * @param sec Inactive time. Unit seconds. + * + * @return + * - ESP_OK: succeed + * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_ARG: invalid argument + */ +esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec); + +/** + * @brief Dump WiFi statistics + * + * @param modules statistic modules to be dumped + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_wifi_statis_dump(uint32_t modules); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h index cc7dc02a..af3c8569 100644 --- a/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h +++ b/tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h @@ -94,7 +94,7 @@ typedef enum { WIFI_REASON_ASSOC_FAIL = 203, WIFI_REASON_HANDSHAKE_TIMEOUT = 204, WIFI_REASON_CONNECTION_FAIL = 205, - WIFI_REASON_AUTH_CHANGED = 206, + WIFI_REASON_AP_TSF_RESET = 206, } wifi_err_reason_t; typedef enum { @@ -581,6 +581,19 @@ typedef enum { WPS_FAIL_REASON_MAX } wifi_event_sta_wps_fail_reason_t; +#define MAX_SSID_LEN 32 +#define MAX_PASSPHRASE_LEN 64 +#define MAX_WPS_AP_CRED 3 + +/** Argument structure for WIFI_EVENT_STA_WPS_ER_SUCCESS event */ +typedef struct { + uint8_t ap_cred_cnt; /**< Number of AP credentials received */ + struct { + uint8_t ssid[MAX_SSID_LEN]; /**< SSID of AP */ + uint8_t passphrase[MAX_PASSPHRASE_LEN]; /**< Passphrase for the AP */ + } ap_cred[MAX_WPS_AP_CRED]; /**< All AP credentials received from WPS handshake */ +} wifi_event_sta_wps_er_success_t; + /** Argument structure for WIFI_EVENT_AP_STACONNECTED event */ typedef struct { uint8_t mac[6]; /**< MAC address of the station connected to ESP32 soft-AP */ @@ -599,6 +612,12 @@ typedef struct { uint8_t mac[6]; /**< MAC address of the station which send probe request */ } wifi_event_ap_probe_req_rx_t; +#define WIFI_STATIS_BUFFER (1<<0) +#define WIFI_STATIS_RXTX (1<<1) +#define WIFI_STATIS_HW (1<<2) +#define WIFI_STATIS_DIAG (1<<3) +#define WIFI_STATIS_ALL (-1) + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/espcoredump/include/esp_core_dump.h b/tools/sdk/esp32/include/espcoredump/include/esp_core_dump.h index 7d8d56c5..2a6c1093 100644 --- a/tools/sdk/esp32/include/espcoredump/include/esp_core_dump.h +++ b/tools/sdk/esp32/include/espcoredump/include/esp_core_dump.h @@ -17,6 +17,7 @@ #include #include "esp_err.h" #include "freertos/xtensa_context.h" +#include "esp_private/panic_internal.h" /**************************************************************************************/ /******************************** EXCEPTION MODE API **********************************/ @@ -46,7 +47,7 @@ void esp_core_dump_init(void); * The structure of core dump data is described below in details. * 1) Core dump starts with header: * 1.1) TOTAL_LEN is total length of core dump data in flash including CRC. Size is 4 bytes. - * 1.2) VERSION field keeps 4 byte version of core dump. + * 1.2) VERSION field keeps 4 byte version of core dump. * 1.2) TASKS_NUM is the number of tasks for which data are stored. Size is 4 bytes. * 1.3) TCB_SIZE is the size of task's TCB structure. Size is 4 bytes. * 2) Core dump header is followed by the data for every task in the system. @@ -58,7 +59,7 @@ void esp_core_dump_init(void); * 4) Task's stack is placed after TCB data. Size is (STACK_END - STACK_TOP) bytes. * 5) CRC is placed at the end of the data. */ -void esp_core_dump_to_flash(XtExcFrame *frame); +void esp_core_dump_to_flash(panic_info_t *info); /** * @brief Print base64-encoded core dump to UART. @@ -68,7 +69,7 @@ void esp_core_dump_to_flash(XtExcFrame *frame); * 2) Since CRC is omitted TOTAL_LEN does not include its size. * 3) Printed base64 data are surrounded with special messages to help user recognize the start and end of actual data. */ -void esp_core_dump_to_uart(XtExcFrame *frame); +void esp_core_dump_to_uart(panic_info_t *info); /**************************************************************************************/ /*********************************** USER MODE API ************************************/ diff --git a/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_common.h b/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_common.h index b44296b3..b6836ba7 100644 --- a/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_common.h +++ b/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_common.h @@ -23,7 +23,7 @@ extern "C" { #endif #define MB_CONTROLLER_STACK_SIZE (CONFIG_FMB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller -#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_SERIAL_TASK_PRIO - 1) // priority of MB controller task +#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_PORT_TASK_PRIO - 1) // priority of MB controller task // Default port defines #define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus @@ -67,8 +67,9 @@ typedef enum MB_PORT_SERIAL_MASTER = 0x00, /*!< Modbus port type serial master. */ MB_PORT_SERIAL_SLAVE, /*!< Modbus port type serial slave. */ MB_PORT_TCP_MASTER, /*!< Modbus port type TCP master. */ - MB_PORT_TCP_SLAVE, /*!< Modbus port type TCP slave. */ - MB_PORT_COUNT /*!< Modbus port count. */ + MB_PORT_TCP_SLAVE, /*!< Modbus port type TCP slave. */ + MB_PORT_COUNT, /*!< Modbus port count. */ + MB_PORT_INACTIVE = 0xFF } mb_port_type_t; /** @@ -104,8 +105,17 @@ typedef enum { typedef enum { MB_MODE_RTU, /*!< RTU transmission mode. */ MB_MODE_ASCII, /*!< ASCII transmission mode. */ - MB_MODE_TCP /*!< TCP mode. */ -} mb_mode_type_t; // Todo: This is common type leave it here for now + MB_MODE_TCP, /*!< TCP communication mode. */ + MB_MODE_UDP /*!< UDP communication mode. */ +} mb_mode_type_t; + +/*! + * \brief Modbus TCP type of address. + */ +typedef enum { + MB_IPV4 = 0, /*!< TCP IPV4 addressing */ + MB_IPV6 = 1 /*!< TCP IPV6 addressing */ +} mb_tcp_addr_type_t; /** * @brief Device communication structure to setup Modbus controller @@ -120,27 +130,27 @@ typedef union { uart_parity_t parity; /*!< Modbus UART parity settings */ uint16_t dummy_port; /*!< Dummy field, unused */ }; - // Tcp communication structure + // TCP/UDP communication structure struct { - mb_mode_type_t tcp_mode; /*!< Modbus communication mode */ - uint8_t dummy_addr; /*!< Modbus slave address field (dummy for master) */ - uart_port_t dummy_uart_port; /*!< Modbus communication port (UART) number */ - uint32_t dummy_baudrate; /*!< Modbus baudrate */ - uart_parity_t dummy_parity; /*!< Modbus UART parity settings */ - uint16_t tcp_port; /*!< Modbus TCP port */ + mb_mode_type_t ip_mode; /*!< Modbus communication mode */ + uint16_t ip_port; /*!< Modbus port */ + mb_tcp_addr_type_t ip_addr_type; /*!< Modbus address type */ + void* ip_addr; /*!< Modbus address table for connection */ + void* ip_netif_ptr; /*!< Modbus network interface */ }; } mb_communication_info_t; /** * common interface method types */ -typedef esp_err_t (*iface_init)(mb_port_type_t, void**); /*!< Interface method init */ -typedef esp_err_t (*iface_destroy)(void); /*!< Interface method destroy */ -typedef esp_err_t (*iface_setup)(void*); /*!< Interface method setup */ -typedef esp_err_t (*iface_start)(void); /*!< Interface method start */ +typedef esp_err_t (*iface_init)(void**); /*!< Interface method init */ +typedef esp_err_t (*iface_destroy)(void); /*!< Interface method destroy */ +typedef esp_err_t (*iface_setup)(void*); /*!< Interface method setup */ +typedef esp_err_t (*iface_start)(void); /*!< Interface method start */ #ifdef __cplusplus } #endif #endif // _MB_IFACE_COMMON_H + diff --git a/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_master.h b/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_master.h index 7b87ffaa..bb7dc7a0 100644 --- a/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_master.h +++ b/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_master.h @@ -107,18 +107,39 @@ typedef struct { uint16_t reg_size; /*!< Modbus number of registers */ } mb_param_request_t; -// Master interface public functions /** - * @brief Initialize Modbus controller and stack + * @brief Initialize Modbus controller and stack for TCP port * * @param[out] handler handler(pointer) to master data structure - * @param[in] port_type the type of port * @return - * - ESP_OK Success - * - ESP_ERR_NO_MEM Parameter error + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure + */ +esp_err_t mbc_master_init_tcp(void** handler); + +/** + * @brief Initialize Modbus Master controller and stack for Serial port + * + * @param[out] handler handler(pointer) to master data structure + * @param[in] port_type type of stack + * @return + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure */ esp_err_t mbc_master_init(mb_port_type_t port_type, void** handler); +/** + * @brief Initialize Modbus Master controller interface handle + * + * @param[in] handler - pointer to master data structure + * @return None + */ +void mbc_master_init_iface(void* handler); + /** * @brief Destroy Modbus controller and stack * diff --git a/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_slave.h b/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_slave.h index 1f911450..ed6a12ed 100644 --- a/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_slave.h +++ b/tools/sdk/esp32/include/freemodbus/common/include/esp_modbus_slave.h @@ -50,17 +50,38 @@ typedef struct { } mb_register_area_descriptor_t; /** - * @brief Initialize Modbus controller and stack + * @brief Initialize Modbus Slave controller and stack for TCP port * * @param[out] handler handler(pointer) to master data structure - * @param[in] port_type type of stack * @return - * - ESP_OK Success - * - ESP_ERR_NO_MEM Parameter error + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure + */ +esp_err_t mbc_slave_init_tcp(void** handler); + +/** + * @brief Initialize Modbus Slave controller and stack for Serial port + * + * @param[out] handler handler(pointer) to master data structure + * @param[in] port_type the type of port + * @return + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure */ -//esp_err_t mbc_slave_init(mb_port_type_t port_type, void** handler); esp_err_t mbc_slave_init(mb_port_type_t port_type, void** handler); +/** + * @brief Initialize Modbus Slave controller interface handle + * + * @param[in] handler - pointer to slave interface data structure + * @return None + */ +void mbc_slave_init_iface(void* handler); + /** * @brief Destroy Modbus controller and stack * diff --git a/tools/sdk/esp32/include/freemodbus/common/include/mbcontroller.h b/tools/sdk/esp32/include/freemodbus/common/include/mbcontroller.h index 3b73d676..08b3c183 100644 --- a/tools/sdk/esp32/include/freemodbus/common/include/mbcontroller.h +++ b/tools/sdk/esp32/include/freemodbus/common/include/mbcontroller.h @@ -30,4 +30,3 @@ #include "esp_modbus_slave.h" #endif - diff --git a/tools/sdk/esp32/include/freertos/include/freertos/task.h b/tools/sdk/esp32/include/freertos/include/freertos/task.h index 46863304..cfea1f0a 100644 --- a/tools/sdk/esp32/include/freertos/include/freertos/task.h +++ b/tools/sdk/esp32/include/freertos/include/freertos/task.h @@ -199,8 +199,6 @@ typedef struct xTASK_SNAPSHOT StackType_t *pxTopOfStack; /*!< Points to the location of the last item placed on the tasks stack. */ StackType_t *pxEndOfStack; /*!< Points to the end of the stack. pxTopOfStack < pxEndOfStack, stack grows hi2lo pxTopOfStack > pxEndOfStack, stack grows lo2hi*/ - eTaskState eState; /*!< Current state of the task. Can be running or suspended */ - BaseType_t xCpuId; /*!< CPU where this task was running */ } TaskSnapshot_t; /** diff --git a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h index 51cbcbce..6e589c67 100644 --- a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h +++ b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h @@ -120,8 +120,9 @@ int xt_clock_freq(void) __attribute__((deprecated)); /* configASSERT behaviour */ #ifndef __ASSEMBLER__ #include /* for abort() */ +#include "esp_rom_sys.h" #if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" +#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" #endif @@ -129,20 +130,20 @@ int xt_clock_freq(void) __attribute__((deprecated)); #if defined(CONFIG_FREERTOS_ASSERT_DISABLE) #define configASSERT(a) /* assertions disabled */ #elif defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE) -#define configASSERT(a) if (unlikely(!(a))) { \ - ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ - __FUNCTION__); \ +#define configASSERT(a) if (unlikely(!(a))) { \ + esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__); \ } #else /* CONFIG_FREERTOS_ASSERT_FAIL_ABORT */ -#define configASSERT(a) if (unlikely(!(a))) { \ - ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ - __FUNCTION__); \ - abort(); \ +#define configASSERT(a) if (unlikely(!(a))) { \ + esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__); \ + abort(); \ } #endif #if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION -#define UNTESTED_FUNCTION() { ets_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0) +#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0) #else #define UNTESTED_FUNCTION() #endif @@ -181,21 +182,30 @@ int xt_clock_freq(void) __attribute__((deprecated)); #define configMAX_PRIORITIES ( 25 ) #endif -#ifndef CONFIG_APPTRACE_ENABLE -#define configMINIMAL_STACK_SIZE 768 -#else +#if defined(CONFIG_APPTRACE_ENABLE) /* apptrace module requires at least 2KB of stack per task */ #define configMINIMAL_STACK_SIZE 2048 +#elif defined(CONFIG_COMPILER_OPTIMIZATION_NONE) +/* with optimizations disabled, scheduler uses additional stack */ +#define configMINIMAL_STACK_SIZE 1024 +#else +#define configMINIMAL_STACK_SIZE 768 #endif #ifndef configIDLE_TASK_STACK_SIZE #define configIDLE_TASK_STACK_SIZE CONFIG_FREERTOS_IDLE_TASK_STACKSIZE #endif -/* The Xtensa port uses a separate interrupt stack. Adjust the stack size */ -/* to suit the needs of your specific application. */ +/* Stack alignment, architecture specifc. Must be a power of two. */ +#define configSTACK_ALIGNMENT 16 + +/* The Xtensa port uses a separate interrupt stack. Adjust the stack size + * to suit the needs of your specific application. + * Size needs to be aligned to the stack increment, since the location of + * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. + */ #ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE CONFIG_FREERTOS_ISR_STACKSIZE +#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) #endif /* Minimal heap size to make sure examples can run on memory limited diff --git a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/portmacro.h b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/portmacro.h index 979ffeca..9c00fa16 100644 --- a/tools/sdk/esp32/include/freertos/xtensa/include/freertos/portmacro.h +++ b/tools/sdk/esp32/include/freertos/xtensa/include/freertos/portmacro.h @@ -84,7 +84,7 @@ extern "C" { #include "esp_timer.h" /* required for FreeRTOS run time stats */ #include "soc/spinlock.h" #include - +#include "esp_rom_sys.h" #include "sdkconfig.h" #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS @@ -225,22 +225,22 @@ static inline void __attribute__((always_inline)) vPortEnterCriticalCompliance(p { if(!xPortInIsrContext()) { vPortEnterCritical(mux); - } else { - ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, - __FUNCTION__); - abort(); - } + } else { + esp_rom_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", + __FILE__, __LINE__, __FUNCTION__); + abort(); + } } static inline void __attribute__((always_inline)) vPortExitCriticalCompliance(portMUX_TYPE *mux) { if(!xPortInIsrContext()) { vPortExitCritical(mux); - } else { - ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, - __FUNCTION__); - abort(); - } + } else { + esp_rom_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", + __FILE__, __LINE__, __FUNCTION__); + abort(); + } } #ifdef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE diff --git a/tools/sdk/esp32/include/idf_test/include/esp32/idf_performance_target.h b/tools/sdk/esp32/include/idf_test/include/esp32/idf_performance_target.h index 92173862..2e906b02 100644 --- a/tools/sdk/esp32/include/idf_test/include/esp32/idf_performance_target.h +++ b/tools/sdk/esp32/include/idf_test/include/esp32/idf_performance_target.h @@ -18,6 +18,18 @@ #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27 +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (359*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600 +#endif + // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/tools/sdk/esp32/include/idf_test/include/esp32s2/idf_performance_target.h b/tools/sdk/esp32/include/idf_test/include/esp32s2/idf_performance_target.h index 64ba9293..ba29e146 100644 --- a/tools/sdk/esp32/include/idf_test/include/esp32s2/idf_performance_target.h +++ b/tools/sdk/esp32/include/idf_test/include/esp32s2/idf_performance_target.h @@ -7,7 +7,7 @@ #define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90.0 // esp_sha() time to process 32KB of input data from RAM #define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 900 -#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 800 +#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 13500 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 130000 @@ -16,3 +16,15 @@ #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (309*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1504*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 52200 +#endif diff --git a/tools/sdk/esp32/include/idf_test/include/idf_performance.h b/tools/sdk/esp32/include/idf_test/include/idf_performance.h index 57d35ff3..4fb6364b 100644 --- a/tools/sdk/esp32/include/idf_test/include/idf_performance.h +++ b/tools/sdk/esp32/include/idf_test/include/idf_performance.h @@ -102,8 +102,9 @@ #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB (7088*1000) #endif +//This value is usually around 44K, but there are some chips with such low performance.... #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE 52200 +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE 12000 #endif #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B @@ -113,7 +114,7 @@ #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B 53600 #endif #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB (1015*1000) +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB (694*1000) #endif #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB (7797*1000) @@ -142,18 +143,12 @@ #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B 68900 #endif -#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (359*1000) -#endif +// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B in target file #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB (475*1000) #endif -#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) -#endif -#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 81300 -#endif +// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB in target file +// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE in target file //time to perform the task selection plus context switch (from task) #ifndef IDF_PERFORMANCE_MAX_SCHEDULING_TIME diff --git a/tools/sdk/esp32/include/log/include/esp_log.h b/tools/sdk/esp32/include/log/include/esp_log.h index cdbe74f6..1abc70c1 100644 --- a/tools/sdk/esp32/include/log/include/esp_log.h +++ b/tools/sdk/esp32/include/log/include/esp_log.h @@ -17,9 +17,10 @@ #include #include +#include "esp_rom_sys.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" +#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" #endif @@ -285,9 +286,9 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format, /// macro to output logs in startup code at ``ESP_LOG_VERBOSE`` level. @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf`` #define ESP_EARLY_LOGV( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__) -#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ - if (LOG_LOCAL_LEVEL >= log_level) { \ - ets_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \ +#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ + if (LOG_LOCAL_LEVEL >= log_level) { \ + esp_rom_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \ }} while(0) #ifndef BOOTLOADER_BUILD @@ -361,24 +362,24 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format, * * @note Placing log strings in DRAM reduces available DRAM, so only use when absolutely essential. * - * @see ``ets_printf``,``ESP_LOGE`` + * @see ``esp_rom_printf``,``ESP_LOGE`` */ #define ESP_DRAM_LOGE( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_ERROR, E, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_WARN`` level. @see ``ESP_DRAM_LOGW``,``ESP_LOGW``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_WARN`` level. @see ``ESP_DRAM_LOGW``,``ESP_LOGW``, ``esp_rom_printf`` #define ESP_DRAM_LOGW( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_WARN, W, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_INFO`` level. @see ``ESP_DRAM_LOGI``,``ESP_LOGI``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_INFO`` level. @see ``ESP_DRAM_LOGI``,``ESP_LOGI``, ``esp_rom_printf`` #define ESP_DRAM_LOGI( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_INFO, I, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_DEBUG`` level. @see ``ESP_DRAM_LOGD``,``ESP_LOGD``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_DEBUG`` level. @see ``ESP_DRAM_LOGD``,``ESP_LOGD``, ``esp_rom_printf`` #define ESP_DRAM_LOGD( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_DEBUG, D, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_VERBOSE`` level. @see ``ESP_DRAM_LOGV``,``ESP_LOGV``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_VERBOSE`` level. @see ``ESP_DRAM_LOGV``,``ESP_LOGV``, ``esp_rom_printf`` #define ESP_DRAM_LOGV( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__) /** @cond */ #define _ESP_LOG_DRAM_LOG_FORMAT(letter, format) DRAM_STR(#letter " %s: " format "\n") -#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ - if (LOG_LOCAL_LEVEL >= log_level) { \ - ets_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \ +#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ + if (LOG_LOCAL_LEVEL >= log_level) { \ + esp_rom_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \ }} while(0) /** @endcond */ diff --git a/tools/sdk/esp32/include/lwip/include/apps/ping/ping_sock.h b/tools/sdk/esp32/include/lwip/include/apps/ping/ping_sock.h index ef1189e8..f2581fdb 100644 --- a/tools/sdk/esp32/include/lwip/include/apps/ping/ping_sock.h +++ b/tools/sdk/esp32/include/lwip/include/apps/ping/ping_sock.h @@ -82,7 +82,7 @@ typedef struct { .count = 5, \ .interval_ms = 1000, \ .timeout_ms = 1000, \ - .data_size = 56, \ + .data_size = 64, \ .tos = 0, \ .target_addr = ip_addr_any_type, \ .task_stack_size = 2048, \ diff --git a/tools/sdk/esp32/include/lwip/lwip/src/include/lwip/opt.h b/tools/sdk/esp32/include/lwip/lwip/src/include/lwip/opt.h index 3a338d5a..cdd7044c 100644 --- a/tools/sdk/esp32/include/lwip/lwip/src/include/lwip/opt.h +++ b/tools/sdk/esp32/include/lwip/lwip/src/include/lwip/opt.h @@ -1534,6 +1534,11 @@ #define LWIP_ALTCP_TLS 0 #endif +#if ESP_LWIP +#if !defined LWIP_TCP_RTO_TIME || defined __DOXYGEN__ +#define LWIP_TCP_RTO_TIME 3000 +#endif +#endif /** * @} */ @@ -2585,6 +2590,14 @@ #define LWIP_ND6_QUEUEING LWIP_IPV6 #endif +/** + * ESP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address + * is being resolved. + */ +#if !defined ESP_ND6_QUEUEING || defined __DOXYGEN__ +#define ESP_ND6_QUEUEING LWIP_IPV6 +#endif + /** * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. */ diff --git a/tools/sdk/esp32/include/lwip/port/esp32/include/lwipopts.h b/tools/sdk/esp32/include/lwip/port/esp32/include/lwipopts.h index 978857d6..5e178a20 100644 --- a/tools/sdk/esp32/include/lwip/port/esp32/include/lwipopts.h +++ b/tools/sdk/esp32/include/lwip/port/esp32/include/lwipopts.h @@ -157,18 +157,32 @@ -------------------------------- */ /** - * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP4 packets. Note that * this option does not affect outgoing packet sizes, which can be controlled * via IP_FRAG. */ -#define IP_REASSEMBLY CONFIG_LWIP_IP_REASSEMBLY +#define IP_REASSEMBLY CONFIG_LWIP_IP4_REASSEMBLY /** - * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * LWIP_IPV6_REASS==1: reassemble incoming IP6 packets that fragmented. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via LWIP_IPV6_FRAG. + */ +#define LWIP_IPV6_REASS CONFIG_LWIP_IP6_REASSEMBLY + +/** + * IP_FRAG==1: Fragment outgoing IP4 packets if their size exceeds MTU. Note * that this option does not affect incoming packet sizes, which can be * controlled via IP_REASSEMBLY. */ -#define IP_FRAG CONFIG_LWIP_IP_FRAG +#define IP_FRAG CONFIG_LWIP_IP4_FRAG + +/** + * LWIP_IPV6_FRAG==1: Fragment outgoing IP6 packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#define LWIP_IPV6_FRAG CONFIG_LWIP_IP6_FRAG /** * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) @@ -400,6 +414,12 @@ #define TCP_RCV_SCALE CONFIG_LWIP_TCP_RCV_SCALE #endif +/** + * LWIP_TCP_RTO_TIME: TCP rto time. + * Default is 3 second. + */ +#define LWIP_TCP_RTO_TIME CONFIG_LWIP_TCP_RTO_TIME + /* ---------------------------------- ---------- Pbuf options ---------- @@ -454,6 +474,34 @@ ------------------------------------ */ +#ifdef CONFIG_LWIP_SLIP_SUPPORT + +/** + * Enable SLIP receive from ISR functions and disable Rx thread + * + * This is the only supported mode of lwIP SLIP interface, so that + * - incoming packets are queued into pbufs + * - no thread is created from lwIP + * meaning it is the application responsibility to read data + * from IO driver and feed them to the slip interface + */ +#define SLIP_RX_FROM_ISR 1 +#define SLIP_USE_RX_THREAD 0 + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#define SLIP_DEBUG_ON CONFIG_LWIP_SLIP_DEBUG_ON + +#if SLIP_DEBUG_ON +#define SLIP_DEBUG LWIP_DBG_ON +#else +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + + +#endif + /* ------------------------------------ ---------- Thread options ---------- @@ -704,6 +752,16 @@ */ #define LWIP_IPV6 1 +/** + * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. + */ +#define MEMP_NUM_ND6_QUEUE CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE + +/** + * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache + */ +#define LWIP_ND6_NUM_NEIGHBORS CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS + /* --------------------------------------- ---------- Hook options --------------- @@ -718,37 +776,82 @@ /** * ETHARP_DEBUG: Enable debugging in etharp.c. */ -#define ETHARP_DEBUG LWIP_DBG_OFF +#ifdef CONFIG_LWIP_ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_ON +#else +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + /** * NETIF_DEBUG: Enable debugging in netif.c. */ +#ifdef CONFIG_LWIP_NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_ON +#else #define NETIF_DEBUG LWIP_DBG_OFF +#endif /** * PBUF_DEBUG: Enable debugging in pbuf.c. */ -#define PBUF_DEBUG LWIP_DBG_OFF +#ifdef CONFIG_LWIP_PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_ON +#else +#define PBUF_DEBUG LWIP_DBG_OFF +#endif /** * API_LIB_DEBUG: Enable debugging in api_lib.c. */ -#define API_LIB_DEBUG LWIP_DBG_OFF +#ifdef CONFIG_LWIP_API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_ON +#else +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + /** * SOCKETS_DEBUG: Enable debugging in sockets.c. */ +#ifdef CONFIG_LWIP_SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_ON +#else #define SOCKETS_DEBUG LWIP_DBG_OFF +#endif /** * ICMP_DEBUG: Enable debugging in icmp.c. */ +#ifdef CONFIG_LWIP_ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_ON +#else #define ICMP_DEBUG LWIP_DBG_OFF +#endif + +#ifdef CONFIG_LWIP_ICMP6_DEBUG +#define ICMP6_DEBUG LWIP_DBG_ON +#else +#define ICMP6_DEBUG LWIP_DBG_OFF +#endif /** * IP_DEBUG: Enable debugging for IP. */ +#ifdef CONFIG_LWIP_IP_DEBUG +#define IP_DEBUG LWIP_DBG_ON +#else #define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifdef CONFIG_LWIP_IP6_DEBUG +#define IP6_DEBUG LWIP_DBG_ON +#else +#define IP6_DEBUG LWIP_DBG_OFF +#endif /** * MEMP_DEBUG: Enable debugging in memp.c. diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bignum.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bignum.h index 1fb3dd7b..1e41d702 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bignum.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bignum.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BIGNUM_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h index 748975ea..42339b7b 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ /* diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/check_config.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/check_config.h index d076c235..8ce73cef 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/check_config.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/check_config.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ @@ -140,6 +167,16 @@ #error "MBEDTLS_ECP_C defined, but not all prerequisites" #endif +#if defined(MBEDTLS_ECP_C) && !( \ + defined(MBEDTLS_ECP_ALT) || \ + defined(MBEDTLS_CTR_DRBG_C) || \ + defined(MBEDTLS_HMAC_DRBG_C) || \ + defined(MBEDTLS_SHA512_C) || \ + defined(MBEDTLS_SHA256_C) || \ + defined(MBEDTLS_ECP_NO_INTERNAL_RNG)) +#error "MBEDTLS_ECP_C requires a DRBG or SHA-2 module unless MBEDTLS_ECP_NO_INTERNAL_RNG is defined or an alternative implementation is used" +#endif + #if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_ASN1_PARSE_C) #error "MBEDTLS_PK_PARSE_C defined, but not all prerequesites" #endif @@ -546,6 +583,23 @@ #error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites" #endif +#if (defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2)) && \ + !(defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) ) +#error "One or more versions of the TLS protocol are enabled " \ + "but no key exchange methods defined with MBEDTLS_KEY_EXCHANGE_xxxx" +#endif + #if defined(MBEDTLS_SSL_PROTO_DTLS) && \ !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \ !defined(MBEDTLS_SSL_PROTO_TLS1_2) @@ -669,6 +723,10 @@ #error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites" #endif +#if defined(MBEDTLS_CERTS_C) && !defined(MBEDTLS_X509_USE_C) +#error "MBEDTLS_CERTS_C defined, but not all prerequisites" +#endif + #if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) #error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites" #endif diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/config.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/config.h index 834cced8..f7e55aef 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/config.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/config.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ @@ -780,6 +807,28 @@ */ #define MBEDTLS_ECP_NIST_OPTIM +/** + * \def MBEDTLS_ECP_NO_INTERNAL_RNG + * + * When this option is disabled, mbedtls_ecp_mul() will make use of an + * internal RNG when called with a NULL \c f_rng argument, in order to protect + * against some side-channel attacks. + * + * This protection introduces a dependency of the ECP module on one of the + * DRBG or SHA modules (HMAC-DRBG, CTR-DRBG, SHA-512 or SHA-256.) For very + * constrained applications that don't require this protection (for example, + * because you're only doing signature verification, so not manipulating any + * secret, or because local/physical side-channel attacks are outside your + * threat model), it might be desirable to get rid of that dependency. + * + * \warning Enabling this option makes some uses of ECP vulnerable to some + * side-channel attacks. Only enable it if you know that's not a problem for + * your use case. + * + * Uncomment this macro to disable some counter-measures in ECP. + */ +//#define MBEDTLS_ECP_NO_INTERNAL_RNG + /** * \def MBEDTLS_ECP_RESTARTABLE * diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h index e0b5ed9c..894fa171 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h @@ -39,7 +39,13 @@ */ /* * Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -53,6 +59,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h index 932acc6d..bc219dca 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h @@ -12,7 +12,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -26,6 +32,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hkdf.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hkdf.h index bcafe425..a8db554d 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hkdf.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hkdf.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2016-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HKDF_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h index 7931c228..231fb459 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HMAC_DRBG_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/pk.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/pk.h index 13642750..408f7bae 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/pk.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/pk.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/platform_util.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/platform_util.h index 09d09651..f10574af 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/platform_util.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/platform_util.h @@ -6,7 +6,13 @@ */ /* * Copyright (C) 2018, Arm Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -20,6 +26,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_UTIL_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/rsa.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/rsa.h index 35bacd87..cd22fc4c 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/rsa.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/rsa.h @@ -11,7 +11,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -25,6 +31,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_RSA_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl.h index 1adf9608..6f569835 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_H @@ -123,6 +150,7 @@ #define MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS -0x6500 /**< The asynchronous operation is not completed yet. */ #define MBEDTLS_ERR_SSL_EARLY_MESSAGE -0x6480 /**< Internal-only message signaling that a message arrived early. */ #define MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS -0x7000 /**< A cryptographic operation is in progress. Try again later. */ +#define MBEDTLS_ERR_SSL_BAD_CONFIG -0x5E80 /**< Invalid value in SSL config */ /* * Various constants @@ -137,6 +165,9 @@ #define MBEDTLS_SSL_TRANSPORT_DATAGRAM 1 /*!< DTLS */ #define MBEDTLS_SSL_MAX_HOST_NAME_LEN 255 /*!< Maximum host name defined in RFC 1035 */ +#define MBEDTLS_SSL_MAX_ALPN_NAME_LEN 255 /*!< Maximum size in bytes of a protocol name in alpn ext., RFC 7301 */ + +#define MBEDTLS_SSL_MAX_ALPN_LIST_LEN 65535 /*!< Maximum size in bytes of list in alpn ext., RFC 7301 */ /* RFC 6066 section 4, see also mfl_code_to_length in ssl_tls.c * NONE must be zero so that memset()ing structure to zero works */ diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h index 774a007a..ac3be043 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_TICKET_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/version.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/version.h index 8e2ce03c..2bff31d5 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/version.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/version.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ /* @@ -40,16 +67,16 @@ */ #define MBEDTLS_VERSION_MAJOR 2 #define MBEDTLS_VERSION_MINOR 16 -#define MBEDTLS_VERSION_PATCH 5 +#define MBEDTLS_VERSION_PATCH 7 /** * The single version number has the following structure: * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x02100500 -#define MBEDTLS_VERSION_STRING "2.16.5" -#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.5" +#define MBEDTLS_VERSION_NUMBER 0x02100700 +#define MBEDTLS_VERSION_STRING "2.16.7" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.7" #if defined(MBEDTLS_VERSION_C) diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509.h index 63aae32d..e9f2fc60 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_H diff --git a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h index fa838d68..0e37f65e 100644 --- a/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h +++ b/tools/sdk/esp32/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CRL_H diff --git a/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h b/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h index 93c8ce28..60826e6c 100644 --- a/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h +++ b/tools/sdk/esp32/include/mbedtls/port/include/mbedtls/esp_config.h @@ -976,6 +976,8 @@ */ #ifdef CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 #define MBEDTLS_SSL_PROTO_TLS1_1 +#else +#undef MBEDTLS_SSL_PROTO_TLS1_1 #endif /** diff --git a/tools/sdk/esp32/include/newlib/platform_include/esp_newlib.h b/tools/sdk/esp32/include/newlib/platform_include/esp_newlib.h index 11658776..c43d6ec2 100644 --- a/tools/sdk/esp32/include/newlib/platform_include/esp_newlib.h +++ b/tools/sdk/esp32/include/newlib/platform_include/esp_newlib.h @@ -17,6 +17,11 @@ #include +/* + * Initialize newlib time functions + */ +void esp_newlib_time_init(void); + /** * Replacement for newlib's _REENT_INIT_PTR and __sinit. * diff --git a/tools/sdk/esp32/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h b/tools/sdk/esp32/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h index 1c74b35c..9be6eea5 100644 --- a/tools/sdk/esp32/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h +++ b/tools/sdk/esp32/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h @@ -28,7 +28,12 @@ /* Define WIN32 when build target is Win32 API (borrowed from libcurl) */ #if (defined(_WIN32) || defined(__WIN32__)) && !defined(WIN32) -#define WIN32 +# define WIN32 +#endif + +/* Compatibility for non-Clang compilers */ +#ifndef __has_declspec_attribute +# define __has_declspec_attribute(x) 0 #endif #ifdef __cplusplus @@ -40,9 +45,9 @@ extern "C" { /* MSVC < 2013 does not have inttypes.h because it is not C99 compliant. See compiler macros and version number in https://sourceforge.net/p/predef/wiki/Compilers/ */ -#include +# include #else /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */ -#include +# include #endif /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */ #include #include @@ -50,20 +55,21 @@ extern "C" { #include #ifdef NGHTTP2_STATICLIB -#define NGHTTP2_EXTERN -#elif defined(WIN32) -#ifdef BUILDING_NGHTTP2 -#define NGHTTP2_EXTERN __declspec(dllexport) -#else /* !BUILDING_NGHTTP2 */ -#define NGHTTP2_EXTERN __declspec(dllimport) -#endif /* !BUILDING_NGHTTP2 */ -#else /* !defined(WIN32) */ -#ifdef BUILDING_NGHTTP2 -#define NGHTTP2_EXTERN __attribute__((visibility("default"))) -#else /* !BUILDING_NGHTTP2 */ -#define NGHTTP2_EXTERN -#endif /* !BUILDING_NGHTTP2 */ -#endif /* !defined(WIN32) */ +# define NGHTTP2_EXTERN +#elif defined(WIN32) || (__has_declspec_attribute(dllexport) && \ + __has_declspec_attribute(dllimport)) +# ifdef BUILDING_NGHTTP2 +# define NGHTTP2_EXTERN __declspec(dllexport) +# else /* !BUILDING_NGHTTP2 */ +# define NGHTTP2_EXTERN __declspec(dllimport) +# endif /* !BUILDING_NGHTTP2 */ +#else /* !defined(WIN32) */ +# ifdef BUILDING_NGHTTP2 +# define NGHTTP2_EXTERN __attribute__((visibility("default"))) +# else /* !BUILDING_NGHTTP2 */ +# define NGHTTP2_EXTERN +# endif /* !BUILDING_NGHTTP2 */ +#endif /* !defined(WIN32) */ /** * @macro @@ -222,6 +228,13 @@ typedef struct { */ #define NGHTTP2_CLIENT_MAGIC_LEN 24 +/** + * @macro + * + * The default max number of settings per SETTINGS frame + */ +#define NGHTTP2_DEFAULT_MAX_SETTINGS 32 + /** * @enum * @@ -387,6 +400,16 @@ typedef enum { * Indicates that a processing was canceled. */ NGHTTP2_ERR_CANCEL = -535, + /** + * When a local endpoint expects to receive SETTINGS frame, it + * receives an other type of frame. + */ + NGHTTP2_ERR_SETTINGS_EXPECTED = -536, + /** + * When a local endpoint receives too many settings entries + * in a single SETTINGS frame. + */ + NGHTTP2_ERR_TOO_MANY_SETTINGS = -537, /** * The errors < :enum:`NGHTTP2_ERR_FATAL` mean that the library is * under unexpected condition and processing was terminated (e.g., @@ -469,6 +492,15 @@ NGHTTP2_EXTERN void nghttp2_rcbuf_decref(nghttp2_rcbuf *rcbuf); */ NGHTTP2_EXTERN nghttp2_vec nghttp2_rcbuf_get_buf(nghttp2_rcbuf *rcbuf); +/** + * @function + * + * Returns nonzero if the underlying buffer is statically allocated, + * and 0 otherwise. This can be useful for language bindings that wish + * to avoid creating duplicate strings for these buffers. + */ +NGHTTP2_EXTERN int nghttp2_rcbuf_is_static(const nghttp2_rcbuf *rcbuf); + /** * @enum * @@ -597,7 +629,12 @@ typedef enum { * The ALTSVC frame, which is defined in `RFC 7383 * `_. */ - NGHTTP2_ALTSVC = 0x0a + NGHTTP2_ALTSVC = 0x0a, + /** + * The ORIGIN frame, which is defined by `RFC 8336 + * `_. + */ + NGHTTP2_ORIGIN = 0x0c } nghttp2_frame_type; /** @@ -661,7 +698,12 @@ typedef enum { /** * SETTINGS_MAX_HEADER_LIST_SIZE */ - NGHTTP2_SETTINGS_MAX_HEADER_LIST_SIZE = 0x06 + NGHTTP2_SETTINGS_MAX_HEADER_LIST_SIZE = 0x06, + /** + * SETTINGS_ENABLE_CONNECT_PROTOCOL + * (`RFC 8441 `_) + */ + NGHTTP2_SETTINGS_ENABLE_CONNECT_PROTOCOL = 0x08 } nghttp2_settings_id; /* Note: If we add SETTINGS, update the capacity of NGHTTP2_INBOUND_NUM_IV as well */ @@ -1978,6 +2020,9 @@ typedef ssize_t (*nghttp2_pack_extension_callback)(nghttp2_session *session, * of length |len|. |len| does not include the sentinel NULL * character. * + * This function is deprecated. The new application should use + * :type:`nghttp2_error_callback2`. + * * The format of error message may change between nghttp2 library * versions. The application should not depend on the particular * format. @@ -1994,6 +2039,33 @@ typedef ssize_t (*nghttp2_pack_extension_callback)(nghttp2_session *session, typedef int (*nghttp2_error_callback)(nghttp2_session *session, const char *msg, size_t len, void *user_data); +/** + * @functypedef + * + * Callback function invoked when library provides the error code, and + * message. This callback is solely for debugging purpose. + * |lib_error_code| is one of error code defined in + * :enum:`nghttp2_error`. The |msg| is typically NULL-terminated + * string of length |len|, and intended for human consumption. |len| + * does not include the sentinel NULL character. + * + * The format of error message may change between nghttp2 library + * versions. The application should not depend on the particular + * format. + * + * Normally, application should return 0 from this callback. If fatal + * error occurred while doing something in this callback, application + * should return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`. In this case, + * library will return immediately with return value + * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`. Currently, if nonzero value + * is returned from this callback, they are treated as + * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`, but application should not + * rely on this details. + */ +typedef int (*nghttp2_error_callback2)(nghttp2_session *session, + int lib_error_code, const char *msg, + size_t len, void *user_data); + struct nghttp2_session_callbacks; /** @@ -2258,10 +2330,30 @@ nghttp2_session_callbacks_set_on_extension_chunk_recv_callback( * * Sets callback function invoked when library tells error message to * the application. + * + * This function is deprecated. The new application should use + * `nghttp2_session_callbacks_set_error_callback2()`. + * + * If both :type:`nghttp2_error_callback` and + * :type:`nghttp2_error_callback2` are set, the latter takes + * precedence. */ NGHTTP2_EXTERN void nghttp2_session_callbacks_set_error_callback( nghttp2_session_callbacks *cbs, nghttp2_error_callback error_callback); +/** + * @function + * + * Sets callback function invoked when library tells error code, and + * message to the application. + * + * If both :type:`nghttp2_error_callback` and + * :type:`nghttp2_error_callback2` are set, the latter takes + * precedence. + */ +NGHTTP2_EXTERN void nghttp2_session_callbacks_set_error_callback2( + nghttp2_session_callbacks *cbs, nghttp2_error_callback2 error_callback2); + /** * @functypedef * @@ -2409,15 +2501,15 @@ nghttp2_option_set_no_auto_window_update(nghttp2_option *option, int val); * * This option sets the SETTINGS_MAX_CONCURRENT_STREAMS value of * remote endpoint as if it is received in SETTINGS frame. Without - * specifying this option, before the local endpoint receives - * SETTINGS_MAX_CONCURRENT_STREAMS in SETTINGS frame from remote - * endpoint, SETTINGS_MAX_CONCURRENT_STREAMS is unlimited. This may - * cause problem if local endpoint submits lots of requests initially - * and sending them at once to the remote peer may lead to the - * rejection of some requests. Specifying this option to the sensible - * value, say 100, may avoid this kind of issue. This value will be - * overwritten if the local endpoint receives - * SETTINGS_MAX_CONCURRENT_STREAMS from the remote endpoint. + * specifying this option, the maximum number of outgoing concurrent + * streams is initially limited to 100 to avoid issues when the local + * endpoint submits lots of requests before receiving initial SETTINGS + * frame from the remote endpoint, since sending them at once to the + * remote endpoint could lead to rejection of some of the requests. + * This value will be overwritten when the local endpoint receives + * initial SETTINGS frame from the remote endpoint, either to the + * value advertised in SETTINGS_MAX_CONCURRENT_STREAMS or to the + * default value (unlimited) if none was advertised. */ NGHTTP2_EXTERN void nghttp2_option_set_peer_max_concurrent_streams(nghttp2_option *option, @@ -2568,6 +2660,28 @@ nghttp2_option_set_max_deflate_dynamic_table_size(nghttp2_option *option, NGHTTP2_EXTERN void nghttp2_option_set_no_closed_streams(nghttp2_option *option, int val); +/** + * @function + * + * This function sets the maximum number of outgoing SETTINGS ACK and + * PING ACK frames retained in :type:`nghttp2_session` object. If + * more than those frames are retained, the peer is considered to be + * misbehaving and session will be closed. The default value is 1000. + */ +NGHTTP2_EXTERN void nghttp2_option_set_max_outbound_ack(nghttp2_option *option, + size_t val); + +/** + * @function + * + * This function sets the maximum number of SETTINGS entries per + * SETTINGS frame that will be accepted. If more than those entries + * are received, the peer is considered to be misbehaving and session + * will be closed. The default value is 32. + */ +NGHTTP2_EXTERN void nghttp2_option_set_max_settings(nghttp2_option *option, + size_t val); + /** * @function * @@ -3017,6 +3131,16 @@ NGHTTP2_EXTERN int nghttp2_session_set_stream_user_data(nghttp2_session *session, int32_t stream_id, void *stream_user_data); +/** + * @function + * + * Sets |user_data| to |session|, overwriting the existing user data + * specified in `nghttp2_session_client_new()`, or + * `nghttp2_session_server_new()`. + */ +NGHTTP2_EXTERN void nghttp2_session_set_user_data(nghttp2_session *session, + void *user_data); + /** * @function * @@ -3723,10 +3847,13 @@ nghttp2_priority_spec_check_default(const nghttp2_priority_spec *pri_spec); * .. warning:: * * This function returns assigned stream ID if it succeeds. But - * that stream is not opened yet. The application must not submit + * that stream is not created yet. The application must not submit * frame to that stream ID before * :type:`nghttp2_before_frame_send_callback` is called for this - * frame. + * frame. This means `nghttp2_session_get_stream_user_data()` does + * not work before the callback. But + * `nghttp2_session_set_stream_user_data()` handles this situation + * specially, and it can set data to a stream during this period. * */ NGHTTP2_EXTERN int32_t nghttp2_submit_request( @@ -4442,8 +4569,7 @@ typedef struct { * Submits ALTSVC frame. * * ALTSVC frame is a non-critical extension to HTTP/2, and defined in - * is defined in `RFC 7383 - * `_. + * `RFC 7383 `_. * * The |flags| is currently ignored and should be * :enum:`NGHTTP2_FLAG_NONE`. @@ -4477,6 +4603,81 @@ NGHTTP2_EXTERN int nghttp2_submit_altsvc(nghttp2_session *session, const uint8_t *field_value, size_t field_value_len); +/** + * @struct + * + * The single entry of an origin. + */ +typedef struct { + /** + * The pointer to origin. No validation is made against this field + * by the library. This is not necessarily NULL-terminated. + */ + uint8_t *origin; + /** + * The length of the |origin|. + */ + size_t origin_len; +} nghttp2_origin_entry; + +/** + * @struct + * + * The payload of ORIGIN frame. ORIGIN frame is a non-critical + * extension to HTTP/2 and defined by `RFC 8336 + * `_. + * + * If this frame is received, and + * `nghttp2_option_set_user_recv_extension_type()` is not set, and + * `nghttp2_option_set_builtin_recv_extension_type()` is set for + * :enum:`NGHTTP2_ORIGIN`, ``nghttp2_extension.payload`` will point to + * this struct. + * + * It has the following members: + */ +typedef struct { + /** + * The number of origins contained in |ov|. + */ + size_t nov; + /** + * The pointer to the array of origins contained in ORIGIN frame. + */ + nghttp2_origin_entry *ov; +} nghttp2_ext_origin; + +/** + * @function + * + * Submits ORIGIN frame. + * + * ORIGIN frame is a non-critical extension to HTTP/2 and defined by + * `RFC 8336 `_. + * + * The |flags| is currently ignored and should be + * :enum:`NGHTTP2_FLAG_NONE`. + * + * The |ov| points to the array of origins. The |nov| specifies the + * number of origins included in |ov|. This function creates copies + * of all elements in |ov|. + * + * The ORIGIN frame is only usable by a server. If this function is + * invoked with client side session, this function returns + * :enum:`NGHTTP2_ERR_INVALID_STATE`. + * + * :enum:`NGHTTP2_ERR_NOMEM` + * Out of memory + * :enum:`NGHTTP2_ERR_INVALID_STATE` + * The function is called from client side session. + * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT` + * There are too many origins, or an origin is too large to fit + * into a default frame payload. + */ +NGHTTP2_EXTERN int nghttp2_submit_origin(nghttp2_session *session, + uint8_t flags, + const nghttp2_origin_entry *ov, + size_t nov); + /** * @function * @@ -4591,6 +4792,19 @@ NGHTTP2_EXTERN int nghttp2_check_header_name(const uint8_t *name, size_t len); */ NGHTTP2_EXTERN int nghttp2_check_header_value(const uint8_t *value, size_t len); +/** + * @function + * + * Returns nonzero if the |value| which is supposed to the value of + * :authority or host header field is valid according to + * https://tools.ietf.org/html/rfc3986#section-3.2 + * + * |value| is valid if it merely consists of the allowed characters. + * In particular, it does not check whether |value| follows the syntax + * of authority. + */ +NGHTTP2_EXTERN int nghttp2_check_authority(const uint8_t *value, size_t len); + /* HPACK API */ struct nghttp2_hd_deflater; @@ -4693,8 +4907,8 @@ nghttp2_hd_deflate_change_table_size(nghttp2_hd_deflater *deflater, * * After this function returns, it is safe to delete the |nva|. * - * This function returns 0 if it succeeds, or one of the following - * negative error codes: + * This function returns the number of bytes written to |buf| if it + * succeeds, or one of the following negative error codes: * * :enum:`NGHTTP2_ERR_NOMEM` * Out of memory. @@ -4725,8 +4939,8 @@ NGHTTP2_EXTERN ssize_t nghttp2_hd_deflate_hd(nghttp2_hd_deflater *deflater, * * After this function returns, it is safe to delete the |nva|. * - * This function returns 0 if it succeeds, or one of the following - * negative error codes: + * This function returns the number of bytes written to |vec| if it + * succeeds, or one of the following negative error codes: * * :enum:`NGHTTP2_ERR_NOMEM` * Out of memory. diff --git a/tools/sdk/esp32/include/openssl/include/internal/ssl_code.h b/tools/sdk/esp32/include/openssl/include/internal/ssl_code.h index 80fdbb20..18e687e5 100644 --- a/tools/sdk/esp32/include/openssl/include/internal/ssl_code.h +++ b/tools/sdk/esp32/include/openssl/include/internal/ssl_code.h @@ -23,6 +23,10 @@ #include "tls1.h" #include "x509_vfy.h" +/* Used in SSL_set_mode() -- supported mode when using BIO */ +#define SSL_MODE_ENABLE_PARTIAL_WRITE 0x00000001L +#define SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER 0x00000002L + /* Used in SSL_set_shutdown()/SSL_get_shutdown(); */ # define SSL_SENT_SHUTDOWN 1 # define SSL_RECEIVED_SHUTDOWN 2 diff --git a/tools/sdk/esp32/include/openssl/include/internal/ssl_pkey.h b/tools/sdk/esp32/include/openssl/include/internal/ssl_pkey.h index e790fcc9..0f361288 100644 --- a/tools/sdk/esp32/include/openssl/include/internal/ssl_pkey.h +++ b/tools/sdk/esp32/include/openssl/include/internal/ssl_pkey.h @@ -55,6 +55,52 @@ EVP_PKEY* d2i_PrivateKey(int type, const unsigned char **pp, long length); +/** + * @brief decodes and load a buffer BIO into a EVP key context. If '*a' is pointed to the + * private key, then load key into it. Or create a new private key object + * + * @param bp BIO object containing the key + * @param a Pointer to an existing EVP_KEY or NULL if a new key shall be created + * + * @return Created or updated EVP_PKEY + */ +EVP_PKEY *d2i_PrivateKey_bio(BIO *bp, EVP_PKEY **a); + +/** + * @brief Same as d2i_PrivateKey_bio + * + * @param bp BIO object containing the key + * @param a Pointer to an existing EVP_KEY or NULL if a new key shall be created + * + * @return Created or updated EVP_PKEY + */ +RSA *d2i_RSAPrivateKey_bio(BIO *bp,RSA **rsa); + +/** + * @brief loads a private key in PEM format from BIO object + * + * @param bp BIO object containing the key + * @param x Pointer to an existent PKEY or NULL if a new key shall be created + * @param cb Password callback (not used) + * @param u User context (not used) + * + * @return Created or updated EVP_PKEY + */ +EVP_PKEY *PEM_read_bio_PrivateKey(BIO *bp, EVP_PKEY **x, pem_password_cb *cb, void *u); + +/** + * @brief RSA key in PEM format from BIO object + * + * @param bp BIO object containing the key + * @param x Pointer to an existent PKEY or NULL if a new key shall be created + * @param cb Password callback (not used) + * @param u User context (not used) + * + * @return Created or updated EVP_PKEY + */ + +RSA *PEM_read_bio_RSAPrivateKey(BIO *bp, RSA **rsa, pem_password_cb *cb, void *u); + /** * @brief free a private key object * diff --git a/tools/sdk/esp32/include/openssl/include/internal/ssl_stack.h b/tools/sdk/esp32/include/openssl/include/internal/ssl_stack.h index 7a7051a0..f1efa579 100644 --- a/tools/sdk/esp32/include/openssl/include/internal/ssl_stack.h +++ b/tools/sdk/esp32/include/openssl/include/internal/ssl_stack.h @@ -17,6 +17,49 @@ } \ #define DEFINE_STACK_OF(t) SKM_DEFINE_STACK_OF(t, t, t) +typedef struct asn1_string_st ASN1_OCTET_STRING; + +struct stack_st_GENERAL_NAME; +typedef struct GENERAL_NAME_st { + int type; + union { + char *ptr; + struct asn1_string_st* dNSName; + ASN1_OCTET_STRING* iPAddress; + } d; +} GENERAL_NAME; + +typedef struct asn1_string_st ASN1_OCTET_STRING; +typedef struct X509_name_st X509_NAME; +typedef struct asn1_string_st ASN1_STRING; +typedef struct X509_name_entry_st X509_NAME_ENTRY; + +typedef struct asn1_string_st { + int type; + int length; + void *data; +} ASN1_IA5STRING; + +typedef STACK_OF(GENERAL_NAME) GENERAL_NAMES; + +/** + * @brief get nr of stack items + * + * @param sk Stack structure pointer + * + * @return number of items in the stack + */ +size_t sk_GENERAL_NAME_num(const struct stack_st_GENERAL_NAME *sk); + +/** + * @brief get GENERAL_NAME value from the stack + * + * @param sk Stack structure pointer + * @param i Index to stack item + * + * @return GENERAL_NAME object pointer + */ +GENERAL_NAME *sk_GENERAL_NAME_value(const struct stack_st_GENERAL_NAME *sk, size_t i); /** * @brief create a openssl stack object diff --git a/tools/sdk/esp32/include/openssl/include/internal/ssl_types.h b/tools/sdk/esp32/include/openssl/include/internal/ssl_types.h index 21ba69f4..2871d3a8 100644 --- a/tools/sdk/esp32/include/openssl/include/internal/ssl_types.h +++ b/tools/sdk/esp32/include/openssl/include/internal/ssl_types.h @@ -20,6 +20,8 @@ #endif #include "ssl_code.h" +#include +#include typedef void SSL_CIPHER; @@ -30,6 +32,8 @@ typedef void RSA; typedef void STACK; +typedef void DH; + #define ossl_inline inline #define SSL_METHOD_CALL(f, s, ...) s->method->func->ssl_##f(s, ##__VA_ARGS__) @@ -37,7 +41,7 @@ typedef void STACK; #define EVP_PKEY_METHOD_CALL(f, k, ...) k->method->pkey_##f(k, ##__VA_ARGS__) typedef int (*OPENSSL_sk_compfunc)(const void *, const void *); - +typedef int (*openssl_verify_callback)(int, X509_STORE_CTX *); struct stack_st; typedef struct stack_st OPENSSL_STACK; @@ -100,6 +104,8 @@ struct evp_pkey_st { void *pkey_pm; const PKEY_METHOD *method; + + int ref_counter; }; struct x509_st { @@ -152,8 +158,16 @@ struct X509_VERIFY_PARAM_st { }; struct bio_st { - const unsigned char * data; + + unsigned char * data; int dlen; + BIO* peer; + size_t offset; + size_t roffset; + size_t size; + size_t flags; + size_t type; + }; typedef enum { ALPN_INIT, ALPN_ENABLE, ALPN_DISABLE, ALPN_ERROR } ALPN_STATUS; @@ -166,6 +180,9 @@ struct ssl_alpn_st { const char *alpn_list[ALPN_LIST_MAX]; }; +typedef int pem_password_cb(char *buf, int size, int rwflag, void *userdata); + + struct ssl_ctx_st { int version; @@ -193,6 +210,16 @@ struct ssl_ctx_st int read_buffer_len; X509_VERIFY_PARAM param; + + void *default_passwd_callback_userdata; + + pem_password_cb *default_passwd_callback; + + struct stack_st_X509 *extra_certs; + + int max_version; + int min_version; + }; struct ssl_st @@ -230,12 +257,13 @@ struct ssl_st X509_VERIFY_PARAM param; - int err; + uint32_t mode; void (*info_callback) (const SSL *ssl, int type, int val); /* SSL low-level system arch point */ void *ssl_pm; + void *bio; }; struct ssl_method_st { @@ -299,6 +327,13 @@ struct pkey_method_st { int (*pkey_load)(EVP_PKEY *pkey, const unsigned char *buf, int len); }; +struct bio_method_st { + + unsigned type; + + unsigned size; +}; + typedef int (*next_proto_cb)(SSL *ssl, unsigned char **out, unsigned char *outlen, const unsigned char *in, diff --git a/tools/sdk/esp32/include/openssl/include/internal/ssl_x509.h b/tools/sdk/esp32/include/openssl/include/internal/ssl_x509.h index e5843972..88e46e2e 100644 --- a/tools/sdk/esp32/include/openssl/include/internal/ssl_x509.h +++ b/tools/sdk/esp32/include/openssl/include/internal/ssl_x509.h @@ -114,23 +114,6 @@ int SSL_use_certificate_ASN1(SSL *ssl, int len, const unsigned char *d); */ int X509_STORE_add_cert(X509_STORE *store, X509 *x); -/** - * @brief load data in BIO - * - * Normally BIO_write should append data but that doesn't happen here, and - * 'data' cannot be freed after the function is called, it should remain valid - * until BIO object is in use. - * - * @param b - pointer to BIO - * @param data - pointer to data - * @param dlen - data bytes - * - * @return result - * 0 : failed - * 1 : OK - */ -int BIO_write(BIO *b, const void *data, int dlen); - /** * @brief load a character certification context into system context. * @@ -145,28 +128,22 @@ int BIO_write(BIO *b, const void *data, int dlen); * * @return X509 certification object point */ -X509 * PEM_read_bio_X509(BIO *bp, X509 **x, void *cb, void *u); +X509 * PEM_read_bio_X509(BIO *bp, X509 **x, pem_password_cb cb, void *u); /** - * @brief create a BIO object - * - * @param method - pointer to BIO_METHOD + * @brief load a character certification context into system context. * - * @return pointer to BIO object - */ -BIO *BIO_new(void * method); - -/** - * @brief get the memory BIO method function - */ -void *BIO_s_mem(void); - -/** - * @brief free a BIO object + * Current implementation directly calls PEM_read_bio_X509 * - * @param x - pointer to BIO object + * @param bp - pointer to BIO + * @param buffer - pointer to the certification context memory + * @param cb - pointer to the callback (not implemented) + * @param u - pointer to arbitrary data (not implemented) + * + * @return X509 certification object point */ -void BIO_free(BIO *b); +X509 *PEM_read_bio_X509_AUX(BIO *bp, X509 **cert, pem_password_cb *cb, void *u); + #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/openssl/include/openssl/bio.h b/tools/sdk/esp32/include/openssl/include/openssl/bio.h new file mode 100644 index 00000000..1fc049b6 --- /dev/null +++ b/tools/sdk/esp32/include/openssl/include/openssl/bio.h @@ -0,0 +1,179 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _OPENSSL_BIO_H +#define _OPENSSL_BIO_H + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* These are the 'types' of BIOs */ +#define BIO_TYPE_NONE 0 +#define BIO_TYPE_MEM (1 | 0x0400) +#define BIO_TYPE_BIO (19 | 0x0400) /* (half a) BIO pair */ + +/* Bio object flags */ +#define BIO_FLAGS_READ 0x01 +#define BIO_FLAGS_WRITE 0x02 + +#define BIO_should_read(a) BIO_test_flags(a, BIO_FLAGS_READ) +#define BIO_should_write(a) BIO_test_flags(a, BIO_FLAGS_WRITE) + +typedef struct bio_st BIO; +typedef struct bio_method_st BIO_METHOD; + +/** + * @brief Create a BIO object as a file type + * Current implementation return NULL as file types are discouraged on ESP platform + * + * @param filename Filename + * @param mode Mode + * + * @return BIO object + */ +BIO *BIO_new_file(const char *filename, const char *mode); + +/** + * @brief Create a BIO object as a membuf type + * Current implementation takes a shallow copy of the buffer + * + * @param buf Pointer to the buffer + * @param len Length of the buffer + * + * @return BIO object + */ +BIO *BIO_new_mem_buf(void *buf, int len); + +/** + * @brief create a BIO object + * + * @param method - pointer to BIO_METHOD + * + * @return pointer to BIO object + */ +BIO *BIO_new(BIO_METHOD * method); + +/** + * @brief get the memory BIO method function + */ +void *BIO_s_mem(void); + +/** + * @brief free a BIO object + * + * @param x - pointer to BIO object + */ +void BIO_free(BIO *b); + +/** + * @brief Create a connected pair of BIOs bio1, bio2 with write buffer sizes writebuf1 and writebuf2 + * + * @param out1 pointer to BIO1 + * @param writebuf1 write size of BIO1 (0 means default size will be used) + * @param out2 pointer to BIO2 + * @param writebuf2 write size of BIO2 (0 means default size will be used) + * + * @return result + * 0 : failed + * 1 : OK + */ +int BIO_new_bio_pair(BIO **out1, size_t writebuf1, BIO **out2, size_t writebuf2); + +/** + * @brief Write data to BIO + * + * BIO_TYPE_BIO behaves the same way as OpenSSL bio object, other BIO types mock + * this functionality to avoid excessive allocation/copy, so the 'data' cannot + * be freed after the function is called, it should remain valid until BIO object is in use. + * + * @param b - pointer to BIO + * @param data - pointer to data + * @param dlen - data bytes + * + * @return result + * -1, 0 : failed + * 1 : OK + */ +int BIO_write(BIO *b, const void *data, int dlen); + +/** + * @brief Read data from BIO + * + * BIO_TYPE_BIO behaves the same way as OpenSSL bio object. + * Other types just hold pointer + * + * @param b - pointer to BIO + * @param data - pointer to data + * @param dlen - data bytes + * + * @return result + * -1, 0 : failed + * 1 : OK + */ +int BIO_read(BIO *bio, void *data, int len); + +/** + * @brief Get number of pending characters in the BIOs write buffers. + * + * @param b Pointer to BIO + * + * @return Amount of pending data + */ +size_t BIO_wpending(const BIO *bio); + +/** + * @brief Get number of pending characters in the BIOs read buffers. + * + * @param b Pointer to BIO + * + * @return Amount of pending data + */ +size_t BIO_ctrl_pending(const BIO *bio); + +/** + * @brief Get the maximum length of data that can be currently written to the BIO + * + * @param b Pointer to BIO + * + * @return Max length of writable data + */ +size_t BIO_ctrl_get_write_guarantee(BIO *bio); + +/** + * @brief Returns the type of a BIO. + * + * @param b Pointer to BIO + * + * @return Type of the BIO object + */ +int BIO_method_type(const BIO *b); + +/** + * @brief Test flags of a BIO. + * + * @param b Pointer to BIO + * @param flags Flags + * + * @return BIO object flags masked with the supplied flags + */ +int BIO_test_flags(const BIO *b, int flags); + +#ifdef __cplusplus +} +#endif + +#endif //_OPENSSL_BIO_H diff --git a/tools/sdk/esp32/include/openssl/include/openssl/err.h b/tools/sdk/esp32/include/openssl/include/openssl/err.h new file mode 100644 index 00000000..f4247a4a --- /dev/null +++ b/tools/sdk/esp32/include/openssl/include/openssl/err.h @@ -0,0 +1,228 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _OPENSSL_ERR_H +#define _OPENSSL_ERR_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @note This file contains a very simple implementation of error stack + * for ESP APIs stubs to OpenSSL + */ + +#define OPENSSL_PUT_SYSTEM_ERROR() \ + ERR_put_error(ERR_LIB_SYS, 0, 0, __FILE__, __LINE__); + +#define OPENSSL_PUT_LIB_ERROR(lib, code) \ + ERR_put_error(lib, 0, code, __FILE__, __LINE__); + +#define ERR_GET_LIB(packed_error) ((int)(((packed_error) >> 24) & 0xff)) +#define ERR_GET_REASON(packed_error) ((int)((packed_error) & 0xffff)) +#define ERR_R_PEM_LIB ERR_LIB_PEM +/* inherent openssl errors */ +# define ERR_R_FATAL 64 +# define ERR_R_MALLOC_FAILURE (1|ERR_R_FATAL) +# define ERR_R_SHOULD_NOT_HAVE_BEEN_CALLED (2|ERR_R_FATAL) +# define ERR_R_PASSED_NULL_PARAMETER (3|ERR_R_FATAL) +# define ERR_R_INTERNAL_ERROR (4|ERR_R_FATAL) +# define ERR_R_DISABLED (5|ERR_R_FATAL) +# define ERR_R_INIT_FAIL (6|ERR_R_FATAL) +# define ERR_R_PASSED_INVALID_ARGUMENT (7) +# define ERR_R_OPERATION_FAIL (8|ERR_R_FATAL) +# define ERR_R_INVALID_PROVIDER_FUNCTIONS (9|ERR_R_FATAL) +# define ERR_R_INTERRUPTED_OR_CANCELLED (10) + +enum { + ERR_LIB_NONE = 1, + ERR_LIB_SYS, + ERR_LIB_BN, + ERR_LIB_RSA, + ERR_LIB_DH, + ERR_LIB_EVP, + ERR_LIB_BUF, + ERR_LIB_OBJ, + ERR_LIB_PEM, + ERR_LIB_DSA, + ERR_LIB_X509, + ERR_LIB_ASN1, + ERR_LIB_CONF, + ERR_LIB_CRYPTO, + ERR_LIB_EC, + ERR_LIB_SSL, + ERR_LIB_BIO, + ERR_LIB_PKCS7, + ERR_LIB_PKCS8, + ERR_LIB_X509V3, + ERR_LIB_RAND, + ERR_LIB_ENGINE, + ERR_LIB_OCSP, + ERR_LIB_UI, + ERR_LIB_COMP, + ERR_LIB_ECDSA, + ERR_LIB_ECDH, + ERR_LIB_HMAC, + ERR_LIB_DIGEST, + ERR_LIB_CIPHER, + ERR_LIB_HKDF, + ERR_LIB_USER, + ERR_NUM_LIBS +}; + +/** + * @brief clear the SSL error code + * + * @param none + * + * @return none + */ +void ERR_clear_error(void); + +/** + * @brief get the current SSL error code + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_get_error(void); + +/** + * @brief peek the current SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_error(void); + +/** + * @brief peek the last SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_last_error(void); + +/** + * @brief register the SSL error strings + * + * @param none + * + * @return none + */ +void ERR_load_SSL_strings(void); + +/** + * @brief clear the SSL error code + * + * @param none + * + * @return none + */ +void ERR_clear_error(void); + +/** + * @brief peek the current SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_error(void); + +/** + * @brief peek the last SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_last_error(void); + +/** + * @brief capture the current error to the error structure + * + * @param library Related library + * @param unused Not used (used for compliant function prototype) + * @param reason The actual error code + * @param file File name of the error report + * @param line Line number of the error report + * + */ +void ERR_put_error(int library, int unused, int reason, const char *file, unsigned line); + +/** + * @brief Peek the current SSL error, not clearing it + * + * @param file file name of the reported error + * @param line line number of the reported error + * @param data Associated data to the reported error + * @param flags Flags associated to the error + * + * @return current SSL error number + */ +uint32_t ERR_peek_error_line_data(const char **file, int *line, + const char **data, int *flags); + +/** + * @brief Get the current SSL error + * + * @param file file name of the reported error + * @param line line number of the reported error + * @param data Associated data to the reported error + * @param flags Flags associated to the error + * + * @return current SSL error number + */ +uint32_t ERR_get_error_line_data(const char **file, int *line, + const char **data, int *flags); + +/** + * @brief API provided as a declaration only + * + */ +void SSL_load_error_strings(void); + +/** + * @brief API provided as a declaration only + * + */ +void ERR_free_strings(void); + +/** + * @brief API provided as a declaration only + * + */ +void ERR_remove_state(unsigned long pid); + +/** + * @brief Returns error string -- Not implemented + * + * @param packed_error Packed error code + * + * @return NULL + */ +const char *ERR_reason_error_string(uint32_t packed_error); + +#ifdef __cplusplus +} +#endif + +#endif // _OPENSSL_ERR_H diff --git a/tools/sdk/esp32/include/openssl/include/openssl/ssl.h b/tools/sdk/esp32/include/openssl/include/openssl/ssl.h index 88d7bca6..4a3376c0 100644 --- a/tools/sdk/esp32/include/openssl/include/openssl/ssl.h +++ b/tools/sdk/esp32/include/openssl/include/openssl/ssl.h @@ -21,6 +21,8 @@ #include "internal/ssl_x509.h" #include "internal/ssl_pkey.h" +#include "openssl/bio.h" +#include "openssl/err.h" /* { @@ -297,6 +299,67 @@ const SSL_METHOD* SSLv3_server_method(void); */ const SSL_METHOD* TLS_server_method(void); +/** + * @brief create the target SSL context method + * + * @return the TLS any version SSL context method + */ +const SSL_METHOD* TLS_method(void); + +/** + * @brief create the target SSL context method + * + * @return the TLS1.2 version SSL context method + */ +const SSL_METHOD* TLSv1_2_method(void); + +/** + * @brief create the target SSL context method + * + * @return the TLS1.1 version SSL context method + */ +const SSL_METHOD* TLSv1_1_method(void); + +/** + * @brief create the target SSL context method + * + * @return the TLS1.0 version SSL context method + */ +const SSL_METHOD* TLSv1_method(void); + +/** + * @brief create the target SSL context method + * + * @return the SSLV3.0 version SSL context method + */ +const SSL_METHOD* SSLv3_method(void); + +/** + * @brief create the target SSL context method + * + * @param none + * + * @return the SSLV2.3 version SSL context method + */ +const SSL_METHOD* SSLv23_method(void); + +/** + * @brief Set minimum protocol version for defined context + * + * @param ctx SSL context + * + * @return 1 on success + */ +int SSL_CTX_set_min_proto_version(SSL_CTX *ctx, int version); + +/** + * @brief Set maximum protocol version for defined context + * + * @param ctx SSL context + * + * @return 1 on success + */ +int SSL_CTX_set_max_proto_version(SSL_CTX *ctx, int version); /** * @brief set the SSL context ALPN select callback function @@ -348,43 +411,6 @@ void SSL_CTX_set_next_proto_select_cb(SSL_CTX *ctx, void *arg), void *arg); -/** - * @brief get SSL error code - * - * @param ssl - SSL point - * @param ret_code - SSL return code - * - * @return SSL error number - */ -int SSL_get_error(const SSL *ssl, int ret_code); - -/** - * @brief clear the SSL error code - * - * @param none - * - * @return none - */ -void ERR_clear_error(void); - -/** - * @brief get the current SSL error code - * - * @param none - * - * @return current SSL error number - */ -int ERR_get_error(void); - -/** - * @brief register the SSL error strings - * - * @param none - * - * @return none - */ -void ERR_load_SSL_strings(void); - /** * @brief initialize the SSL library * @@ -1399,7 +1425,17 @@ SSL_CTX *SSL_get_SSL_CTX(const SSL *ssl); * * @return application data */ -char *SSL_get_app_data(SSL *ssl); +void *SSL_get_app_data(SSL *ssl); + +/** + * @brief get SSL error code + * + * @param ssl - SSL point + * @param ret_code - SSL return code + * + * @return SSL error number + */ +int SSL_get_error(const SSL *ssl, int ret_code); /** * @brief get SSL cipher bits @@ -1667,7 +1703,7 @@ void SSL_set_accept_state(SSL *ssl); * * @return none */ -void SSL_set_app_data(SSL *ssl, char *arg); +void SSL_set_app_data(SSL *ssl, void *arg); /** * @brief set SSL BIO @@ -1756,7 +1792,7 @@ void SSL_set_timeout(SSL *ssl, long t); * * @return SSL statement string */ -char *SSL_state_string(const SSL *ssl); +const char *SSL_state_string(const SSL *ssl); /** * @brief get SSL statement long string @@ -1815,6 +1851,52 @@ const char *SSL_get_psk_identity_hint(SSL *ssl); */ const char *SSL_get_psk_identity(SSL *ssl); +/** + * @brief set the SSL verify depth of the SSL + * + * @param ssl - SSL context + * @param depth - Depth level to verify + * + */ +void SSL_set_verify_depth(SSL *ssl, int depth); + +/** + * @brief Get default verify callback + * + * @param ctx - SSL context + * @return verify_callback - verifying callback function + * + */ +openssl_verify_callback SSL_CTX_get_verify_callback(const SSL_CTX *ctx); + +/** + * @brief Get default verify callback + * + * @param ctx - SSL context + * @return verify_callback - verifying callback function + * + */ +openssl_verify_callback SSL_get_verify_callback(const SSL *s); + +/** + * @brief Frees RSA object + * + * Current implementation calls directly EVP_PKEY free + * + * @param r RSA object + * + */ +void RSA_free(RSA *r); + +/** + * @brief Sets SSL mode, partially implemented + * + * @param ssl SSL context + * + * @return the new mode bitmask after adding mode + */ +uint32_t SSL_set_mode(SSL *ssl, uint32_t mode); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/pthread/include/esp_pthread.h b/tools/sdk/esp32/include/pthread/include/esp_pthread.h index cdff0519..95e182c1 100644 --- a/tools/sdk/esp32/include/pthread/include/esp_pthread.h +++ b/tools/sdk/esp32/include/pthread/include/esp_pthread.h @@ -82,6 +82,11 @@ esp_err_t esp_pthread_set_cfg(const esp_pthread_cfg_t *cfg); */ esp_err_t esp_pthread_get_cfg(esp_pthread_cfg_t *p); +/** + * @brief Initialize pthread library + */ +esp_err_t esp_pthread_init(void); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/soc/include/hal/adc_hal.h b/tools/sdk/esp32/include/soc/include/hal/adc_hal.h index 621b23d1..e497149e 100644 --- a/tools/sdk/esp32/include/soc/include/hal/adc_hal.h +++ b/tools/sdk/esp32/include/soc/include/hal/adc_hal.h @@ -168,6 +168,20 @@ int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value); */ #define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en) +/** + * Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @note ESP32 only supports output of ADC2's internal reference voltage. + * @param[in] adc ADC unit select + * @param[in] channel ADC2 channel number + * @param[in] en Enable/disable the reference voltage output + */ +#define adc_hal_vref_output(adc, channel, en) adc_ll_vref_output(adc, channel, en) + /*--------------------------------------------------------------- Digital controller setting ---------------------------------------------------------------*/ diff --git a/tools/sdk/esp32/include/soc/include/hal/adc_types.h b/tools/sdk/esp32/include/soc/include/hal/adc_types.h index 1305d276..5f3d5a13 100644 --- a/tools/sdk/esp32/include/soc/include/hal/adc_types.h +++ b/tools/sdk/esp32/include/soc/include/hal/adc_types.h @@ -1,8 +1,22 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. #pragma once -#include "soc/adc_caps.h" -#include "sdkconfig.h" #include +#include +#include "sdkconfig.h" +#include "soc/adc_caps.h" /** * @brief ADC units selected handle. @@ -69,7 +83,7 @@ typedef enum { ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. Only ESP32 is supported. */ ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */ ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */ -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if !CONFIG_IDF_TARGET_ESP32 ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32S2 is supported. */ #endif ADC_WIDTH_MAX, @@ -108,11 +122,11 @@ typedef struct { If (channel > ADC_CHANNEL_MAX), The data is invalid. */ uint16_t unit: 1; /*! #include +#include "esp_err.h" + #include "soc/soc_caps.h" #include "hal/cpu_hal.h" #include "hal/soc_ll.h" -#include "esp_err.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32/include/soc/include/hal/spi_flash_hal.h b/tools/sdk/esp32/include/soc/include/hal/spi_flash_hal.h index 6992daf6..ffc1a22f 100644 --- a/tools/sdk/esp32/include/soc/include/hal/spi_flash_hal.h +++ b/tools/sdk/esp32/include/soc/include/hal/spi_flash_hal.h @@ -37,20 +37,22 @@ * implementations that also use the SPI peripheral. */ typedef struct { + spi_flash_host_inst_t inst; ///< Host instance, containing host data and function pointer table. May update with the host (hardware version). spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation. int cs_num; ///< Which cs pin is used, 0-2. - int extra_dummy; - spi_flash_ll_clock_reg_t clock_conf; -} spi_flash_memspi_data_t; + int extra_dummy; ///< Pre-calculated extra dummy used for compensation + spi_flash_ll_clock_reg_t clock_conf; ///< Pre-calculated clock configuration value + uint32_t reserved_config[2]; ///< The ROM has reserved some memory for configurations with one set of driver code. (e.g. QPI mode, 64-bit address mode, etc.) +} spi_flash_hal_context_t; /// Configuration structure for the SPI driver. typedef struct { spi_host_device_t host_id; ///< SPI peripheral ID. - int cs_num; ///< Which cs pin is used, 0-2. + int cs_num; ///< Which cs pin is used, 0-(SOC_SPI_PERIPH_CS_NUM-1). bool iomux; ///< Whether the IOMUX is used, used for timing compensation. int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation. esp_flash_speed_t speed;///< SPI flash clock speed to work at. -} spi_flash_memspi_config_t; +} spi_flash_hal_config_t; /** * Configure SPI flash hal settings. @@ -62,16 +64,16 @@ typedef struct { * - ESP_OK: success * - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM. */ -esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg); +esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg); /** * Configure the device-related register before transactions. * - * @param driver The driver context. + * @param host The driver context. * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver); +esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host); /** * Send an user-defined spi transaction to the device. @@ -80,60 +82,60 @@ esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver); * particular commands. Since this function supports timing compensation, it is * also used to receive some data when the frequency is high. * - * @param driver The driver context. + * @param host The driver context. * @param trans The transaction to send, also holds the received data. * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans); +esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans); /** * Erase whole flash chip by using the erase chip (C7h) command. * - * @param driver The driver context. + * @param host The driver context. */ -void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver); +void spi_flash_hal_erase_chip(spi_flash_host_inst_t *host); /** * Erase a specific sector by its start address through the sector erase (20h) * command. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Start address of the sector to erase. */ -void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address); +void spi_flash_hal_erase_sector(spi_flash_host_inst_t *host, uint32_t start_address); /** * Erase a specific 64KB block by its start address through the 64KB block * erase (D8h) command. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Start address of the block to erase. */ -void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address); +void spi_flash_hal_erase_block(spi_flash_host_inst_t *host, uint32_t start_address); /** * Program a page of the flash using the page program (02h) command. * - * @param driver The driver context. + * @param host The driver context. * @param address Address of the page to program * @param buffer Data to program * @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes. */ -void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length); +void spi_flash_hal_program_page(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length); /** * Read from the flash. Call ``spi_flash_hal_configure_host_read_mode`` to * configure the read command before calling this function. * - * @param driver The driver context. + * @param host The driver context. * @param buffer Buffer to store the read data * @param address Address to read * @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes. * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len); +esp_err_t spi_flash_hal_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len); /** * @brief Send the write enable (06h) or write disable (04h) command to the flash chip. @@ -143,16 +145,16 @@ esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp); +esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_inst_t *host, bool wp); /** * Check whether the SPI host is idle and can perform other operations. * - * @param driver The driver context. + * @param host The driver context. * * @return ture if idle, otherwise false. */ -bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver); +bool spi_flash_hal_host_idle(spi_flash_host_inst_t *host); /** * @brief Configure the SPI host hardware registers for the specified io mode. @@ -177,7 +179,7 @@ bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver); * - Common write: set command value, address value (or length to 0 if not * used), disable dummy phase, and set output data. * - * @param driver The driver context + * @param host The driver context * @param io_mode The HW read mode to use * @param addr_bitlen Length of the address phase, in bits * @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing. @@ -185,34 +187,34 @@ bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver); * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen, +esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_inst_t *host, uint32_t command, uint32_t addr_bitlen, int dummy_cyclelen_base, esp_flash_io_mode_t io_mode); /** * Poll until the last operation is done. * - * @param driver The driver context. + * @param host The driver context. */ -void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver); +void spi_flash_hal_poll_cmd_done(spi_flash_host_inst_t *host); /** * Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from * regions that are accessible ith cache disabled. * * - * @param driver The driver context + * @param host The driver context * @param p The buffer holding data to send. * * @return True if the buffer can be used to send data, otherwise false. */ -bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p); +bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p); /** * Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from * regions that are accessible ith cache disabled. * * - * @param driver The driver context + * @param host The driver context * @param p The buffer to hold the received data. * * @return True if the buffer can be used to receive data, otherwise false. */ -bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p); +bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p); diff --git a/tools/sdk/esp32/include/soc/include/hal/spi_flash_types.h b/tools/sdk/esp32/include/soc/include/hal/spi_flash_types.h index 0a468c60..d2efe3e8 100644 --- a/tools/sdk/esp32/include/soc/include/hal/spi_flash_types.h +++ b/tools/sdk/esp32/include/soc/include/hal/spi_flash_types.h @@ -68,84 +68,105 @@ typedef enum { ///Slowest io mode supported by ESP32, currently SlowRd #define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD -struct spi_flash_host_driver_t; -typedef struct spi_flash_host_driver_t spi_flash_host_driver_t; +struct spi_flash_host_driver_s; +typedef struct spi_flash_host_driver_s spi_flash_host_driver_t; + +/** SPI Flash Host driver instance */ +typedef struct { + const struct spi_flash_host_driver_s* driver; ///< Pointer to the implementation function table + // Implementations can wrap this structure into their own ones, and append other data here +} spi_flash_host_inst_t ; + /** Host driver configuration and context structure. */ -struct spi_flash_host_driver_t { - /** - * Configuration and static data used by the specific host driver. The type - * is determined by the host driver. - */ - void *driver_data; +struct spi_flash_host_driver_s { /** * Configure the device-related register before transactions. This saves * some time to re-configure those registers when we send continuously */ - esp_err_t (*dev_config)(spi_flash_host_driver_t *driver); + esp_err_t (*dev_config)(spi_flash_host_inst_t *host); /** * Send an user-defined spi transaction to the device. */ - esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t); + esp_err_t (*common_command)(spi_flash_host_inst_t *host, spi_flash_trans_t *t); /** * Read flash ID. */ - esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id); + esp_err_t (*read_id)(spi_flash_host_inst_t *host, uint32_t *id); /** * Erase whole flash chip. */ - void (*erase_chip)(spi_flash_host_driver_t *driver); + void (*erase_chip)(spi_flash_host_inst_t *host); /** * Erase a specific sector by its start address. */ - void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address); + void (*erase_sector)(spi_flash_host_inst_t *host, uint32_t start_address); /** * Erase a specific block by its start address. */ - void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address); + void (*erase_block)(spi_flash_host_inst_t *host, uint32_t start_address); /** * Read the status of the flash chip. */ - esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr); + esp_err_t (*read_status)(spi_flash_host_inst_t *host, uint8_t *out_sr); /** * Disable write protection. */ - esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp); + esp_err_t (*set_write_protect)(spi_flash_host_inst_t *host, bool wp); /** * Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length. */ - void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length); - /** Check whether need to allocate new buffer to write */ - bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p); - /** Check whether need to allocate new buffer to read */ - bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p); - /** maximum length of program_page */ - int max_write_bytes; + void (*program_page)(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length); + /** Check whether given buffer can be directly used to write */ + bool (*supports_direct_write)(spi_flash_host_inst_t *host, const void *p); + /** + * Slicer for write data. The `program_page` should be called iteratively with the return value + * of this function. + * + * @param address Beginning flash address to write + * @param len Length request to write + * @param align_addr Output of the aligned address to write to + * @param page_size Physical page size of the flash chip + * @return Length that can be actually written in one `program_page` call + */ + int (*write_data_slicer)(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_addr, + uint32_t page_size); /** * Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length. */ - esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len); - /** maximum length of read */ - int max_read_bytes; + esp_err_t (*read)(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len); + /** Check whether given buffer can be directly used to read */ + bool (*supports_direct_read)(spi_flash_host_inst_t *host, const void *p); + /** + * Slicer for read data. The `read` should be called iteratively with the return value + * of this function. + * + * @param address Beginning flash address to read + * @param len Length request to read + * @param align_addr Output of the aligned address to read + * @param page_size Physical page size of the flash chip + * @return Length that can be actually read in one `read` call + */ + int (*read_data_slicer)(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_addr, uint32_t page_size); /** * Check whether the host is idle to perform new operations. */ - bool (*host_idle)(spi_flash_host_driver_t *driver); + bool (*host_idle)(spi_flash_host_inst_t *host); /** * Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode. */ - esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command, + esp_err_t (*configure_host_io_mode)(spi_flash_host_inst_t *host, uint32_t command, uint32_t addr_bitlen, int dummy_bitlen_base, esp_flash_io_mode_t io_mode); /** * Internal use, poll the HW until the last operation is done. */ - void (*poll_cmd_done)(spi_flash_host_driver_t *driver); + void (*poll_cmd_done)(spi_flash_host_inst_t *host); /** * For some host (SPI1), they are shared with a cache. When the data is * modified, the cache needs to be flushed. Left NULL if not supported. */ - esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size); + esp_err_t (*flush_cache)(spi_flash_host_inst_t* host, uint32_t addr, uint32_t size); }; #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/soc/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32/include/soc/include/hal/spi_slave_hd_hal.h new file mode 100644 index 00000000..c9e3684d --- /dev/null +++ b/tools/sdk/esp32/include/soc/include/hal/spi_slave_hd_hal.h @@ -0,0 +1,212 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +/* + * The HAL layer for SPI Slave HD mode, currently only segment mode is supported + * + * Usage: + * - Firstly, initialize the slave with `slave_hd_hal_init` + * + * - Event handling: + * - (Optional) Call ``spi_slave_hd_hal_enable_event_intr`` to enable the used interrupts + * - (Basic) Call ``spi_slave_hd_hal_check_clear_event`` to check whether an event happen, and also + * clear its interrupt. For events: SPI_EV_BUF_TX, SPI_EV_BUF_RX, SPI_EV_BUF_RX, SPI_EV_CMD9, + * SPI_EV_CMDA. + * - (Advanced) Call ``spi_slave_hd_hal_check_disable_event`` to disable the interrupt of an event, + * so that the task can call ``spi_slave_hd_hal_invoke_event_intr`` later to manually invoke the + * ISR. For SPI_EV_SEND, SPI_EV_RECV. + * + * - TXDMA: + * - To send data through DMA, call `spi_slave_hd_hal_txdma` + * - When the operation is done, SPI_EV_SEND will be triggered. + * + * - RXDMA: + * - To receive data through DMA, call `spi_slave_hd_hal_rxdma` + * - When the operation is done, SPI_EV_RECV will be triggered. + * - Call ``spi_slave_hd_hal_rxdma_get_len`` to get the received length + * + * - Shared buffer: + * - Call ``spi_slave_hd_hal_write_buffer`` to write the shared register buffer. When the buffer is + * read by the master (regardless of the read address), SPI_EV_BUF_TX will be triggered + * - Call ``spi_slave_hd_hal_read_buffer`` to read the shared register buffer. When the buffer is + * written by the master (regardless of the written address), SPI_EV_BUF_RX will be triggered. + */ + +#pragma once + +#include +#include "esp_err.h" +#include "hal/spi_ll.h" +#include "hal/spi_types.h" + + +/// Configuration of the HAL +typedef struct { + int host_id; ///< Host ID of the spi peripheral + int spics_io_num; ///< CS GPIO pin for this device + uint8_t mode; ///< SPI mode (0-3) + int command_bits; ///< command field bits, multiples of 8 and at least 8. + int address_bits; ///< address field bits, multiples of 8 and at least 8. + int dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. + + struct { + uint32_t tx_lsbfirst : 1;///< Whether TX data should be sent with LSB first. + uint32_t rx_lsbfirst : 1;///< Whether RX data should be read with LSB first. + }; + int dma_chan; ///< The dma channel used. +} spi_slave_hd_hal_config_t; + +/// Context of the HAL, initialized by :cpp:func:`slave_hd_hal_init`. +typedef struct { + spi_dev_t* dev; ///< Beginning address of the peripheral registers. + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + + /* Internal status used by the HAL implementation, initialized as 0. */ + uint32_t intr_not_triggered; +} spi_slave_hd_hal_context_t; + + +/** + * @brief Initialize the hardware and part of the context + * + * @param hal Context of the HAL layer + * @param config Configuration of the HAL + */ +void slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *config); + +/** + * @brief Check and clear signal of one event + * + * @param hal Context of the HAL layer + * @param ev Event to check + * @return true if event triggered, otherwise false + */ +bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +/** + * @brief Check and clear the interrupt of one event. + * + * @note The event source will be kept, so that the interrupt can be invoked by + * :cpp:func:`spi_slave_hd_hal_invoke_event_intr`. If event not triggered, its interrupt source + * will not be disabled either. + * + * @param hal Context of the HAL layer + * @param ev Event to check and disable + * @return true if event triggered, otherwise false + */ +bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +/** + * @brief Enable to invole the ISR of corresponding event. + * + * @note The function, compared with :cpp:func:`spi_slave_hd_hal_enable_event_intr`, contains a + * workaround to force trigger the interrupt, even if the interrupt source cannot be initialized + * correctly. + * + * @param hal Context of the HAL layer + * @param ev Event (reason) to invoke the ISR + */ +void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +/** + * @brief Enable the interrupt source of corresponding event. + * + * @param hal Context of the HAL layer + * @param ev Event whose corresponding interrupt source should be enabled. + */ +void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +//////////////////////////////////////////////////////////////////////////////// +// RX DMA +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Start the RX DMA operation to the specified buffer. + * + * @param hal Context of the HAL layer + * @param[out] out_buf Buffer to receive the data + * @param len Maximul length to receive + */ +void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len); + +/** + * @brief Get the length of total received data + * + * @param hal Context of the HAL layer + * @return The received length + */ +int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal); + +//////////////////////////////////////////////////////////////////////////////// +// TX DMA +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Start the TX DMA operation with the specified buffer + * + * @param hal Context of the HAL layer + * @param data Buffer of data to send + * @param len Size of the buffer, also the maximum length to send + */ +void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len); + +//////////////////////////////////////////////////////////////////////////////// +// Shared buffer +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Read from the shared register buffer + * + * @param hal Context of the HAL layer + * @param addr Address of the shared regsiter to read + * @param out_data Buffer to store the read data + * @param len Length to read from the shared buffer + */ +void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len); + +/** + * @brief Write the shared register buffer + * + * @param hal Context of the HAL layer + * @param addr Address of the shared register to write + * @param data Buffer of the data to write + * @param len Length to write into the shared buffer + */ +void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *data, size_t len); + +/** + * @brief Get the length of previous transaction. + * + * @param hal Context of the HAL layer + * @return The length of previous transaction + */ +int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); + +/** + * @brief Get the address of last transaction + * + * @param hal Context of the HAL layer + * @return The address of last transaction + */ +int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); diff --git a/tools/sdk/esp32/include/soc/include/hal/spi_types.h b/tools/sdk/esp32/include/soc/include/hal/spi_types.h index 379f1398..b2fef1c3 100644 --- a/tools/sdk/esp32/include/soc/include/hal/spi_types.h +++ b/tools/sdk/esp32/include/soc/include/hal/spi_types.h @@ -15,7 +15,9 @@ #pragma once #include "soc/spi_caps.h" +#include "esp_attr.h" #include "sdkconfig.h" +#include /** * @brief Enum with the three SPI peripherals that are software-accessible in it @@ -27,6 +29,19 @@ typedef enum { SPI3_HOST=2, ///< SPI3 } spi_host_device_t; +/// SPI Events +typedef enum { + SPI_EV_BUF_TX = BIT(0), ///< The buffer has sent data to master, Slave HD only + SPI_EV_BUF_RX = BIT(1), ///< The buffer has received data from master, Slave HD only + SPI_EV_SEND = BIT(2), ///< Has sent data to master through RDDMA, Slave HD only + SPI_EV_RECV = BIT(3), ///< Has received data from master through WRDMA, Slave HD only + SPI_EV_CMD9 = BIT(4), ///< Received CMD9 from master, Slave HD only + SPI_EV_CMDA = BIT(5), ///< Received CMDA from master, Slave HD only + SPI_EV_TRANS = BIT(6), ///< A transaction has done +} spi_event_t; +FLAG_ATTR(spi_event_t) + + /** @cond */ //Doxy command to hide preprocessor definitions from docs */ //alias for different chips @@ -34,7 +49,7 @@ typedef enum { #define SPI_HOST SPI1_HOST #define HSPI_HOST SPI2_HOST #define VSPI_HOST SPI3_HOST -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 #define SPI_HOST SPI1_HOST #define FSPI_HOST SPI2_HOST diff --git a/tools/sdk/esp32/include/soc/include/hal/systimer_hal.h b/tools/sdk/esp32/include/soc/include/hal/systimer_hal.h index a26ffdde..e070f686 100644 --- a/tools/sdk/esp32/include/soc/include/hal/systimer_hal.h +++ b/tools/sdk/esp32/include/soc/include/hal/systimer_hal.h @@ -71,6 +71,11 @@ void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_ */ void systimer_hal_init(void); +/** + * @brief connect alarm unit to selected counter + */ +void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/soc/include/hal/systimer_types.h b/tools/sdk/esp32/include/soc/include/hal/systimer_types.h index ebe5fb4e..2ae7c4a2 100644 --- a/tools/sdk/esp32/include/soc/include/hal/systimer_types.h +++ b/tools/sdk/esp32/include/soc/include/hal/systimer_types.h @@ -46,7 +46,7 @@ _Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t typedef enum { SYSTIMER_COUNTER_0, /*!< systimer counter 0 */ #if SOC_SYSTIMER_COUNTER_NUM > 1 - SYSTIEMR_COUNTER_1, /*!< systimer counter 1 */ + SYSTIMER_COUNTER_1, /*!< systimer counter 1 */ #endif } systimer_counter_id_t; diff --git a/tools/sdk/esp32/include/soc/include/hal/touch_sensor_types.h b/tools/sdk/esp32/include/soc/include/hal/touch_sensor_types.h index 3de534a3..d2ddf33e 100644 --- a/tools/sdk/esp32/include/soc/include/hal/touch_sensor_types.h +++ b/tools/sdk/esp32/include/soc/include/hal/touch_sensor_types.h @@ -14,6 +14,9 @@ #pragma once +#include + +#include "soc/soc.h" #include "soc/touch_sensor_caps.h" #include "sdkconfig.h" #include "esp_attr.h" @@ -129,7 +132,7 @@ typedef enum { #define TOUCH_TRIGGER_MODE_DEFAULT (TOUCH_TRIGGER_BELOW) /*! (touch threshold + hysteresis), the touch channel be touched. - If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released. - Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 1/32; 3: OFF */ - uint32_t noise_thr; /*! (noise), the baseline stop updating. - If (raw data - baseline) < (noise), the baseline start updating. + uint32_t noise_thr; /*! (negative noise), the baseline restart reset process(refer to `baseline_reset`). - If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`). - Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1/8; */ - uint32_t neg_noise_limit; /*! #include -#include "hal/can_types.h" -#include "hal/can_ll.h" +#include "hal/twai_types.h" +#include "hal/twai_ll.h" /* ------------------------- Defines and Typedefs --------------------------- */ //Error active interrupt related -#define CAN_HAL_EVENT_BUS_OFF (1 << 0) -#define CAN_HAL_EVENT_BUS_RECOV_CPLT (1 << 1) -#define CAN_HAL_EVENT_BUS_RECOV_PROGRESS (1 << 2) -#define CAN_HAL_EVENT_ABOVE_EWL (1 << 3) -#define CAN_HAL_EVENT_BELOW_EWL (1 << 4) -#define CAN_HAL_EVENT_ERROR_PASSIVE (1 << 5) -#define CAN_HAL_EVENT_ERROR_ACTIVE (1 << 6) -#define CAN_HAL_EVENT_BUS_ERR (1 << 7) -#define CAN_HAL_EVENT_ARB_LOST (1 << 8) -#define CAN_HAL_EVENT_RX_BUFF_FRAME (1 << 9) -#define CAN_HAL_EVENT_TX_BUFF_FREE (1 << 10) +#define TWAI_HAL_EVENT_BUS_OFF (1 << 0) +#define TWAI_HAL_EVENT_BUS_RECOV_CPLT (1 << 1) +#define TWAI_HAL_EVENT_BUS_RECOV_PROGRESS (1 << 2) +#define TWAI_HAL_EVENT_ABOVE_EWL (1 << 3) +#define TWAI_HAL_EVENT_BELOW_EWL (1 << 4) +#define TWAI_HAL_EVENT_ERROR_PASSIVE (1 << 5) +#define TWAI_HAL_EVENT_ERROR_ACTIVE (1 << 6) +#define TWAI_HAL_EVENT_BUS_ERR (1 << 7) +#define TWAI_HAL_EVENT_ARB_LOST (1 << 8) +#define TWAI_HAL_EVENT_RX_BUFF_FRAME (1 << 9) +#define TWAI_HAL_EVENT_TX_BUFF_FREE (1 << 10) typedef struct { - can_dev_t *dev; -} can_hal_context_t; + twai_dev_t *dev; +} twai_hal_context_t; -typedef can_ll_frame_buffer_t can_hal_frame_t; +typedef twai_ll_frame_buffer_t twai_hal_frame_t; /* ---------------------------- Init and Config ----------------------------- */ /** - * @brief Initialize CAN peripheral and HAL context + * @brief Initialize TWAI peripheral and HAL context * - * Sets HAL context, puts CAN peripheral into reset mode, then sets some + * Sets HAL context, puts TWAI peripheral into reset mode, then sets some * registers with default values. * * @param hal_ctx Context of the HAL layer * @return True if successfully initialized, false otherwise. */ -bool can_hal_init(can_hal_context_t *hal_ctx); +bool twai_hal_init(twai_hal_context_t *hal_ctx); /** - * @brief Deinitialize the CAN peripheral and HAL context + * @brief Deinitialize the TWAI peripheral and HAL context * * Clears any unhandled interrupts and unsets HAL context * * @param hal_ctx Context of the HAL layer */ -void can_hal_deinit(can_hal_context_t *hal_ctx); +void twai_hal_deinit(twai_hal_context_t *hal_ctx); /** - * @brief Configure the CAN peripheral + * @brief Configure the TWAI peripheral * * @param hal_ctx Context of the HAL layer * @param t_config Pointer to timing configuration structure @@ -81,32 +81,32 @@ void can_hal_deinit(can_hal_context_t *hal_ctx); * @param intr_mask Mask of interrupts to enable * @param clkout_divider Clock divider value for CLKOUT. Set to -1 to disable CLKOUT */ -void can_hal_configure(can_hal_context_t *hal_ctx, const can_timing_config_t *t_config, const can_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider); +void twai_hal_configure(twai_hal_context_t *hal_ctx, const twai_timing_config_t *t_config, const twai_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider); /* -------------------------------- Actions --------------------------------- */ /** - * @brief Start the CAN peripheral + * @brief Start the TWAI peripheral * - * Start the CAN peripheral by configuring its operating mode, then exiting - * reset mode so that the CAN peripheral can participate in bus activities. + * Start the TWAI peripheral by configuring its operating mode, then exiting + * reset mode so that the TWAI peripheral can participate in bus activities. * * @param hal_ctx Context of the HAL layer * @param mode Operating mode * @return True if successfully started, false otherwise. */ -bool can_hal_start(can_hal_context_t *hal_ctx, can_mode_t mode); +bool twai_hal_start(twai_hal_context_t *hal_ctx, twai_mode_t mode); /** - * @brief Stop the CAN peripheral + * @brief Stop the TWAI peripheral * - * Stop the CAN peripheral by entering reset mode to stop any bus activity, then + * Stop the TWAI peripheral by entering reset mode to stop any bus activity, then * setting the operating mode to Listen Only so that REC is frozen. * * @param hal_ctx Context of the HAL layer * @return True if successfully stopped, false otherwise. */ -bool can_hal_stop(can_hal_context_t *hal_ctx); +bool twai_hal_stop(twai_hal_context_t *hal_ctx); /** * @brief Start bus recovery @@ -114,9 +114,9 @@ bool can_hal_stop(can_hal_context_t *hal_ctx); * @param hal_ctx Context of the HAL layer * @return True if successfully started bus recovery, false otherwise. */ -static inline bool can_hal_start_bus_recovery(can_hal_context_t *hal_ctx) +static inline bool twai_hal_start_bus_recovery(twai_hal_context_t *hal_ctx) { - return can_ll_exit_reset_mode(hal_ctx->dev); + return twai_ll_exit_reset_mode(hal_ctx->dev); } /** @@ -125,9 +125,9 @@ static inline bool can_hal_start_bus_recovery(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return TX Error Counter Value */ -static inline uint32_t can_hal_get_tec(can_hal_context_t *hal_ctx) +static inline uint32_t twai_hal_get_tec(twai_hal_context_t *hal_ctx) { - return can_ll_get_tec((hal_ctx)->dev); + return twai_ll_get_tec((hal_ctx)->dev); } /** @@ -136,9 +136,9 @@ static inline uint32_t can_hal_get_tec(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return RX Error Counter Value */ -static inline uint32_t can_hal_get_rec(can_hal_context_t *hal_ctx) +static inline uint32_t twai_hal_get_rec(twai_hal_context_t *hal_ctx) { - return can_ll_get_rec((hal_ctx)->dev); + return twai_ll_get_rec((hal_ctx)->dev); } /** @@ -147,9 +147,9 @@ static inline uint32_t can_hal_get_rec(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return RX message count */ -static inline uint32_t can_hal_get_rx_msg_count(can_hal_context_t *hal_ctx) +static inline uint32_t twai_hal_get_rx_msg_count(twai_hal_context_t *hal_ctx) { - return can_ll_get_rx_msg_count((hal_ctx)->dev); + return twai_ll_get_rx_msg_count((hal_ctx)->dev); } /** @@ -158,9 +158,9 @@ static inline uint32_t can_hal_get_rx_msg_count(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return True if successful */ -static inline bool can_hal_check_last_tx_successful(can_hal_context_t *hal_ctx) +static inline bool twai_hal_check_last_tx_successful(twai_hal_context_t *hal_ctx) { - return can_ll_is_last_tx_successful((hal_ctx)->dev); + return twai_ll_is_last_tx_successful((hal_ctx)->dev); } /* ----------------------------- Event Handling ----------------------------- */ @@ -168,15 +168,15 @@ static inline bool can_hal_check_last_tx_successful(can_hal_context_t *hal_ctx) /** * @brief Decode current events that triggered an interrupt * - * This function should be called on every CAN interrupt. It will read (and + * This function should be called on every TWAI interrupt. It will read (and * thereby clear) the interrupt register, then determine what events have * occurred to trigger the interrupt. * * @param hal_ctx Context of the HAL layer - * @param bus_recovering Whether the CAN peripheral was previous undergoing bus recovery + * @param bus_recovering Whether the TWAI peripheral was previous undergoing bus recovery * @return Bit mask of events that have occurred */ -uint32_t can_hal_decode_interrupt_events(can_hal_context_t *hal_ctx, bool bus_recovering); +uint32_t twai_hal_decode_interrupt_events(twai_hal_context_t *hal_ctx, bool bus_recovering); /** * @brief Handle bus recovery complete @@ -187,9 +187,9 @@ uint32_t can_hal_decode_interrupt_events(can_hal_context_t *hal_ctx, bool bus_re * @param hal_ctx Context of the HAL layer * @return True if successfully handled bus recovery completion, false otherwise. */ -static inline bool can_hal_handle_bus_recov_cplt(can_hal_context_t *hal_ctx) +static inline bool twai_hal_handle_bus_recov_cplt(twai_hal_context_t *hal_ctx) { - return can_ll_enter_reset_mode((hal_ctx)->dev); + return twai_ll_enter_reset_mode((hal_ctx)->dev); } /** @@ -200,9 +200,9 @@ static inline bool can_hal_handle_bus_recov_cplt(can_hal_context_t *hal_ctx) * * @param hal_ctx Context of the HAL layer */ -static inline void can_hal_handle_arb_lost(can_hal_context_t *hal_ctx) +static inline void twai_hal_handle_arb_lost(twai_hal_context_t *hal_ctx) { - can_ll_clear_arb_lost_cap((hal_ctx)->dev); + twai_ll_clear_arb_lost_cap((hal_ctx)->dev); } /** @@ -213,9 +213,9 @@ static inline void can_hal_handle_arb_lost(can_hal_context_t *hal_ctx) * * @param hal_ctx Context of the HAL layer */ -static inline void can_hal_handle_bus_error(can_hal_context_t *hal_ctx) +static inline void twai_hal_handle_bus_error(twai_hal_context_t *hal_ctx) { - can_ll_clear_err_code_cap((hal_ctx)->dev); + twai_ll_clear_err_code_cap((hal_ctx)->dev); } /** @@ -226,42 +226,42 @@ static inline void can_hal_handle_bus_error(can_hal_context_t *hal_ctx) * * @param hal_ctx Context of the HAL layer */ -static inline void can_hal_handle_bus_off(can_hal_context_t *hal_ctx) +static inline void twai_hal_handle_bus_off(twai_hal_context_t *hal_ctx) { - can_ll_set_mode((hal_ctx)->dev, CAN_MODE_LISTEN_ONLY); + twai_ll_set_mode((hal_ctx)->dev, TWAI_MODE_LISTEN_ONLY); } /* ------------------------------- TX and RX -------------------------------- */ /** - * @brief Format a CAN Frame + * @brief Format a TWAI Frame * - * This function takes a CAN message structure (containing ID, DLC, data, and + * This function takes a TWAI message structure (containing ID, DLC, data, and * flags) and formats it to match the layout of the TX frame buffer. * - * @param message Pointer to CAN message + * @param message Pointer to TWAI message * @param frame Pointer to empty frame structure */ -static inline void can_hal_format_frame(const can_message_t *message, can_hal_frame_t *frame) +static inline void twai_hal_format_frame(const twai_message_t *message, twai_hal_frame_t *frame) { //Direct call to ll function - can_ll_format_frame_buffer(message->identifier, message->data_length_code, message->data, + twai_ll_format_frame_buffer(message->identifier, message->data_length_code, message->data, message->flags, frame); } /** - * @brief Parse a CAN Frame + * @brief Parse a TWAI Frame * - * This function takes a CAN frame (in the format of the RX frame buffer) and - * parses it to a CAN message (containing ID, DLC, data and flags). + * This function takes a TWAI frame (in the format of the RX frame buffer) and + * parses it to a TWAI message (containing ID, DLC, data and flags). * * @param frame Pointer to frame structure * @param message Pointer to empty message structure */ -static inline void can_hal_parse_frame(can_hal_frame_t *frame, can_message_t *message) +static inline void twai_hal_parse_frame(twai_hal_frame_t *frame, twai_message_t *message) { //Direct call to ll function - can_ll_prase_frame_buffer(frame, &message->identifier, &message->data_length_code, + twai_ll_prase_frame_buffer(frame, &message->identifier, &message->data_length_code, message->data, &message->flags); } @@ -275,7 +275,7 @@ static inline void can_hal_parse_frame(can_hal_frame_t *frame, can_message_t *me * @param hal_ctx Context of the HAL layer * @param tx_frame Pointer to structure containing formatted TX frame */ -void can_hal_set_tx_buffer_and_transmit(can_hal_context_t *hal_ctx, can_hal_frame_t *tx_frame); +void twai_hal_set_tx_buffer_and_transmit(twai_hal_context_t *hal_ctx, twai_hal_frame_t *tx_frame); /** * @brief Copy a frame from the RX buffer and release @@ -286,10 +286,10 @@ void can_hal_set_tx_buffer_and_transmit(can_hal_context_t *hal_ctx, can_hal_fram * @param hal_ctx Context of the HAL layer * @param rx_frame Pointer to structure to store RX frame */ -static inline void can_hal_read_rx_buffer_and_clear(can_hal_context_t *hal_ctx, can_hal_frame_t *rx_frame) +static inline void twai_hal_read_rx_buffer_and_clear(twai_hal_context_t *hal_ctx, twai_hal_frame_t *rx_frame) { - can_ll_get_rx_buffer(hal_ctx->dev, rx_frame); - can_ll_set_cmd_release_rx_buffer(hal_ctx->dev); + twai_ll_get_rx_buffer(hal_ctx->dev, rx_frame); + twai_ll_set_cmd_release_rx_buffer(hal_ctx->dev); /* * Todo: Support overrun handling by: * - Check overrun status bit. Return false if overrun diff --git a/tools/sdk/esp32s2/include/soc/include/hal/can_types.h b/tools/sdk/esp32/include/soc/include/hal/twai_types.h similarity index 55% rename from tools/sdk/esp32s2/include/soc/include/hal/can_types.h rename to tools/sdk/esp32/include/soc/include/hal/twai_types.h index d7947e65..1e6fc7ed 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/can_types.h +++ b/tools/sdk/esp32/include/soc/include/hal/twai_types.h @@ -20,72 +20,78 @@ extern "C" { #include #include +#include "sdkconfig.h" /** - * @brief CAN2.0B Constants + * @brief TWAI Constants */ -#define CAN_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */ -#define CAN_STD_ID_MASK 0x7FF /**< Bit mask for 11 bit Standard Frame Format ID */ -#define CAN_FRAME_MAX_DLC 8 /**< Max data bytes allowed in CAN2.0 */ -#define CAN_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */ -#define CAN_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */ -#define CAN_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */ +#define TWAI_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */ +#define TWAI_STD_ID_MASK 0x7FF /**< Bit mask for 11 bit Standard Frame Format ID */ +#define TWAI_FRAME_MAX_DLC 8 /**< Max data bytes allowed in TWAI */ +#define TWAI_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */ +#define TWAI_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */ +#define TWAI_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */ /** @cond */ //Doxy command to hide preprocessor definitions from docs /** - * @brief CAN Message flags + * @brief TWAI Message flags * * The message flags are used to indicate the type of message transmitted/received. * Some flags also specify the type of transmission. */ -#define CAN_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */ -#define CAN_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */ -#define CAN_MSG_FLAG_RTR 0x02 /**< Message is a Remote Transmit Request */ -#define CAN_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */ -#define CAN_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */ -#define CAN_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B */ +#define TWAI_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */ +#define TWAI_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */ +#define TWAI_MSG_FLAG_RTR 0x02 /**< Message is a Remote Frame */ +#define TWAI_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */ +#define TWAI_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */ +#define TWAI_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with TWAI */ /** * @brief Initializer macros for timing configuration structure * - * The following initializer macros offer commonly found bit rates. + * The following initializer macros offer commonly found bit rates. These macros + * place the sample point at 80% or 67% of a bit time. * * @note These timing values are based on the assumption APB clock is at 80MHz - * @note The 20K, 16K and 12.5K bit rates are only available from ESP32 Revision 2 onwards + * @note The available bit rates are dependent on the chip target and revision. */ -#ifdef CAN_BRP_DIV_SUPPORTED -#define CAN_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#if (TWAI_BRP_MAX > 256) +#define TWAI_TIMING_CONFIG_1KBITS() {.brp = 4000, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_5KBITS() {.brp = 800, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_10KBITS() {.brp = 400, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} #endif -#define CAN_TIMING_CONFIG_25KBITS() {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_50KBITS() {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_100KBITS() {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_125KBITS() {.brp = 32, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_250KBITS() {.brp = 16, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_500KBITS() {.brp = 8, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_800KBITS() {.brp = 4, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_1MBITS() {.brp = 4, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2) +#define TWAI_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#endif +#define TWAI_TIMING_CONFIG_25KBITS() {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_50KBITS() {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_100KBITS() {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_125KBITS() {.brp = 32, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_250KBITS() {.brp = 16, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_500KBITS() {.brp = 8, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_800KBITS() {.brp = 4, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_1MBITS() {.brp = 4, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} /** * @brief Initializer macro for filter configuration to accept all IDs */ -#define CAN_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true} +#define TWAI_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true} /** @endcond */ /** - * @brief CAN Controller operating modes + * @brief TWAI Controller operating modes */ typedef enum { - CAN_MODE_NORMAL, /**< Normal operating mode where CAN controller can send/receive/acknowledge messages */ - CAN_MODE_NO_ACK, /**< Transmission does not require acknowledgment. Use this mode for self testing */ - CAN_MODE_LISTEN_ONLY, /**< The CAN controller will not influence the bus (No transmissions or acknowledgments) but can receive messages */ -} can_mode_t; + TWAI_MODE_NORMAL, /**< Normal operating mode where TWAI controller can send/receive/acknowledge messages */ + TWAI_MODE_NO_ACK, /**< Transmission does not require acknowledgment. Use this mode for self testing */ + TWAI_MODE_LISTEN_ONLY, /**< The TWAI controller will not influence the bus (No transmissions or acknowledgments) but can receive messages */ +} twai_mode_t; /** - * @brief Structure to store a CAN message + * @brief Structure to store a TWAI message * - * @note * @note The flags member is deprecated */ typedef struct { @@ -93,36 +99,36 @@ typedef struct { struct { //The order of these bits must match deprecated message flags for compatibility reasons uint32_t extd: 1; /**< Extended Frame Format (29bit ID) */ - uint32_t rtr: 1; /**< Message is a Remote Transmit Request */ + uint32_t rtr: 1; /**< Message is a Remote Frame */ uint32_t ss: 1; /**< Transmit as a Single Shot Transmission. Unused for received. */ uint32_t self: 1; /**< Transmit as a Self Reception Request. Unused for received. */ - uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B. */ + uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with ISO 11898-1 */ uint32_t reserved: 27; /**< Reserved bits */ }; //Todo: Deprecate flags - uint32_t flags; /**< Alternate way to set message flags using message flag macros (see documentation) */ + uint32_t flags; /**< Deprecated: Alternate way to set bits using message flags */ }; uint32_t identifier; /**< 11 or 29 bit identifier */ uint8_t data_length_code; /**< Data length code */ - uint8_t data[CAN_FRAME_MAX_DLC]; /**< Data bytes (not relevant in RTR frame) */ -} can_message_t; + uint8_t data[TWAI_FRAME_MAX_DLC]; /**< Data bytes (not relevant in RTR frame) */ +} twai_message_t; /** - * @brief Structure for bit timing configuration of the CAN driver + * @brief Structure for bit timing configuration of the TWAI driver * * @note Macro initializers are available for this structure */ typedef struct { - uint32_t brp; /**< Baudrate prescaler (i.e., APB clock divider) can be any even number from 2 to 128. + uint32_t brp; /**< Baudrate prescaler (i.e., APB clock divider). Any even number from 2 to 128 for ESP32, 2 to 32768 for ESP32S2. For ESP32 Rev 2 or later, multiples of 4 from 132 to 256 are also supported */ uint8_t tseg_1; /**< Timing segment 1 (Number of time quanta, between 1 to 16) */ uint8_t tseg_2; /**< Timing segment 2 (Number of time quanta, 1 to 8) */ uint8_t sjw; /**< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4) */ - bool triple_sampling; /**< Enables triple sampling when the CAN controller samples a bit */ -} can_timing_config_t; + bool triple_sampling; /**< Enables triple sampling when the TWAI controller samples a bit */ +} twai_timing_config_t; /** - * @brief Structure for acceptance filter configuration of the CAN driver (see documentation) + * @brief Structure for acceptance filter configuration of the TWAI driver (see documentation) * * @note Macro initializers are available for this structure */ @@ -130,7 +136,7 @@ typedef struct { uint32_t acceptance_code; /**< 32-bit acceptance code */ uint32_t acceptance_mask; /**< 32-bit acceptance mask */ bool single_filter; /**< Use Single Filter Mode (see documentation) */ -} can_filter_config_t; +} twai_filter_config_t; #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/soc/include/soc/lldesc.h b/tools/sdk/esp32/include/soc/include/soc/lldesc.h index 541fa1b7..a991a95d 100644 --- a/tools/sdk/esp32/include/soc/include/soc/lldesc.h +++ b/tools/sdk/esp32/include/soc/include/soc/lldesc.h @@ -20,6 +20,8 @@ #include "esp32/rom/lldesc.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/lldesc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/lldesc.h" #endif //the size field has 12 bits, but 0 not for 4096. @@ -33,13 +35,23 @@ * The caller should ensure there is enough size to hold the array, by calling * ``lldesc_get_required_num``. * - * @param out_desc_array Output of a descriptor array, the head should be fed to the DMA. + * @param[out] out_desc_array Output of a descriptor array, the head should be fed to the DMA. * @param buffer Buffer for the descriptors to point to. * @param size Size (or length for TX) of the buffer * @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false. */ void lldesc_setup_link(lldesc_t *out_desc_array, const void *buffer, int size, bool isrx); +/** + * @brief Get the received length of a linked list, until end of the link or eof. + * + * @param head The head of the linked list. + * @param[out] out_next Output of the next descriptor of the EOF descriptor. Return NULL if there's no + * EOF. Can be set to NULL if next descriptor is not needed. + * @return The accumulation of the `len` field of all descriptors until EOF or the end of the link. + */ +int lldesc_get_received_len(lldesc_t* head, lldesc_t** out_next); + /** * Get the number of descriptors required for a given buffer size. * diff --git a/tools/sdk/esp32/include/soc/include/soc/soc_memory_layout.h b/tools/sdk/esp32/include/soc/include/soc/soc_memory_layout.h index 00f69aec..01b13c51 100644 --- a/tools/sdk/esp32/include/soc/include/soc/soc_memory_layout.h +++ b/tools/sdk/esp32/include/soc/include/soc/soc_memory_layout.h @@ -211,10 +211,10 @@ inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) { } inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) { -#if !CONFIG_FREERTOS_UNICORE || CONFIG_IDF_TARGET_ESP32S2 - return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH); -#else +#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH); +#else + return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH); #endif } diff --git a/tools/sdk/esp32/include/soc/include/soc_log.h b/tools/sdk/esp32/include/soc/include/soc_log.h index a3f955d8..2934eb0c 100644 --- a/tools/sdk/esp32/include/soc/include/soc_log.h +++ b/tools/sdk/esp32/include/soc/include/soc_log.h @@ -13,7 +13,7 @@ // limitations under the License. #pragma once - +#include "esp_rom_sys.h" /** * @file soc_log.h * @brief SOC library logging functions @@ -33,14 +33,16 @@ #else #include "sdkconfig.h" #ifdef CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" +#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif -#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGW(tag, fmt, ...) esp_rom_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGI(tag, fmt, ...) esp_rom_printf("%s(info): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGD(tag, fmt, ...) esp_rom_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGV(tag, fmt, ...) esp_rom_printf("%s: " fmt, tag, ##__VA_ARGS__) #endif //ESP_PLATFORM diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_caps.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_caps.h index 19294fd8..f372e9e0 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_caps.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_caps.h @@ -18,21 +18,15 @@ extern "C" { #endif -#include "sdkconfig.h" +#warning soc/can_caps.h is deprecated, please use soc/twai_caps.h instead -#if __DOXYGEN__ || (CONFIG_ESP32_REV_MIN >= 2) -#define CAN_BRP_DIV_SUPPORTED 1 -#define CAN_BRP_DIV_THRESH 128 -//Any even number from 2 to 128, or multiples of 4 from 132 to 256 -#define CAN_BRP_IS_VALID(brp) (((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) || ((brp) >= 132 && (brp) <= 256 && ((brp) & 0x3) == 0)) -#else -//Any even number from 2 to 128 -#define CAN_BRP_IS_VALID(brp) ((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0) -#endif +/* ---------------------------- Compatibility ------------------------------- */ -//Todo: Add FIFO overrun errata workaround -//Todo: Add ECC decode capabilities -//Todo: Add ALC decode capability +#define CAN_BRP_MIN 2 +#define CAN_BRP_MAX 128 +#define CAN_BRP_MAX_ECO 256 +#define CAN_BRP_DIV_THRESH 128 +#define CAN_SUPPORT_MULTI_ADDRESS_LAYOUT 1 #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/soc/soc/include/soc/can_periph.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_periph.h similarity index 91% rename from tools/sdk/esp32/include/soc/soc/include/soc/can_periph.h rename to tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_periph.h index d21c08d4..f4862b57 100644 --- a/tools/sdk/esp32/include/soc/soc/include/soc/can_periph.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_periph.h @@ -20,6 +20,8 @@ extern "C" { #endif +#warning soc/can_periph.h is deprecated, please use soc/twai_periph.h instead + #if CONFIG_IDF_TARGET_ESP32 #include "soc/can_struct.h" #include "soc/can_caps.h" diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_struct.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_struct.h index 7325cd5a..d56efedd 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_struct.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/can_struct.h @@ -18,191 +18,11 @@ extern "C" { #endif -#include +#warning soc/can_struct.h is deprecated, please use soc/twai_struct.h instead -/* ---------------------------- Register Layout ------------------------------ */ - -/* The CAN peripheral's registers are 8bits, however the ESP32 can only access - * peripheral registers every 32bits. Therefore each CAN register is mapped to - * the least significant byte of every 32bits. - */ - -typedef volatile struct can_dev_s { - //Configuration and Control Registers - union { - struct { - uint32_t rm: 1; /* MOD.0 Reset Mode */ - uint32_t lom: 1; /* MOD.1 Listen Only Mode */ - uint32_t stm: 1; /* MOD.2 Self Test Mode */ - uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */ - uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ - }; - uint32_t val; - } mode_reg; /* Address 0 */ - union { - struct { - uint32_t tr: 1; /* CMR.0 Transmission Request */ - uint32_t at: 1; /* CMR.1 Abort Transmission */ - uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */ - uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */ - uint32_t srr: 1; /* CMR.4 Self Reception Request */ - uint32_t reserved27: 27; /* Internal Reserved */ - }; - uint32_t val; - } command_reg; /* Address 1 */ - union { - struct { - uint32_t rbs: 1; /* SR.0 Receive Buffer Status */ - uint32_t dos: 1; /* SR.1 Data Overrun Status */ - uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */ - uint32_t tcs: 1; /* SR.3 Transmission Complete Status */ - uint32_t rs: 1; /* SR.4 Receive Status */ - uint32_t ts: 1; /* SR.5 Transmit Status */ - uint32_t es: 1; /* SR.6 Error Status */ - uint32_t bs: 1; /* SR.7 Bus Status */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } status_reg; /* Address 2 */ - union { - struct { - uint32_t ri: 1; /* IR.0 Receive Interrupt */ - uint32_t ti: 1; /* IR.1 Transmit Interrupt */ - uint32_t ei: 1; /* IR.2 Error Interrupt */ - uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ - uint32_t epi: 1; /* IR.5 Error Passive Interrupt */ - uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */ - uint32_t bei: 1; /* IR.7 Bus Error Interrupt */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } interrupt_reg; /* Address 3 */ - union { - struct { - uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */ - uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */ - uint32_t eie: 1; /* IER.2 Error Interrupt Enable */ - uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */ - uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */ - uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */ - uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */ - uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } interrupt_enable_reg; /* Address 4 */ - uint32_t reserved_05; /* Address 5 */ - union { - struct { - uint32_t brp: 6; /* BTR0[5:0] Baud Rate Prescaler */ - uint32_t sjw: 2; /* BTR0[7:6] Synchronization Jump Width*/ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } bus_timing_0_reg; /* Address 6 */ - union { - struct { - uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */ - uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */ - uint32_t sam: 1; /* BTR1.7 Sampling*/ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } bus_timing_1_reg; /* Address 7 */ - uint32_t reserved_08; /* Address 8 (Output control not supported) */ - uint32_t reserved_09; /* Address 9 (Test Register not supported) */ - uint32_t reserved_10; /* Address 10 */ - - //Capture and Counter Registers - union { - struct { - uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */ - uint32_t reserved27: 27; /* Internal Reserved */ - }; - uint32_t val; - } arbitration_lost_captue_reg; /* Address 11 */ - union { - struct { - uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ - uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */ - uint32_t errc: 2; /* ECC[7:6] Error Code */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } error_code_capture_reg; /* Address 12 */ - union { - struct { - uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */ - union { - struct { - uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } rx_error_counter_reg; /* Address 12 */ - union { - struct { - uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } tx_error_counter_reg; /* Address 15 */ - - //Shared Registers (TX Buff/RX Buff/Acc Filter) - union { - struct { - union { - struct { - uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } acr[4]; - union { - struct { - uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } amr[4]; - uint32_t reserved32[5]; - } acceptance_filter; - union { - struct { - uint32_t byte: 8; - uint32_t reserved24: 24; - }; - uint32_t val; - } tx_rx_buffer[13]; - }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; - - //Misc Registers - union { - struct { - uint32_t rmc: 5; /* RMC[4:0] RX Message Counter */ - uint32_t reserved27: 27; /* Internal Reserved */ - }; - uint32_t val; - } rx_message_counter_reg; /* Address 29 */ - uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */ - union { - struct { - uint32_t cd: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */ - uint32_t co: 1; /* CDR.3 CLKOUT enable/disable */ - uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */ - uint32_t cm: 1; /* CDR.7 BasicCAN:0 PeliCAN:1 */ - uint32_t reserved24: 24; /* Internal Reserved */ - }; - uint32_t val; - } clock_divider_reg; /* Address 31 */ -} can_dev_t; - -_Static_assert(sizeof(can_dev_t) == 128, "CAN registers should be 32 * 4 bytes"); +#include "soc/twai_struct.h" +typedef twai_dev_t can_dev_t; extern can_dev_t CAN; #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/dport_reg.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/dport_reg.h index b9f2c31e..fe015003 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/dport_reg.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/dport_reg.h @@ -958,7 +958,8 @@ #define DPORT_SPI_DMA_CLK_EN (BIT(22)) #define DPORT_I2S1_CLK_EN (BIT(21)) #define DPORT_PWM1_CLK_EN (BIT(20)) -#define DPORT_CAN_CLK_EN (BIT(19)) +#define DPORT_TWAI_CLK_EN (BIT(19)) +#define DPORT_CAN_CLK_EN DPORT_TWAI_CLK_EN #define DPORT_I2C_EXT1_CLK_EN (BIT(18)) #define DPORT_PWM0_CLK_EN (BIT(17)) #define DPORT_SPI3_CLK_EN (BIT(16)) @@ -992,7 +993,8 @@ #define DPORT_SPI_DMA_RST (BIT(22)) #define DPORT_I2S1_RST (BIT(21)) #define DPORT_PWM1_RST (BIT(20)) -#define DPORT_CAN_RST (BIT(19)) +#define DPORT_TWAI_RST (BIT(19)) +#define DPORT_CAN_RST DPORT_TWAI_RST #define DPORT_I2C_EXT1_RST (BIT(18)) #define DPORT_PWM0_RST (BIT(17)) #define DPORT_SPI3_RST (BIT(16)) diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h index bbe96771..8aa78999 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/efuse_reg.h @@ -114,6 +114,7 @@ #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ /*description: read for SPI_pad_config_hd*/ #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_caps.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_caps.h index 0737f140..3c202c73 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_caps.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_caps.h @@ -43,6 +43,9 @@ extern "C" { #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34)) /*!< Check whether it can be a valid GPIO number of output mode */ #define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) /*!< Check whether it contains input io */ +#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30) + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_sig_map.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_sig_map.h index 1d3dc5b0..b2114d85 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_sig_map.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/gpio_sig_map.h @@ -194,7 +194,8 @@ #define RMT_SIG_OUT5_IDX 92 #define EXT_ADC_START_IDX 93 #define RMT_SIG_OUT6_IDX 93 -#define CAN_RX_IDX 94 +#define TWAI_RX_IDX 94 +#define CAN_RX_IDX TWAI_RX_IDX #define RMT_SIG_OUT7_IDX 94 #define I2CEXT1_SCL_IN_IDX 95 #define I2CEXT1_SCL_OUT_IDX 95 @@ -252,10 +253,13 @@ #define PWM2_OUT4L_IDX 121 #define PWM3_CAP1_IN_IDX 122 #define PWM3_CAP2_IN_IDX 123 -#define CAN_TX_IDX 123 +#define TWAI_TX_IDX 123 +#define CAN_TX_IDX TWAI_TX_IDX #define PWM3_CAP3_IN_IDX 124 -#define CAN_BUS_OFF_ON_IDX 124 -#define CAN_CLKOUT_IDX 125 +#define TWAI_BUS_OFF_ON_IDX 124 +#define CAN_BUS_OFF_ON_IDX TWAI_BUS_OFF_ON_IDX +#define TWAI_CLKOUT_IDX 125 +#define CAN_CLKOUT_IDX TWAI_CLKOUT_IDX #define SPID4_IN_IDX 128 #define SPID4_OUT_IDX 128 #define SPID5_IN_IDX 129 diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/host_reg.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/host_reg.h index ef556e21..fe7c59bd 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/host_reg.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/host_reg.h @@ -812,8 +812,6 @@ #define HOST_SLCHOST_STATE4_V 0xFF #define HOST_SLCHOST_STATE4_S 0 -#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0)) - #define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C) /* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ /*description: */ diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/periph_defs.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/periph_defs.h index 98dce396..a818ac30 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/periph_defs.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/periph_defs.h @@ -44,7 +44,8 @@ typedef enum { PERIPH_SPI_DMA_MODULE, PERIPH_SDMMC_MODULE, PERIPH_SDIO_SLAVE_MODULE, - PERIPH_CAN_MODULE, + PERIPH_TWAI_MODULE, + PERIPH_CAN_MODULE = PERIPH_TWAI_MODULE, PERIPH_EMAC_MODULE, PERIPH_RNG_MODULE, PERIPH_WIFI_MODULE, diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h index 96982a03..e955a69f 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/rtc.h @@ -645,6 +645,8 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void); */ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h index dd78cab5..a6c62f28 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc.h @@ -327,7 +327,8 @@ #define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/ #define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ #define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ -#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/ +#define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/ +#define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE #define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ #define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ #define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc_caps.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc_caps.h index bb01067a..a9e8e2c9 100644 --- a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc_caps.h +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/soc_caps.h @@ -9,7 +9,8 @@ #define SOC_SDMMC_HOST_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 #define SOC_SDIO_SLAVE_SUPPORTED 1 -#define SOC_CAN_SUPPORTED 1 +#define SOC_TWAI_SUPPORTED 1 +#define SOC_CAN_SUPPORTED SOC_TWAI_SUPPORTED #define SOC_EMAC_SUPPORTED 1 - +#define SOC_RISCV_COPROC_SUPPORTED 0 #define SOC_CPU_CORES_NUM 2 diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/twai_caps.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/twai_caps.h new file mode 100644 index 00000000..03cf1559 --- /dev/null +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/twai_caps.h @@ -0,0 +1,29 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define TWAI_BRP_MIN 2 +#define TWAI_BRP_MAX 128 +#define TWAI_BRP_MAX_ECO 256 +#define TWAI_BRP_DIV_THRESH 128 +#define TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT 1 + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/soc/esp32/include/soc/twai_struct.h b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/twai_struct.h new file mode 100644 index 00000000..e9454e1c --- /dev/null +++ b/tools/sdk/esp32/include/soc/soc/esp32/include/soc/twai_struct.h @@ -0,0 +1,210 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* ---------------------------- Register Layout ------------------------------ */ + +/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access + * peripheral registers every 32bits. Therefore each TWAI register is mapped to + * the least significant byte of every 32bits. + */ + +typedef volatile struct twai_dev_s { + //Configuration and Control Registers + union { + struct { + uint32_t rm: 1; /* MOD.0 Reset Mode */ + uint32_t lom: 1; /* MOD.1 Listen Only Mode */ + uint32_t stm: 1; /* MOD.2 Self Test Mode */ + uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */ + uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ + }; + uint32_t val; + } mode_reg; /* Address 0 */ + union { + struct { + uint32_t tr: 1; /* CMR.0 Transmission Request */ + uint32_t at: 1; /* CMR.1 Abort Transmission */ + uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */ + uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */ + uint32_t srr: 1; /* CMR.4 Self Reception Request */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; + } command_reg; /* Address 1 */ + union { + struct { + uint32_t rbs: 1; /* SR.0 Receive Buffer Status */ + uint32_t dos: 1; /* SR.1 Data Overrun Status */ + uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */ + uint32_t tcs: 1; /* SR.3 Transmission Complete Status */ + uint32_t rs: 1; /* SR.4 Receive Status */ + uint32_t ts: 1; /* SR.5 Transmit Status */ + uint32_t es: 1; /* SR.6 Error Status */ + uint32_t bs: 1; /* SR.7 Bus Status */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } status_reg; /* Address 2 */ + union { + struct { + uint32_t ri: 1; /* IR.0 Receive Interrupt */ + uint32_t ti: 1; /* IR.1 Transmit Interrupt */ + uint32_t ei: 1; /* IR.2 Error Interrupt */ + uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ + uint32_t epi: 1; /* IR.5 Error Passive Interrupt */ + uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */ + uint32_t bei: 1; /* IR.7 Bus Error Interrupt */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } interrupt_reg; /* Address 3 */ + union { + struct { + uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */ + uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */ + uint32_t eie: 1; /* IER.2 Error Interrupt Enable */ + uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */ + uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */ + uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */ + uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */ + uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } interrupt_enable_reg; /* Address 4 */ + uint32_t reserved_05; /* Address 5 */ + union { + struct { + uint32_t brp: 6; /* BTR0[5:0] Baud Rate Prescaler */ + uint32_t sjw: 2; /* BTR0[7:6] Synchronization Jump Width*/ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } bus_timing_0_reg; /* Address 6 */ + union { + struct { + uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */ + uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */ + uint32_t sam: 1; /* BTR1.7 Sampling*/ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } bus_timing_1_reg; /* Address 7 */ + uint32_t reserved_08; /* Address 8 (Output control not supported) */ + uint32_t reserved_09; /* Address 9 (Test Register not supported) */ + uint32_t reserved_10; /* Address 10 */ + + //Capture and Counter Registers + union { + struct { + uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; + } arbitration_lost_captue_reg; /* Address 11 */ + union { + struct { + uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ + uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */ + uint32_t errc: 2; /* ECC[7:6] Error Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } error_code_capture_reg; /* Address 12 */ + union { + struct { + uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */ + union { + struct { + uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } rx_error_counter_reg; /* Address 12 */ + union { + struct { + uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } tx_error_counter_reg; /* Address 15 */ + + //Shared Registers (TX Buff/RX Buff/Acc Filter) + union { + struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved32[5]; + } acceptance_filter; + union { + struct { + uint32_t byte: 8; + uint32_t reserved24: 24; + }; + uint32_t val; + } tx_rx_buffer[13]; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + + //Misc Registers + union { + struct { + uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */ + uint32_t reserved25: 25; /* Internal Reserved */ + }; + uint32_t val; + } rx_message_counter_reg; /* Address 29 */ + uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */ + union { + struct { + uint32_t cd: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */ + uint32_t co: 1; /* CDR.3 CLKOUT enable/disable */ + uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */ + uint32_t cm: 1; /* CDR.7 Register Layout. Basic:0 Extended:1 */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } clock_divider_reg; /* Address 31 */ +} twai_dev_t; + +_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes"); + +extern twai_dev_t TWAI; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/soc/include/soc/spi_periph.h b/tools/sdk/esp32/include/soc/soc/include/soc/spi_periph.h index 32b873fe..79b637ce 100644 --- a/tools/sdk/esp32/include/soc/soc/include/soc/spi_periph.h +++ b/tools/sdk/esp32/include/soc/soc/include/soc/spi_periph.h @@ -14,6 +14,7 @@ #pragma once #include +#include "sdkconfig.h" #include "soc/soc.h" #include "soc/periph_defs.h" @@ -22,8 +23,7 @@ #include "soc/spi_reg.h" #include "soc/spi_struct.h" #include "soc/gpio_sig_map.h" -#include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32S2 +#if SOC_MEMSPI_IS_INDEPENDENT #include "soc/spi_mem_struct.h" #include "soc/spi_mem_reg.h" #endif diff --git a/tools/sdk/esp32s2/include/soc/soc/include/soc/can_periph.h b/tools/sdk/esp32/include/soc/soc/include/soc/twai_periph.h similarity index 89% rename from tools/sdk/esp32s2/include/soc/soc/include/soc/can_periph.h rename to tools/sdk/esp32/include/soc/soc/include/soc/twai_periph.h index d21c08d4..b59a4bae 100644 --- a/tools/sdk/esp32s2/include/soc/soc/include/soc/can_periph.h +++ b/tools/sdk/esp32/include/soc/soc/include/soc/twai_periph.h @@ -20,10 +20,8 @@ extern "C" { #endif -#if CONFIG_IDF_TARGET_ESP32 -#include "soc/can_struct.h" -#include "soc/can_caps.h" -#endif +#include "soc/twai_struct.h" +#include "soc/twai_caps.h" #ifdef __cplusplus } diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_hal.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_hal.h index 091c51d2..1bd84bd2 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_hal.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_hal.h @@ -100,19 +100,6 @@ void adc_hal_digi_deinit(void); */ int adc_hal_hall_convert(void); -/** - * @brief Output ADC2 reference voltage to gpio - * - * This function utilizes the testing mux exclusive to ADC2 to route the - * reference voltage one of ADC2's channels. - * - * @param[in] io GPIO number - * @return - * - true: v_ref successfully routed to selected gpio - * - false: Unsupported gpio - */ -#define adc_hal_vref_output(io) adc_ll_vref_output(io) - #ifdef __cplusplus } #endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_ll.h index 6e15d882..a472ae66 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_ll.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_ll.h @@ -673,43 +673,43 @@ static inline void adc_ll_set_hall_controller(adc_ll_hall_controller_t hall_ctrl } /** - * Output ADC2 reference voltage to gpio 25 or 26 or 27 + * Output ADC internal reference voltage to channels, only available for ADC2 on ESP32. * - * This function utilizes the testing mux exclusive to ADC 2 to route the - * reference voltage one of ADC2's channels. Supported gpios are gpios - * 25, 26, and 27. This refernce voltage can be manually read from the pin - * and used in the esp_adc_cal component. + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. * - * @param[in] io GPIO number (gpios 25,26,27 supported) - * - * @return - * - true: v_ref successfully routed to selected gpio - * - false: Unsupported gpio + * @param[in] adc ADC unit select + * @param[in] channel ADC2 channel number + * @param[in] en Enable/disable the reference voltage output */ -static inline bool adc_ll_vref_output(int io) +static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) { - int channel; - if (io == 25) { - channel = 8; //Channel 8 bit - } else if (io == 26) { - channel = 9; //Channel 9 bit - } else if (io == 27) { - channel = 7; //Channel 7 bit + if (adc != ADC_NUM_2) return; + + if (en) { + RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode + //set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2) + RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels + //set ent + RTCCNTL.test_mux.ent_rtc = 1; + //set sar2_en_test + SENS.sar_start_force.sar2_en_test = 1; + //set sar2 en force + SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW + //set en_pad for channels 7,8,9 (bits 0x380) + SENS.sar_meas_start2.sar2_en_pad = 1 << channel; } else { - return false; + RTCCNTL.test_mux.dtest_rtc = 0; //Config test mux to route v_ref to ADC2 Channels + //set ent + RTCCNTL.test_mux.ent_rtc = 0; + //set sar2_en_test + SENS.sar_start_force.sar2_en_test = 0; + //set sar2 en force + SENS.sar_meas_start2.sar2_en_pad_force = 0; //Pad bitmap controlled by SW + //set en_pad for channels 7,8,9 (bits 0x380) + SENS.sar_meas_start2.sar2_en_pad = 0; } - RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode - //set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2) - RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels - //set ent - RTCCNTL.test_mux.ent_rtc = 1; - //set sar2_en_test - SENS.sar_start_force.sar2_en_test = 1; - //set sar2 en force - SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW - //set en_pad for channels 7,8,9 (bits 0x380) - SENS.sar_meas_start2.sar2_en_pad = 1 << channel; - return true; } #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_hal.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_hal.h new file mode 100644 index 00000000..9a1c1246 --- /dev/null +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_hal.h @@ -0,0 +1,154 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#warning hal/can_hal.h is deprecated, please use hal/twai_hal.h instead + +#include "hal/twai_hal.h" +#include "hal/can_types.h" + +/* ------------------------- Defines and Typedefs --------------------------- */ + +//Error active interrupt related +#define CAN_HAL_EVENT_BUS_OFF TWAI_HAL_EVENT_BUS_OFF +#define CAN_HAL_EVENT_BUS_RECOV_CPLT TWAI_HAL_EVENT_BUS_RECOV_CPLT +#define CAN_HAL_EVENT_BUS_RECOV_PROGRESS TWAI_HAL_EVENT_BUS_RECOV_PROGRESS +#define CAN_HAL_EVENT_ABOVE_EWL TWAI_HAL_EVENT_ABOVE_EWL +#define CAN_HAL_EVENT_BELOW_EWL TWAI_HAL_EVENT_BELOW_EWL +#define CAN_HAL_EVENT_ERROR_PASSIVE TWAI_HAL_EVENT_ERROR_PASSIVE +#define CAN_HAL_EVENT_ERROR_ACTIVE TWAI_HAL_EVENT_ERROR_ACTIVE +#define CAN_HAL_EVENT_BUS_ERR TWAI_HAL_EVENT_BUS_ERR +#define CAN_HAL_EVENT_ARB_LOST TWAI_HAL_EVENT_ARB_LOST +#define CAN_HAL_EVENT_RX_BUFF_FRAME TWAI_HAL_EVENT_RX_BUFF_FRAME +#define CAN_HAL_EVENT_TX_BUFF_FREE TWAI_HAL_EVENT_TX_BUFF_FREE + +typedef twai_hal_context_t can_hal_context_t; + +typedef twai_hal_frame_t can_hal_frame_t; + +/* ---------------------------- Init and Config ----------------------------- */ + +static inline bool can_hal_init(can_hal_context_t *hal_ctx){ + return twai_hal_init(hal_ctx); +} + +static inline void can_hal_deinit(can_hal_context_t *hal_ctx) +{ + twai_hal_deinit(hal_ctx); +} + +static inline void can_hal_configure(can_hal_context_t *hal_ctx, const can_timing_config_t *t_config, const can_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider) +{ + twai_hal_configure(hal_ctx, t_config, f_config, intr_mask, clkout_divider); +} + +/* -------------------------------- Actions --------------------------------- */ + +static inline bool can_hal_start(can_hal_context_t *hal_ctx, can_mode_t mode) +{ + return twai_hal_start(hal_ctx, mode); +} + +static inline bool can_hal_stop(can_hal_context_t *hal_ctx) +{ + return twai_hal_stop(hal_ctx); +} + +static inline bool can_hal_start_bus_recovery(can_hal_context_t *hal_ctx) +{ + return twai_hal_start_bus_recovery(hal_ctx); +} + +static inline uint32_t can_hal_get_tec(can_hal_context_t *hal_ctx) +{ + return twai_hal_get_tec(hal_ctx); +} + +static inline uint32_t can_hal_get_rec(can_hal_context_t *hal_ctx) +{ + return twai_hal_get_rec(hal_ctx); +} + +static inline uint32_t can_hal_get_rx_msg_count(can_hal_context_t *hal_ctx) +{ + return twai_hal_get_rx_msg_count(hal_ctx); +} + +static inline bool can_hal_check_last_tx_successful(can_hal_context_t *hal_ctx) +{ + return twai_hal_check_last_tx_successful(hal_ctx); +} + +/* ----------------------------- Event Handling ----------------------------- */ + +static inline uint32_t can_hal_decode_interrupt_events(can_hal_context_t *hal_ctx, bool bus_recovering) { + return twai_hal_decode_interrupt_events(hal_ctx, bus_recovering); +} + +static inline bool can_hal_handle_bus_recov_cplt(can_hal_context_t *hal_ctx) +{ + return twai_hal_handle_bus_recov_cplt(hal_ctx); +} + +static inline void can_hal_handle_arb_lost(can_hal_context_t *hal_ctx) +{ + twai_hal_handle_arb_lost(hal_ctx); +} + +static inline void can_hal_handle_bus_error(can_hal_context_t *hal_ctx) +{ + twai_hal_handle_bus_error(hal_ctx); +} + +static inline void can_hal_handle_bus_off(can_hal_context_t *hal_ctx) +{ + twai_hal_handle_bus_off(hal_ctx); +} + +/* ------------------------------- TX and RX -------------------------------- */ + +static inline void can_hal_format_frame(const can_message_t *message, can_hal_frame_t *frame) +{ + twai_hal_format_frame(message, frame); +} + +static inline void can_hal_parse_frame(can_hal_frame_t *frame, can_message_t *message) +{ + twai_hal_parse_frame(frame, message); +} + +static inline void can_hal_set_tx_buffer_and_transmit(can_hal_context_t *hal_ctx, can_hal_frame_t *tx_frame) +{ + twai_hal_set_tx_buffer_and_transmit(hal_ctx, tx_frame); +} + +static inline void can_hal_read_rx_buffer_and_clear(can_hal_context_t *hal_ctx, can_hal_frame_t *rx_frame) +{ + twai_hal_read_rx_buffer_and_clear(hal_ctx, rx_frame); +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_ll.h index c498ed59..9fa48179 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_ll.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_ll.h @@ -26,676 +26,227 @@ extern "C" { #endif -#include -#include +#warning hal/can_ll.h is deprecated, please use hal/twai_ll.h instead + +#include "hal/twai_ll.h" #include "hal/can_types.h" #include "soc/can_periph.h" /* ------------------------- Defines and Typedefs --------------------------- */ -#define CAN_LL_STATUS_RBS (0x1 << 0) -#define CAN_LL_STATUS_DOS (0x1 << 1) -#define CAN_LL_STATUS_TBS (0x1 << 2) -#define CAN_LL_STATUS_TCS (0x1 << 3) -#define CAN_LL_STATUS_RS (0x1 << 4) -#define CAN_LL_STATUS_TS (0x1 << 5) -#define CAN_LL_STATUS_ES (0x1 << 6) -#define CAN_LL_STATUS_BS (0x1 << 7) +#define CAN_LL_STATUS_RBS TWAI_LL_STATUS_RBS +#define CAN_LL_STATUS_DOS TWAI_LL_STATUS_DOS +#define CAN_LL_STATUS_TBS TWAI_LL_STATUS_TBS +#define CAN_LL_STATUS_TCS TWAI_LL_STATUS_TCS +#define CAN_LL_STATUS_RS TWAI_LL_STATUS_RS +#define CAN_LL_STATUS_TS TWAI_LL_STATUS_TS +#define CAN_LL_STATUS_ES TWAI_LL_STATUS_ES +#define CAN_LL_STATUS_BS TWAI_LL_STATUS_BS -#define CAN_LL_INTR_RI (0x1 << 0) -#define CAN_LL_INTR_TI (0x1 << 1) -#define CAN_LL_INTR_EI (0x1 << 2) -//Data overrun interrupt not supported in SW due to HW peculiarities -#define CAN_LL_INTR_EPI (0x1 << 5) -#define CAN_LL_INTR_ALI (0x1 << 6) -#define CAN_LL_INTR_BEI (0x1 << 7) +#define CAN_LL_INTR_RI TWAI_LL_INTR_RI +#define CAN_LL_INTR_TI TWAI_LL_INTR_TI +#define CAN_LL_INTR_EI TWAI_LL_INTR_EI +#define CAN_LL_INTR_EPI TWAI_LL_INTR_EPI +#define CAN_LL_INTR_ALI TWAI_LL_INTR_ALI +#define CAN_LL_INTR_BEI TWAI_LL_INTR_BEI -/* - * The following frame structure has an NEARLY identical bit field layout to - * each byte of the TX buffer. This allows for formatting and parsing frames to - * be done outside of time critical regions (i.e., ISRs). All the ISR needs to - * do is to copy byte by byte to/from the TX/RX buffer. The two reserved bits in - * TX buffer are used in the frame structure to store the self_reception and - * single_shot flags which in turn indicate the type of transmission to execute. - */ -typedef union { - struct { - struct { - uint8_t dlc: 4; //Data length code (0 to 8) of the frame - uint8_t self_reception: 1; //This frame should be transmitted using self reception command - uint8_t single_shot: 1; //This frame should be transmitted using single shot command - uint8_t rtr: 1; //This frame is a remote transmission request - uint8_t frame_format: 1; //Format of the frame (1 = extended, 0 = standard) - }; - union { - struct { - uint8_t id[2]; //11 bit standard frame identifier - uint8_t data[8]; //Data bytes (0 to 8) - uint8_t reserved8[2]; - } standard; - struct { - uint8_t id[4]; //29 bit extended frame identifier - uint8_t data[8]; //Data bytes (0 to 8) - } extended; - }; - }; - uint8_t bytes[13]; -} __attribute__((packed)) can_ll_frame_buffer_t; +typedef twai_ll_frame_buffer_t can_ll_frame_buffer_t; /* ---------------------------- Mode Register ------------------------------- */ -/** - * @brief Enter reset mode - * - * When in reset mode, the CAN controller is effectively disconnected from the - * CAN bus and will not participate in any bus activates. Reset mode is required - * in order to write the majority of configuration registers. - * - * @param hw Start address of the CAN registers - * @return true if reset mode was entered successfully - * - * @note Reset mode is automatically entered on BUS OFF condition - */ static inline bool can_ll_enter_reset_mode(can_dev_t *hw) { - hw->mode_reg.rm = 1; - return hw->mode_reg.rm; + return twai_ll_enter_reset_mode(hw); } -/** - * @brief Exit reset mode - * - * When not in reset mode, the CAN controller will take part in bus activities - * (e.g., send/receive/acknowledge messages and error frames) depending on the - * operating mode. - * - * @param hw Start address of the CAN registers - * @return true if reset mode was exit successfully - * - * @note Reset mode must be exit to initiate BUS OFF recovery - */ static inline bool can_ll_exit_reset_mode(can_dev_t *hw) { - hw->mode_reg.rm = 0; - return !(hw->mode_reg.rm); + return twai_ll_exit_reset_mode(hw); } -/** - * @brief Check if in reset mode - * @param hw Start address of the CAN registers - * @return true if in reset mode - */ static inline bool can_ll_is_in_reset_mode(can_dev_t *hw) { - return hw->mode_reg.rm; + return twai_ll_is_in_reset_mode(hw); } -/** - * @brief Set operating mode of CAN controller - * - * @param hw Start address of the CAN registers - * @param mode Operating mode - * - * @note Must be called in reset mode - */ static inline void can_ll_set_mode(can_dev_t *hw, can_mode_t mode) { - if (mode == CAN_MODE_NORMAL) { //Normal Operating mode - hw->mode_reg.lom = 0; - hw->mode_reg.stm = 0; - } else if (mode == CAN_MODE_NO_ACK) { //Self Test Mode (No Ack) - hw->mode_reg.lom = 0; - hw->mode_reg.stm = 1; - } else if (mode == CAN_MODE_LISTEN_ONLY) { //Listen Only Mode - hw->mode_reg.lom = 1; - hw->mode_reg.stm = 0; - } + twai_ll_set_mode(hw, mode); } /* --------------------------- Command Register ----------------------------- */ -/** - * @brief Set TX command - * - * Setting the TX command will cause the CAN controller to attempt to transmit - * the frame stored in the TX buffer. The TX buffer will be occupied (i.e., - * locked) until TX completes. - * - * @param hw Start address of the CAN registers - * - * @note Transmit commands should be called last (i.e., after handling buffer - * release and clear data overrun) in order to prevent the other commands - * overwriting this latched TX bit with 0. - */ static inline void can_ll_set_cmd_tx(can_dev_t *hw) { - hw->command_reg.tr = 1; + twai_ll_set_cmd_tx(hw); } -/** - * @brief Set single shot TX command - * - * Similar to setting TX command, but the CAN controller will not automatically - * retry transmission upon an error (e.g., due to an acknowledgement error). - * - * @param hw Start address of the CAN registers - * - * @note Transmit commands should be called last (i.e., after handling buffer - * release and clear data overrun) in order to prevent the other commands - * overwriting this latched TX bit with 0. - */ static inline void can_ll_set_cmd_tx_single_shot(can_dev_t *hw) { - hw->command_reg.val = 0x03; //Writing to TR and AT simultaneously + twai_ll_set_cmd_tx_single_shot(hw); } -/** - * @brief Aborts TX - * - * Frames awaiting TX will be aborted. Frames already being TX are not aborted. - * Transmission Complete Status bit is automatically set to 1. - * Similar to setting TX command, but the CAN controller will not automatically - * retry transmission upon an error (e.g., due to acknowledge error). - * - * @param hw Start address of the CAN registers - * - * @note Transmit commands should be called last (i.e., after handling buffer - * release and clear data overrun) in order to prevent the other commands - * overwriting this latched TX bit with 0. - */ static inline void can_ll_set_cmd_abort_tx(can_dev_t *hw) { - hw->command_reg.at = 1; + twai_ll_set_cmd_abort_tx(hw); } -/** - * @brief Release RX buffer - * - * Rotates RX buffer to the next frame in the RX FIFO. - * - * @param hw Start address of the CAN registers - */ static inline void can_ll_set_cmd_release_rx_buffer(can_dev_t *hw) { - hw->command_reg.rrb = 1; + twai_ll_set_cmd_release_rx_buffer(hw); } -/** - * @brief Clear data overrun - * - * Clears the data overrun status bit - * - * @param hw Start address of the CAN registers - */ static inline void can_ll_set_cmd_clear_data_overrun(can_dev_t *hw) { - hw->command_reg.cdo = 1; + twai_ll_set_cmd_clear_data_overrun(hw); } -/** - * @brief Set self reception single shot command - * - * Similar to setting TX command, but the CAN controller also simultaneously - * receive the transmitted frame and is generally used for self testing - * purposes. The CAN controller will not ACK the received message, so consider - * using the NO_ACK operating mode. - * - * @param hw Start address of the CAN registers - * - * @note Transmit commands should be called last (i.e., after handling buffer - * release and clear data overrun) in order to prevent the other commands - * overwriting this latched TX bit with 0. - */ static inline void can_ll_set_cmd_self_rx_request(can_dev_t *hw) { - hw->command_reg.srr = 1; + twai_ll_set_cmd_self_rx_request(hw); } -/** - * @brief Set self reception request command - * - * Similar to setting the self reception request, but the CAN controller will - * not automatically retry transmission upon an error (e.g., due to and - * acknowledgement error). - * - * @param hw Start address of the CAN registers - * - * @note Transmit commands should be called last (i.e., after handling buffer - * release and clear data overrun) in order to prevent the other commands - * overwriting this latched TX bit with 0. - */ static inline void can_ll_set_cmd_self_rx_single_shot(can_dev_t *hw) { - hw->command_reg.val = 0x12; + twai_ll_set_cmd_self_rx_single_shot(hw); } /* --------------------------- Status Register ------------------------------ */ -/** - * @brief Get all status bits - * - * @param hw Start address of the CAN registers - * @return Status bits - */ static inline uint32_t can_ll_get_status(can_dev_t *hw) { - return hw->status_reg.val; + return twai_ll_get_status(hw); } -/** - * @brief Check if RX FIFO overrun status bit is set - * - * @param hw Start address of the CAN registers - * @return Overrun status bit - */ static inline bool can_ll_is_fifo_overrun(can_dev_t *hw) { - return hw->status_reg.dos; + return twai_ll_is_fifo_overrun(hw); } -/** - * @brief Check if previously TX was successful - * - * @param hw Start address of the CAN registers - * @return Whether previous TX was successful - */ static inline bool can_ll_is_last_tx_successful(can_dev_t *hw) { - return hw->status_reg.tcs; + return twai_ll_is_last_tx_successful(hw); } -//Todo: Add stand alone status bit check functions when necessary - /* -------------------------- Interrupt Register ---------------------------- */ -/** - * @brief Get currently set interrupts - * - * Reading the interrupt registers will automatically clear all interrupts - * except for the Receive Interrupt. - * - * @param hw Start address of the CAN registers - * @return Bit mask of set interrupts - */ static inline uint32_t can_ll_get_and_clear_intrs(can_dev_t *hw) { - return hw->interrupt_reg.val; + return twai_ll_get_and_clear_intrs(hw); } /* ----------------------- Interrupt Enable Register ------------------------ */ -/** - * @brief Set which interrupts are enabled - * - * @param hw Start address of the CAN registers - * @param Bit mask of interrupts to enable - * - * @note Must be called in reset mode - */ static inline void can_ll_set_enabled_intrs(can_dev_t *hw, uint32_t intr_mask) { -#ifdef CAN_BRP_DIV_SUPPORTED - //ESP32 Rev 2 has brp div. Need to mask when setting - hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask; -#else - hw->interrupt_enable_reg.val = intr_mask; -#endif + twai_ll_set_enabled_intrs(hw, intr_mask); } /* ------------------------ Bus Timing Registers --------------------------- */ -/** - * @brief Set bus timing - * - * @param hw Start address of the CAN registers - * @param brp Baud Rate Prescaler - * @param sjw Synchronization Jump Width - * @param tseg1 Timing Segment 1 - * @param tseg2 Timing Segment 2 - * @param triple_sampling Triple Sampling enable/disable - * - * @note Must be called in reset mode - * @note ESP32 rev 2 or later can support a x2 brp by setting a brp_div bit, - * allowing the brp to go from a maximum of 128 to 256. - */ static inline void can_ll_set_bus_timing(can_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling) { -#ifdef CAN_BRP_DIV_SUPPORTED - if (brp > CAN_BRP_DIV_THRESH) { - //Need to set brp_div bit - hw->interrupt_enable_reg.brp_div = 1; - brp /= 2; - } -#endif - hw->bus_timing_0_reg.brp = (brp / 2) - 1; - hw->bus_timing_0_reg.sjw = sjw - 1; - hw->bus_timing_1_reg.tseg1 = tseg1 - 1; - hw->bus_timing_1_reg.tseg2 = tseg2 - 1; - hw->bus_timing_1_reg.sam = triple_sampling; + twai_ll_set_bus_timing(hw, brp, sjw, tseg1, tseg2, triple_sampling); } /* ----------------------------- ALC Register ------------------------------- */ -/** - * @brief Clear Arbitration Lost Capture Register - * - * Reading the ALC register rearms the Arbitration Lost Interrupt - * - * @param hw Start address of the CAN registers - */ static inline void can_ll_clear_arb_lost_cap(can_dev_t *hw) { - (void)hw->arbitration_lost_captue_reg.val; - //Todo: Decode ALC register + twai_ll_clear_arb_lost_cap(hw); } /* ----------------------------- ECC Register ------------------------------- */ -/** - * @brief Clear Error Code Capture register - * - * Reading the ECC register rearms the Bus Error Interrupt - * - * @param hw Start address of the CAN registers - */ static inline void can_ll_clear_err_code_cap(can_dev_t *hw) { - (void)hw->error_code_capture_reg.val; - //Todo: Decode error code capture + twai_ll_clear_err_code_cap(hw); } /* ----------------------------- EWL Register ------------------------------- */ -/** - * @brief Set Error Warning Limit - * - * @param hw Start address of the CAN registers - * @param ewl Error Warning Limit - * - * @note Must be called in reset mode - */ static inline void can_ll_set_err_warn_lim(can_dev_t *hw, uint32_t ewl) { - hw->error_warning_limit_reg.ewl = ewl; + twai_ll_set_err_warn_lim(hw, ewl); } -/** - * @brief Get Error Warning Limit - * - * @param hw Start address of the CAN registers - * @return Error Warning Limit - */ static inline uint32_t can_ll_get_err_warn_lim(can_dev_t *hw) { - return hw->error_warning_limit_reg.val; + return twai_ll_get_err_warn_lim(hw); } /* ------------------------ RX Error Count Register ------------------------- */ -/** - * @brief Get RX Error Counter - * - * @param hw Start address of the CAN registers - * @return REC value - * - * @note REC is not frozen in reset mode. Listen only mode will freeze it. A BUS - * OFF condition automatically sets the REC to 0. - */ static inline uint32_t can_ll_get_rec(can_dev_t *hw) { - return hw->rx_error_counter_reg.val; + return twai_ll_get_rec(hw); } -/** - * @brief Set RX Error Counter - * - * @param hw Start address of the CAN registers - * @param rec REC value - * - * @note Must be called in reset mode - */ static inline void can_ll_set_rec(can_dev_t *hw, uint32_t rec) { - hw->rx_error_counter_reg.rxerr = rec; + twai_ll_set_rec(hw, rec); } /* ------------------------ TX Error Count Register ------------------------- */ -/** - * @brief Get TX Error Counter - * - * @param hw Start address of the CAN registers - * @return TEC value - * - * @note A BUS OFF condition will automatically set this to 128 - */ static inline uint32_t can_ll_get_tec(can_dev_t *hw) { - return hw->tx_error_counter_reg.val; + return twai_ll_get_tec(hw); } -/** - * @brief Set TX Error Counter - * - * @param hw Start address of the CAN registers - * @param tec TEC value - * - * @note Must be called in reset mode - */ static inline void can_ll_set_tec(can_dev_t *hw, uint32_t tec) { - hw->tx_error_counter_reg.txerr = tec; + twai_ll_set_tec(hw, tec); } /* ---------------------- Acceptance Filter Registers ----------------------- */ -/** - * @brief Set Acceptance Filter - * @param hw Start address of the CAN registers - * @param code Acceptance Code - * @param mask Acceptance Mask - * @param single_filter Whether to enable single filter mode - * - * @note Must be called in reset mode - */ static inline void can_ll_set_acc_filter(can_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter) { - uint32_t code_swapped = __builtin_bswap32(code); - uint32_t mask_swapped = __builtin_bswap32(mask); - for (int i = 0; i < 4; i++) { - hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF); - hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF); - } - hw->mode_reg.afm = single_filter; + twai_ll_set_acc_filter(hw, code, mask, single_filter); } /* ------------------------- TX/RX Buffer Registers ------------------------- */ -/** - * @brief Copy a formatted CAN frame into TX buffer for transmission - * - * @param hw Start address of the CAN registers - * @param tx_frame Pointer to formatted frame - * - * @note Call can_ll_format_frame_buffer() to format a frame - */ static inline void can_ll_set_tx_buffer(can_dev_t *hw, can_ll_frame_buffer_t *tx_frame) { - //Copy formatted frame into TX buffer - for (int i = 0; i < 13; i++) { - hw->tx_rx_buffer[i].val = tx_frame->bytes[i]; - } + twai_ll_set_tx_buffer(hw, tx_frame); } -/** - * @brief Copy a received frame from the RX buffer for parsing - * - * @param hw Start address of the CAN registers - * @param rx_frame Pointer to store formatted frame - * - * @note Call can_ll_prase_frame_buffer() to parse the formatted frame - */ static inline void can_ll_get_rx_buffer(can_dev_t *hw, can_ll_frame_buffer_t *rx_frame) { - //Copy RX buffer registers into frame - for (int i = 0; i < 13; i++) { - rx_frame->bytes[i] = hw->tx_rx_buffer[i].byte; - } + twai_ll_get_rx_buffer(hw, rx_frame); } -/** - * @brief Format contents of a CAN frame into layout of TX Buffer - * - * @param[in] id 11 or 29bit ID - * @param[in] dlc Data length code - * @param[in] data Pointer to an 8 byte array containing data. NULL if no data - * @param[in] format Type of CAN frame - * @param[in] single_shot Frame will not be retransmitted on failure - * @param[in] self_rx Frame will also be simultaneously received - * @param[out] tx_frame Pointer to store formatted frame - */ static inline void can_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const uint8_t *data, uint32_t flags, can_ll_frame_buffer_t *tx_frame) { - /* This function encodes a message into a frame structure. The frame structure has - an identical layout to the TX buffer, allowing the frame structure to be directly - copied into TX buffer. */ - bool is_extd = flags & CAN_MSG_FLAG_EXTD; - bool is_rtr = flags & CAN_MSG_FLAG_RTR; - - //Set frame information - tx_frame->dlc = dlc; - tx_frame->frame_format = is_extd; - tx_frame->rtr = is_rtr; - tx_frame->self_reception = (flags & CAN_MSG_FLAG_SELF) ? 1 : 0; - tx_frame->single_shot = (flags & CAN_MSG_FLAG_SS) ? 1 : 0; - - //Set ID - if (is_extd) { - uint32_t id_temp = __builtin_bswap32((id & CAN_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i)) - for (int i = 0; i < 4; i++) { - tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF; - } - } else { - uint32_t id_temp = __builtin_bswap16((id & CAN_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i)) - for (int i = 0; i < 2; i++) { - tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF; - } - } - - //Set Data - uint8_t *data_buffer = (is_extd) ? tx_frame->extended.data : tx_frame->standard.data; - if (!is_rtr) { - for (int i = 0; (i < dlc) && (i < CAN_FRAME_MAX_DLC); i++) { - data_buffer[i] = data[i]; - } - } + twai_ll_format_frame_buffer(id, dlc, data, flags, tx_frame); } -/** - * @brief Parse formatted CAN frame (RX Buffer Layout) into its contents - * - * @param[in] rx_frame Pointer to formatted frame - * @param[out] id 11 or 29bit ID - * @param[out] dlc Data length code - * @param[out] data Data. Left over bytes set to 0. - * @param[out] format Type of CAN frame - */ static inline void can_ll_prase_frame_buffer(can_ll_frame_buffer_t *rx_frame, uint32_t *id, uint8_t *dlc, uint8_t *data, uint32_t *flags) { - //This function decodes a frame structure into it's constituent components. - - //Copy frame information - *dlc = rx_frame->dlc; - uint32_t flags_temp = 0; - flags_temp |= (rx_frame->frame_format) ? CAN_MSG_FLAG_EXTD : 0; - flags_temp |= (rx_frame->rtr) ? CAN_MSG_FLAG_RTR : 0; - flags_temp |= (rx_frame->dlc > CAN_FRAME_MAX_DLC) ? CAN_MSG_FLAG_DLC_NON_COMP : 0; - *flags = flags_temp; - - //Copy ID - if (rx_frame->frame_format) { - uint32_t id_temp = 0; - for (int i = 0; i < 4; i++) { - id_temp |= rx_frame->extended.id[i] << (8 * i); - } - id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3) - *id = id_temp & CAN_EXTD_ID_MASK; - } else { - uint32_t id_temp = 0; - for (int i = 0; i < 2; i++) { - id_temp |= rx_frame->standard.id[i] << (8 * i); - } - id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5) - *id = id_temp & CAN_STD_ID_MASK; - } - - //Copy data - uint8_t *data_buffer = (rx_frame->frame_format) ? rx_frame->extended.data : rx_frame->standard.data; - int data_length = (rx_frame->rtr) ? 0 : ((rx_frame->dlc > CAN_FRAME_MAX_DLC) ? CAN_FRAME_MAX_DLC : rx_frame->dlc); - for (int i = 0; i < data_length; i++) { - data[i] = data_buffer[i]; - } - //Set remaining bytes of data to 0 - for (int i = data_length; i < CAN_FRAME_MAX_DLC; i++) { - data[i] = 0; - } + twai_ll_prase_frame_buffer(rx_frame, id, dlc, data, flags); } /* ----------------------- RX Message Count Register ------------------------ */ -/** - * @brief Get RX Message Counter - * - * @param hw Start address of the CAN registers - * @return RX Message Counter - */ static inline uint32_t can_ll_get_rx_msg_count(can_dev_t *hw) { - return hw->rx_message_counter_reg.val; + return twai_ll_get_rx_msg_count(hw); } /* ------------------------- Clock Divider Register ------------------------- */ -/** - * @brief Set CLKOUT Divider and enable/disable - * - * @param hw Start address of the CAN registers - * @param divider Divider for CLKOUT. Set to 0 to disable CLKOUT - */ static inline void can_ll_set_clkout(can_dev_t *hw, uint32_t divider) { - /* Configure CLKOUT. CLKOUT is a pre-scaled version of APB CLK. Divider can be - 1, or any even number from 2 to 14. Set to out of range value (0) to disable - CLKOUT. */ - - if (divider >= 2 && divider <= 14) { - CAN.clock_divider_reg.co = 0; - CAN.clock_divider_reg.cd = (divider / 2) - 1; - } else if (divider == 1) { - CAN.clock_divider_reg.co = 0; - CAN.clock_divider_reg.cd = 7; - } else { - CAN.clock_divider_reg.co = 1; - CAN.clock_divider_reg.cd = 0; - } + twai_ll_set_clkout(hw, divider); } -/** - * @brief Set register address mapping to extended mode - * - * Extended mode register address mapping consists of more registers and extra - * features. - * - * @param hw Start address of the CAN registers - * - * @note Must be called before setting any configuration - * @note Must be called in reset mode - */ static inline void can_ll_enable_extended_reg_layout(can_dev_t *hw) { - hw->clock_divider_reg.cm = 1; + twai_ll_enable_extended_reg_layout(hw); } #ifdef __cplusplus diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_types.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_types.h new file mode 100644 index 00000000..2c65d213 --- /dev/null +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/can_types.h @@ -0,0 +1,68 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#warning hal/can_types.h is deprecated, please use hal/twai_types.h instead + +#include "hal/twai_types.h" + +/* ---------------------------- Compatibility ------------------------------- */ + +#define CAN_EXTD_ID_MASK TWAI_EXTD_ID_MASK +#define CAN_STD_ID_MASK TWAI_STD_ID_MASK +#define CAN_FRAME_MAX_DLC TWAI_FRAME_MAX_DLC +#define CAN_FRAME_EXTD_ID_LEN_BYTES TWAI_FRAME_EXTD_ID_LEN_BYTES +#define CAN_FRAME_STD_ID_LEN_BYTES TWAI_FRAME_STD_ID_LEN_BYTES +#define CAN_ERR_PASS_THRESH TWAI_ERR_PASS_THRESH + +#define CAN_MSG_FLAG_NONE TWAI_MSG_FLAG_NONE +#define CAN_MSG_FLAG_EXTD TWAI_MSG_FLAG_EXTD +#define CAN_MSG_FLAG_RTR TWAI_MSG_FLAG_RTR +#define CAN_MSG_FLAG_SS TWAI_MSG_FLAG_SS +#define CAN_MSG_FLAG_SELF TWAI_MSG_FLAG_SELF +#define CAN_MSG_FLAG_DLC_NON_COMP TWAI_MSG_FLAG_DLC_NON_COMP + +#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2) +#define CAN_TIMING_CONFIG_12_5KBITS() TWAI_TIMING_CONFIG_12_5KBITS() +#define CAN_TIMING_CONFIG_16KBITS() TWAI_TIMING_CONFIG_16KBITS() +#define CAN_TIMING_CONFIG_20KBITS() TWAI_TIMING_CONFIG_20KBITS() +#endif +#define CAN_TIMING_CONFIG_25KBITS() TWAI_TIMING_CONFIG_25KBITS() +#define CAN_TIMING_CONFIG_50KBITS() TWAI_TIMING_CONFIG_50KBITS() +#define CAN_TIMING_CONFIG_100KBITS() TWAI_TIMING_CONFIG_100KBITS() +#define CAN_TIMING_CONFIG_125KBITS() TWAI_TIMING_CONFIG_125KBITS() +#define CAN_TIMING_CONFIG_250KBITS() TWAI_TIMING_CONFIG_250KBITS() +#define CAN_TIMING_CONFIG_500KBITS() TWAI_TIMING_CONFIG_500KBITS() +#define CAN_TIMING_CONFIG_800KBITS() TWAI_TIMING_CONFIG_800KBITS() +#define CAN_TIMING_CONFIG_1MBITS() TWAI_TIMING_CONFIG_1MBITS() + +#define CAN_FILTER_CONFIG_ACCEPT_ALL() TWAI_FILTER_CONFIG_ACCEPT_ALL() + +typedef twai_mode_t can_mode_t; +#define CAN_MODE_NORMAL TWAI_MODE_NORMAL +#define CAN_MODE_NO_ACK TWAI_MODE_NO_ACK +#define CAN_MODE_LISTEN_ONLY TWAI_MODE_LISTEN_ONLY + +typedef twai_message_t can_message_t; +typedef twai_timing_config_t can_timing_config_t; +typedef twai_filter_config_t can_filter_config_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/clk_gate_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/clk_gate_ll.h index 7849433b..bedfc6e7 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/clk_gate_ll.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/clk_gate_ll.h @@ -75,8 +75,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return DPORT_WIFI_CLK_SDIO_HOST_EN; case PERIPH_SDIO_SLAVE_MODULE: return DPORT_WIFI_CLK_SDIOSLAVE_EN; - case PERIPH_CAN_MODULE: - return DPORT_CAN_CLK_EN; + case PERIPH_TWAI_MODULE: + return DPORT_TWAI_CLK_EN; case PERIPH_EMAC_MODULE: return DPORT_WIFI_CLK_EMAC_EN; case PERIPH_RNG_MODULE: @@ -153,8 +153,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en return DPORT_SDIO_HOST_RST; case PERIPH_SDIO_SLAVE_MODULE: return DPORT_SDIO_RST; - case PERIPH_CAN_MODULE: - return DPORT_CAN_RST; + case PERIPH_TWAI_MODULE: + return DPORT_TWAI_RST; case PERIPH_EMAC_MODULE: return DPORT_EMAC_RST; case PERIPH_AES_MODULE: @@ -242,12 +242,30 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +{ + DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +{ + DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); +} + static inline void periph_ll_reset(periph_module_t periph) { DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } +static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) +{ + return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 && + DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; +} + #ifdef __cplusplus } #endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_cntl_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_cntl_ll.h new file mode 100644 index 00000000..3c77d4c0 --- /dev/null +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_cntl_ll.h @@ -0,0 +1,55 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" +#include "soc/rtc.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +{ + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); +} + +static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +{ + REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); +} + +static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +{ + return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); +} + +static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +{ + REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, + mode, RTC_CNTL_EXT_WAKEUP1_LV_S); +} + +static inline void rtc_cntl_ll_ulp_wakeup_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_io_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_io_ll.h index 07ecad56..3a404299 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_io_ll.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/rtc_io_ll.h @@ -353,6 +353,14 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num) CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel); } +static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) +{ + REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num); + // Set level which will trigger wakeup + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, + level , RTC_CNTL_EXT_WAKEUP0_LV_S); +} + #ifdef __cplusplus } #endif \ No newline at end of file diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/soc_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/soc_ll.h index b83a0756..93f4bbf6 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/soc_ll.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/soc_ll.h @@ -16,6 +16,7 @@ #include "soc/soc.h" #include "soc/rtc_cntl_reg.h" #include "soc/soc_caps.h" +#include "soc/rtc.h" #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/spi_flash_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/spi_flash_ll.h index 74f37db4..50a3d0d6 100644 --- a/tools/sdk/esp32/include/soc/src/esp32/include/hal/spi_flash_ll.h +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/spi_flash_ll.h @@ -238,9 +238,9 @@ static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev) */ static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) { - dev->pin.cs0_dis = (pin == 0) ? 0 : 1; - dev->pin.cs1_dis = (pin == 1) ? 0 : 1; - dev->pin.cs2_dis = (pin == 2) ? 0 : 1; + dev->pin.cs0_dis = (pin != 0); + dev->pin.cs1_dis = (pin != 1); + dev->pin.cs2_dis = (pin != 2); } /** diff --git a/tools/sdk/esp32/include/soc/src/esp32/include/hal/twai_ll.h b/tools/sdk/esp32/include/soc/src/esp32/include/hal/twai_ll.h new file mode 100644 index 00000000..c82692af --- /dev/null +++ b/tools/sdk/esp32/include/soc/src/esp32/include/hal/twai_ll.h @@ -0,0 +1,706 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for TWAI + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "sdkconfig.h" +#include "hal/twai_types.h" +#include "soc/twai_periph.h" + +/* ------------------------- Defines and Typedefs --------------------------- */ + +#define TWAI_LL_STATUS_RBS (0x1 << 0) +#define TWAI_LL_STATUS_DOS (0x1 << 1) +#define TWAI_LL_STATUS_TBS (0x1 << 2) +#define TWAI_LL_STATUS_TCS (0x1 << 3) +#define TWAI_LL_STATUS_RS (0x1 << 4) +#define TWAI_LL_STATUS_TS (0x1 << 5) +#define TWAI_LL_STATUS_ES (0x1 << 6) +#define TWAI_LL_STATUS_BS (0x1 << 7) + +#define TWAI_LL_INTR_RI (0x1 << 0) +#define TWAI_LL_INTR_TI (0x1 << 1) +#define TWAI_LL_INTR_EI (0x1 << 2) +//Data overrun interrupt not supported in SW due to HW peculiarities +#define TWAI_LL_INTR_EPI (0x1 << 5) +#define TWAI_LL_INTR_ALI (0x1 << 6) +#define TWAI_LL_INTR_BEI (0x1 << 7) + +/* + * The following frame structure has an NEARLY identical bit field layout to + * each byte of the TX buffer. This allows for formatting and parsing frames to + * be done outside of time critical regions (i.e., ISRs). All the ISR needs to + * do is to copy byte by byte to/from the TX/RX buffer. The two reserved bits in + * TX buffer are used in the frame structure to store the self_reception and + * single_shot flags which in turn indicate the type of transmission to execute. + */ +typedef union { + struct { + struct { + uint8_t dlc: 4; //Data length code (0 to 8) of the frame + uint8_t self_reception: 1; //This frame should be transmitted using self reception command + uint8_t single_shot: 1; //This frame should be transmitted using single shot command + uint8_t rtr: 1; //This frame is a remote transmission request + uint8_t frame_format: 1; //Format of the frame (1 = extended, 0 = standard) + }; + union { + struct { + uint8_t id[2]; //11 bit standard frame identifier + uint8_t data[8]; //Data bytes (0 to 8) + uint8_t reserved8[2]; + } standard; + struct { + uint8_t id[4]; //29 bit extended frame identifier + uint8_t data[8]; //Data bytes (0 to 8) + } extended; + }; + }; + uint8_t bytes[13]; +} __attribute__((packed)) twai_ll_frame_buffer_t; + +_Static_assert(sizeof(twai_ll_frame_buffer_t) == 13, "TX/RX buffer type should be 13 bytes"); + +/* ---------------------------- Mode Register ------------------------------- */ + +/** + * @brief Enter reset mode + * + * When in reset mode, the TWAI controller is effectively disconnected from the + * TWAI bus and will not participate in any bus activates. Reset mode is required + * in order to write the majority of configuration registers. + * + * @param hw Start address of the TWAI registers + * @return true if reset mode was entered successfully + * + * @note Reset mode is automatically entered on BUS OFF condition + */ +static inline bool twai_ll_enter_reset_mode(twai_dev_t *hw) +{ + hw->mode_reg.rm = 1; + return hw->mode_reg.rm; +} + +/** + * @brief Exit reset mode + * + * When not in reset mode, the TWAI controller will take part in bus activities + * (e.g., send/receive/acknowledge messages and error frames) depending on the + * operating mode. + * + * @param hw Start address of the TWAI registers + * @return true if reset mode was exit successfully + * + * @note Reset mode must be exit to initiate BUS OFF recovery + */ +static inline bool twai_ll_exit_reset_mode(twai_dev_t *hw) +{ + hw->mode_reg.rm = 0; + return !(hw->mode_reg.rm); +} + +/** + * @brief Check if in reset mode + * @param hw Start address of the TWAI registers + * @return true if in reset mode + */ +static inline bool twai_ll_is_in_reset_mode(twai_dev_t *hw) +{ + return hw->mode_reg.rm; +} + +/** + * @brief Set operating mode of TWAI controller + * + * @param hw Start address of the TWAI registers + * @param mode Operating mode + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_mode(twai_dev_t *hw, twai_mode_t mode) +{ + if (mode == TWAI_MODE_NORMAL) { //Normal Operating mode + hw->mode_reg.lom = 0; + hw->mode_reg.stm = 0; + } else if (mode == TWAI_MODE_NO_ACK) { //Self Test Mode (No Ack) + hw->mode_reg.lom = 0; + hw->mode_reg.stm = 1; + } else if (mode == TWAI_MODE_LISTEN_ONLY) { //Listen Only Mode + hw->mode_reg.lom = 1; + hw->mode_reg.stm = 0; + } +} + +/* --------------------------- Command Register ----------------------------- */ + +/** + * @brief Set TX command + * + * Setting the TX command will cause the TWAI controller to attempt to transmit + * the frame stored in the TX buffer. The TX buffer will be occupied (i.e., + * locked) until TX completes. + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_tx(twai_dev_t *hw) +{ + hw->command_reg.tr = 1; +} + +/** + * @brief Set single shot TX command + * + * Similar to setting TX command, but the TWAI controller will not automatically + * retry transmission upon an error (e.g., due to an acknowledgement error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_tx_single_shot(twai_dev_t *hw) +{ + hw->command_reg.val = 0x03; //Writing to TR and AT simultaneously +} + +/** + * @brief Aborts TX + * + * Frames awaiting TX will be aborted. Frames already being TX are not aborted. + * Transmission Complete Status bit is automatically set to 1. + * Similar to setting TX command, but the TWAI controller will not automatically + * retry transmission upon an error (e.g., due to acknowledge error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_abort_tx(twai_dev_t *hw) +{ + hw->command_reg.at = 1; +} + +/** + * @brief Release RX buffer + * + * Rotates RX buffer to the next frame in the RX FIFO. + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_set_cmd_release_rx_buffer(twai_dev_t *hw) +{ + hw->command_reg.rrb = 1; +} + +/** + * @brief Clear data overrun + * + * Clears the data overrun status bit + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_set_cmd_clear_data_overrun(twai_dev_t *hw) +{ + hw->command_reg.cdo = 1; +} + +/** + * @brief Set self reception single shot command + * + * Similar to setting TX command, but the TWAI controller also simultaneously + * receive the transmitted frame and is generally used for self testing + * purposes. The TWAI controller will not ACK the received message, so consider + * using the NO_ACK operating mode. + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_self_rx_request(twai_dev_t *hw) +{ + hw->command_reg.srr = 1; +} + +/** + * @brief Set self reception request command + * + * Similar to setting the self reception request, but the TWAI controller will + * not automatically retry transmission upon an error (e.g., due to and + * acknowledgement error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_self_rx_single_shot(twai_dev_t *hw) +{ + hw->command_reg.val = 0x12; +} + +/* --------------------------- Status Register ------------------------------ */ + +/** + * @brief Get all status bits + * + * @param hw Start address of the TWAI registers + * @return Status bits + */ +static inline uint32_t twai_ll_get_status(twai_dev_t *hw) +{ + return hw->status_reg.val; +} + +/** + * @brief Check if RX FIFO overrun status bit is set + * + * @param hw Start address of the TWAI registers + * @return Overrun status bit + */ +static inline bool twai_ll_is_fifo_overrun(twai_dev_t *hw) +{ + return hw->status_reg.dos; +} + +/** + * @brief Check if previously TX was successful + * + * @param hw Start address of the TWAI registers + * @return Whether previous TX was successful + */ +static inline bool twai_ll_is_last_tx_successful(twai_dev_t *hw) +{ + return hw->status_reg.tcs; +} + +//Todo: Add stand alone status bit check functions when necessary + +/* -------------------------- Interrupt Register ---------------------------- */ + +/** + * @brief Get currently set interrupts + * + * Reading the interrupt registers will automatically clear all interrupts + * except for the Receive Interrupt. + * + * @param hw Start address of the TWAI registers + * @return Bit mask of set interrupts + */ +static inline uint32_t twai_ll_get_and_clear_intrs(twai_dev_t *hw) +{ + return hw->interrupt_reg.val; +} + +/* ----------------------- Interrupt Enable Register ------------------------ */ + +/** + * @brief Set which interrupts are enabled + * + * @param hw Start address of the TWAI registers + * @param Bit mask of interrupts to enable + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask) +{ +#if (CONFIG_ESP32_REV_MIN >= 2) + //ESP32 Rev 2 or later has brp div field. Need to mask it out + hw->interrupt_enable_reg.val = (hw->interrupt_enable_reg.val & 0x10) | intr_mask; +#else + hw->interrupt_enable_reg.val = intr_mask; +#endif +} + +/* ------------------------ Bus Timing Registers --------------------------- */ + +/** + * @brief Set bus timing + * + * @param hw Start address of the TWAI registers + * @param brp Baud Rate Prescaler + * @param sjw Synchronization Jump Width + * @param tseg1 Timing Segment 1 + * @param tseg2 Timing Segment 2 + * @param triple_sampling Triple Sampling enable/disable + * + * @note Must be called in reset mode + * @note ESP32 rev 2 or later can support a x2 brp by setting a brp_div bit, + * allowing the brp to go from a maximum of 128 to 256. + */ +static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling) +{ +#if (CONFIG_ESP32_REV_MIN >= 2) + if (brp > TWAI_BRP_DIV_THRESH) { + //Need to set brp_div bit + hw->interrupt_enable_reg.brp_div = 1; + brp /= 2; + } else { + hw->interrupt_enable_reg.brp_div = 0; + } +#endif + hw->bus_timing_0_reg.brp = (brp / 2) - 1; + hw->bus_timing_0_reg.sjw = sjw - 1; + hw->bus_timing_1_reg.tseg1 = tseg1 - 1; + hw->bus_timing_1_reg.tseg2 = tseg2 - 1; + hw->bus_timing_1_reg.sam = triple_sampling; +} + +/* ----------------------------- ALC Register ------------------------------- */ + +/** + * @brief Clear Arbitration Lost Capture Register + * + * Reading the ALC register rearms the Arbitration Lost Interrupt + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_clear_arb_lost_cap(twai_dev_t *hw) +{ + (void)hw->arbitration_lost_captue_reg.val; + //Todo: Decode ALC register +} + +/* ----------------------------- ECC Register ------------------------------- */ + +/** + * @brief Clear Error Code Capture register + * + * Reading the ECC register rearms the Bus Error Interrupt + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw) +{ + (void)hw->error_code_capture_reg.val; + //Todo: Decode error code capture +} + +/* ----------------------------- EWL Register ------------------------------- */ + +/** + * @brief Set Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @param ewl Error Warning Limit + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl) +{ + hw->error_warning_limit_reg.ewl = ewl; +} + +/** + * @brief Get Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @return Error Warning Limit + */ +static inline uint32_t twai_ll_get_err_warn_lim(twai_dev_t *hw) +{ + return hw->error_warning_limit_reg.val; +} + +/* ------------------------ RX Error Count Register ------------------------- */ + +/** + * @brief Get RX Error Counter + * + * @param hw Start address of the TWAI registers + * @return REC value + * + * @note REC is not frozen in reset mode. Listen only mode will freeze it. A BUS + * OFF condition automatically sets the REC to 0. + */ +static inline uint32_t twai_ll_get_rec(twai_dev_t *hw) +{ + return hw->rx_error_counter_reg.val; +} + +/** + * @brief Set RX Error Counter + * + * @param hw Start address of the TWAI registers + * @param rec REC value + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec) +{ + hw->rx_error_counter_reg.rxerr = rec; +} + +/* ------------------------ TX Error Count Register ------------------------- */ + +/** + * @brief Get TX Error Counter + * + * @param hw Start address of the TWAI registers + * @return TEC value + * + * @note A BUS OFF condition will automatically set this to 128 + */ +static inline uint32_t twai_ll_get_tec(twai_dev_t *hw) +{ + return hw->tx_error_counter_reg.val; +} + +/** + * @brief Set TX Error Counter + * + * @param hw Start address of the TWAI registers + * @param tec TEC value + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec) +{ + hw->tx_error_counter_reg.txerr = tec; +} + +/* ---------------------- Acceptance Filter Registers ----------------------- */ + +/** + * @brief Set Acceptance Filter + * @param hw Start address of the TWAI registers + * @param code Acceptance Code + * @param mask Acceptance Mask + * @param single_filter Whether to enable single filter mode + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter) +{ + uint32_t code_swapped = __builtin_bswap32(code); + uint32_t mask_swapped = __builtin_bswap32(mask); + for (int i = 0; i < 4; i++) { + hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF); + hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF); + } + hw->mode_reg.afm = single_filter; +} + +/* ------------------------- TX/RX Buffer Registers ------------------------- */ + +/** + * @brief Copy a formatted TWAI frame into TX buffer for transmission + * + * @param hw Start address of the TWAI registers + * @param tx_frame Pointer to formatted frame + * + * @note Call twai_ll_format_frame_buffer() to format a frame + */ +static inline void twai_ll_set_tx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t *tx_frame) +{ + //Copy formatted frame into TX buffer + for (int i = 0; i < 13; i++) { + hw->tx_rx_buffer[i].val = tx_frame->bytes[i]; + } +} + +/** + * @brief Copy a received frame from the RX buffer for parsing + * + * @param hw Start address of the TWAI registers + * @param rx_frame Pointer to store formatted frame + * + * @note Call twai_ll_prase_frame_buffer() to parse the formatted frame + */ +static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t *rx_frame) +{ + //Copy RX buffer registers into frame + for (int i = 0; i < 13; i++) { + rx_frame->bytes[i] = hw->tx_rx_buffer[i].byte; + } +} + +/** + * @brief Format contents of a TWAI frame into layout of TX Buffer + * + * This function encodes a message into a frame structure. The frame structure + * has an identical layout to the TX buffer, allowing the frame structure to be + * directly copied into TX buffer. + * + * @param[in] 11bit or 29bit ID + * @param[in] dlc Data length code + * @param[in] data Pointer to an 8 byte array containing data. NULL if no data + * @param[in] format Type of TWAI frame + * @param[in] single_shot Frame will not be retransmitted on failure + * @param[in] self_rx Frame will also be simultaneously received + * @param[out] tx_frame Pointer to store formatted frame + */ +static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const uint8_t *data, + uint32_t flags, twai_ll_frame_buffer_t *tx_frame) +{ + bool is_extd = flags & TWAI_MSG_FLAG_EXTD; + bool is_rtr = flags & TWAI_MSG_FLAG_RTR; + + //Set frame information + tx_frame->dlc = dlc; + tx_frame->frame_format = is_extd; + tx_frame->rtr = is_rtr; + tx_frame->self_reception = (flags & TWAI_MSG_FLAG_SELF) ? 1 : 0; + tx_frame->single_shot = (flags & TWAI_MSG_FLAG_SS) ? 1 : 0; + + //Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required + if (is_extd) { + uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i)) + for (int i = 0; i < 4; i++) { + tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF; + } + } else { + uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i)) + for (int i = 0; i < 2; i++) { + tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF; + } + } + + uint8_t *data_buffer = (is_extd) ? tx_frame->extended.data : tx_frame->standard.data; + if (!is_rtr) { //Only copy data if the frame is a data frame (i.e not RTR) + for (int i = 0; (i < dlc) && (i < TWAI_FRAME_MAX_DLC); i++) { + data_buffer[i] = data[i]; + } + } +} + +/** + * @brief Parse formatted TWAI frame (RX Buffer Layout) into its constituent contents + * + * @param[in] rx_frame Pointer to formatted frame + * @param[out] id 11 or 29bit ID + * @param[out] dlc Data length code + * @param[out] data Data. Left over bytes set to 0. + * @param[out] format Type of TWAI frame + */ +static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame, uint32_t *id, uint8_t *dlc, + uint8_t *data, uint32_t *flags) +{ + //Copy frame information + *dlc = rx_frame->dlc; + uint32_t flags_temp = 0; + flags_temp |= (rx_frame->frame_format) ? TWAI_MSG_FLAG_EXTD : 0; + flags_temp |= (rx_frame->rtr) ? TWAI_MSG_FLAG_RTR : 0; + flags_temp |= (rx_frame->dlc > TWAI_FRAME_MAX_DLC) ? TWAI_MSG_FLAG_DLC_NON_COMP : 0; + *flags = flags_temp; + + //Copy ID. The ID registers are big endian and left aligned, therefore a bswap will be required + if (rx_frame->frame_format) { + uint32_t id_temp = 0; + for (int i = 0; i < 4; i++) { + id_temp |= rx_frame->extended.id[i] << (8 * i); + } + id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3) + *id = id_temp & TWAI_EXTD_ID_MASK; + } else { + uint32_t id_temp = 0; + for (int i = 0; i < 2; i++) { + id_temp |= rx_frame->standard.id[i] << (8 * i); + } + id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5) + *id = id_temp & TWAI_STD_ID_MASK; + } + + uint8_t *data_buffer = (rx_frame->frame_format) ? rx_frame->extended.data : rx_frame->standard.data; + //Only copy data if the frame is a data frame (i.e. not a remote frame) + int data_length = (rx_frame->rtr) ? 0 : ((rx_frame->dlc > TWAI_FRAME_MAX_DLC) ? TWAI_FRAME_MAX_DLC : rx_frame->dlc); + for (int i = 0; i < data_length; i++) { + data[i] = data_buffer[i]; + } + //Set remaining bytes of data to 0 + for (int i = data_length; i < TWAI_FRAME_MAX_DLC; i++) { + data[i] = 0; + } +} + +/* ----------------------- RX Message Count Register ------------------------ */ + +/** + * @brief Get RX Message Counter + * + * @param hw Start address of the TWAI registers + * @return RX Message Counter + */ +static inline uint32_t twai_ll_get_rx_msg_count(twai_dev_t *hw) +{ + return hw->rx_message_counter_reg.val; +} + +/* ------------------------- Clock Divider Register ------------------------- */ + +/** + * @brief Set CLKOUT Divider and enable/disable + * + * Configure CLKOUT. CLKOUT is a pre-scaled version of APB CLK. Divider can be + * 1, or any even number from 2 to 14. Set the divider to 0 to disable CLKOUT. + * + * @param hw Start address of the TWAI registers + * @param divider Divider for CLKOUT. Set to 0 to disable CLKOUT + */ +static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) +{ + if (divider >= 2 && divider <= 14) { + hw->clock_divider_reg.co = 0; + hw->clock_divider_reg.cd = (divider / 2) - 1; + } else if (divider == 1) { + //Setting the divider reg to max value (7) means a divider of 1 + hw->clock_divider_reg.co = 0; + hw->clock_divider_reg.cd = 7; + } else { + hw->clock_divider_reg.co = 1; + hw->clock_divider_reg.cd = 0; + } +} + +/** + * @brief Set register address mapping to extended mode + * + * Extended mode register address mapping consists of more registers and extra + * features. + * + * @param hw Start address of the TWAI registers + * + * @note Must be called before setting any configuration + * @note Must be called in reset mode + */ +static inline void twai_ll_enable_extended_reg_layout(twai_dev_t *hw) +{ + hw->clock_divider_reg.cm = 1; +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/soc/src/esp32/soc_log.h b/tools/sdk/esp32/include/soc/src/esp32/soc_log.h deleted file mode 100644 index 1710d0c8..00000000 --- a/tools/sdk/esp32/include/soc/src/esp32/soc_log.h +++ /dev/null @@ -1,40 +0,0 @@ -// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -/** - * @file soc_log.h - * @brief SOC library logging functions - * - * To make SOC library compatible with environments which don't use ESP-IDF, - * this header file provides wrappers for logging functions. - */ - -#ifdef ESP_PLATFORM -#include "esp_log.h" -#define SOC_LOGE(tag, fmt, ...) ESP_EARLY_LOGE(tag, fmt, ##__VA_ARGS__) -#define SOC_LOGW(tag, fmt, ...) ESP_EARLY_LOGW(tag, fmt, ##__VA_ARGS__) -#define SOC_LOGI(tag, fmt, ...) ESP_EARLY_LOGI(tag, fmt, ##__VA_ARGS__) -#define SOC_LOGD(tag, fmt, ...) ESP_EARLY_LOGD(tag, fmt, ##__VA_ARGS__) -#define SOC_LOGV(tag, fmt, ...) ESP_EARLY_LOGV(tag, fmt, ##__VA_ARGS__) - -#else -#include "esp32/rom/ets_sys.h" -#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__) -#endif //ESP_PLATFORM diff --git a/tools/sdk/esp32/include/spi_flash/include/esp_flash.h b/tools/sdk/esp32/include/spi_flash/include/esp_flash.h index a60bfe43..d100c57f 100644 --- a/tools/sdk/esp32/include/spi_flash/include/esp_flash.h +++ b/tools/sdk/esp32/include/spi_flash/include/esp_flash.h @@ -34,7 +34,15 @@ typedef struct { uint32_t size; ///< Size of the region } esp_flash_region_t; -/** OS-level integration hooks for accessing flash chips inside a running OS */ +/** @brief OS-level integration hooks for accessing flash chips inside a running OS + * + * It's in the public header because some instances should be allocated statically in the startup + * code. May be updated according to hardware version and new flash chip feature requirements, + * shouldn't be treated as public API. + * + * For advanced developers, you may replace some of them with your implementations at your own + * risk. +*/ typedef struct { /** * Called before commencing any flash operation. Does not need to be @@ -50,14 +58,29 @@ typedef struct { /** Delay for at least 'us' microseconds. Called in between 'start' and 'end'. */ esp_err_t (*delay_us)(void *arg, unsigned us); + + /** Called for get temp buffer when buffer from application cannot be directly read into/write from. */ + void *(*get_temp_buffer)(void* arg, size_t reqest_size, size_t* out_size); + + /** Called for release temp buffer. */ + void (*release_temp_buffer)(void* arg, void *temp_buf); + + /** Yield to other tasks. Called during erase operations. */ + esp_err_t (*yield)(void *arg); } esp_flash_os_functions_t; /** @brief Structure to describe a SPI flash chip connected to the system. - Structure must be initialized before use (passed to esp_flash_init()). + Structure must be initialized before use (passed to esp_flash_init()). It's in the public + header because some instances should be allocated statically in the startup code. May be + updated according to hardware version and new flash chip feature requirements, shouldn't be + treated as public API. + + For advanced developers, you may replace some of them with your implementations at your own + risk. */ struct esp_flash_t { - spi_flash_host_driver_t *host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used. + spi_flash_host_inst_t* host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used. const spi_flash_chip_t *chip_drv; ///< Pointer to chip-model-specific "adapter" structure. If NULL, will be detected during initialisation. const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized. diff --git a/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash.h b/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash.h index 9e8b19e8..59d3679d 100644 --- a/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash.h +++ b/tools/sdk/esp32/include/spi_flash/include/esp_spi_flash.h @@ -341,6 +341,10 @@ typedef void (*spi_flash_op_unlock_func_t)(void); * @brief Function to protect SPI flash critical regions corruption. */ typedef bool (*spi_flash_is_safe_write_address_t)(size_t addr, size_t size); +/** + * @brief Function to yield to the OS during erase operation. + */ +typedef void (*spi_flash_os_yield_t)(void); /** * Structure holding SPI flash access critical sections management functions. @@ -381,6 +385,7 @@ typedef struct { #if !CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED spi_flash_is_safe_write_address_t is_safe_write_address; /**< checks flash write addresses.*/ #endif + spi_flash_os_yield_t yield; /**< yield to the OS during flash erase */ } spi_flash_guard_funcs_t; /** diff --git a/tools/sdk/esp32/include/spi_flash/include/memspi_host_driver.h b/tools/sdk/esp32/include/spi_flash/include/memspi_host_driver.h index 8832adfc..a94260b2 100644 --- a/tools/sdk/esp32/include/spi_flash/include/memspi_host_driver.h +++ b/tools/sdk/esp32/include/spi_flash/include/memspi_host_driver.h @@ -28,9 +28,9 @@ .supports_direct_write = spi_flash_hal_supports_direct_write, \ .supports_direct_read = spi_flash_hal_supports_direct_read, \ .program_page = spi_flash_hal_program_page, \ - .max_write_bytes = SPI_FLASH_HAL_MAX_WRITE_BYTES, \ + .write_data_slicer = memspi_host_write_data_slicer, \ .read = spi_flash_hal_read, \ - .max_read_bytes = SPI_FLASH_HAL_MAX_READ_BYTES, \ + .read_data_slicer = memspi_host_read_data_slicer, \ .host_idle = spi_flash_hal_host_idle, \ .configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \ .poll_cmd_done = spi_flash_hal_poll_cmd_done, \ @@ -38,20 +38,19 @@ } /// configuration for the memspi host -typedef spi_flash_memspi_config_t memspi_host_config_t; +typedef spi_flash_hal_config_t memspi_host_config_t; /// context for the memspi host -typedef spi_flash_memspi_data_t memspi_host_data_t; +typedef spi_flash_hal_context_t memspi_host_inst_t; /** * Initialize the memory SPI host. * * @param host Pointer to the host structure. - * @param data Pointer to allocated space to hold the context of host driver. * @param cfg Pointer to configuration structure * * @return always return ESP_OK */ -esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_data_t *data, const memspi_host_config_t *cfg); +esp_err_t memspi_host_init_pointers(memspi_host_inst_t *host, const memspi_host_config_t *cfg); /******************************************************************************* * NOTICE @@ -66,7 +65,7 @@ esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_d * High speed implementation of RDID through memspi interface relying on the * ``common_command``. * - * @param driver The driver context. + * @param host The driver context. * @param id Output of the read ID from the slave. * * @return @@ -74,69 +73,106 @@ esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_d * - ESP_ERR_FLASH_NO_RESPONSE: if no response from chip * - or other cases from ``spi_hal_common_command`` */ -esp_err_t memspi_host_read_id_hs(spi_flash_host_driver_t *driver, uint32_t *id); +esp_err_t memspi_host_read_id_hs(spi_flash_host_inst_t *host, uint32_t *id); /** * High speed implementation of RDSR through memspi interface relying on the * ``common_command``. * - * @param driver The driver context. + * @param host The driver context. * @param id Output of the read ID from the slave. * * @return * - ESP_OK: if success * - or other cases from ``spi_hal_common_command`` */ -esp_err_t memspi_host_read_status_hs(spi_flash_host_driver_t *driver, uint8_t *out_sr); +esp_err_t memspi_host_read_status_hs(spi_flash_host_inst_t *host, uint8_t *out_sr); /** * Flush the cache (if needed) after the contents are modified. * - * @param driver The driver context. + * @param host The driver context. * @param addr Start address of the modified region * @param size Size of the region modified. * * @return always ESP_OK. */ -esp_err_t memspi_host_flush_cache(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size); +esp_err_t memspi_host_flush_cache(spi_flash_host_inst_t *host, uint32_t addr, uint32_t size); /** * Erase contents of entire chip. * - * @param driver The driver context. + * @param host The driver context. */ -void memspi_host_erase_chip(spi_flash_host_driver_t *driver); +void memspi_host_erase_chip(spi_flash_host_inst_t *host); /** * Erase a sector starting from a given address. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Starting address of the sector. */ -void memspi_host_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address); +void memspi_host_erase_sector(spi_flash_host_inst_t *host, uint32_t start_address); /** * Erase a block starting from a given address. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Starting address of the block. */ -void memspi_host_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address); +void memspi_host_erase_block(spi_flash_host_inst_t *host, uint32_t start_address); /** * Program a page with contents of a buffer. * - * @param driver The driver context. + * @param host The driver context. * @param buffer Buffer which contains the data to be flashed. * @param address Starting address of where to flash the data. * @param length The number of bytes to flash. */ -void memspi_host_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length); +void memspi_host_program_page(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length); /** * Set ability to write to chip. * - * @param driver The driver context. + * @param host The driver context. * @param wp Enable or disable write protect (true - enable, false - disable). */ -esp_err_t memspi_host_set_write_protect(spi_flash_host_driver_t *driver, bool wp); +esp_err_t memspi_host_set_write_protect(spi_flash_host_inst_t *host, bool wp); + +/** + * Read data to buffer. + * + * @param host The driver context. + * @param buffer Buffer which contains the data to be read. + * @param address Starting address of where to read the data. + * @param length The number of bytes to read. + */ +esp_err_t memspi_host_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len); + +/** + * @brief Slicer for read data used in non-encrypted regions. This slicer does nothing but + * limit the length to the maximum size the host supports. + * + * @param address Flash address to read + * @param len Length to read + * @param align_address Output of the address to read, should be equal to the input `address` + * @param page_size Physical SPI flash page size + * + * @return Length that can actually be read in one `read` call in `spi_flash_host_driver_t`. + */ +int memspi_host_read_data_slicer(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_address, uint32_t page_size); + +/** + * @brief Slicer for write data used in non-encrypted regions. This slicer limit the length to the + * maximum size the host supports, and truncate if the write data lie accross the page boundary + * (256 bytes) + * + * @param address Flash address to write + * @param len Length to write + * @param align_address Output of the address to write, should be equal to the input `address` + * @param page_size Physical SPI flash page size + * + * @return Length that can actually be written in one `program_page` call in `spi_flash_host_driver_t`. + */ +int memspi_host_write_data_slicer(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_address, uint32_t page_size); \ No newline at end of file diff --git a/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_driver.h b/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_driver.h index 46667350..c0b19bad 100644 --- a/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_driver.h +++ b/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_driver.h @@ -19,6 +19,16 @@ struct esp_flash_t; typedef struct esp_flash_t esp_flash_t; typedef struct spi_flash_chip_t spi_flash_chip_t; + +/** Timeout configurations for flash operations, all in us */ +typedef struct { + uint32_t chip_erase_timeout; ///< Timeout for chip erase operation + uint32_t block_erase_timeout; ///< Timeout for block erase operation + uint32_t sector_erase_timeout; ///< Timeout for sector erase operation + uint32_t idle_timeout; ///< Default timeout for other commands to be sent by host and get done by flash + uint32_t page_program_timeout; ///< Timeout for page program operation +} flash_chip_op_timeout_t; + /** @brief SPI flash chip driver definition structure. * * The chip driver structure contains chip-specific pointers to functions to perform SPI flash operations, and some @@ -38,6 +48,7 @@ typedef struct spi_flash_chip_t spi_flash_chip_t; */ struct spi_flash_chip_t { const char *name; ///< Name of the chip driver + const flash_chip_op_timeout_t *timeout; ///< Timeout configuration for this chip /* Probe to detect if a supported SPI flash chip is found. * * Attempts to configure 'chip' with these operations and probes for a matching SPI flash chip. diff --git a/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h b/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h index 15ff8f7b..814502d2 100644 --- a/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h +++ b/tools/sdk/esp32/include/spi_flash/include/spi_flash_chip_generic.h @@ -368,3 +368,6 @@ esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t * - or other error passed from the ``configure_host_mode`` function of host driver */ esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip); + +/// Default timeout configuration used by most chips +const flash_chip_op_timeout_t spi_flash_chip_generic_timeout; \ No newline at end of file diff --git a/tools/sdk/esp32/include/ulp/include/esp32s2/ulp_riscv.h b/tools/sdk/esp32/include/ulp/include/esp32s2/ulp_riscv.h new file mode 100644 index 00000000..6b1682d3 --- /dev/null +++ b/tools/sdk/esp32/include/ulp/include/esp32s2/ulp_riscv.h @@ -0,0 +1,44 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include +#include "esp_err.h" +#include "soc/soc.h" +#include "ulp_common.h" + +/** + * @brief Run the program loaded into RTC memory + * @return ESP_OK on success + */ +esp_err_t ulp_riscv_run(void); + +/** + * @brief Load ULP-RISC-V program binary into RTC memory + * + * Different than ULP FSM, the binary program has no special format, it is the ELF + * file generated by RISC-V toolchain converted to binary format using objcopy. + * + * Linker script in components/ulp/ld/esp32s2.ulp.riscv.ld produces ELF files which + * correspond to this format. This linker script produces binaries with load_addr == 0. + * + * @param program_binary pointer to program binary + * @param program_size_bytes size of the program binary + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_SIZE if program_size_bytes is more than 8KiB + */ +esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes); diff --git a/tools/sdk/esp32/include/vfs/include/esp_vfs.h b/tools/sdk/esp32/include/vfs/include/esp_vfs.h index 2fbdbba0..98180e57 100644 --- a/tools/sdk/esp32/include/vfs/include/esp_vfs.h +++ b/tools/sdk/esp32/include/vfs/include/esp_vfs.h @@ -259,12 +259,16 @@ typedef struct * Register a virtual filesystem for given path prefix. * * @param base_path file path prefix associated with the filesystem. - * Must be a zero-terminated C string, up to ESP_VFS_PATH_MAX + * Must be a zero-terminated C string, may be empty. + * If not empty, must be up to ESP_VFS_PATH_MAX * characters long, and at least 2 characters long. * Name must start with a "/" and must not end with "/". * For example, "/data" or "/dev/spi" are valid. * These VFSes would then be called to handle file paths such as * "/data/myfile.txt" or "/dev/spi/0". + * In the special case of an empty base_path, a "fallback" + * VFS is registered. Such VFS will handle paths which are not + * matched by any other registered VFS. * @param vfs Pointer to esp_vfs_t, a structure which maps syscalls to * the filesystem driver functions. VFS component doesn't * assume ownership of this pointer. diff --git a/tools/sdk/esp32/include/vfs/include/esp_vfs_cdcacm.h b/tools/sdk/esp32/include/vfs/include/esp_vfs_cdcacm.h new file mode 100644 index 00000000..b8dd03d9 --- /dev/null +++ b/tools/sdk/esp32/include/vfs/include/esp_vfs_cdcacm.h @@ -0,0 +1,66 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_err.h" +#include "esp_vfs.h" +#include "esp_vfs_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief add /dev/cdcacm virtual filesystem driver + * + * This function is called from startup code to enable console output + */ +esp_err_t esp_vfs_dev_cdcacm_register(void); + +/** + * @brief Set the line endings expected to be received + * + * This specifies the conversion between line endings received and + * newlines ('\n', LF) passed into stdin: + * + * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF + * - ESP_LINE_ENDINGS_CR: convert CR to LF + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. reading + * + * @param mode line endings expected + */ +void esp_vfs_dev_cdcacm_set_rx_line_endings(esp_line_endings_t mode); + +/** + * @brief Set the line endings to sent + * + * This specifies the conversion between newlines ('\n', LF) on stdout and line + * endings sent: + * + * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF + * - ESP_LINE_ENDINGS_CR: convert LF to CR + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. writing + * + * @param mode line endings to send + */ +void esp_vfs_dev_cdcacm_set_tx_line_endings(esp_line_endings_t mode); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/vfs/include/esp_vfs_common.h b/tools/sdk/esp32/include/vfs/include/esp_vfs_common.h new file mode 100644 index 00000000..2d7986a6 --- /dev/null +++ b/tools/sdk/esp32/include/vfs/include/esp_vfs_common.h @@ -0,0 +1,32 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Line ending settings + */ +typedef enum { + ESP_LINE_ENDINGS_CRLF,//!< CR + LF + ESP_LINE_ENDINGS_CR, //!< CR + ESP_LINE_ENDINGS_LF, //!< LF +} esp_line_endings_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/vfs/include/esp_vfs_dev.h b/tools/sdk/esp32/include/vfs/include/esp_vfs_dev.h index 95daaa61..30201784 100644 --- a/tools/sdk/esp32/include/vfs/include/esp_vfs_dev.h +++ b/tools/sdk/esp32/include/vfs/include/esp_vfs_dev.h @@ -15,20 +15,12 @@ #pragma once #include "esp_vfs.h" +#include "esp_vfs_common.h" #ifdef __cplusplus extern "C" { #endif -/** - * @brief Line ending settings - */ -typedef enum { - ESP_LINE_ENDINGS_CRLF,//!< CR + LF - ESP_LINE_ENDINGS_CR, //!< CR - ESP_LINE_ENDINGS_LF, //!< LF -} esp_line_endings_t; - /** * @brief add /dev/uart virtual filesystem driver * @@ -50,7 +42,7 @@ void esp_vfs_dev_uart_register(void); * * @param mode line endings expected on UART */ -void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode); +void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) __attribute__((deprecated)); /** * @brief Set the line endings to sent to UART @@ -66,7 +58,45 @@ void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode); * * @param mode line endings to send to UART */ -void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode); +void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) __attribute__((deprecated)); + +/** + * @brief Set the line endings expected to be received on specified UART + * + * This specifies the conversion between line endings received on UART and + * newlines ('\n', LF) passed into stdin: + * + * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF + * - ESP_LINE_ENDINGS_CR: convert CR to LF + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. reading from UART + * + * @param uart_num the UART number + * @param mode line endings to send to UART + * @return 0 if successed, or -1 + * when an error (specified by errno) have occurred. + */ +int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode); + +/** + * @brief Set the line endings to sent to specified UART + * + * This specifies the conversion between newlines ('\n', LF) on stdout and line + * endings sent over UART: + * + * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF + * - ESP_LINE_ENDINGS_CR: convert LF to CR + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. writing to UART + * + * @param uart_num the UART number + * @param mode line endings to send to UART + * @return 0 if successed, or -1 + * when an error (specified by errno) have occurred. + */ +int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode); /** * @brief set VFS to use simple functions for reading and writing UART diff --git a/tools/sdk/esp32/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h b/tools/sdk/esp32/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h index 53156065..c6c2930a 100644 --- a/tools/sdk/esp32/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h +++ b/tools/sdk/esp32/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h @@ -19,6 +19,14 @@ #include "esp_err.h" +typedef enum { + ESP_EAP_TTLS_PHASE2_EAP, + ESP_EAP_TTLS_PHASE2_MSCHAPV2, + ESP_EAP_TTLS_PHASE2_MSCHAP, + ESP_EAP_TTLS_PHASE2_PAP, + ESP_EAP_TTLS_PHASE2_CHAP +} esp_eap_ttls_phase2_types ; + #ifdef __cplusplus extern "C" { #endif @@ -191,6 +199,16 @@ esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable); */ esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable); +/** + * @brief Set wpa2 enterprise ttls phase2 method + * + * @param type: the type of phase 2 method to be used + * + * @return + * - ESP_OK: succeed + */ +esp_err_t esp_wifi_sta_wpa2_ent_set_ttls_phase2_method(esp_eap_ttls_phase2_types type); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32/include/wpa_supplicant/port/include/os.h b/tools/sdk/esp32/include/wpa_supplicant/port/include/os.h index bff8b146..f39fc599 100644 --- a/tools/sdk/esp32/include/wpa_supplicant/port/include/os.h +++ b/tools/sdk/esp32/include/wpa_supplicant/port/include/os.h @@ -19,7 +19,6 @@ #include #include #include "esp_err.h" -// #include "esp32/rom/ets_sys.h" typedef time_t os_time_t; @@ -278,6 +277,9 @@ char * ets_strdup(const char *s); #ifndef os_strstr #define os_strstr(h, n) strstr((h), (n)) #endif +#ifndef os_strlcpy +#define os_strlcpy(d, s, n) strlcpy((d), (s), (n)) +#endif #ifndef os_snprintf #ifdef _MSC_VER @@ -291,16 +293,4 @@ static inline int os_snprintf_error(size_t size, int res) { return res < 0 || (unsigned int) res >= size; } - -/** - * os_strlcpy - Copy a string with size bound and NUL-termination - * @dest: Destination - * @src: Source - * @siz: Size of the target buffer - * Returns: Total length of the target string (length of src) (not including - * NUL-termination) - * - * This function matches in behavior with the strlcpy(3) function in OpenBSD. - */ -size_t os_strlcpy(char *dest, const char *src, size_t siz); #endif /* OS_H */ diff --git a/tools/sdk/esp32/include/wpa_supplicant/port/include/supplicant_opt.h b/tools/sdk/esp32/include/wpa_supplicant/port/include/supplicant_opt.h index f58692a1..a3d4c666 100644 --- a/tools/sdk/esp32/include/wpa_supplicant/port/include/supplicant_opt.h +++ b/tools/sdk/esp32/include/wpa_supplicant/port/include/supplicant_opt.h @@ -19,14 +19,13 @@ #if CONFIG_WPA_MBEDTLS_CRYPTO #define USE_MBEDTLS_CRYPTO 1 +#else +#define CONFIG_TLS_INTERNAL_CLIENT +#define CONFIG_TLSV12 #endif #if CONFIG_WPA_DEBUG_PRINT #define DEBUG_PRINT #endif -#if CONFIG_WPA_TLS_V12 -#define CONFIG_TLSV12 -#endif - #endif /* _SUPPLICANT_OPT_H */ diff --git a/tools/sdk/esp32/include/xtensa/include/esp_attr.h b/tools/sdk/esp32/include/xtensa/include/esp_attr.h index d267346b..2b59f16e 100644 --- a/tools/sdk/esp32/include/xtensa/include/esp_attr.h +++ b/tools/sdk/esp32/include/xtensa/include/esp_attr.h @@ -32,9 +32,13 @@ // Forces data into IRAM instead of DRAM #define IRAM_DATA_ATTR __attribute__((section(".iram.data"))) +// Forces data into IRAM instead of DRAM and map it to coredump +#define COREDUMP_IRAM_DATA_ATTR _SECTION_ATTR_IMPL(".iram.data.coredump", __COUNTER__) + // Forces bss into IRAM instead of DRAM #define IRAM_BSS_ATTR __attribute__((section(".iram.bss"))) #else +#define COREDUMP_IRAM_DATA_ATTR #define IRAM_DATA_ATTR #define IRAM_BSS_ATTR @@ -50,7 +54,7 @@ #define FORCE_INLINE_ATTR static inline __attribute__((always_inline)) // Forces a string into DRAM instead of flash -// Use as ets_printf(DRAM_STR("Hello world!\n")); +// Use as esp_rom_printf(DRAM_STR("Hello world!\n")); #define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;})) // Forces code into RTC fast memory. See "docs/deep-sleep-stub.rst" @@ -85,6 +89,15 @@ // after restart or during a deep sleep / wake cycle. #define RTC_NOINIT_ATTR _SECTION_ATTR_IMPL(".rtc_noinit", __COUNTER__) +// Forces code into DRAM instead of flash and map it to coredump +#define COREDUMP_DRAM_ATTR _SECTION_ATTR_IMPL(".dram1.coredump", __COUNTER__) + +// Forces data into RTC memory and map it to coredump +#define COREDUMP_RTC_DATA_ATTR _SECTION_ATTR_IMPL(".rtc.coredump", __COUNTER__) + +// Allows to place data into RTC_FAST memory and map it to coredump +#define COREDUMP_RTC_FAST_ATTR _SECTION_ATTR_IMPL(".rtc.fast.coredump", __COUNTER__) + // Forces to not inline function #define NOINLINE_ATTR __attribute__((noinline)) diff --git a/tools/sdk/esp32/ld/esp32.peripherals.ld b/tools/sdk/esp32/ld/esp32.peripherals.ld index 254deb11..e4ba980d 100644 --- a/tools/sdk/esp32/ld/esp32.peripherals.ld +++ b/tools/sdk/esp32/ld/esp32.peripherals.ld @@ -29,6 +29,7 @@ PROVIDE ( SDMMC = 0x3ff68000 ); PROVIDE ( EMAC_DMA = 0x3ff69000 ); PROVIDE ( EMAC_EXT = 0x3ff69800 ); PROVIDE ( EMAC_MAC = 0x3ff6A000 ); +PROVIDE ( TWAI = 0x3ff6B000 ); PROVIDE ( CAN = 0x3ff6B000 ); PROVIDE ( MCPWM1 = 0x3ff6C000 ); PROVIDE ( I2S1 = 0x3ff6D000 ); diff --git a/tools/sdk/esp32/ld/esp32.project.ld b/tools/sdk/esp32/ld/esp32.project.ld index 5d75b5fd..ea6b6bc6 100644 --- a/tools/sdk/esp32/ld/esp32.project.ld +++ b/tools/sdk/esp32/ld/esp32.project.ld @@ -43,8 +43,17 @@ SECTIONS { . = ALIGN(4); _rtc_force_fast_start = ABSOLUTE(.); + + _coredump_rtc_fast_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.fast.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.fast.coredump.*) + *libfreertos.a:queue.*( .rtc.fast.coredump.*) + *libfreertos.a:queue.*(.rtc.fast.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .rtc.fast.coredump .rtc.fast.coredump.*) + _coredump_rtc_fast_end = ABSOLUTE(.); + *(.rtc.force_fast .rtc.force_fast.*) . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); } > rtc_data_seg @@ -59,13 +68,23 @@ SECTIONS { _rtc_data_start = ABSOLUTE(.); + /* coredump mapping */ + _coredump_rtc_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.coredump.*) + *libfreertos.a:queue.*( .rtc.coredump.*) + *libfreertos.a:queue.*(.rtc.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .rtc.coredump .rtc.coredump.*) + _coredump_rtc_end = ABSOLUTE(.); + + /* should be placed after coredump mapping */ *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.data EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.data.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.rodata EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.rodata.*) *libfreertos.a:queue.*( .rtc.data.* .rtc.rodata.*) *libfreertos.a:queue.*(.rtc.data.xQueueGenericCreateStatic .rtc.rodata.xQueueGenericCreateStatic) *libsoc.a:uart_hal_iram.*( .rtc.data .rtc.data.* .rtc.rodata .rtc.rodata.*) - + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*) _rtc_data_end = ABSOLUTE(.); + } > rtc_data_location /* RTC bss, from any source file named rtc_wake_stub*.c */ @@ -162,6 +181,7 @@ SECTIONS *(.entry.text) *(.init.literal) *(.init) + _init_end = ABSOLUTE(.); } > iram0_0_seg @@ -302,14 +322,13 @@ SECTIONS *libc.a:lib_a-wctomb_r.*( .literal .literal.* .text .text.*) *libc.a:lib_a-wsetup.*( .literal .literal.* .text .text.*) *libc.a:lock.*( .literal .literal.* .text .text.*) - *libdriver.a:gpio.*(.literal.gpio_iomux_in .text.gpio_iomux_in) - *libdriver.a:gpio.*(.literal.gpio_iomux_out .text.gpio_iomux_out) *libesp_common.a:esp_err.*( .literal .literal.* .text .text.*) *libesp_event.a:default_event_loop.*(.literal.esp_event_isr_post .text.esp_event_isr_post) *libesp_event.a:esp_event.*(.literal.esp_event_isr_post_to .text.esp_event_isr_post_to) *libesp_ringbuf.a:( .literal .literal.* .text .text.*) *libesp_system.a:panic.*( .literal .literal.* .text .text.*) *libesp_system.a:panic_handler.*( .literal .literal.* .text .text.*) + *libesp_system.a:reset_reason.*( .literal .literal.* .text .text.*) *libesp_system.a:system_api.*(.literal.esp_system_abort .text.esp_system_abort) *libfreertos.a:( .literal EXCLUDE_FILE(*libfreertos.a:queue.*) .literal.* .text EXCLUDE_FILE(*libfreertos.a:queue.*) .text.*) *libfreertos.a:queue.*( .iram1.* .literal.prvIsQueueFull .literal.prvCopyDataToQueue .literal.prvNotifyQueueSetContainer .literal.prvCopyDataFromQueue .literal.xQueueGenericReset .literal.prvInitialiseNewQueue .literal.xQueueGenericCreate .literal.xQueueGetMutexHolder .literal.xQueueCreateCountingSemaphoreStatic .literal.xQueueCreateCountingSemaphore .literal.xQueueGenericSend .literal.prvInitialiseMutex .literal.xQueueCreateMutex .literal.xQueueCreateMutexStatic .literal.xQueueGiveMutexRecursive .literal.xQueueGenericSendFromISR .literal.xQueueGiveFromISR .literal.xQueueGenericReceive .literal.xQueueTakeMutexRecursive .literal.xQueueReceiveFromISR .literal.xQueuePeekFromISR .literal.uxQueueMessagesWaiting .literal.uxQueueSpacesAvailable .literal.uxQueueMessagesWaitingFromISR .literal.vQueueDelete .literal.xQueueIsQueueEmptyFromISR .literal.xQueueIsQueueFullFromISR .literal.vQueueWaitForMessageRestricted .literal.xQueueCreateSet .literal.xQueueAddToSet .literal.xQueueRemoveFromSet .literal.xQueueSelectFromSet .literal.xQueueSelectFromSetFromISR .text.prvIsQueueEmpty .text.prvIsQueueFull .text.prvCopyDataToQueue .text.prvNotifyQueueSetContainer .text.prvCopyDataFromQueue .text.xQueueGenericReset .text.prvInitialiseNewQueue .text.xQueueGenericCreate .text.xQueueGetMutexHolder .text.xQueueCreateCountingSemaphoreStatic .text.xQueueCreateCountingSemaphore .text.xQueueGenericSend .text.prvInitialiseMutex .text.xQueueCreateMutex .text.xQueueCreateMutexStatic .text.xQueueGiveMutexRecursive .text.xQueueGenericSendFromISR .text.xQueueGiveFromISR .text.xQueueGenericReceive .text.xQueueTakeMutexRecursive .text.xQueueReceiveFromISR .text.xQueuePeekFromISR .text.uxQueueMessagesWaiting .text.uxQueueSpacesAvailable .text.uxQueueMessagesWaitingFromISR .text.vQueueDelete .text.xQueueIsQueueEmptyFromISR .text.xQueueIsQueueFullFromISR .text.vQueueWaitForMessageRestricted .text.xQueueCreateSet .text.xQueueAddToSet .text.xQueueRemoveFromSet .text.xQueueSelectFromSet .text.xQueueSelectFromSetFromISR) @@ -337,8 +356,6 @@ SECTIONS *libsoc.a:ledc_hal_iram.*( .literal .literal.* .text .text.*) *libsoc.a:lldesc.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_clk.*( .literal .literal.* .text .text.*) - *libsoc.a:rtc_clk_init.*( .literal .literal.* .text .text.*) - *libsoc.a:rtc_init.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_periph.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_pm.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_sleep.*( .literal .literal.* .text .text.*) @@ -352,6 +369,7 @@ SECTIONS *libsoc.a:systimer_hal.*( .literal .literal.* .text .text.*) *libsoc.a:uart_hal_iram.*( .iram1 .iram1.*) *libsoc.a:wdt_hal_iram.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_init.*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) *libspi_flash.a:memspi_host_driver.*( .literal .literal.* .text .text.*) *libspi_flash.a:spi_flash_chip_gd.*( .literal .literal.* .text .text.*) *libspi_flash.a:spi_flash_chip_generic.*( .literal .literal.* .text .text.*) @@ -388,6 +406,18 @@ SECTIONS *(.gnu.linkonce.s2.*) *(.jcr) + /* coredump mapping */ + _coredump_dram_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .dram1.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.coredump.*) + *libfreertos.a:queue.*( .dram1.coredump.*) + *libfreertos.a:queue.*(.dram1.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .dram1.coredump .dram1.coredump.*) + _coredump_dram_end = ABSOLUTE(.); + + /* should be placed after coredump mapping */ + _esp_system_init_fn_array_start = ABSOLUTE(.); + KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .data EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .data.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .dram1 EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.*) *libapp_trace.a:SEGGER_RTT_esp32.*( .rodata .rodata.*) @@ -521,13 +551,12 @@ SECTIONS *libc.a:lib_a-wctomb_r.*( .rodata .rodata.*) *libc.a:lib_a-wsetup.*( .rodata .rodata.*) *libc.a:lock.*( .rodata .rodata.*) - *libdriver.a:gpio.*(.rodata.gpio_iomux_in) - *libdriver.a:gpio.*(.rodata.gpio_iomux_out) *libesp_common.a:esp_err.*( .rodata .rodata.*) *libesp_event.a:default_event_loop.*(.rodata.esp_event_isr_post) *libesp_event.a:esp_event.*(.rodata.esp_event_isr_post_to) *libesp_system.a:panic.*( .rodata .rodata.*) *libesp_system.a:panic_handler.*( .rodata .rodata.*) + *libesp_system.a:reset_reason.*( .rodata .rodata.*) *libesp_system.a:system_api.*(.rodata.esp_system_abort) *libfreertos.a:queue.*( .data.* .dram1.*) *libfreertos.a:queue.*(.data.xQueueGenericCreateStatic .dram1.xQueueGenericCreateStatic) @@ -557,6 +586,7 @@ SECTIONS *libsoc.a:systimer_hal.*( .rodata .rodata.*) *libsoc.a:uart_hal_iram.*( .data .data.* .dram1 .dram1.*) *libsoc.a:wdt_hal_iram.*( .rodata .rodata.*) + *libsoc.a:rtc_init.*(.rodata.rtc_vddsdio_set_config) *libspi_flash.a:memspi_host_driver.*( .rodata .rodata.*) *libspi_flash.a:spi_flash_chip_gd.*( .rodata .rodata.*) *libspi_flash.a:spi_flash_chip_generic.*( .rodata .rodata.*) @@ -634,17 +664,18 @@ SECTIONS *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libgcc.a:_divsf3.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-impure.* *libc.a:lib_a-atol.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-abs.* *libc.a:lib_a-memchr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-refill.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strtol.* *libc.a:lock.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-system.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-quorem.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-strlen.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-atoi.* *libc.a:lib_a-rshift.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-isspace.* *libc.a:lib_a-strsep.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-rand.* *libc.a:lib_a-fflush.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-srand.* *libc.a:lib_a-tzset.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-sf_nan.* *libc.a:creat.* *libc.a:lib_a-asctime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-memset.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-read.* *libc.a:lib_a-time.* *libc.a:lib_a-isascii.* *libc.a:lib_a-envlock.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-open.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-toascii.* *libc.a:lib_a-div.* *libc.a:lib_a-toupper.* *libc.a:lib_a-sccl.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-strncmp.* *libc.a:isatty.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-raise.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-mktime.* *libc.a:lib_a-stdio.* *libc.a:lib_a-memmove.* *libc.a:lib_a-itoa.* *libc.a:lib_a-isupper.* *libc.a:lib_a-environ.* *libc.a:lib_a-fclose.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-syswrite.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-strncat.* *libc.a:lib_a-close.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-islower.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-ctime.* *libc.a:lib_a-systimes.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysread.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-strndup.* *libc.a:lib_a-labs.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-strupr.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-strftime.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-creat.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-utoa.* *libc.a:lib_a-strspn.* *libc.a:lib_a-isprint.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-strptime.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strcspn.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:systimer_hal.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:ledc_hal_iram.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *liblog.a:log_freertos.* *liblog.a:log.* *libgcc.a:_divsf3.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-impure.* *libc.a:lib_a-atol.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-abs.* *libc.a:lib_a-memchr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-refill.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strtol.* *libc.a:lock.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-system.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-quorem.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-strlen.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-atoi.* *libc.a:lib_a-rshift.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-isspace.* *libc.a:lib_a-strsep.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-rand.* *libc.a:lib_a-fflush.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-srand.* *libc.a:lib_a-tzset.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-sf_nan.* *libc.a:creat.* *libc.a:lib_a-asctime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-memset.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-read.* *libc.a:lib_a-time.* *libc.a:lib_a-isascii.* *libc.a:lib_a-envlock.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-open.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-toascii.* *libc.a:lib_a-div.* *libc.a:lib_a-toupper.* *libc.a:lib_a-sccl.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-strncmp.* *libc.a:isatty.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-raise.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-mktime.* *libc.a:lib_a-stdio.* *libc.a:lib_a-memmove.* *libc.a:lib_a-itoa.* *libc.a:lib_a-isupper.* *libc.a:lib_a-environ.* *libc.a:lib_a-fclose.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-syswrite.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-strncat.* *libc.a:lib_a-close.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-islower.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-ctime.* *libc.a:lib_a-systimes.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysread.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-strndup.* *libc.a:lib_a-labs.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-strupr.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-strftime.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-creat.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-utoa.* *libc.a:lib_a-strspn.* *libc.a:lib_a-isprint.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-strptime.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strcspn.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:systimer_hal.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:ledc_hal_iram.* *libdriver.a:gpio.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libfreertos.a:queue.* *libphy.a) .rodata.*) - *libdriver.a:gpio.*(.rodata.gpio_od_enable.str1.4 .rodata.gpio_input_enable.str1.4 .rodata.gpio_input_disable.str1.4 .rodata.gpio_output_disable.str1.4 .rodata.gpio_output_enable.str1.4 .rodata.gpio_pullup_en.str1.4 .rodata.gpio_pullup_dis.str1.4 .rodata.gpio_set_intr_type.str1.4 .rodata.gpio_set_pull_mode.str1.4 .rodata.gpio_set_direction.str1.4 .rodata.gpio_config.str1.4 .rodata.gpio_reset_pin.str1.4 .rodata.gpio_isr_handler_add.str1.4 .rodata.gpio_isr_register.str1.4 .rodata.gpio_install_isr_service.str1.4 .rodata.gpio_wakeup_enable.str1.4 .rodata.gpio_set_drive_capability.str1.4 .rodata.gpio_get_drive_capability.str1.4 .rodata.gpio_hold_en.str1.4 .rodata.gpio_iomux_in.str1.4 .rodata.gpio_iomux_out.str1.4 .rodata.__func__$6500 .rodata.__func__$6490 .rodata.__FUNCTION__$6721 .rodata.__FUNCTION__$6716 .rodata.__func__$6452 .rodata.__FUNCTION__$6711 .rodata.__func__$6443 .rodata.__FUNCTION__$6705 .rodata.__FUNCTION__$6699 .rodata.__FUNCTION__$6694 .rodata.__FUNCTION__$6687 .rodata.__FUNCTION__$6672 .rodata.__FUNCTION__$6668 .rodata.__FUNCTION__$6661 .rodata.__func__$6642 .rodata.__func__$6633 .rodata.__FUNCTION__$6591 .rodata.__FUNCTION__$6595 .rodata.__func__$6406 .rodata.__FUNCTION__$6583 .rodata.__FUNCTION__$6587 .rodata.__func__$6390 .rodata.__FUNCTION__$6575 .rodata.__func__$6398 .rodata.__FUNCTION__$6579 .rodata.__FUNCTION__$6620 .rodata.__FUNCTION__$6608 .rodata.__FUNCTION__$6600 .rodata.__FUNCTION__$6571 .rodata.__FUNCTION__$6563 .rodata.__FUNCTION__$6567 .rodata.__FUNCTION__$6558 .rodata.__func__$6352 .rodata.__FUNCTION__$6553 .rodata.__func__$6346 .rodata.__FUNCTION__$6549 .rodata.__func__$6340 .rodata.__FUNCTION__$6545 .rodata.__func__$6334 .rodata.__FUNCTION__$6541) + *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:spi_hal_iram.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log_freertos.* *liblog.a:log.* *libgcc.a:_divsf3.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:spi_hal_iram.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libfreertos.a:queue.* *libphy.a) .rodata.*) *libesp_event.a:default_event_loop.*(.rodata.esp_event_loop_create_default.str1.4 .rodata.esp_event_send_to_default_loop) - *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$8941 .rodata.__func__$8928 .rodata.__func__$8895 .rodata.__func__$8863 .rodata.__func__$8838 .rodata.__func__$8797 .rodata.__func__$8788) + *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$8990 .rodata.__func__$8977 .rodata.__func__$8944 .rodata.__func__$8912 .rodata.__func__$8887 .rodata.__func__$8846 .rodata.__func__$8837) *libesp_system.a:system_api.*(.rodata.esp_get_idf_version.str1.4) - *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.xQueueGenericReset.str1.4 .rodata.__FUNCTION__$5314 .rodata.__FUNCTION__$5304 .rodata.__FUNCTION__$5284 .rodata.__FUNCTION__$5279 .rodata.__FUNCTION__$5273 .rodata.__FUNCTION__$5267 .rodata.__FUNCTION__$5261 .rodata.__FUNCTION__$5252 .rodata.__FUNCTION__$5242 .rodata.__FUNCTION__$5231 .rodata.__FUNCTION__$5223 .rodata.__FUNCTION__$5350 .rodata.__FUNCTION__$5212 .rodata.__FUNCTION__$5201 .rodata.__FUNCTION__$5195 .rodata.__FUNCTION__$5188 .rodata.__FUNCTION__$5181 .rodata.__FUNCTION__$5147 .rodata.__FUNCTION__$5137 .rodata.__func__$4308 .rodata.__FUNCTION__$5128) + *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.xQueueGenericReset.str1.4 .rodata.__FUNCTION__$5327 .rodata.__FUNCTION__$5317 .rodata.__FUNCTION__$5297 .rodata.__FUNCTION__$5292 .rodata.__FUNCTION__$5286 .rodata.__FUNCTION__$5280 .rodata.__FUNCTION__$5274 .rodata.__FUNCTION__$5265 .rodata.__FUNCTION__$5255 .rodata.__FUNCTION__$5244 .rodata.__FUNCTION__$5236 .rodata.__FUNCTION__$5363 .rodata.__FUNCTION__$5225 .rodata.__FUNCTION__$5214 .rodata.__FUNCTION__$5208 .rodata.__FUNCTION__$5201 .rodata.__FUNCTION__$5194 .rodata.__FUNCTION__$5160 .rodata.__FUNCTION__$5150 .rodata.__func__$4318 .rodata.__FUNCTION__$5141) *libfreertos.a:queue.*(.rodata.xQueueGenericCreateStatic) - *liblog.a:log.*(.rodata.esp_log_level_set.str1.4 .rodata.__func__$3534 .rodata.__func__$3505) + *liblog.a:log.*(.rodata.esp_log_level_set.str1.4 .rodata.__func__$3544 .rodata.__func__$3515) *liblog.a:log_freertos.*(.rodata.esp_log_system_timestamp.str1.4) + *libsoc.a:rtc_init.*( .rodata.*) *libsoc.a:uart_hal_iram.*( .rodata .rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ *(.gnu.linkonce.r.*) *(.rodata1) @@ -664,6 +695,7 @@ SECTIONS __init_array_start = ABSOLUTE(.); KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*))) __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) KEEP (*(SORT(.dtors.*))) @@ -703,15 +735,15 @@ SECTIONS _stext = .; _text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-impure.* *libc.a:lib_a-atol.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-abs.* *libc.a:lib_a-memchr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-refill.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strtol.* *libc.a:lock.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-system.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-quorem.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-strlen.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-atoi.* *libc.a:lib_a-rshift.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-isspace.* *libc.a:lib_a-strsep.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-rand.* *libc.a:lib_a-fflush.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-srand.* *libc.a:lib_a-tzset.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-sf_nan.* *libc.a:creat.* *libc.a:lib_a-asctime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-memset.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-read.* *libc.a:lib_a-time.* *libc.a:lib_a-isascii.* *libc.a:lib_a-envlock.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-open.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-toascii.* *libc.a:lib_a-div.* *libc.a:lib_a-toupper.* *libc.a:lib_a-sccl.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-strncmp.* *libc.a:isatty.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-raise.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-mktime.* *libc.a:lib_a-stdio.* *libc.a:lib_a-memmove.* *libc.a:lib_a-itoa.* *libc.a:lib_a-isupper.* *libc.a:lib_a-environ.* *libc.a:lib_a-fclose.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-syswrite.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-strncat.* *libc.a:lib_a-close.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-islower.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-ctime.* *libc.a:lib_a-systimes.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysread.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-strndup.* *libc.a:lib_a-labs.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-strupr.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-strftime.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-creat.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-utoa.* *libc.a:lib_a-strspn.* *libc.a:lib_a-isprint.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-strptime.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strcspn.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *librtc.a *libsoc.a:wdt_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-impure.* *libc.a:lib_a-atol.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-abs.* *libc.a:lib_a-memchr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-refill.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strtol.* *libc.a:lock.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-system.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-quorem.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-strlen.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-atoi.* *libc.a:lib_a-rshift.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-isspace.* *libc.a:lib_a-strsep.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-rand.* *libc.a:lib_a-fflush.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-srand.* *libc.a:lib_a-tzset.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-sf_nan.* *libc.a:creat.* *libc.a:lib_a-asctime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-memset.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-read.* *libc.a:lib_a-time.* *libc.a:lib_a-isascii.* *libc.a:lib_a-envlock.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-open.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-toascii.* *libc.a:lib_a-div.* *libc.a:lib_a-toupper.* *libc.a:lib_a-sccl.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-strncmp.* *libc.a:isatty.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-raise.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-mktime.* *libc.a:lib_a-stdio.* *libc.a:lib_a-memmove.* *libc.a:lib_a-itoa.* *libc.a:lib_a-isupper.* *libc.a:lib_a-environ.* *libc.a:lib_a-fclose.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-syswrite.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-strncat.* *libc.a:lib_a-close.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-islower.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-ctime.* *libc.a:lib_a-systimes.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysread.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-strndup.* *libc.a:lib_a-labs.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-strupr.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-strftime.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-creat.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-utoa.* *libc.a:lib_a-strspn.* *libc.a:lib_a-isprint.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-strptime.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strcspn.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *librtc.a *libsoc.a:wdt_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libdriver.a:gpio.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-impure.* *libc.a:lib_a-atol.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-abs.* *libc.a:lib_a-memchr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-refill.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strtol.* *libc.a:lock.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-system.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-quorem.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-strlen.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-atoi.* *libc.a:lib_a-rshift.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-isspace.* *libc.a:lib_a-strsep.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-rand.* *libc.a:lib_a-fflush.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-srand.* *libc.a:lib_a-tzset.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-sf_nan.* *libc.a:creat.* *libc.a:lib_a-asctime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-memset.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-read.* *libc.a:lib_a-time.* *libc.a:lib_a-isascii.* *libc.a:lib_a-envlock.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-open.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-toascii.* *libc.a:lib_a-div.* *libc.a:lib_a-toupper.* *libc.a:lib_a-sccl.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-strncmp.* *libc.a:isatty.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-raise.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-mktime.* *libc.a:lib_a-stdio.* *libc.a:lib_a-memmove.* *libc.a:lib_a-itoa.* *libc.a:lib_a-isupper.* *libc.a:lib_a-environ.* *libc.a:lib_a-fclose.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-syswrite.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-strncat.* *libc.a:lib_a-close.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-islower.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-ctime.* *libc.a:lib_a-systimes.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysread.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-strndup.* *libc.a:lib_a-labs.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-strupr.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-strftime.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-creat.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-utoa.* *libc.a:lib_a-strspn.* *libc.a:lib_a-isprint.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-strptime.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strcspn.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *librtc.a *libsoc.a:wdt_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-impure.* *libc.a:lib_a-atol.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-abs.* *libc.a:lib_a-memchr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-refill.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strtol.* *libc.a:lock.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-system.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-quorem.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-strlen.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-atoi.* *libc.a:lib_a-rshift.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-isspace.* *libc.a:lib_a-strsep.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-rand.* *libc.a:lib_a-fflush.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-srand.* *libc.a:lib_a-tzset.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-sf_nan.* *libc.a:creat.* *libc.a:lib_a-asctime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-memset.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-read.* *libc.a:lib_a-time.* *libc.a:lib_a-isascii.* *libc.a:lib_a-envlock.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-open.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-toascii.* *libc.a:lib_a-div.* *libc.a:lib_a-toupper.* *libc.a:lib_a-sccl.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-strncmp.* *libc.a:isatty.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-raise.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-mktime.* *libc.a:lib_a-stdio.* *libc.a:lib_a-memmove.* *libc.a:lib_a-itoa.* *libc.a:lib_a-isupper.* *libc.a:lib_a-environ.* *libc.a:lib_a-fclose.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-syswrite.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-strncat.* *libc.a:lib_a-close.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-islower.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-ctime.* *libc.a:lib_a-systimes.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysread.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-strndup.* *libc.a:lib_a-labs.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-strupr.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-strftime.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-creat.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-utoa.* *libc.a:lib_a-strspn.* *libc.a:lib_a-isprint.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-strptime.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strcspn.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *librtc.a *libsoc.a:wdt_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libdriver.a:gpio.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text.* 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.text.gpio_wakeup_disable .text.gpio_set_drive_capability .text.gpio_get_drive_capability .text.gpio_hold_en .text.gpio_hold_dis .text.gpio_deep_sleep_hold_en .text.gpio_deep_sleep_hold_dis) + *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:rtc_init.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *libgcc.a:_divsf3.* *libc.a:lib_a-tzvars.* *libc.a:lib_a-isblank.* *libc.a:lib_a-sysopen.* *libc.a:lib_a-time.* *libc.a:lib_a-rand_r.* *libc.a:lib_a-tzset.* *libc.a:lib_a-raise.* *libc.a:lib_a-sysread.* *libc.a:lib_a-systimes.* *libc.a:lib_a-strlwr.* *libc.a:lib_a-gmtime.* *libc.a:lib_a-sf_nan.* *libc.a:lib_a-strcasecmp.* *libc.a:lib_a-strftime.* *libc.a:lib_a-wbuf.* *libc.a:lib_a-strnlen.* *libc.a:lib_a-close.* *libc.a:lib_a-strupr.* *libc.a:lib_a-bzero.* *libc.a:lib_a-gmtime_r.* *libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* 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*libc.a:lib_a-memchr.* *libc.a:lib_a-isdigit.* *libc.a:lib_a-isupper.* *libc.a:lock.* *libc.a:lib_a-itoa.* *libc.a:lib_a-asctime_r.* *libc.a:lib_a-wctomb_r.* *libc.a:lib_a-fclose.* *libc.a:lib_a-strncpy.* *libc.a:lib_a-open.* *libc.a:lib_a-lcltime_r.* *libc.a:lib_a-syswrite.* *libc.a:creat.* *libc.a:lib_a-tolower.* *libc.a:lib_a-strlcpy.* *libc.a:lib_a-abs.* *libc.a:lib_a-system.* *libc.a:lib_a-strcspn.* *libc.a:isatty.* *libc.a:lib_a-gettzinfo.* *libc.a:lib_a-s_fpclassify.* *libc.a:lib_a-tzset_r.* *libc.a:lib_a-strncmp.* *libc.a:lib_a-strcat.* *libc.a:lib_a-strndup_r.* *libc.a:lib_a-strcmp.* *libc.a:lib_a-memccpy.* *libc.a:lib_a-fwalk.* *libc.a:lib_a-tzlock.* *libc.a:lib_a-strncasecmp.* *libc.a:lib_a-refill.* *libc.a:lib_a-longjmp.* *libc.a:lib_a-memrchr.* *libc.a:lib_a-toascii.* *libc.a:lib_a-ctime.* *libc.a:lib_a-strspn.* *libc.a:lib_a-ungetc.* *libc.a:lib_a-strndup.* *libc.a:lib_a-strtoul.* *libc.a:lib_a-strtol.* *libc.a:lib_a-memcpy.* *libc.a:lib_a-isprint.* *libc.a:lib_a-sbrk.* *libc.a:lib_a-strchr.* *libc.a:lib_a-strdup.* *libc.a:lib_a-isspace.* *libc.a:lib_a-isalpha.* *libc.a:lib_a-isascii.* *libc.a:lib_a-rand.* *libc.a:lib_a-strncat.* *libc.a:lib_a-creat.* *libc.a:lib_a-read.* *libc.a:lib_a-memcmp.* *libc.a:lib_a-fflush.* *libc.a:lib_a-fputwc.* *libc.a:lib_a-toupper.* *libc.a:lib_a-quorem.* *libc.a:lib_a-div.* *libc.a:lib_a-tzcalc_limits.* *libc.a:lib_a-labs.* *libc.a:lib_a-strtok_r.* *libc.a:lib_a-strcpy.* *libc.a:lib_a-iscntrl.* *libc.a:lib_a-mktime.* *libc.a:lib_a-strdup_r.* *libc.a:lib_a-strstr.* *libc.a:lib_a-strsep.* *libc.a:lib_a-stdio.* *libc.a:lib_a-isgraph.* *libc.a:lib_a-wsetup.* *libc.a:lib_a-timelocal.* *libc.a:lib_a-strlcat.* *libc.a:lib_a-islower.* *libc.a:lib_a-ldiv.* *libc.a:lib_a-lcltime.* *libc.a:lib_a-environ.* *libc.a:lib_a-sccl.* *libc.a:lib_a-getenv_r.* *libc.a:lib_a-sysclose.* *libc.a:lib_a-strcasestr.* *libc.a:lib_a-ctime_r.* *libc.a:lib_a-syssbrk.* *libc.a:lib_a-setjmp.* *libc.a:lib_a-isalnum.* *libc.a:lib_a-strcoll.* *libc.a:lib_a-memmove.* *libc.a:lib_a-rshift.* *libc.a:lib_a-envlock.* *libc.a:lib_a-strlen.* *libc.a:lib_a-wcrtomb.* *libc.a:lib_a-strptime.* *libc.a:lib_a-findfp.* *libc.a:lib_a-impure.* *libc.a:lib_a-fvwrite.* *libc.a:lib_a-ispunct.* *libc.a:lib_a-utoa.* *libc.a:lib_a-srand.* *libc.a:lib_a-month_lengths.* *libc.a:lib_a-asctime.* *libc.a:lib_a-strrchr.* *libc.a:lib_a-makebuf.* *libc.a:lib_a-atoi.* *libc.a:lib_a-ctype_.* *libc.a:lib_a-memset.* *libc.a:lib_a-atol.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *librtc.a *libsoc.a:rtc_init.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libsoc.a:uart_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifirxiram.*) *libesp_event.a:default_event_loop.*(.literal.esp_event_handler_register .literal.esp_event_handler_instance_register .literal.esp_event_handler_unregister .literal.esp_event_handler_instance_unregister .literal.esp_event_post .literal.esp_event_loop_create_default .literal.esp_event_loop_delete_default .literal.esp_event_send_to_default_loop .text.esp_event_handler_register .text.esp_event_handler_instance_register .text.esp_event_handler_unregister .text.esp_event_handler_instance_unregister .text.esp_event_post .text.esp_event_loop_create_default .text.esp_event_loop_delete_default .text.esp_event_send_to_default_loop) *libesp_event.a:esp_event.*(.literal.handler_instances_remove_all .literal.base_node_remove_all_handler .literal.loop_node_remove_all_handler .literal.handler_instances_add .literal.base_node_add_handler .literal.loop_node_add_handler .literal.handler_instances_remove .literal.base_node_remove_handler .literal.loop_node_remove_handler .literal.esp_event_loop_create .literal.esp_event_loop_run .literal.esp_event_loop_run_task .literal.esp_event_loop_delete .literal.esp_event_handler_register_with_internal .literal.esp_event_handler_register_with .literal.esp_event_handler_instance_register_with .literal.esp_event_handler_unregister_with_internal .literal.esp_event_handler_unregister_with .literal.esp_event_handler_instance_unregister_with .literal.esp_event_post_to .text.handler_execute .text.handler_instances_remove_all .text.base_node_remove_all_handler .text.loop_node_remove_all_handler .text.handler_instances_add .text.base_node_add_handler .text.loop_node_add_handler .text.handler_instances_remove .text.base_node_remove_handler .text.loop_node_remove_handler .text.esp_event_loop_create .text.esp_event_loop_run .text.esp_event_loop_run_task .text.esp_event_loop_delete .text.esp_event_handler_register_with_internal .text.esp_event_handler_register_with .text.esp_event_handler_instance_register_with .text.esp_event_handler_unregister_with_internal .text.esp_event_handler_unregister_with .text.esp_event_handler_instance_unregister_with .text.esp_event_post_to .text.esp_event_dump) - *libesp_system.a:system_api.*(.literal.esp_register_shutdown_handler .literal.esp_unregister_shutdown_handler .literal.esp_get_free_heap_size .literal.esp_get_minimum_free_heap_size .literal.esp_get_idf_version .text.esp_register_shutdown_handler .text.esp_unregister_shutdown_handler .text.esp_get_free_heap_size .text.esp_get_minimum_free_heap_size .text.esp_get_idf_version) + *libesp_system.a:system_api.*(.literal.esp_register_shutdown_handler .literal.esp_unregister_shutdown_handler .literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_minimum_free_heap_size .literal.esp_get_idf_version .text.esp_register_shutdown_handler .text.esp_unregister_shutdown_handler .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_minimum_free_heap_size .text.esp_get_idf_version) *libfreertos.a:queue.*( .wifi0iram.* .wifirxiram.*) *libfreertos.a:queue.*(.literal.xQueueGenericCreateStatic .text.xQueueGenericCreateStatic .wifi0iram.xQueueGenericCreateStatic .wifirxiram.xQueueGenericCreateStatic) *liblog.a:log.*(.literal.heap_bubble_down .literal.esp_log_set_vprintf .literal.esp_log_level_set .literal.esp_log_writev .text.heap_bubble_down .text.esp_log_set_vprintf .text.esp_log_level_set .text.esp_log_writev) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text.esp_log_system_timestamp) + *libsoc.a:rtc_init.*(.literal.rtc_init .literal.rtc_vddsdio_get_config .text.rtc_init .text.rtc_vddsdio_get_config) *libsoc.a:uart_hal_iram.*( .literal .literal.* .text .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) @@ -741,6 +773,15 @@ SECTIONS . = ALIGN(4); _iram_data_start = ABSOLUTE(.); + /* coredump mapping */ + _coredump_iram_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .iram.data.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram.data.coredump.*) + *libfreertos.a:queue.*( .iram.data.coredump.*) + *libfreertos.a:queue.*(.iram.data.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .iram.data.coredump .iram.data.coredump.*) + _coredump_iram_end = ABSOLUTE(.); + + /* should be placed after coredump mapping */ *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .iram.data EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .iram.data.*) *libfreertos.a:queue.*( .iram.data.*) *libfreertos.a:queue.*(.iram.data.xQueueGenericCreateStatic) diff --git a/tools/sdk/esp32/ld/esp32.rom.api.ld b/tools/sdk/esp32/ld/esp32.rom.api.ld new file mode 100644 index 00000000..f3904f81 --- /dev/null +++ b/tools/sdk/esp32/ld/esp32.rom.api.ld @@ -0,0 +1,38 @@ +/** + * ROM APIs + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); +PROVIDE ( esp_rom_crc32_be = crc32_be ); +PROVIDE ( esp_rom_crc16_be = crc16_be ); +PROVIDE ( esp_rom_crc8_be = crc8_be ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */ +/* so here we directly assign the symbols with the ROM API address */ +PROVIDE ( esp_rom_md5_init = 0x4005da7c ); +PROVIDE ( esp_rom_md5_update = 0x4005da9c ); +PROVIDE ( esp_rom_md5_final = 0x4005db1c ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); diff --git a/tools/sdk/esp32/ld/esp32.rom.ld b/tools/sdk/esp32/ld/esp32.rom.ld index 073a6a94..79798402 100644 --- a/tools/sdk/esp32/ld/esp32.rom.ld +++ b/tools/sdk/esp32/ld/esp32.rom.ld @@ -1363,6 +1363,8 @@ PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 ); PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 ); PROVIDE ( llcp_length_req_handler = 0x40043808 ); PROVIDE ( llcp_unknown_rsp_handler = 0x40043ba8 ); +PROVIDE ( llcp_channel_map_req_handler = 0x4004291c ); +PROVIDE ( llcp_con_up_req_handler = 0x400426f0 ); /* These functions are xtos-related (or call xtos-related functions) and do not play well with multicore FreeRTOS. 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a/tools/sdk/esp32/lib/libxtensa.a b/tools/sdk/esp32/lib/libxtensa.a index 5b1d8a0f..fe98199d 100644 Binary files a/tools/sdk/esp32/lib/libxtensa.a and b/tools/sdk/esp32/lib/libxtensa.a differ diff --git a/tools/sdk/esp32/sdkconfig b/tools/sdk/esp32/sdkconfig index 792b573c..b81de5db 100644 --- a/tools/sdk/esp32/sdkconfig +++ b/tools/sdk/esp32/sdkconfig @@ -37,6 +37,7 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 # # Bootloader config # +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set @@ -73,7 +74,7 @@ CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 # Serial flasher config # CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 -CONFIG_ESPTOOLPY_WITH_STUB=y +# CONFIG_ESPTOOLPY_NO_STUB is not set # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set CONFIG_ESPTOOLPY_FLASHMODE_DIO=y @@ -97,6 +98,7 @@ CONFIG_ESPTOOLPY_BEFORE="default_reset" CONFIG_ESPTOOLPY_AFTER_RESET=y # CONFIG_ESPTOOLPY_AFTER_NORESET is not set CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set # CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set # CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y @@ -198,6 +200,12 @@ CONFIG_APPTRACE_DEST_NONE=y CONFIG_APPTRACE_LOCK_ENABLE=y # end of Application Level Tracing +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + # # Bluetooth # @@ -215,7 +223,16 @@ CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=0 # CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_HCI is not set CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM=y CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=1 +CONFIG_BTDM_CTRL_PCM_ROLE_EDGE_CONFIG=y +CONFIG_BTDM_CTRL_PCM_ROLE_MASTER=y +# CONFIG_BTDM_CTRL_PCM_ROLE_SLAVE is not set +CONFIG_BTDM_CTRL_PCM_POLAR_FALLING_EDGE=y +# CONFIG_BTDM_CTRL_PCM_POLAR_RISING_EDGE is not set +CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 +CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 # CONFIG_BTDM_CTRL_AUTO_LATENCY is not set +CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT=y +CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF=y CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=3 CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=2 CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 @@ -362,6 +379,7 @@ CONFIG_ESP_TLS_USING_MBEDTLS=y # # ESP32-specific # +CONFIG_ESP32_ECO3_CACHE_LOCK_FIX=y CONFIG_ESP32_REV_MIN_0=y # CONFIG_ESP32_REV_MIN_1 is not set # CONFIG_ESP32_REV_MIN_2 is not set @@ -378,6 +396,7 @@ CONFIG_ESP32_SPIRAM_SUPPORT=y # SPI RAM config # CONFIG_SPIRAM_TYPE_AUTO=y +# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set # CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set # CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set CONFIG_SPIRAM_SIZE=-1 @@ -425,6 +444,7 @@ CONFIG_D2WD_PSRAM_CS_IO=10 CONFIG_PICO_PSRAM_CS_IO=10 # end of PSRAM clock and cs IO for ESP32-PICO +# CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN is not set CONFIG_SPIRAM_SPIWP_SD3_PIN=7 # CONFIG_SPIRAM_2T_MODE is not set # end of SPI RAM config @@ -494,10 +514,9 @@ CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 CONFIG_ESP_CONSOLE_UART_DEFAULT=y # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set -# CONFIG_ESP_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_UART=y CONFIG_ESP_CONSOLE_UART_NUM=0 -CONFIG_ESP_CONSOLE_UART_TX_GPIO=1 -CONFIG_ESP_CONSOLE_UART_RX_GPIO=3 CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 CONFIG_ESP_INT_WDT=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 @@ -612,6 +631,7 @@ CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32 # CONFIG_ESP32_WIFI_CSI_ENABLED is not set CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y CONFIG_ESP32_WIFI_TX_BA_WIN=6 @@ -687,16 +707,20 @@ CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y # # Modbus configuration # +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 CONFIG_FMB_COMM_MODE_RTU_EN=y CONFIG_FMB_COMM_MODE_ASCII_EN=y CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 CONFIG_FMB_QUEUE_LENGTH=20 -CONFIG_FMB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 CONFIG_FMB_SERIAL_BUF_SIZE=256 CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 -CONFIG_FMB_SERIAL_TASK_PRIO=10 +CONFIG_FMB_PORT_TASK_PRIO=10 # CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT is not set CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 @@ -801,8 +825,10 @@ CONFIG_LWIP_SO_REUSE=y CONFIG_LWIP_SO_REUSE_RXTOALL=y CONFIG_LWIP_SO_RCVBUF=y # CONFIG_LWIP_NETBUF_RECVINFO is not set -# CONFIG_LWIP_IP_FRAG is not set -# CONFIG_LWIP_IP_REASSEMBLY is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set # CONFIG_LWIP_IP_FORWARD is not set # CONFIG_LWIP_STATS is not set CONFIG_LWIP_ETHARP_TRUST_IP_MAC=y @@ -843,6 +869,7 @@ CONFIG_LWIP_TCP_QUEUE_OOSEQ=y CONFIG_LWIP_TCP_OVERSIZE_MSS=y # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=3000 # end of TCP # @@ -859,12 +886,15 @@ CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0=y CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x0 CONFIG_LWIP_PPP_SUPPORT=y CONFIG_LWIP_PPP_ENABLE_IPV6=y +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 # CONFIG_LWIP_PPP_NOTIFY_PHASE_SUPPORT is not set CONFIG_LWIP_PPP_PAP_SUPPORT=y CONFIG_LWIP_PPP_CHAP_SUPPORT=y CONFIG_LWIP_PPP_MSCHAP_SUPPORT=y CONFIG_LWIP_PPP_MPPE_SUPPORT=y # CONFIG_LWIP_PPP_DEBUG_ON is not set +# CONFIG_LWIP_SLIP_SUPPORT is not set # # ICMP @@ -887,6 +917,20 @@ CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 # end of SNTP CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Debug +# +# CONFIG_LWIP_NETIF_DEBUG is not set +# CONFIG_LWIP_PBUF_DEBUG is not set +# CONFIG_LWIP_ETHARP_DEBUG is not set +# CONFIG_LWIP_API_LIB_DEBUG is not set +# CONFIG_LWIP_SOCKETS_DEBUG is not set +# CONFIG_LWIP_IP_DEBUG is not set +# CONFIG_LWIP_ICMP_DEBUG is not set +# CONFIG_LWIP_IP6_DEBUG is not set +# CONFIG_LWIP_ICMP6_DEBUG is not set +# end of Debug # end of LWIP # @@ -1054,6 +1098,7 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y # OpenSSL # # CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y CONFIG_OPENSSL_ASSERT_DO_NOTHING=y # CONFIG_OPENSSL_ASSERT_EXIT is not set # end of OpenSSL @@ -1086,6 +1131,7 @@ CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 # # Auto-detect flash chips @@ -1133,15 +1179,14 @@ CONFIG_SPIFFS_USE_MTIME=y # end of SPIFFS Configuration # -# TinyUSB +# TCP Transport # +CONFIG_WS_BUFFER_SIZE=1024 +# end of TCP Transport # -# Descriptor configuration +# TinyUSB # -CONFIG_USB_DESC_CUSTOM_VID=0x1234 -CONFIG_USB_DESC_CUSTOM_PID=0x5678 -# end of Descriptor configuration # end of TinyUSB # @@ -1193,7 +1238,6 @@ CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 CONFIG_WPA_MBEDTLS_CRYPTO=y # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set -# CONFIG_WPA_TLS_V12 is not set # CONFIG_WPA_WPS_WARS is not set # end of Supplicant # end of Component config @@ -1328,10 +1372,9 @@ CONFIG_MAIN_TASK_STACK_SIZE=4096 CONFIG_IPC_TASK_STACK_SIZE=1024 CONFIG_CONSOLE_UART_DEFAULT=y # CONFIG_CONSOLE_UART_CUSTOM is not set -# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y CONFIG_CONSOLE_UART_NUM=0 -CONFIG_CONSOLE_UART_TX_GPIO=1 -CONFIG_CONSOLE_UART_RX_GPIO=3 CONFIG_CONSOLE_UART_BAUDRATE=115200 CONFIG_INT_WDT=y CONFIG_INT_WDT_TIMEOUT_MS=300 @@ -1353,7 +1396,7 @@ CONFIG_SW_COEXIST_ENABLE=y CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 CONFIG_MB_QUEUE_LENGTH=20 -CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096 CONFIG_MB_SERIAL_BUF_SIZE=256 CONFIG_MB_SERIAL_TASK_PRIO=10 # CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set diff --git a/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin b/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin index 02019b7f..150e7d9f 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin and b/tools/sdk/esp32s2/bin/bootloader_dio_40m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin b/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin index 4bef8248..1bddbfa4 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin and b/tools/sdk/esp32s2/bin/bootloader_dio_80m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin b/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin index 02019b7f..150e7d9f 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin and b/tools/sdk/esp32s2/bin/bootloader_dout_40m.bin differ diff --git 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b/tools/sdk/esp32s2/bin/bootloader_qout_40m.bin differ diff --git a/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin b/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin index 4bef8248..1bddbfa4 100644 Binary files a/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin and b/tools/sdk/esp32s2/bin/bootloader_qout_80m.bin differ diff --git a/tools/sdk/esp32s2/include/app_update/include/esp_ota_ops.h b/tools/sdk/esp32s2/include/app_update/include/esp_ota_ops.h index 3bb063d3..ac0ae656 100644 --- a/tools/sdk/esp32s2/include/app_update/include/esp_ota_ops.h +++ b/tools/sdk/esp32s2/include/app_update/include/esp_ota_ops.h @@ -299,6 +299,34 @@ esp_err_t esp_ota_erase_last_boot_app_partition(void); */ bool esp_ota_check_rollback_is_possible(void); +#if CONFIG_IDF_TARGET_ESP32S2 && (CONFIG_SECURE_BOOT_V2_ENABLED || __DOXYGEN__) + +/** + * Secure Boot V2 public key indexes. + */ +typedef enum { + SECURE_BOOT_PUBLIC_KEY_INDEX_0, /*!< Points to the 0th index of the Secure Boot v2 public key */ + SECURE_BOOT_PUBLIC_KEY_INDEX_1, /*!< Points to the 1st index of the Secure Boot v2 public key */ + SECURE_BOOT_PUBLIC_KEY_INDEX_2 /*!< Points to the 2nd index of the Secure Boot v2 public key */ +} esp_ota_secure_boot_public_key_index_t; + +/** + * @brief Revokes the old signature digest. To be called in the application after the rollback logic. + * + * Relevant for Secure boot v2 on ESP32-S2 where upto 3 key digests can be stored (Key #N-1, Key #N, Key #N+1). + * When key #N-1 used to sign an app is invalidated, an OTA update is to be sent with an app signed with key #N-1 & Key #N. + * After successfully booting the OTA app should call this function to revoke Key #N-1. + * + * @param index - The index of the signature block to be revoked + * + * @return + * - ESP_OK: If revocation is successful. + * - ESP_ERR_INVALID_ARG: If the index of the public key to be revoked is incorrect. + * - ESP_FAIL: If secure boot v2 has not been enabled. + */ +esp_err_t esp_ota_revoke_secure_boot_public_key(esp_ota_secure_boot_public_key_index_t index); +#endif /* CONFIG_IDF_TARGET_ESP32S2 */ + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/asio/asio/asio/include/asio/ssl/error.hpp b/tools/sdk/esp32s2/include/asio/asio/asio/include/asio/ssl/error.hpp index bbb5ef82..71599e7b 100644 --- a/tools/sdk/esp32s2/include/asio/asio/asio/include/asio/ssl/error.hpp +++ b/tools/sdk/esp32s2/include/asio/asio/asio/include/asio/ssl/error.hpp @@ -56,7 +56,8 @@ enum stream_errors #else // defined(GENERATING_DOCUMENTATION) # if (OPENSSL_VERSION_NUMBER < 0x10100000L) \ && !defined(OPENSSL_IS_BORINGSSL) \ - && !defined(ASIO_USE_WOLFSSL) + && !defined(ASIO_USE_WOLFSSL) \ + && !defined(ASIO_USE_ESP_OPENSSL) stream_truncated = ERR_PACK(ERR_LIB_SSL, 0, SSL_R_SHORT_READ), # else stream_truncated = 1, diff --git a/tools/sdk/esp32s2/include/asio/port/include/esp_asio_config.h b/tools/sdk/esp32s2/include/asio/port/include/esp_asio_config.h index 750f4cbe..bcf8c38d 100644 --- a/tools/sdk/esp32s2/include/asio/port/include/esp_asio_config.h +++ b/tools/sdk/esp32s2/include/asio/port/include/esp_asio_config.h @@ -40,4 +40,11 @@ # define ASIO_STANDALONE # define ASIO_HAS_PTHREADS +# ifdef CONFIG_ASIO_USE_ESP_OPENSSL +# define ASIO_USE_ESP_OPENSSL +# define OPENSSL_NO_ENGINE +# elif CONFIG_ASIO_USE_ESP_WOLFSSL +# define ASIO_USE_WOLFSSL +# endif // CONFIG_ASIO_USE_ESP_OPENSSL + #endif // _ESP_ASIO_CONFIG_H_ diff --git a/tools/sdk/esp32s2/include/asio/port/include/openssl/conf.h b/tools/sdk/esp32s2/include/asio/port/include/openssl/conf.h new file mode 100644 index 00000000..f125c3e6 --- /dev/null +++ b/tools/sdk/esp32s2/include/asio/port/include/openssl/conf.h @@ -0,0 +1,26 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_CONF_H +#define _ESP_ASIO_OPENSSL_CONF_H +#include "esp_asio_config.h" +#include "openssl/esp_asio_openssl_stubs.h" + +#if defined(ASIO_USE_WOLFSSL) +// SSLv3 Methods not present in current wolfSSL library +#define OPENSSL_NO_SSL3 +#include_next "openssl/conf.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_CONF_H diff --git a/tools/sdk/esp32s2/include/asio/port/include/openssl/dh.h b/tools/sdk/esp32s2/include/asio/port/include/openssl/dh.h new file mode 100644 index 00000000..def713cf --- /dev/null +++ b/tools/sdk/esp32s2/include/asio/port/include/openssl/dh.h @@ -0,0 +1,23 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_DH_STUB_H +#define _ESP_ASIO_OPENSSL_DH_STUB_H +// Dummy header needed for ASIO compilation with esp-openssl + +#if defined(ASIO_USE_WOLFSSL) +#include_next "openssl/dh.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_DH_STUB_H diff --git a/tools/sdk/esp32s2/include/asio/port/include/openssl/esp_asio_openssl_stubs.h b/tools/sdk/esp32s2/include/asio/port/include/openssl/esp_asio_openssl_stubs.h new file mode 100644 index 00000000..fde52317 --- /dev/null +++ b/tools/sdk/esp32s2/include/asio/port/include/openssl/esp_asio_openssl_stubs.h @@ -0,0 +1,209 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_STUBS_H +#define _ESP_ASIO_OPENSSL_STUBS_H + +/** + * @note This header contains openssl API which are NOT implemented, and are only provided + * as stubs or no-operations to get the ASIO library compiled and working with most + * practical use cases as an embedded application on ESP platform + */ + +#if defined(ASIO_USE_WOLFSSL) + +#include "wolfssl/ssl.h" +// esp-wolfssl disables filesystem by default, but the ssl filesystem functions are needed for the ASIO to compile +// - so we could either configure wolfSSL to use filesystem +// - or use the default wolfSSL and declare the filesystem functions -- preferred option, as whenever +// the filesystem functions are used from app code (potential security impact if private keys in a filesystem) +// compilation fails with linking errors. + +#if defined(NO_FILESYSTEM) +// WolfSSL methods that are not included in standard esp-wolfssl config, must be defined here +// as function stubs, so ASIO compiles, but would get link errors, if these functions were used. + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct WOLFSSL_CTX WOLFSSL_CTX; + +void wolfSSL_CTX_set_verify_depth(WOLFSSL_CTX *ctx,int depth); +int SSL_CTX_load_verify_locations(WOLFSSL_CTX*, const char*, const char*); +int SSL_CTX_use_certificate_file(WOLFSSL_CTX*, const char*, int); +int SSL_CTX_use_certificate_chain_file(WOLFSSL_CTX*, const char*); +int SSL_CTX_use_PrivateKey_file(WOLFSSL_CTX*, const char*, int); +int SSL_CTX_use_RSAPrivateKey_file(WOLFSSL_CTX*, const char*, int); + +#if defined(__cplusplus) +} /* extern C */ +#endif + +#endif // NO_FILESYSTEM + +#elif defined(ASIO_USE_ESP_OPENSSL) + +#include "internal/ssl_x509.h" +#include "internal/ssl_pkey.h" +#include "mbedtls/pem.h" +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +// The most applicable OpenSSL version wrtt ASIO usage +#define OPENSSL_VERSION_NUMBER 0x10100001L +// SSLv2 methods not supported +// OpenSSL port supports: TLS_ANY, TLS_1, TLS_1_1, TLS_1_2, SSL_3 +#define OPENSSL_NO_SSL2 +#define SSL2_VERSION 0x0002 + +#define SSL_R_SHORT_READ 219 +#define SSL_OP_ALL 0 +#define SSL_OP_SINGLE_DH_USE 0 +#define SSL_OP_NO_COMPRESSION 0 +// Translates mbedTLS PEM parse error, used by ASIO +#define PEM_R_NO_START_LINE -MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT + +#define SSL_OP_NO_SSLv2 0x01000000L +#define SSL_OP_NO_SSLv3 0x02000000L +#define SSL_OP_NO_TLSv1 0x04000000L + +#define X509_FILETYPE_PEM 1 +#define X509_FILETYPE_ASN1 2 +#define SSL_FILETYPE_ASN1 X509_FILETYPE_ASN1 +#define SSL_FILETYPE_PEM X509_FILETYPE_PEM + +#define NID_subject_alt_name 85 + + +#define GEN_DNS 2 +#define GEN_IPADD 7 +#define V_ASN1_OCTET_STRING 4 +#define V_ASN1_IA5STRING 22 +#define NID_commonName 13 + +#define SSL_CTX_get_app_data(ctx) ((void*)SSL_CTX_get_ex_data(ctx, 0)) + +/** +* @brief Frees DH object -- not implemented +* +* Current implementation calls SSL_ASSERT +* +* @param r DH object +*/ +void DH_free(DH *r); + +/** + * @brief Frees GENERAL_NAMES -- not implemented + * + * Current implementation calls SSL_ASSERT + * + * @param r GENERAL_NAMES object + */ +void GENERAL_NAMES_free(GENERAL_NAMES * gens); + +/** + * @brief Returns subject name from X509 -- not implemented + * + * Current implementation calls SSL_ASSERT + * + * @param r X509 object + */ +X509_NAME *X509_get_subject_name(X509 *a); + +/** + * @brief API provaded as declaration only + * + */ +int X509_STORE_CTX_get_error_depth(X509_STORE_CTX *ctx); + +/** + * @brief API provaded as declaration only + * + */ +int X509_NAME_get_index_by_NID(X509_NAME *name, int nid, int lastpos); + +/** + * @brief API provaded as declaration only + * + */ +X509_NAME_ENTRY *X509_NAME_get_entry(X509_NAME *name, int loc); + +/** + * @brief API provaded as declaration only + * + */ +ASN1_STRING *X509_NAME_ENTRY_get_data(X509_NAME_ENTRY *ne); + +/** + * @brief API provaded as declaration only + * + */ +void *X509_get_ext_d2i(X509 *x, int nid, int *crit, int *idx); + +/** + * @brief API provaded as declaration only + * + */ +X509 * X509_STORE_CTX_get_current_cert(X509_STORE_CTX *ctx); + +/** + * @brief Reads DH params from a bio object -- not implemented + * + * Current implementation calls SSL_ASSERT + */ +DH *PEM_read_bio_DHparams(BIO *bp, DH **x, pem_password_cb *cb, void *u); + +/** + * @brief API provaded as declaration only + * + */ +void * X509_STORE_CTX_get_ex_data(X509_STORE_CTX *ctx,int idx); + +/** + * @brief Sets DH params to ssl ctx -- not implemented + * + * Current implementation calls SSL_ASSERT + */ +int SSL_CTX_set_tmp_dh(SSL_CTX *ctx, const DH *dh); + +/** + * @brief API provaded as declaration only + * + */ +void SSL_CTX_set_default_passwd_cb_userdata(SSL_CTX *ctx, void *data); + +/** + * @brief API provaded as declaration only + * + */ +void SSL_CTX_set_default_passwd_cb(SSL_CTX *ctx, pem_password_cb *cb); + +/** + * @brief Clears any existing chain associated with the current certificate of ctx. + * + */ +int SSL_CTX_clear_chain_certs(SSL_CTX *ctx); + +#if defined(__cplusplus) +} /* extern C */ +#endif + +#endif /* ASIO_USE_ESP_OPENSSL, ASIO_USE_WOLFSSL */ +#endif /* _ESP_ASIO_OPENSSL_STUBS_H */ diff --git a/tools/sdk/esp32s2/include/asio/port/include/openssl/rsa.h b/tools/sdk/esp32s2/include/asio/port/include/openssl/rsa.h new file mode 100644 index 00000000..5d9d10e8 --- /dev/null +++ b/tools/sdk/esp32s2/include/asio/port/include/openssl/rsa.h @@ -0,0 +1,23 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_RSA_STUB_H +#define _ESP_ASIO_OPENSSL_RSA_STUB_H +// Dummy header needed for ASIO compilation with esp-openssl + +#if defined(ASIO_USE_WOLFSSL) +#include_next "openssl/rsa.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_RSA_STUB_H diff --git a/tools/sdk/esp32s2/include/asio/port/include/openssl/x509v3.h b/tools/sdk/esp32s2/include/asio/port/include/openssl/x509v3.h new file mode 100644 index 00000000..5ae8e784 --- /dev/null +++ b/tools/sdk/esp32s2/include/asio/port/include/openssl/x509v3.h @@ -0,0 +1,23 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _ESP_ASIO_OPENSSL_X509V3_STUB_H +#define _ESP_ASIO_OPENSSL_X509V3_STUB_H +// Dummy header needed for ASIO compilation with esp-openssl + +#if defined(ASIO_USE_WOLFSSL) +#include_next "openssl/x509v3.h" +#endif // ASIO_USE_WOLFSSL + +#endif // _ESP_ASIO_OPENSSL_X509V3_STUB_H diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash_config.h b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash_config.h index 98c169f4..45367730 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash_config.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash_config.h @@ -14,6 +14,7 @@ #pragma once +#include "sdkconfig.h" #include "esp_image_format.h" #ifdef __cplusplus @@ -66,6 +67,22 @@ void bootloader_flash_gpio_config(const esp_image_header_t* pfhdr); */ void bootloader_flash_dummy_config(const esp_image_header_t* pfhdr); +#ifdef CONFIG_IDF_TARGET_ESP32 +/** + * @brief Return the pin number used for custom SPI flash and/or SPIRAM WP pin + * + * Can be determined by eFuse values in most cases, or overriden in configuration + * + * This value is only meaningful if the other SPI flash pins are overriden via eFuse. + * + * This value is only meaningful if flash is set to QIO or QOUT mode, or if + * SPIRAM is enabled. + * + * @return Pin number to use, or -1 if the default should be kept + */ +int bootloader_flash_get_wp_pin(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/esp_app_format.h b/tools/sdk/esp32s2/include/bootloader_support/include/esp_app_format.h index 0f0a6038..a67c38ee 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/esp_app_format.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/esp_app_format.h @@ -19,7 +19,8 @@ */ typedef enum { ESP_CHIP_ID_ESP32 = 0x0000, /*!< chip ID: ESP32 */ - ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32S2 */ + ESP_CHIP_ID_ESP32S2 = 0x0002, /*!< chip ID: ESP32-S2 */ + ESP_CHIP_ID_ESP32S3 = 0x0004, /*!< chip ID: ESP32-S3 */ ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */ } __attribute__((packed)) esp_chip_id_t; diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_partitions.h b/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_partitions.h index 004bbeb2..1fc9d4f6 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_partitions.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/esp_flash_partitions.h @@ -44,7 +44,7 @@ extern "C" { /* Pre-partition table fixed flash offsets */ #define ESP_BOOTLOADER_DIGEST_OFFSET 0x0 -#define ESP_BOOTLOADER_OFFSET 0x1000 /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */ +#define ESP_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */ #define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/ #define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */ diff --git a/tools/sdk/esp32s2/include/bootloader_support/include/esp_secure_boot.h b/tools/sdk/esp32s2/include/bootloader_support/include/esp_secure_boot.h index 551a7370..f15c240d 100644 --- a/tools/sdk/esp32s2/include/bootloader_support/include/esp_secure_boot.h +++ b/tools/sdk/esp32s2/include/bootloader_support/include/esp_secure_boot.h @@ -17,11 +17,10 @@ #include #include "soc/efuse_periph.h" #include "esp_image_format.h" - +#include "esp_rom_efuse.h" #include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/efuse.h" -#else + +#if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/secure_boot.h" #endif @@ -57,8 +56,8 @@ static inline bool esp_secure_boot_enabled(void) #elif CONFIG_SECURE_BOOT_V2_ENABLED return ets_use_secure_boot_v2(); #endif -#elif CONFIG_IDF_TARGET_ESP32S2 - return ets_efuse_secure_boot_enabled(); +#else + return esp_rom_efuse_is_secure_boot_enabled(); #endif return false; /* Secure Boot not enabled in menuconfig */ } diff --git a/tools/sdk/esp32s2/include/config/sdkconfig.h b/tools/sdk/esp32s2/include/config/sdkconfig.h index 35519c02..6292780b 100644 --- a/tools/sdk/esp32s2/include/config/sdkconfig.h +++ b/tools/sdk/esp32s2/include/config/sdkconfig.h @@ -14,17 +14,17 @@ #define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1 #define CONFIG_APP_COMPILE_TIME_DATE 1 #define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 16 +#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000 #define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1 #define CONFIG_BOOTLOADER_LOG_LEVEL_NONE 1 #define CONFIG_BOOTLOADER_LOG_LEVEL 0 -#define CONFIG_BOOTLOADER_SPI_WP_PIN 7 #define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 #define CONFIG_BOOTLOADER_WDT_ENABLE 1 #define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 #define CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP 1 #define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10 +#define CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE 1 #define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 -#define CONFIG_ESPTOOLPY_WITH_STUB 1 #define CONFIG_ESPTOOLPY_FLASHMODE_QIO 1 #define CONFIG_ESPTOOLPY_FLASHMODE "dio" #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1 @@ -67,6 +67,8 @@ #define CONFIG_APPTRACE_DEST_NONE 1 #define CONFIG_APPTRACE_LOCK_ENABLE 1 #define CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF 0 +#define CONFIG_BTDM_CTRL_PCM_ROLE_EFF 0 +#define CONFIG_BTDM_CTRL_PCM_POLAR_EFF 0 #define CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF 0 #define CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF 0 #define CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF 0 @@ -79,8 +81,8 @@ #define CONFIG_EFUSE_MAX_BLK_LEN 256 #define CONFIG_ESP_TLS_USING_MBEDTLS 1 #define CONFIG_ESP_TLS_SERVER 1 -#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160 1 -#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 160 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 1 +#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ 240 #define CONFIG_ESP32S2_MEMPROT_FEATURE 1 #define CONFIG_ESP32S2_MEMPROT_FEATURE_LOCK 1 #define CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB 1 @@ -109,6 +111,7 @@ #define CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 1 #define CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC 1 #define CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES 576 +#define CONFIG_ESP32S2_KEEP_USB_ALIVE 1 #define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 #define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32 #define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2048 @@ -116,9 +119,8 @@ #define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024 #define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048 #define CONFIG_ESP_CONSOLE_UART_DEFAULT 1 +#define CONFIG_ESP_CONSOLE_UART 1 #define CONFIG_ESP_CONSOLE_UART_NUM 0 -#define CONFIG_ESP_CONSOLE_UART_TX_GPIO 43 -#define CONFIG_ESP_CONSOLE_UART_RX_GPIO 44 #define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200 #define CONFIG_ESP_INT_WDT 1 #define CONFIG_ESP_INT_WDT_TIMEOUT_MS 1000 @@ -143,6 +145,7 @@ #define CONFIG_ESP_NETIF_TCPIP_LWIP 1 #define CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER 1 #define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1 +#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1 #define CONFIG_ESP_TIMER_TASK_STACK_SIZE 4096 #define CONFIG_ESP_TIMER_IMPL_SYSTIMER 1 #define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 16 @@ -150,6 +153,7 @@ #define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER 1 #define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 0 #define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM 16 +#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 #define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 #define CONFIG_ESP32_WIFI_TX_BA_WIN 6 #define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 @@ -170,16 +174,20 @@ #define CONFIG_FATFS_TIMEOUT_MS 10000 #define CONFIG_FATFS_PER_FILE_CACHE 1 #define CONFIG_FATFS_ALLOC_PREFER_EXTRAM 1 +#define CONFIG_FMB_COMM_MODE_TCP_EN 1 +#define CONFIG_FMB_TCP_PORT_DEFAULT 502 +#define CONFIG_FMB_TCP_PORT_MAX_CONN 5 +#define CONFIG_FMB_TCP_CONNECTION_TOUT_SEC 20 #define CONFIG_FMB_COMM_MODE_RTU_EN 1 #define CONFIG_FMB_COMM_MODE_ASCII_EN 1 #define CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND 150 #define CONFIG_FMB_MASTER_DELAY_MS_CONVERT 200 #define CONFIG_FMB_QUEUE_LENGTH 20 -#define CONFIG_FMB_SERIAL_TASK_STACK_SIZE 2048 +#define CONFIG_FMB_PORT_TASK_STACK_SIZE 4096 #define CONFIG_FMB_SERIAL_BUF_SIZE 256 #define CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB 8 #define CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS 1000 -#define CONFIG_FMB_SERIAL_TASK_PRIO 10 +#define CONFIG_FMB_PORT_TASK_PRIO 10 #define CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT 20 #define CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE 20 #define CONFIG_FMB_CONTROLLER_STACK_SIZE 4096 @@ -221,6 +229,8 @@ #define CONFIG_LWIP_SO_REUSE 1 #define CONFIG_LWIP_SO_REUSE_RXTOALL 1 #define CONFIG_LWIP_SO_RCVBUF 1 +#define CONFIG_LWIP_IP4_FRAG 1 +#define CONFIG_LWIP_IP6_FRAG 1 #define CONFIG_LWIP_ETHARP_TRUST_IP_MAC 1 #define CONFIG_LWIP_ESP_GRATUITOUS_ARP 1 #define CONFIG_LWIP_GARP_TMR_INTERVAL 60 @@ -242,6 +252,7 @@ #define CONFIG_LWIP_TCP_RECVMBOX_SIZE 6 #define CONFIG_LWIP_TCP_QUEUE_OOSEQ 1 #define CONFIG_LWIP_TCP_OVERSIZE_MSS 1 +#define CONFIG_LWIP_TCP_RTO_TIME 3000 #define CONFIG_LWIP_MAX_UDP_PCBS 16 #define CONFIG_LWIP_UDP_RECVMBOX_SIZE 6 #define CONFIG_LWIP_TCPIP_TASK_STACK_SIZE 2560 @@ -249,6 +260,8 @@ #define CONFIG_LWIP_TCPIP_TASK_AFFINITY 0x0 #define CONFIG_LWIP_PPP_SUPPORT 1 #define CONFIG_LWIP_PPP_ENABLE_IPV6 1 +#define CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE 3 +#define CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS 5 #define CONFIG_LWIP_PPP_PAP_SUPPORT 1 #define CONFIG_LWIP_PPP_CHAP_SUPPORT 1 #define CONFIG_LWIP_PPP_MSCHAP_SUPPORT 1 @@ -328,6 +341,7 @@ #define CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE 1 #define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 #define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_OPENSSL_ERROR_STACK 1 #define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1 #define CONFIG_PTHREAD_TASK_PRIO_DEFAULT 5 #define CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT 2048 @@ -339,6 +353,7 @@ #define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 #define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 #define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE 8192 #define CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP 1 #define CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP 1 #define CONFIG_SPI_FLASH_SUPPORT_GD_CHIP 1 @@ -353,32 +368,32 @@ #define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 #define CONFIG_SPIFFS_META_LENGTH 4 #define CONFIG_SPIFFS_USE_MTIME 1 +#define CONFIG_WS_BUFFER_SIZE 1024 #define CONFIG_USB_ENABLED 1 -#define CONFIG_USB_MAX_POWER_USAGE 100 +#define CONFIG_USB_DO_NOT_CREATE_TASK 1 +#define CONFIG_USB_TASK_PRIORITY 5 +#define CONFIG_USB_CUSTOM 1 #define CONFIG_USB_CDC_ENABLED 1 +#define CONFIG_USB_DESC_CDC_STRING "Espressif CDC Device" #define CONFIG_USB_CDC_RX_BUFSIZE 64 #define CONFIG_USB_CDC_TX_BUFSIZE 64 -#define CONFIG_USB_DFU_RT_ENABLED 1 #define CONFIG_USB_MSC_ENABLED 1 +#define CONFIG_USB_DESC_MSC_STRING "Espressif MSC Device" #define CONFIG_USB_MSC_BUFSIZE 512 #define CONFIG_USB_HID_ENABLED 1 +#define CONFIG_USB_DESC_HID_STRING "Espressif HID Device" #define CONFIG_USB_HID_BUFSIZE 64 #define CONFIG_USB_MIDI_ENABLED 1 +#define CONFIG_USB_DESC_MIDI_STRING "Espressif MIDI Device" #define CONFIG_USB_MIDI_RX_BUFSIZE 64 #define CONFIG_USB_MIDI_TX_BUFSIZE 64 -#define CONFIG_USB_VENDOR_ENABLED 1 -#define CONFIG_USB_DESC_USE_ESPRESSIF_VID 1 -#define CONFIG_USB_DESC_USE_DEFAULT_PID 1 -#define CONFIG_USB_DESC_BCDDEVICE 0x0100 -#define CONFIG_USB_DESC_MANUFACTURER_STRING "Espressif Systems" -#define CONFIG_USB_DESC_PRODUCT_STRING "Espressif Device" -#define CONFIG_USB_DESC_SERIAL_STRING "0" -#define CONFIG_USB_DESC_CDC_STRING "Espressif CDC Device" +#define CONFIG_USB_DFU_RT_ENABLED 1 #define CONFIG_USB_DESC_DFU_RT_STRING "Espressif DFU Device" -#define CONFIG_USB_DESC_MSC_STRING "Espressif MSC Device" -#define CONFIG_USB_DESC_MIDI_STRING "Espressif MIDI Device" -#define CONFIG_USB_DESC_HID_STRING "Espressif HID Device" +#define CONFIG_USB_VENDOR_ENABLED 1 #define CONFIG_USB_DESC_VENDOR_STRING "Espressif VENDOR Device" +#define CONFIG_USB_VENDOR_RX_BUFSIZE 64 +#define CONFIG_USB_VENDOR_TX_BUFSIZE 64 +#define CONFIG_USB_DEBUG_LEVEL 0 #define CONFIG_UNITY_ENABLE_FLOAT 1 #define CONFIG_UNITY_ENABLE_DOUBLE 1 #define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1 @@ -398,10 +413,7 @@ /* List of deprecated options */ #define CONFIG_ADC2_DISABLE_DAC CONFIG_ADC_DISABLE_DAC #define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEFAULT -#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE #define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT -#define CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO -#define CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO #define CONFIG_CXX_EXCEPTIONS CONFIG_COMPILER_CXX_EXCEPTIONS #define CONFIG_CXX_EXCEPTIONS_EMG_POOL_SIZE CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE #define CONFIG_ESP32S2_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT @@ -427,8 +439,8 @@ #define CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND #define CONFIG_MB_QUEUE_LENGTH CONFIG_FMB_QUEUE_LENGTH #define CONFIG_MB_SERIAL_BUF_SIZE CONFIG_FMB_SERIAL_BUF_SIZE -#define CONFIG_MB_SERIAL_TASK_PRIO CONFIG_FMB_SERIAL_TASK_PRIO -#define CONFIG_MB_SERIAL_TASK_STACK_SIZE CONFIG_FMB_SERIAL_TASK_STACK_SIZE +#define CONFIG_MB_SERIAL_TASK_PRIO CONFIG_FMB_PORT_TASK_PRIO +#define CONFIG_MB_SERIAL_TASK_STACK_SIZE CONFIG_FMB_PORT_TASK_STACK_SIZE #define CONFIG_MB_TIMER_GROUP CONFIG_FMB_TIMER_GROUP #define CONFIG_MB_TIMER_INDEX CONFIG_FMB_TIMER_INDEX #define CONFIG_MB_TIMER_PORT_ENABLED CONFIG_FMB_TIMER_PORT_ENABLED diff --git a/tools/sdk/esp32s2/include/console/esp_console.h b/tools/sdk/esp32s2/include/console/esp_console.h index 1409bfe5..98201cdb 100644 --- a/tools/sdk/esp32s2/include/console/esp_console.h +++ b/tools/sdk/esp32s2/include/console/esp_console.h @@ -56,60 +56,49 @@ typedef struct { uint32_t task_stack_size; //!< repl task stack size uint32_t task_priority; //!< repl task priority const char *prompt; //!< prompt (NULL represents default: "esp> ") - union { - struct { - int channel; //!< UART channel - uint32_t baud_rate; //!< Comunication baud rate - int tx_gpio; //!< GPIO number for TX path, -1 means using the default - int rx_gpio; //!< GPIO number for RX path, -1 means using the default - } uart; //!< UART specific configuration - } device; //!< device configuration } esp_console_repl_config_t; -#ifdef CONFIG_ESP_CONSOLE_UART_NUM -#define CONSOLE_DEFAULT_UART_CHANNEL CONFIG_ESP_CONSOLE_UART_NUM -#else -#define CONSOLE_DEFAULT_UART_CHANNEL 0 -#endif - -#ifdef CONFIG_ESP_CONSOLE_UART_BAUDRATE -#define CONSOLE_DEFAULT_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE -#else -#define CONSOLE_DEFAULT_UART_BAUDRATE 115200 -#endif - -#ifdef CONFIG_ESP_CONSOLE_UART_TX_GPIO -#define CONSOLE_DEFAULT_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO -#else -#define CONSOLE_DEFAULT_UART_TX_GPIO 1 -#endif - -#ifdef CONFIG_ESP_CONSOLE_UART_RX_GPIO -#define CONSOLE_DEFAULT_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO -#else -#define CONSOLE_DEFAULT_UART_RX_GPIO 3 -#endif - /** * @brief Default console repl configuration value * */ -#define ESP_CONSOLE_REPL_CONFIG_DEFAULT() \ - { \ - .max_history_len = 32, \ - .history_save_path = NULL, \ - .task_stack_size = 4096, \ - .task_priority = 2, \ - .prompt = NULL, \ - .device = { \ - .uart = { \ - .channel = CONSOLE_DEFAULT_UART_CHANNEL, \ - .baud_rate = CONSOLE_DEFAULT_UART_BAUDRATE, \ - .tx_gpio = CONSOLE_DEFAULT_UART_TX_GPIO, \ - .rx_gpio = CONSOLE_DEFAULT_UART_RX_GPIO, \ - } \ - } \ - } +#define ESP_CONSOLE_REPL_CONFIG_DEFAULT() \ +{ \ + .max_history_len = 32, \ + .history_save_path = NULL, \ + .task_stack_size = 4096, \ + .task_priority = 2, \ + .prompt = NULL, \ +} + +/** + * @brief Parameters for console device: UART + * + */ +typedef struct { + int channel; //!< UART channel number (count from zero) + int baud_rate; //!< Comunication baud rate + int tx_gpio_num; //!< GPIO number for TX path, -1 means using default one + int rx_gpio_num; //!< GPIO number for RX path, -1 means using default one +} esp_console_dev_uart_config_t; + +#ifdef CONFIG_ESP_CONSOLE_UART_CUSTOM +#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \ +{ \ + .channel = CONFIG_ESP_CONSOLE_UART_NUM, \ + .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \ + .tx_gpio_num = CONFIG_ESP_CONSOLE_UART_TX_GPIO, \ + .rx_gpio_num = CONFIG_ESP_CONSOLE_UART_RX_GPIO, \ +} +#else +#define ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT() \ +{ \ + .channel = CONFIG_ESP_CONSOLE_UART_NUM, \ + .baud_rate = CONFIG_ESP_CONSOLE_UART_BAUDRATE, \ + .tx_gpio_num = -1, \ + .rx_gpio_num = -1, \ +} +#endif /** * @brief initialize console module @@ -270,10 +259,34 @@ esp_err_t esp_console_register_help_command(void); /****************************************************************************** * Console REPL ******************************************************************************/ + /** - * @brief Initialize console REPL environment + * @brief Type defined for console REPL * - * @param config REPL configuration + */ +typedef struct esp_console_repl_s esp_console_repl_t; + +/** + * @brief Console REPL base structure + * + */ +struct esp_console_repl_s { + /** + * @brief Delete console REPL environment + * @param[in] repl REPL handle returned from esp_console_new_repl_xxx + * @return + * - ESP_OK on success + * - ESP_FAIL on errors + */ + esp_err_t (*del)(esp_console_repl_t *repl); +}; + +/** + * @brief Establish a console REPL environment over UART driver + * + * @param[in] dev_config UART device configuration + * @param[in] repl_config REPL configuration + * @param[out] ret_repl return REPL handle after initialization succeed, return NULL otherwise * * @note This is a all-in-one function to establish the environment needed for REPL, includes: * - Install the UART driver on the console UART (8n1, 115200, REF_TICK clock source) @@ -289,27 +302,17 @@ esp_err_t esp_console_register_help_command(void); * - ESP_OK on success * - ESP_FAIL Parameter error */ -esp_err_t esp_console_repl_init(const esp_console_repl_config_t *config); +esp_err_t esp_console_new_repl_uart(const esp_console_dev_uart_config_t *dev_config, const esp_console_repl_config_t *repl_config, esp_console_repl_t **ret_repl); /** - * @brief Start REPL task - * + * @brief Start REPL environment + * @param[in] repl REPL handle returned from esp_console_new_repl_xxx + * @note Once the REPL got started, it won't be stopped until user call repl->del(repl) to destory the REPL environment. * @return * - ESP_OK on success * - ESP_ERR_INVALID_STATE, if repl has started already */ -esp_err_t esp_console_repl_start(void); - -/** - * @brief Register a 'quit' command - * - * Default 'quit' command will destory resources and exit REPL environment. - * - * @return - * - ESP_OK on success - * - others on failed - */ -esp_err_t esp_console_register_quit_command(void); +esp_err_t esp_console_start_repl(esp_console_repl_t *repl); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/driver/esp32s2/include/driver/touch_sensor.h b/tools/sdk/esp32s2/include/driver/esp32s2/include/driver/touch_sensor.h index 999235c1..2a34950a 100644 --- a/tools/sdk/esp32s2/include/driver/esp32s2/include/driver/touch_sensor.h +++ b/tools/sdk/esp32s2/include/driver/esp32s2/include/driver/touch_sensor.h @@ -22,7 +22,7 @@ extern "C" { /** * @brief Set touch sensor FSM start * @note Start FSM after the touch sensor FSM mode is set. - * @note Call this function will reset baseline of all touch channels. + * @note Call this function will reset benchmark of all touch channels. * @return * - ESP_OK on success */ @@ -98,7 +98,7 @@ esp_err_t touch_pad_get_idle_channel_connect(touch_pad_conn_type_t *type); /** * @brief Set the trigger threshold of touch sensor. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * @note If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered. * @param touch_num touch pad index * @param threshold threshold of touch sensor. Should be less than the max change value of touch. @@ -264,15 +264,15 @@ esp_err_t touch_pad_timeout_resume(void); esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data); /** - * @brief get baseline of touch sensor. - * @note After initialization, the baseline value is the maximum during the first measurement period. + * @brief get benchmark of touch sensor. + * @note After initialization, the benchmark value is the maximum during the first measurement period. * @param touch_num touch pad index - * @param basedata pointer to accept touch sensor baseline value + * @param benchmark pointer to accept touch sensor benchmark value * @return * - ESP_OK Success * - ESP_ERR_INVALID_ARG Touch channel 0 haven't this parameter. */ -esp_err_t touch_pad_filter_read_baseline(touch_pad_t touch_num, uint32_t *basedata); +esp_err_t touch_pad_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark); /** * @brief Get smoothed data that obtained by filtering the raw data. @@ -283,13 +283,13 @@ esp_err_t touch_pad_filter_read_baseline(touch_pad_t touch_num, uint32_t *baseda esp_err_t touch_pad_filter_read_smooth(touch_pad_t touch_num, uint32_t *smooth); /** - * @brief Force reset baseline to raw data of touch sensor. + * @brief Force reset benchmark to raw data of touch sensor. * @param touch_num touch pad index * - TOUCH_PAD_MAX Reset basaline of all channels * @return * - ESP_OK Success */ -esp_err_t touch_pad_filter_reset_baseline(touch_pad_t touch_num); +esp_err_t touch_pad_reset_benchmark(touch_pad_t touch_num); /** * @brief set parameter of touch sensor filter and detection algorithm. @@ -375,11 +375,12 @@ esp_err_t touch_pad_denoise_read_data(uint32_t *data); /** * @brief set parameter of waterproof function. + * * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. + * Guard pad is used to detect the large area of water covering the touch panel. + * Shield pad is used to shield the influence of water droplets covering the touch panel. * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. + * * @param waterproof parameter of waterproof * @return * - ESP_OK Success @@ -396,23 +397,14 @@ esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof); /** * @brief Enable parameter of waterproof function. - * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. - * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. + * Should be called after function ``touch_pad_waterproof_set_config``. * @return * - ESP_OK Success */ esp_err_t touch_pad_waterproof_enable(void); /** - * @brief Enable parameter of waterproof function. - * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. - * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. + * @brief Disable parameter of waterproof function. * @return * - ESP_OK Success */ @@ -537,14 +529,14 @@ esp_err_t touch_pad_sleep_set_threshold(touch_pad_t pad_num, uint32_t touch_thre esp_err_t touch_pad_sleep_get_threshold(touch_pad_t pad_num, uint32_t *touch_thres); /** - * @brief Read baseline of touch sensor sleep channel. + * @brief Read benchmark of touch sensor sleep channel. * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode. - * @param baseline pointer to accept touch sensor baseline value + * @param benchmark pointer to accept touch sensor benchmark value * @return * - ESP_OK Success * - ESP_ERR_INVALID_ARG parameter is NULL */ -esp_err_t touch_pad_sleep_channel_read_baseline(touch_pad_t pad_num, uint32_t *baseline); +esp_err_t touch_pad_sleep_channel_read_benchmark(touch_pad_t pad_num, uint32_t *benchmark); /** * @brief Read smoothed data of touch sensor sleep channel. @@ -568,12 +560,12 @@ esp_err_t touch_pad_sleep_channel_read_smooth(touch_pad_t pad_num, uint32_t *smo esp_err_t touch_pad_sleep_channel_read_data(touch_pad_t pad_num, uint32_t *raw_data); /** - * @brief Reset baseline of touch sensor sleep channel. + * @brief Reset benchmark of touch sensor sleep channel. * * @return * - ESP_OK Success */ -esp_err_t touch_pad_sleep_channel_reset_baseline(void); +esp_err_t touch_pad_sleep_channel_reset_benchmark(void); /** * @brief Read proximity count of touch sensor sleep channel. diff --git a/tools/sdk/esp32s2/include/driver/include/driver/adc_common.h b/tools/sdk/esp32s2/include/driver/include/driver/adc_common.h index 9f896a55..2c426b71 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/adc_common.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/adc_common.h @@ -312,6 +312,40 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten); */ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out); +/** + * @brief Output ADC1 or ADC2's reference voltage to ``adc2_channe_t``'s IO. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @note ESP32 only supports output of ADC2's internal reference voltage. + * @param[in] adc_unit ADC unit index + * @param[in] gpio GPIO number (Only ADC2's channels IO are supported) + * + * @return + * - ESP_OK: v_ref successfully routed to selected GPIO + * - ESP_ERR_INVALID_ARG: Unsupported GPIO + */ +esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio); + +/** + * @brief Output ADC2 reference voltage to ``adc2_channe_t``'s IO. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @deprecated Use ``adc_vref_to_gpio`` instead. + * + * @param[in] gpio GPIO number (ADC2's channels are supported) + * + * @return + * - ESP_OK: v_ref successfully routed to selected GPIO + * - ESP_ERR_INVALID_ARG: Unsupported GPIO + */ +esp_err_t adc2_vref_to_gpio(gpio_num_t gpio) __attribute__((deprecated)); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/driver/include/driver/can.h b/tools/sdk/esp32s2/include/driver/include/driver/can.h index 16b88f98..7b42ce1d 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/can.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/can.h @@ -18,330 +18,57 @@ extern "C" { #endif -#include "soc/soc_caps.h" -#ifndef SOC_CAN_SUPPORTED -#error CAN is not supported in this chip target -#endif +#warning driver/can.h is deprecated, please use driver/twai.h instead -#include "freertos/FreeRTOS.h" -#include "esp_types.h" -#include "esp_intr_alloc.h" -#include "esp_err.h" -#include "gpio.h" -#include "soc/can_caps.h" #include "hal/can_types.h" +#include "driver/twai.h" -/* -------------------- Default initializers and flags ---------------------- */ -/** @cond */ //Doxy command to hide preprocessor definitions from docs -/** - * @brief Initializer macro for general configuration structure. - * - * This initializer macros allows the TX GPIO, RX GPIO, and operating mode to be - * configured. The other members of the general configuration structure are - * assigned default values. - */ -#define CAN_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ - .clkout_io = CAN_IO_UNUSED, .bus_off_io = CAN_IO_UNUSED, \ - .tx_queue_len = 5, .rx_queue_len = 5, \ - .alerts_enabled = CAN_ALERT_NONE, .clkout_divider = 0, } +/* ---------------------------- Compatibility ------------------------------- */ -/** - * @brief Alert flags - * - * The following flags represents the various kind of alerts available in - * the CAN driver. These flags can be used when configuring/reconfiguring - * alerts, or when calling can_read_alerts(). - * - * @note The CAN_ALERT_AND_LOG flag is not an actual alert, but will configure - * the CAN driver to log to UART when an enabled alert occurs. - */ -#define CAN_ALERT_TX_IDLE 0x0001 /**< Alert(1): No more messages to transmit */ -#define CAN_ALERT_TX_SUCCESS 0x0002 /**< Alert(2): The previous transmission was successful */ -#define CAN_ALERT_BELOW_ERR_WARN 0x0004 /**< Alert(4): Both error counters have dropped below error warning limit */ -#define CAN_ALERT_ERR_ACTIVE 0x0008 /**< Alert(8): CAN controller has become error active */ -#define CAN_ALERT_RECOVERY_IN_PROGRESS 0x0010 /**< Alert(16): CAN controller is undergoing bus recovery */ -#define CAN_ALERT_BUS_RECOVERED 0x0020 /**< Alert(32): CAN controller has successfully completed bus recovery */ -#define CAN_ALERT_ARB_LOST 0x0040 /**< Alert(64): The previous transmission lost arbitration */ -#define CAN_ALERT_ABOVE_ERR_WARN 0x0080 /**< Alert(128): One of the error counters have exceeded the error warning limit */ -#define CAN_ALERT_BUS_ERROR 0x0100 /**< Alert(256): A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus */ -#define CAN_ALERT_TX_FAILED 0x0200 /**< Alert(512): The previous transmission has failed (for single shot transmission) */ -#define CAN_ALERT_RX_QUEUE_FULL 0x0400 /**< Alert(1024): The RX queue is full causing a frame to be lost */ -#define CAN_ALERT_ERR_PASS 0x0800 /**< Alert(2048): CAN controller has become error passive */ -#define CAN_ALERT_BUS_OFF 0x1000 /**< Alert(4096): Bus-off condition occurred. CAN controller can no longer influence bus */ -#define CAN_ALERT_ALL 0x1FFF /**< Bit mask to enable all alerts during configuration */ -#define CAN_ALERT_NONE 0x0000 /**< Bit mask to disable all alerts during configuration */ -#define CAN_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur */ +#define CAN_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) -/** @endcond */ +#define CAN_ALERT_TX_IDLE TWAI_ALERT_TX_IDLE +#define CAN_ALERT_TX_SUCCESS TWAI_ALERT_TX_SUCCESS +#define CAN_ALERT_BELOW_ERR_WARN TWAI_ALERT_BELOW_ERR_WARN +#define CAN_ALERT_ERR_ACTIVE TWAI_ALERT_ERR_ACTIVE +#define CAN_ALERT_RECOVERY_IN_PROGRESS TWAI_ALERT_RECOVERY_IN_PROGRESS +#define CAN_ALERT_BUS_RECOVERED TWAI_ALERT_BUS_RECOVERED +#define CAN_ALERT_ARB_LOST TWAI_ALERT_ARB_LOST +#define CAN_ALERT_ABOVE_ERR_WARN TWAI_ALERT_ABOVE_ERR_WARN +#define CAN_ALERT_BUS_ERROR TWAI_ALERT_BUS_ERROR +#define CAN_ALERT_TX_FAILED TWAI_ALERT_TX_FAILED +#define CAN_ALERT_RX_QUEUE_FULL TWAI_ALERT_RX_QUEUE_FULL +#define CAN_ALERT_ERR_PASS TWAI_ALERT_ERR_PASS +#define CAN_ALERT_BUS_OFF TWAI_ALERT_BUS_OFF +#define CAN_ALERT_ALL TWAI_ALERT_ALL +#define CAN_ALERT_NONE TWAI_ALERT_NONE +#define CAN_ALERT_AND_LOG TWAI_ALERT_AND_LOG -#define CAN_IO_UNUSED ((gpio_num_t) -1) /**< Marks GPIO as unused in CAN configuration */ +#define CAN_IO_UNUSED TWAI_IO_UNUSED -/* ----------------------- Enum and Struct Definitions ---------------------- */ +#define CAN_STATE_STOPPED TWAI_STATE_STOPPED +#define CAN_STATE_RUNNING TWAI_STATE_RUNNING +#define CAN_STATE_BUS_OFF TWAI_STATE_BUS_OFF +#define CAN_STATE_RECOVERING TWAI_STATE_RECOVERING -/** - * @brief CAN driver states - */ -typedef enum { - CAN_STATE_STOPPED, /**< Stopped state. The CAN controller will not participate in any CAN bus activities */ - CAN_STATE_RUNNING, /**< Running state. The CAN controller can transmit and receive messages */ - CAN_STATE_BUS_OFF, /**< Bus-off state. The CAN controller cannot participate in bus activities until it has recovered */ - CAN_STATE_RECOVERING, /**< Recovering state. The CAN controller is undergoing bus recovery */ -} can_state_t; +typedef twai_state_t can_state_t; +typedef twai_general_config_t can_general_config_t; +typedef twai_status_info_t can_status_info_t; -/** - * @brief Structure for general configuration of the CAN driver - * - * @note Macro initializers are available for this structure - */ -typedef struct { - can_mode_t mode; /**< Mode of CAN controller */ - gpio_num_t tx_io; /**< Transmit GPIO number */ - gpio_num_t rx_io; /**< Receive GPIO number */ - gpio_num_t clkout_io; /**< CLKOUT GPIO number (optional, set to -1 if unused) */ - gpio_num_t bus_off_io; /**< Bus off indicator GPIO number (optional, set to -1 if unused) */ - uint32_t tx_queue_len; /**< Number of messages TX queue can hold (set to 0 to disable TX Queue) */ - uint32_t rx_queue_len; /**< Number of messages RX queue can hold */ - uint32_t alerts_enabled; /**< Bit field of alerts to enable (see documentation) */ - uint32_t clkout_divider; /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */ -} can_general_config_t; -/** - * @brief Structure to store status information of CAN driver - */ -typedef struct { - can_state_t state; /**< Current state of CAN controller (Stopped/Running/Bus-Off/Recovery) */ - uint32_t msgs_to_tx; /**< Number of messages queued for transmission or awaiting transmission completion */ - uint32_t msgs_to_rx; /**< Number of messages in RX queue waiting to be read */ - uint32_t tx_error_counter; /**< Current value of Transmit Error Counter */ - uint32_t rx_error_counter; /**< Current value of Receive Error Counter */ - uint32_t tx_failed_count; /**< Number of messages that failed transmissions */ - uint32_t rx_missed_count; /**< Number of messages that were lost due to a full RX queue */ - uint32_t arb_lost_count; /**< Number of instances arbitration was lost */ - uint32_t bus_error_count; /**< Number of instances a bus error has occurred */ -} can_status_info_t; - -/* ----------------------------- Public API -------------------------------- */ - -/** - * @brief Install CAN driver - * - * This function installs the CAN driver using three configuration structures. - * The required memory is allocated and the CAN driver is placed in the stopped - * state after running this function. - * - * @param[in] g_config General configuration structure - * @param[in] t_config Timing configuration structure - * @param[in] f_config Filter configuration structure - * - * @note Macro initializers are available for the configuration structures (see documentation) - * - * @note To reinstall the CAN driver, call can_driver_uninstall() first - * - * @return - * - ESP_OK: Successfully installed CAN driver - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_NO_MEM: Insufficient memory - * - ESP_ERR_INVALID_STATE: Driver is already installed - */ -esp_err_t can_driver_install(const can_general_config_t *g_config, const can_timing_config_t *t_config, const can_filter_config_t *f_config); - -/** - * @brief Uninstall the CAN driver - * - * This function uninstalls the CAN driver, freeing the memory utilized by the - * driver. This function can only be called when the driver is in the stopped - * state or the bus-off state. - * - * @warning The application must ensure that no tasks are blocked on TX/RX - * queues or alerts when this function is called. - * - * @return - * - ESP_OK: Successfully uninstalled CAN driver - * - ESP_ERR_INVALID_STATE: Driver is not in stopped/bus-off state, or is not installed - */ -esp_err_t can_driver_uninstall(void); - -/** - * @brief Start the CAN driver - * - * This function starts the CAN driver, putting the CAN driver into the running - * state. This allows the CAN driver to participate in CAN bus activities such - * as transmitting/receiving messages. The RX queue is reset in this function, - * clearing any unread messages. This function can only be called when the CAN - * driver is in the stopped state. - * - * @return - * - ESP_OK: CAN driver is now running - * - ESP_ERR_INVALID_STATE: Driver is not in stopped state, or is not installed - */ -esp_err_t can_start(void); - -/** - * @brief Stop the CAN driver - * - * This function stops the CAN driver, preventing any further message from being - * transmitted or received until can_start() is called. Any messages in the TX - * queue are cleared. Any messages in the RX queue should be read by the - * application after this function is called. This function can only be called - * when the CAN driver is in the running state. - * - * @warning A message currently being transmitted/received on the CAN bus will - * be ceased immediately. This may lead to other CAN nodes interpreting - * the unfinished message as an error. - * - * @return - * - ESP_OK: CAN driver is now Stopped - * - ESP_ERR_INVALID_STATE: Driver is not in running state, or is not installed - */ -esp_err_t can_stop(void); - -/** - * @brief Transmit a CAN message - * - * This function queues a CAN message for transmission. Transmission will start - * immediately if no other messages are queued for transmission. If the TX queue - * is full, this function will block until more space becomes available or until - * it timesout. If the TX queue is disabled (TX queue length = 0 in configuration), - * this function will return immediately if another message is undergoing - * transmission. This function can only be called when the CAN driver is in the - * running state and cannot be called under Listen Only Mode. - * - * @param[in] message Message to transmit - * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on the TX queue - * - * @note This function does not guarantee that the transmission is successful. - * The TX_SUCCESS/TX_FAILED alert can be enabled to alert the application - * upon the success/failure of a transmission. - * - * @note The TX_IDLE alert can be used to alert the application when no other - * messages are awaiting transmission. - * - * @return - * - ESP_OK: Transmission successfully queued/initiated - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_TIMEOUT: Timed out waiting for space on TX queue - * - ESP_FAIL: TX queue is disabled and another message is currently transmitting - * - ESP_ERR_INVALID_STATE: CAN driver is not in running state, or is not installed - * - ESP_ERR_NOT_SUPPORTED: Listen Only Mode does not support transmissions - */ -esp_err_t can_transmit(const can_message_t *message, TickType_t ticks_to_wait); - -/** - * @brief Receive a CAN message - * - * This function receives a message from the RX queue. The flags field of the - * message structure will indicate the type of message received. This function - * will block if there are no messages in the RX queue - * - * @param[out] message Received message - * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on RX queue - * - * @warning The flags field of the received message should be checked to determine - * if the received message contains any data bytes. - * - * @return - * - ESP_OK: Message successfully received from RX queue - * - ESP_ERR_TIMEOUT: Timed out waiting for message - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_receive(can_message_t *message, TickType_t ticks_to_wait); - -/** - * @brief Read CAN driver alerts - * - * This function will read the alerts raised by the CAN driver. If no alert has - * been when this function is called, this function will block until an alert - * occurs or until it timeouts. - * - * @param[out] alerts Bit field of raised alerts (see documentation for alert flags) - * @param[in] ticks_to_wait Number of FreeRTOS ticks to block for alert - * - * @note Multiple alerts can be raised simultaneously. The application should - * check for all alerts that have been enabled. - * - * @return - * - ESP_OK: Alerts read - * - ESP_ERR_TIMEOUT: Timed out waiting for alerts - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_read_alerts(uint32_t *alerts, TickType_t ticks_to_wait); - -/** - * @brief Reconfigure which alerts are enabled - * - * This function reconfigures which alerts are enabled. If there are alerts - * which have not been read whilst reconfiguring, this function can read those - * alerts. - * - * @param[in] alerts_enabled Bit field of alerts to enable (see documentation for alert flags) - * @param[out] current_alerts Bit field of currently raised alerts. Set to NULL if unused - * - * @return - * - ESP_OK: Alerts reconfigured - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_reconfigure_alerts(uint32_t alerts_enabled, uint32_t *current_alerts); - -/** - * @brief Start the bus recovery process - * - * This function initiates the bus recovery process when the CAN driver is in - * the bus-off state. Once initiated, the CAN driver will enter the recovering - * state and wait for 128 occurrences of the bus-free signal on the CAN bus - * before returning to the stopped state. This function will reset the TX queue, - * clearing any messages pending transmission. - * - * @note The BUS_RECOVERED alert can be enabled to alert the application when - * the bus recovery process completes. - * - * @return - * - ESP_OK: Bus recovery started - * - ESP_ERR_INVALID_STATE: CAN driver is not in the bus-off state, or is not installed - */ -esp_err_t can_initiate_recovery(void); - -/** - * @brief Get current status information of the CAN driver - * - * @param[out] status_info Status information - * - * @return - * - ESP_OK: Status information retrieved - * - ESP_ERR_INVALID_ARG: Arguments are invalid - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_get_status_info(can_status_info_t *status_info); - -/** - * @brief Clear the transmit queue - * - * This function will clear the transmit queue of all messages. - * - * @note The transmit queue is automatically cleared when can_stop() or - * can_initiate_recovery() is called. - * - * @return - * - ESP_OK: Transmit queue cleared - * - ESP_ERR_INVALID_STATE: CAN driver is not installed or TX queue is disabled - */ -esp_err_t can_clear_transmit_queue(void); - -/** - * @brief Clear the receive queue - * - * This function will clear the receive queue of all messages. - * - * @note The receive queue is automatically cleared when can_start() is - * called. - * - * @return - * - ESP_OK: Transmit queue cleared - * - ESP_ERR_INVALID_STATE: CAN driver is not installed - */ -esp_err_t can_clear_receive_queue(void); +#define can_driver_install(g_config, t_config, f_config) twai_driver_install(g_config, t_config, f_config) +#define can_driver_uninstall() twai_driver_uninstall() +#define can_start() twai_start() +#define can_stop() twai_stop() +#define can_transmit(message, ticks_to_wait) twai_transmit(message, ticks_to_wait) +#define can_receive(message, ticks_to_wait) twai_receive(message, ticks_to_wait) +#define can_read_alerts(alerts, ticks_to_wait) twai_read_alerts(alerts, ticks_to_wait) +#define can_reconfigure_alerts(alerts_enabled, current_alerts) twai_reconfigure_alerts(alerts_enabled, current_alerts) +#define can_initiate_recovery() twai_initiate_recovery() +#define can_get_status_info(status_info) twai_get_status_info(status_info) +#define can_clear_transmit_queue() twai_clear_transmit_queue() +#define can_clear_receive_queue() twai_clear_receive_queue() #ifdef __cplusplus } -#endif +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/driver/include/driver/gpio.h b/tools/sdk/esp32s2/include/driver/include/driver/gpio.h index 270d738a..bc3c56cd 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/gpio.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/gpio.h @@ -22,6 +22,10 @@ #include "soc/gpio_periph.h" #include "hal/gpio_types.h" +// |================================= WARNING ====================================================== | +// | Including ROM header file in a PUBLIC API file will be REMOVED in the next major release (5.x). | +// | User should include "esp_rom_gpio.h" in their code if they have to use those ROM API. | +// |================================================================================================ | #if CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/gpio.h" #elif CONFIG_IDF_TARGET_ESP32S2 diff --git a/tools/sdk/esp32s2/include/driver/include/driver/i2c.h b/tools/sdk/esp32s2/include/driver/include/driver/i2c.h index 197bca29..8a1084c2 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/i2c.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/i2c.h @@ -225,7 +225,7 @@ esp_err_t i2c_master_write_byte(i2c_cmd_handle_t cmd_handle, uint8_t data, bool * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error */ -esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, uint8_t *data, size_t data_len, bool ack_en); +esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, const uint8_t *data, size_t data_len, bool ack_en); /** * @brief Queue command for I2C master to read one byte from I2C bus diff --git a/tools/sdk/esp32s2/include/driver/include/driver/periph_ctrl.h b/tools/sdk/esp32s2/include/driver/include/driver/periph_ctrl.h index b6147722..b6c6a9d7 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/periph_ctrl.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/periph_ctrl.h @@ -67,6 +67,29 @@ void periph_module_disable(periph_module_t periph); */ void periph_module_reset(periph_module_t periph); +/** + * @brief enable wifi bt common module + * + * @note If wifi_bt_common_module_enable is called a number of times, + * wifi_bt_common_module_disable has to be called the same number of times + * in order to put the peripheral into disabled state. + * + * @return NULL + * + */ +void wifi_bt_common_module_enable(void); + +/** + * @brief disable wifi bt common module + * + * @note If wifi_bt_common_module_enable is called a number of times, + * wifi_bt_common_module_disable has to be called the same number of times + * in order to put the peripheral into disabled state. + * + * @return NULL + * + */ +void wifi_bt_common_module_disable(void); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/driver/include/driver/spi_common.h b/tools/sdk/esp32s2/include/driver/include/driver/spi_common.h index 89160b9e..da12bb36 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/spi_common.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/spi_common.h @@ -62,11 +62,12 @@ extern "C" #define SPICOMMON_BUSFLAG_SLAVE 0 ///< Initialize I/O in slave mode #define SPICOMMON_BUSFLAG_MASTER (1<<0) ///< Initialize I/O in master mode #define SPICOMMON_BUSFLAG_IOMUX_PINS (1<<1) ///< Check using iomux pins. Or indicates the pins are configured through the IO mux rather than GPIO matrix. -#define SPICOMMON_BUSFLAG_SCLK (1<<2) ///< Check existing of SCLK pin. Or indicates CLK line initialized. -#define SPICOMMON_BUSFLAG_MISO (1<<3) ///< Check existing of MISO pin. Or indicates MISO line initialized. -#define SPICOMMON_BUSFLAG_MOSI (1<<4) ///< Check existing of MOSI pin. Or indicates CLK line initialized. -#define SPICOMMON_BUSFLAG_DUAL (1<<5) ///< Check MOSI and MISO pins can output. Or indicates bus able to work under DIO mode. -#define SPICOMMON_BUSFLAG_WPHD (1<<6) ///< Check existing of WP and HD pins. Or indicates WP & HD pins initialized. +#define SPICOMMON_BUSFLAG_GPIO_PINS (1<<2) ///< Force the signals to be routed through GPIO matrix. Or indicates the pins are routed through the GPIO matrix. +#define SPICOMMON_BUSFLAG_SCLK (1<<3) ///< Check existing of SCLK pin. Or indicates CLK line initialized. +#define SPICOMMON_BUSFLAG_MISO (1<<4) ///< Check existing of MISO pin. Or indicates MISO line initialized. +#define SPICOMMON_BUSFLAG_MOSI (1<<5) ///< Check existing of MOSI pin. Or indicates MOSI line initialized. +#define SPICOMMON_BUSFLAG_DUAL (1<<6) ///< Check MOSI and MISO pins can output. Or indicates bus able to work under DIO mode. +#define SPICOMMON_BUSFLAG_WPHD (1<<7) ///< Check existing of WP and HD pins. Or indicates WP & HD pins initialized. #define SPICOMMON_BUSFLAG_QUAD (SPICOMMON_BUSFLAG_DUAL|SPICOMMON_BUSFLAG_WPHD) ///< Check existing of MOSI/MISO/WP/HD pins as output. Or indicates bus able to work under QIO mode. #define SPICOMMON_BUSFLAG_NATIVE_PINS SPICOMMON_BUSFLAG_IOMUX_PINS diff --git a/tools/sdk/esp32s2/include/driver/include/driver/spi_slave_hd.h b/tools/sdk/esp32s2/include/driver/include/driver/spi_slave_hd.h new file mode 100644 index 00000000..f096f34c --- /dev/null +++ b/tools/sdk/esp32s2/include/driver/include/driver/spi_slave_hd.h @@ -0,0 +1,168 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_types.h" +#include "soc/spi_caps.h" +#include "freertos/FreeRTOS.h" + +#include "hal/spi_types.h" +#include "driver/spi_common.h" +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !SOC_SPI_SUPPORT_SLAVE_HD_VER2 && !CI_HEADER_CHECK +#error The SPI peripheral does not support this feature +#endif + +/// Descriptor of data to send/receive +typedef struct { + uint8_t* data; ///< Buffer to send, must be DMA capable + size_t len; ///< Len of data to send/receive. For receiving the buffer length should be multiples of 4 bytes, otherwise the extra part will be truncated. + size_t trans_len; ///< Data actually received + void* arg; ///< Extra argument indiciating this data +} spi_slave_hd_data_t; + +/// Information of SPI Slave HD event +typedef struct { + spi_event_t event; ///< Event type + spi_slave_hd_data_t* trans; ///< Corresponding transaction for SPI_EV_SEND and SPI_EV_RECV events +} spi_slave_hd_event_t; + +/// Callback for SPI Slave HD +typedef bool (*slave_cb_t)(void* arg, spi_slave_hd_event_t* event, BaseType_t* awoken); + +/// Channel of SPI Slave HD to do data transaction +typedef enum { + SPI_SLAVE_CHAN_TX = 0, ///< The output channel (RDDMA) + SPI_SLAVE_CHAN_RX = 1, ///< The input channel (WRDMA) +} spi_slave_chan_t; + +/// Callback configuration structure for SPI Slave HD +typedef struct { + slave_cb_t cb_recv; ///< Callback when receive data + slave_cb_t cb_sent; ///< Callback when data sent + slave_cb_t cb_buffer_tx; ///< Callback when master reads from shared buffer + slave_cb_t cb_buffer_rx; ///< Callback when master writes to shared buffer + slave_cb_t cb_cmd9; ///< Callback when CMD9 received + slave_cb_t cb_cmdA; ///< Callback when CMDA received + void* arg; ///< Argument indicating this SPI Slave HD peripheral instance +} spi_slave_hd_callback_config_t; + +/// Configuration structure for the SPI Slave HD driver +typedef struct { + int spics_io_num; ///< CS GPIO pin for this device + uint32_t flags; ///< Bitwise OR of SPI_SLAVE_HD_* flags +#define SPI_SLAVE_HD_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first +#define SPI_SLAVE_HD_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first +#define SPI_SLAVE_HD_BIT_LSBFIRST (SPI_SLAVE_HD_TXBIT_LSBFIRST|SPI_SLAVE_HD_RXBIT_LSBFIRST) ///< Transmit and receive LSB first + + uint8_t mode; ///< SPI mode (0-3) + int command_bits; ///< command field bits, multiples of 8 and at least 8. + int address_bits; ///< address field bits, multiples of 8 and at least 8. + int dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. + + int queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_hd_queue_trans but not yet finished using spi_slave_hd_get_trans_result) at the same time + + int dma_chan; ///< DMA channel used + spi_slave_hd_callback_config_t cb_config; ///< Callback configuration +} spi_slave_hd_slot_config_t; + +/** + * @brief Initialize the SPI Slave HD driver. + * + * @param host_id The host to use + * @param bus_config Bus configuration for the bus used + * @param config Configuration for the SPI Slave HD driver + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: invalid argument given + * - ESP_ERR_INVALID_STATE: function called in invalid state, may be some resources are already in use + * - ESP_ERR_NO_MEM: memory allocation failed + * - or other return value from `esp_intr_alloc` + */ +esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, + const spi_slave_hd_slot_config_t *config); + +/** + * @brief Deinitialize the SPI Slave HD driver + * + * @param host_id The host to deinitialize the driver + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: if the host_id is not correct + */ +esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id); + +/** + * @brief Queue data transaction + * + * @param host_id Host to queue the transaction + * @param chan Channel to queue the data, SPI_SLAVE_CHAN_TX or SPI_SLAVE_CHAN_RX + * @param trans Descriptor of data to queue + * @param timeout Timeout before the data is queued + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: The input argument is invalid. Can be the following reason: + * - The buffer given is not DMA capable + * - The length of data is invalid (not larger than 0, or exceed the max transfer length) + * - The function is invalid + * - ESP_ERR_TIMEOUT: Cannot queue the data before timeout. This is quite possible if the master + * doesn't read/write the slave on time. + */ +esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t* trans, TickType_t timeout); + +/** + * @brief Get the result of a data transaction + * + * @param host_id Host to queue the transaction + * @param chan Channel to get the result, SPI_SLAVE_CHAN_TX or SPI_SLAVE_CHAN_RX + * @param[out] out_trans Output descriptor of the returned transaction + * @param timeout Timeout before the result is got + * @return + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: Function is not valid + * - ESP_ERR_TIMEOUT: There's no transaction done before timeout + */ +esp_err_t spi_slave_hd_get_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t** out_trans, TickType_t timeout); + +/** + * @brief Read the shared registers + * + * @param host_id Host to read the shared registers + * @param addr Address of register to read, 0 to ``SOC_SPI_MAXIMUM_BUFFER_SIZE-1`` + * @param[out] out_data Output buffer to store the read data + * @param len Length to read, not larger than ``SOC_SPI_MAXIMUM_BUFFER_SIZE-addr`` + */ +void spi_slave_hd_read_buffer(spi_host_device_t host_id, int addr, uint8_t *out_data, size_t len); + +/** + * @brief Write the shared registers + * + * @param host_id Host to write the shared registers + * @param addr Address of register to write, 0 to ``SOC_SPI_MAXIMUM_BUFFER_SIZE-1`` + * @param data Buffer holding the data to write + * @param len Length to write, ``SOC_SPI_MAXIMUM_BUFFER_SIZE-addr`` + */ +void spi_slave_hd_write_buffer(spi_host_device_t host_id, int addr, uint8_t *data, size_t len); + + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/driver/include/driver/timer.h b/tools/sdk/esp32s2/include/driver/include/driver/timer.h index a4888fb0..1a4c074a 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/timer.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/timer.h @@ -27,7 +27,20 @@ extern "C" { #define TIMER_BASE_CLK (APB_CLK_FREQ) /*!< Frequency of the clock on the input of the timer groups */ -typedef void (*timer_isr_t)(void *); +/** + * @brief Interrupt handle callback function. User need to retrun a bool value + * in callback. + * + * @return + * - True Do task yield at the end of ISR + * - False Not do task yield at the end of ISR + * + * @note If you called FreeRTOS functions in callback, you need to return true or false based on + * the retrun value of argument `pxHigherPriorityTaskWoken`. + * For example, `xQueueSendFromISR` is called in callback, if the return value `pxHigherPriorityTaskWoken` + * of any FreeRTOS calls is pdTRUE, return true; otherwise return false. + */ +typedef bool (*timer_isr_t)(void *); /** * @brief Interrupt handle, used in order to free the isr after use. @@ -191,6 +204,9 @@ esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_ * If you want to realize some specific applications or write the whole ISR, you can * call timer_isr_register(...) to register ISR. * + * The callback should return a bool value to determine whether need to do YIELD at + * the end of the ISR. + * * If the intr_alloc_flags value ESP_INTR_FLAG_IRAM is set, * the handler function must be declared with IRAM_ATTR attribute * and can only call functions in IRAM or ROM. It cannot call other timer APIs. diff --git a/tools/sdk/esp32s2/include/driver/include/driver/twai.h b/tools/sdk/esp32s2/include/driver/include/driver/twai.h new file mode 100644 index 00000000..5313d953 --- /dev/null +++ b/tools/sdk/esp32s2/include/driver/include/driver/twai.h @@ -0,0 +1,347 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc/soc_caps.h" +#ifndef SOC_TWAI_SUPPORTED +#error TWAI is not supported in this chip target +#endif + +#include "freertos/FreeRTOS.h" +#include "esp_types.h" +#include "esp_intr_alloc.h" +#include "esp_err.h" +#include "gpio.h" +#include "soc/twai_caps.h" +#include "hal/twai_types.h" + +/* -------------------- Default initializers and flags ---------------------- */ +/** @cond */ //Doxy command to hide preprocessor definitions from docs +/** + * @brief Initializer macro for general configuration structure. + * + * This initializer macros allows the TX GPIO, RX GPIO, and operating mode to be + * configured. The other members of the general configuration structure are + * assigned default values. + */ +#define TWAI_GENERAL_CONFIG_DEFAULT(tx_io_num, rx_io_num, op_mode) {.mode = op_mode, .tx_io = tx_io_num, .rx_io = rx_io_num, \ + .clkout_io = TWAI_IO_UNUSED, .bus_off_io = TWAI_IO_UNUSED, \ + .tx_queue_len = 5, .rx_queue_len = 5, \ + .alerts_enabled = TWAI_ALERT_NONE, .clkout_divider = 0, } + +/** + * @brief Alert flags + * + * The following flags represents the various kind of alerts available in + * the TWAI driver. These flags can be used when configuring/reconfiguring + * alerts, or when calling twai_read_alerts(). + * + * @note The TWAI_ALERT_AND_LOG flag is not an actual alert, but will configure + * the TWAI driver to log to UART when an enabled alert occurs. + */ +#define TWAI_ALERT_TX_IDLE 0x0001 /**< Alert(1): No more messages to transmit */ +#define TWAI_ALERT_TX_SUCCESS 0x0002 /**< Alert(2): The previous transmission was successful */ +#define TWAI_ALERT_BELOW_ERR_WARN 0x0004 /**< Alert(4): Both error counters have dropped below error warning limit */ +#define TWAI_ALERT_ERR_ACTIVE 0x0008 /**< Alert(8): TWAI controller has become error active */ +#define TWAI_ALERT_RECOVERY_IN_PROGRESS 0x0010 /**< Alert(16): TWAI controller is undergoing bus recovery */ +#define TWAI_ALERT_BUS_RECOVERED 0x0020 /**< Alert(32): TWAI controller has successfully completed bus recovery */ +#define TWAI_ALERT_ARB_LOST 0x0040 /**< Alert(64): The previous transmission lost arbitration */ +#define TWAI_ALERT_ABOVE_ERR_WARN 0x0080 /**< Alert(128): One of the error counters have exceeded the error warning limit */ +#define TWAI_ALERT_BUS_ERROR 0x0100 /**< Alert(256): A (Bit, Stuff, CRC, Form, ACK) error has occurred on the bus */ +#define TWAI_ALERT_TX_FAILED 0x0200 /**< Alert(512): The previous transmission has failed (for single shot transmission) */ +#define TWAI_ALERT_RX_QUEUE_FULL 0x0400 /**< Alert(1024): The RX queue is full causing a frame to be lost */ +#define TWAI_ALERT_ERR_PASS 0x0800 /**< Alert(2048): TWAI controller has become error passive */ +#define TWAI_ALERT_BUS_OFF 0x1000 /**< Alert(4096): Bus-off condition occurred. TWAI controller can no longer influence bus */ +#define TWAI_ALERT_ALL 0x1FFF /**< Bit mask to enable all alerts during configuration */ +#define TWAI_ALERT_NONE 0x0000 /**< Bit mask to disable all alerts during configuration */ +#define TWAI_ALERT_AND_LOG 0x2000 /**< Bit mask to enable alerts to also be logged when they occur */ + +/** @endcond */ + +#define TWAI_IO_UNUSED ((gpio_num_t) -1) /**< Marks GPIO as unused in TWAI configuration */ + +/* ----------------------- Enum and Struct Definitions ---------------------- */ + +/** + * @brief TWAI driver states + */ +typedef enum { + TWAI_STATE_STOPPED, /**< Stopped state. The TWAI controller will not participate in any TWAI bus activities */ + TWAI_STATE_RUNNING, /**< Running state. The TWAI controller can transmit and receive messages */ + TWAI_STATE_BUS_OFF, /**< Bus-off state. The TWAI controller cannot participate in bus activities until it has recovered */ + TWAI_STATE_RECOVERING, /**< Recovering state. The TWAI controller is undergoing bus recovery */ +} twai_state_t; + +/** + * @brief Structure for general configuration of the TWAI driver + * + * @note Macro initializers are available for this structure + */ +typedef struct { + twai_mode_t mode; /**< Mode of TWAI controller */ + gpio_num_t tx_io; /**< Transmit GPIO number */ + gpio_num_t rx_io; /**< Receive GPIO number */ + gpio_num_t clkout_io; /**< CLKOUT GPIO number (optional, set to -1 if unused) */ + gpio_num_t bus_off_io; /**< Bus off indicator GPIO number (optional, set to -1 if unused) */ + uint32_t tx_queue_len; /**< Number of messages TX queue can hold (set to 0 to disable TX Queue) */ + uint32_t rx_queue_len; /**< Number of messages RX queue can hold */ + uint32_t alerts_enabled; /**< Bit field of alerts to enable (see documentation) */ + uint32_t clkout_divider; /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */ +} twai_general_config_t; + +/** + * @brief Structure to store status information of TWAI driver + */ +typedef struct { + twai_state_t state; /**< Current state of TWAI controller (Stopped/Running/Bus-Off/Recovery) */ + uint32_t msgs_to_tx; /**< Number of messages queued for transmission or awaiting transmission completion */ + uint32_t msgs_to_rx; /**< Number of messages in RX queue waiting to be read */ + uint32_t tx_error_counter; /**< Current value of Transmit Error Counter */ + uint32_t rx_error_counter; /**< Current value of Receive Error Counter */ + uint32_t tx_failed_count; /**< Number of messages that failed transmissions */ + uint32_t rx_missed_count; /**< Number of messages that were lost due to a full RX queue */ + uint32_t arb_lost_count; /**< Number of instances arbitration was lost */ + uint32_t bus_error_count; /**< Number of instances a bus error has occurred */ +} twai_status_info_t; + +/* ------------------------------ Public API -------------------------------- */ + +/** + * @brief Install TWAI driver + * + * This function installs the TWAI driver using three configuration structures. + * The required memory is allocated and the TWAI driver is placed in the stopped + * state after running this function. + * + * @param[in] g_config General configuration structure + * @param[in] t_config Timing configuration structure + * @param[in] f_config Filter configuration structure + * + * @note Macro initializers are available for the configuration structures (see documentation) + * + * @note To reinstall the TWAI driver, call twai_driver_uninstall() first + * + * @return + * - ESP_OK: Successfully installed TWAI driver + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_NO_MEM: Insufficient memory + * - ESP_ERR_INVALID_STATE: Driver is already installed + */ +esp_err_t twai_driver_install(const twai_general_config_t *g_config, const twai_timing_config_t *t_config, const twai_filter_config_t *f_config); + +/** + * @brief Uninstall the TWAI driver + * + * This function uninstalls the TWAI driver, freeing the memory utilized by the + * driver. This function can only be called when the driver is in the stopped + * state or the bus-off state. + * + * @warning The application must ensure that no tasks are blocked on TX/RX + * queues or alerts when this function is called. + * + * @return + * - ESP_OK: Successfully uninstalled TWAI driver + * - ESP_ERR_INVALID_STATE: Driver is not in stopped/bus-off state, or is not installed + */ +esp_err_t twai_driver_uninstall(void); + +/** + * @brief Start the TWAI driver + * + * This function starts the TWAI driver, putting the TWAI driver into the running + * state. This allows the TWAI driver to participate in TWAI bus activities such + * as transmitting/receiving messages. The RX queue is reset in this function, + * clearing any unread messages. This function can only be called when the TWAI + * driver is in the stopped state. + * + * @return + * - ESP_OK: TWAI driver is now running + * - ESP_ERR_INVALID_STATE: Driver is not in stopped state, or is not installed + */ +esp_err_t twai_start(void); + +/** + * @brief Stop the TWAI driver + * + * This function stops the TWAI driver, preventing any further message from being + * transmitted or received until twai_start() is called. Any messages in the TX + * queue are cleared. Any messages in the RX queue should be read by the + * application after this function is called. This function can only be called + * when the TWAI driver is in the running state. + * + * @warning A message currently being transmitted/received on the TWAI bus will + * be ceased immediately. This may lead to other TWAI nodes interpreting + * the unfinished message as an error. + * + * @return + * - ESP_OK: TWAI driver is now Stopped + * - ESP_ERR_INVALID_STATE: Driver is not in running state, or is not installed + */ +esp_err_t twai_stop(void); + +/** + * @brief Transmit a TWAI message + * + * This function queues a TWAI message for transmission. Transmission will start + * immediately if no other messages are queued for transmission. If the TX queue + * is full, this function will block until more space becomes available or until + * it times out. If the TX queue is disabled (TX queue length = 0 in configuration), + * this function will return immediately if another message is undergoing + * transmission. This function can only be called when the TWAI driver is in the + * running state and cannot be called under Listen Only Mode. + * + * @param[in] message Message to transmit + * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on the TX queue + * + * @note This function does not guarantee that the transmission is successful. + * The TX_SUCCESS/TX_FAILED alert can be enabled to alert the application + * upon the success/failure of a transmission. + * + * @note The TX_IDLE alert can be used to alert the application when no other + * messages are awaiting transmission. + * + * @return + * - ESP_OK: Transmission successfully queued/initiated + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_TIMEOUT: Timed out waiting for space on TX queue + * - ESP_FAIL: TX queue is disabled and another message is currently transmitting + * - ESP_ERR_INVALID_STATE: TWAI driver is not in running state, or is not installed + * - ESP_ERR_NOT_SUPPORTED: Listen Only Mode does not support transmissions + */ +esp_err_t twai_transmit(const twai_message_t *message, TickType_t ticks_to_wait); + +/** + * @brief Receive a TWAI message + * + * This function receives a message from the RX queue. The flags field of the + * message structure will indicate the type of message received. This function + * will block if there are no messages in the RX queue + * + * @param[out] message Received message + * @param[in] ticks_to_wait Number of FreeRTOS ticks to block on RX queue + * + * @warning The flags field of the received message should be checked to determine + * if the received message contains any data bytes. + * + * @return + * - ESP_OK: Message successfully received from RX queue + * - ESP_ERR_TIMEOUT: Timed out waiting for message + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_receive(twai_message_t *message, TickType_t ticks_to_wait); + +/** + * @brief Read TWAI driver alerts + * + * This function will read the alerts raised by the TWAI driver. If no alert has + * been issued when this function is called, this function will block until an alert + * occurs or until it timeouts. + * + * @param[out] alerts Bit field of raised alerts (see documentation for alert flags) + * @param[in] ticks_to_wait Number of FreeRTOS ticks to block for alert + * + * @note Multiple alerts can be raised simultaneously. The application should + * check for all alerts that have been enabled. + * + * @return + * - ESP_OK: Alerts read + * - ESP_ERR_TIMEOUT: Timed out waiting for alerts + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_read_alerts(uint32_t *alerts, TickType_t ticks_to_wait); + +/** + * @brief Reconfigure which alerts are enabled + * + * This function reconfigures which alerts are enabled. If there are alerts + * which have not been read whilst reconfiguring, this function can read those + * alerts. + * + * @param[in] alerts_enabled Bit field of alerts to enable (see documentation for alert flags) + * @param[out] current_alerts Bit field of currently raised alerts. Set to NULL if unused + * + * @return + * - ESP_OK: Alerts reconfigured + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_reconfigure_alerts(uint32_t alerts_enabled, uint32_t *current_alerts); + +/** + * @brief Start the bus recovery process + * + * This function initiates the bus recovery process when the TWAI driver is in + * the bus-off state. Once initiated, the TWAI driver will enter the recovering + * state and wait for 128 occurrences of the bus-free signal on the TWAI bus + * before returning to the stopped state. This function will reset the TX queue, + * clearing any messages pending transmission. + * + * @note The BUS_RECOVERED alert can be enabled to alert the application when + * the bus recovery process completes. + * + * @return + * - ESP_OK: Bus recovery started + * - ESP_ERR_INVALID_STATE: TWAI driver is not in the bus-off state, or is not installed + */ +esp_err_t twai_initiate_recovery(void); + +/** + * @brief Get current status information of the TWAI driver + * + * @param[out] status_info Status information + * + * @return + * - ESP_OK: Status information retrieved + * - ESP_ERR_INVALID_ARG: Arguments are invalid + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_get_status_info(twai_status_info_t *status_info); + +/** + * @brief Clear the transmit queue + * + * This function will clear the transmit queue of all messages. + * + * @note The transmit queue is automatically cleared when twai_stop() or + * twai_initiate_recovery() is called. + * + * @return + * - ESP_OK: Transmit queue cleared + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed or TX queue is disabled + */ +esp_err_t twai_clear_transmit_queue(void); + +/** + * @brief Clear the receive queue + * + * This function will clear the receive queue of all messages. + * + * @note The receive queue is automatically cleared when twai_start() is + * called. + * + * @return + * - ESP_OK: Transmit queue cleared + * - ESP_ERR_INVALID_STATE: TWAI driver is not installed + */ +esp_err_t twai_clear_receive_queue(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/driver/include/driver/uart.h b/tools/sdk/esp32s2/include/driver/include/driver/uart.h index ef750873..7be0fb02 100644 --- a/tools/sdk/esp32s2/include/driver/include/driver/uart.h +++ b/tools/sdk/esp32s2/include/driver/include/driver/uart.h @@ -514,7 +514,7 @@ int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len); * - (-1) Parameter error * - OTHERS (>=0) The number of bytes pushed to the TX FIFO */ -int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size); +int uart_write_bytes(uart_port_t uart_num, const void* src, size_t size); /** * @brief Send data to the UART port from a given buffer and length, @@ -536,7 +536,7 @@ int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size); * - (-1) Parameter error * - OTHERS (>=0) The number of bytes pushed to the TX FIFO */ -int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len); +int uart_write_bytes_with_break(uart_port_t uart_num, const void* src, size_t size, int brk_len); /** * @brief UART read bytes from UART buffer @@ -550,7 +550,7 @@ int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t si * - (-1) Error * - OTHERS (>=0) The number of bytes read from UART FIFO */ -int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait); +int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t ticks_to_wait); /** * @brief Alias of uart_flush_input. @@ -858,7 +858,6 @@ esp_err_t uart_set_loop_back(uart_port_t uart_num, bool loop_back_en); * @param always_rx_timeout_en Set to false enable the default behavior of timeout interrupt, * set it to true to always trigger timeout interrupt. * - * * @return None */ void uart_set_always_rx_timeout(uart_port_t uart_num, bool always_rx_timeout_en); diff --git a/tools/sdk/esp32s2/include/esp32s2/include/cp_dma.h b/tools/sdk/esp32s2/include/esp32s2/include/cp_dma.h new file mode 100644 index 00000000..e95959ec --- /dev/null +++ b/tools/sdk/esp32s2/include/esp32s2/include/cp_dma.h @@ -0,0 +1,126 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "esp_err.h" + +/** + * @brief Handle of CP_DMA driver + * + */ +typedef struct cp_dma_driver_context_s *cp_dma_driver_t; + +/** + * @brief CP_DMA event ID + * + */ +typedef enum { + CP_DMA_EVENT_M2M_DONE, /*!< One or more memory copy transactions are done */ +} cp_dma_event_id_t; + +/** + * @brief Type defined for CP_DMA event object (including event ID, event data) + * + */ +typedef struct { + cp_dma_event_id_t id; /*!< Event ID */ + void *data; /*!< Event data */ +} cp_dma_event_t; + +/** + * @brief Type defined for cp_dma ISR callback function + * + * @param drv_hdl Handle of CP_DMA driver + * @param event Event object, which contains the event ID, event data, and so on + * @param cb_args User defined arguments for the callback function. It's passed in cp_dma_memcpy function + * @return Whether a high priority task is woken up by the callback function + * + */ +typedef bool (*cp_dma_isr_cb_t)(cp_dma_driver_t drv_hdl, cp_dma_event_t *event, void *cb_args); + +/** + * @brief Type defined for configuration of CP_DMA driver + * + */ +typedef struct { + uint32_t max_out_stream; /*!< maximum number of out link streams that can work simultaneously */ + uint32_t max_in_stream; /*!< maximum number of in link streams that can work simultaneously */ + uint32_t flags; /*!< Extra flags to control some special behaviour of CP_DMA, OR'ed of CP_DMA_FLAGS_xxx macros */ +} cp_dma_config_t; + +#define CP_DMA_FLAGS_WORK_WITH_CACHE_DISABLED (1 << 0) /*!< CP_DMA can work even when cache is diabled */ + +/** + * @brief Default configuration for CP_DMA driver + * + */ +#define CP_DMA_DEFAULT_CONFIG() \ + { \ + .max_out_stream = 8, \ + .max_in_stream = 8, \ + .flags = 0, \ + } + +/** + * @brief Install CP_DMA driver + * + * @param[in] config Configuration of CP_DMA driver + * @param[out] drv_hdl Returned handle of CP_DMA driver or NULL if driver installation failed + * @return + * - ESP_OK: Install CP_DMA driver successfully + * - ESP_ERR_INVALID_ARG: Install CP_DMA driver failed because of some invalid argument + * - ESP_ERR_NO_MEM: Install CP_DMA driver failed because there's no enough capable memory + * - ESP_FAIL: Install CP_DMA driver failed because of other error + */ +esp_err_t cp_dma_driver_install(const cp_dma_config_t *config, cp_dma_driver_t *drv_hdl); + +/** + * @brief Uninstall CP_DMA driver + * + * @param[in] drv_hdl Handle of CP_DMA driver that returned from cp_dma_driver_install + * @return + * - ESP_OK: Uninstall CP_DMA driver successfully + * - ESP_ERR_INVALID_ARG: Uninstall CP_DMA driver failed because of some invalid argument + * - ESP_FAIL: Uninstall CP_DMA driver failed because of other error + */ +esp_err_t cp_dma_driver_uninstall(cp_dma_driver_t drv_hdl); + +/** + * @brief Send an asynchronous memory copy request + * + * @param[in] drv_hdl Handle of CP_DMA driver that returned from cp_dma_driver_install + * @param[in] dst Destination address (copy to) + * @param[in] src Source address (copy from) + * @param[in] n Number of bytes to copy + * @param[in] cb_isr Callback function, which got invoked in ISR context. A NULL pointer here can bypass the callback. + * @param[in] cb_args User defined argument to be passed to the callback function + * @return + * - ESP_OK: Send memcopy request successfully + * - ESP_ERR_INVALID_ARG: Send memcopy request failed because of some invalid argument + * - ESP_FAIL: Send memcopy request failed because of other error + * + * @note The callback function is invoked in ISR context, please never handle heavy load in the callback. + * The default ISR handler is placed in IRAM, please place callback function in IRAM as well by applying IRAM_ATTR to it. + */ +esp_err_t cp_dma_memcpy(cp_dma_driver_t drv_hdl, void *dst, void *src, size_t n, cp_dma_isr_cb_t cb_isr, void *cb_args); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/rtc.h b/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/rtc.h new file mode 100644 index 00000000..296292e2 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp32s2/include/esp32s2/rtc.h @@ -0,0 +1,39 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file esp32s2/rtc.h + * + * This file contains declarations of rtc related functions. + */ + +/** + * @brief Get current value of RTC counter in microseconds + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter in microseconds + */ +uint64_t esp_rtc_get_time_us(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp32s2/include/esp_spiram.h b/tools/sdk/esp32s2/include/esp32s2/include/esp_spiram.h index 414cc310..16212e54 100644 --- a/tools/sdk/esp32s2/include/esp32s2/include/esp_spiram.h +++ b/tools/sdk/esp32s2/include/esp32s2/include/esp_spiram.h @@ -78,18 +78,6 @@ size_t esp_spiram_get_size(void); void esp_spiram_writeback_cache(void); - -/** - * @brief Reserve a pool of internal memory for specific DMA/internal allocations - * - * @param size Size of reserved pool in bytes - * - * @return - * - ESP_OK on success - * - ESP_ERR_NO_MEM when no memory available for pool - */ -esp_err_t esp_spiram_reserve_dma_pool(size_t size); - #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_adc_cal/include/esp_adc_cal.h b/tools/sdk/esp32s2/include/esp_adc_cal/include/esp_adc_cal.h new file mode 100644 index 00000000..7d8f1278 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_adc_cal/include/esp_adc_cal.h @@ -0,0 +1,138 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef __ESP_ADC_CAL_H__ +#define __ESP_ADC_CAL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "esp_err.h" +#include "driver/adc.h" + +/** + * @brief Type of calibration value used in characterization + */ +typedef enum { + ESP_ADC_CAL_VAL_EFUSE_VREF = 0, /**< Characterization based on reference voltage stored in eFuse*/ + ESP_ADC_CAL_VAL_EFUSE_TP = 1, /**< Characterization based on Two Point values stored in eFuse*/ + ESP_ADC_CAL_VAL_DEFAULT_VREF = 2, /**< Characterization based on default reference voltage*/ + ESP_ADC_CAL_VAL_MAX +} esp_adc_cal_value_t; + +/** + * @brief Structure storing characteristics of an ADC + * + * @note Call esp_adc_cal_characterize() to initialize the structure + */ +typedef struct { + adc_unit_t adc_num; /**< ADC number*/ + adc_atten_t atten; /**< ADC attenuation*/ + adc_bits_width_t bit_width; /**< ADC bit width */ + uint32_t coeff_a; /**< Gradient of ADC-Voltage curve*/ + uint32_t coeff_b; /**< Offset of ADC-Voltage curve*/ + uint32_t vref; /**< Vref used by lookup table*/ + const uint32_t *low_curve; /**< Pointer to low Vref curve of lookup table (NULL if unused)*/ + const uint32_t *high_curve; /**< Pointer to high Vref curve of lookup table (NULL if unused)*/ +} esp_adc_cal_characteristics_t; + +/** + * @brief Checks if ADC calibration values are burned into eFuse + * + * This function checks if ADC reference voltage or Two Point values have been + * burned to the eFuse of the current ESP32 + * + * @param value_type Type of calibration value (ESP_ADC_CAL_VAL_EFUSE_VREF or ESP_ADC_CAL_VAL_EFUSE_TP) + * + * @return + * - ESP_OK: The calibration mode is supported in eFuse + * - ESP_ERR_NOT_SUPPORTED: Error, eFuse values are not burned + * - ESP_ERR_INVALID_ARG: Error, invalid argument (ESP_ADC_CAL_VAL_DEFAULT_VREF) + */ +esp_err_t esp_adc_cal_check_efuse(esp_adc_cal_value_t value_type); + +/** + * @brief Characterize an ADC at a particular attenuation + * + * This function will characterize the ADC at a particular attenuation and generate + * the ADC-Voltage curve in the form of [y = coeff_a * x + coeff_b]. + * Characterization can be based on Two Point values, eFuse Vref, or default Vref + * and the calibration values will be prioritized in that order. + * + * @note + * For ESP32, Two Point values and eFuse Vref calibration can be enabled/disabled using menuconfig. + * For ESP32s2, only Two Point values calibration and only ADC_WIDTH_BIT_13 is supported. The parameter default_vref is unused. + * + * + * @param[in] adc_num ADC to characterize (ADC_UNIT_1 or ADC_UNIT_2) + * @param[in] atten Attenuation to characterize + * @param[in] bit_width Bit width configuration of ADC + * @param[in] default_vref Default ADC reference voltage in mV (Only in ESP32, used if eFuse values is not available) + * @param[out] chars Pointer to empty structure used to store ADC characteristics + * + * @return + * - ESP_ADC_CAL_VAL_EFUSE_VREF: eFuse Vref used for characterization + * - ESP_ADC_CAL_VAL_EFUSE_TP: Two Point value used for characterization (only in Linear Mode) + * - ESP_ADC_CAL_VAL_DEFAULT_VREF: Default Vref used for characterization + */ +esp_adc_cal_value_t esp_adc_cal_characterize(adc_unit_t adc_num, + adc_atten_t atten, + adc_bits_width_t bit_width, + uint32_t default_vref, + esp_adc_cal_characteristics_t *chars); + +/** + * @brief Convert an ADC reading to voltage in mV + * + * This function converts an ADC reading to a voltage in mV based on the ADC's + * characteristics. + * + * @note Characteristics structure must be initialized before this function + * is called (call esp_adc_cal_characterize()) + * + * @param[in] adc_reading ADC reading + * @param[in] chars Pointer to initialized structure containing ADC characteristics + * + * @return Voltage in mV + */ +uint32_t esp_adc_cal_raw_to_voltage(uint32_t adc_reading, const esp_adc_cal_characteristics_t *chars); + +/** + * @brief Reads an ADC and converts the reading to a voltage in mV + * + * This function reads an ADC then converts the raw reading to a voltage in mV + * based on the characteristics provided. The ADC that is read is also + * determined by the characteristics. + * + * @note The Characteristics structure must be initialized before this + * function is called (call esp_adc_cal_characterize()) + * + * @param[in] channel ADC Channel to read + * @param[in] chars Pointer to initialized ADC characteristics structure + * @param[out] voltage Pointer to store converted voltage + * + * @return + * - ESP_OK: ADC read and converted to mV + * - ESP_ERR_TIMEOUT: Error, timed out attempting to read ADC + * - ESP_ERR_INVALID_ARG: Error due to invalid arguments + */ +esp_err_t esp_adc_cal_get_voltage(adc_channel_t channel, const esp_adc_cal_characteristics_t *chars, uint32_t *voltage); + +#ifdef __cplusplus +} +#endif + +#endif /* __ESP_ADC_CAL_H__ */ diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_crc.h b/tools/sdk/esp32s2/include/esp_common/include/esp_crc.h index cc14c6ac..6294a7b6 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_crc.h +++ b/tools/sdk/esp32s2/include/esp_common/include/esp_crc.h @@ -18,21 +18,9 @@ extern "C" { #endif #include -#include "sdkconfig.h" -#if defined(CONFIG_IDF_TARGET_ESP32) -#include "esp32/rom/crc.h" -#endif - -#if defined(CONFIG_IDF_TARGET_ESP32S2) -#include "esp32s2/rom/crc.h" -#endif - -/******************* Polynomials Used in the CRC APIs **************************** -* CRC-8 x8+x2+x1+1 0x07 -* CRC16-CCITT x16+x12+x5+1 0x1021 -* CRC32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1 0x04c11db7 -********************************************************************************/ +// This header is only a wrapper on ROM CRC API +#include "esp_rom_crc.h" /** * @brief CRC32 value in little endian. @@ -44,10 +32,9 @@ extern "C" { */ static inline uint32_t esp_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len) { - return crc32_le(crc, buf, len); + return esp_rom_crc32_le(crc, buf, len); } -#if defined(CONFIG_IDF_TARGET_ESP32) /** * @brief CRC32 value in big endian. * @@ -58,9 +45,8 @@ static inline uint32_t esp_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t l */ static inline uint32_t esp_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len) { - return crc32_be(crc, buf, len); + return esp_rom_crc32_be(crc, buf, len); } -#endif /** * @brief CRC16 value in little endian. @@ -72,10 +58,9 @@ static inline uint32_t esp_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t l */ static inline uint16_t esp_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len) { - return crc16_le(crc, buf, len); + return esp_rom_crc16_le(crc, buf, len); } -#if defined(CONFIG_IDF_TARGET_ESP32) /** * @brief CRC16 value in big endian. * @@ -86,9 +71,8 @@ static inline uint16_t esp_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t l */ static inline uint16_t esp_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len) { - return crc16_be(crc, buf, len); + return esp_rom_crc16_be(crc, buf, len); } -#endif /** * @brief CRC8 value in little endian. @@ -100,10 +84,9 @@ static inline uint16_t esp_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t l */ static inline uint8_t esp_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len) { - return crc8_le(crc, buf, len); + return esp_rom_crc8_le(crc, buf, len); } -#if defined(CONFIG_IDF_TARGET_ESP32) /** * @brief CRC8 value in big endian. * @@ -114,9 +97,8 @@ static inline uint8_t esp_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len) */ static inline uint8_t esp_crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len) { - return crc8_be(crc, buf, len); + return esp_rom_crc8_be(crc, buf, len); } -#endif #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_expression_with_stack.h b/tools/sdk/esp32s2/include/esp_common/include/esp_expression_with_stack.h index 3c94f9d3..096b4575 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_expression_with_stack.h +++ b/tools/sdk/esp32s2/include/esp_common/include/esp_expression_with_stack.h @@ -13,6 +13,7 @@ // limitations under the License. #pragma once +#include #include "freertos/FreeRTOS.h" #include "freertos/semphr.h" #include "freertos/task.h" @@ -23,56 +24,25 @@ extern "C" { #endif +typedef void (*shared_stack_function)(void); + +#define ESP_EXECUTE_EXPRESSION_WITH_STACK(lock, stack, stack_size, expression) \ + esp_execute_shared_stack_function(lock, stack, stack_size, expression) + /** - * @brief Executes a 1-line expression with a application alocated stack + * @brief Calls user defined shared stack space function * @param lock Mutex object to protect in case of shared stack * @param stack Pointer to user alocated stack * @param stack_size Size of current stack in bytes - * @param expression Expression or function to be executed using the stack + * @param function pointer to the shared stack function to be executed * @note if either lock, stack or stack size is invalid, the expression will * be called using the current stack. */ -#define ESP_EXECUTE_EXPRESSION_WITH_STACK(lock, stack, stack_size, expression) \ -({ \ - assert(lock && stack && (stack_size >= CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE)); \ - uint32_t backup; \ - xSemaphoreTake(lock, portMAX_DELAY); \ - StackType_t *top_of_stack = esp_switch_stack_setup(stack, stack_size); \ - esp_switch_stack_enter(top_of_stack, &backup); \ - { \ - expression; \ - } \ - esp_switch_stack_exit(&backup); \ - StaticTask_t *current = (StaticTask_t *)xTaskGetCurrentTaskHandle(); \ - /* pxDummy6 is the stack base of current thread defined in TCB_t */ \ - /* place the watchpoint on current task stack after function execution*/ \ - vPortSetStackWatchpoint(current->pxDummy6); \ - xSemaphoreGive(lock); \ -}) +void esp_execute_shared_stack_function(SemaphoreHandle_t lock, + void *stack, + size_t stack_size, + shared_stack_function function); -/** - * @brief Fill stack frame with CPU-specifics value before use - * @param stack Caller allocated stack pointer - * @param stack_size Size of stack in bytes - * @return New pointer to the top of stack - * @note Application must not call this function directly - */ -StackType_t * esp_switch_stack_setup(StackType_t *stack, size_t stack_size); - -/** - * @brief Changes CPU sp-register to use another stack space and save the previous one - * @param stack Caller allocated stack pointer - * @param backup_stack Pointer to a place to save the current stack - * @note Application must not call this function directly - */ -extern void esp_switch_stack_enter(StackType_t *stack, uint32_t *backup_stack); - -/** - * @brief Restores the previous CPU sp-register - * @param backup_stack Pointer to the place where stack was saved - * @note Application must not call this function directly - */ -extern void esp_switch_stack_exit(uint32_t *backup_stack); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_fault.h b/tools/sdk/esp32s2/include/esp_common/include/esp_fault.h index 0eb7ebb6..4ccb259c 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_fault.h +++ b/tools/sdk/esp32s2/include/esp_common/include/esp_fault.h @@ -13,6 +13,7 @@ // limitations under the License. #include "sdkconfig.h" #include "soc/rtc_cntl_reg.h" +#include "esp_rom_sys.h" #pragma once @@ -81,9 +82,9 @@ extern "C" { #warning "Enabling ESP_FAULT_ASSERT_DEBUG makes ESP_FAULT_ASSERT() less effective" -#define _ESP_FAULT_RESET() do { \ - ets_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \ - asm volatile("ill;"); \ +#define _ESP_FAULT_RESET() do { \ + esp_rom_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \ + asm volatile("ill;"); \ } while(0) #endif // ESP_FAULT_ASSERT_DEBUG diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_idf_version.h b/tools/sdk/esp32s2/include/esp_common/include/esp_idf_version.h index cb9a8b45..bf910010 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_idf_version.h +++ b/tools/sdk/esp32s2/include/esp_common/include/esp_idf_version.h @@ -21,7 +21,7 @@ extern "C" { /** Major version number (X.x.x) */ #define ESP_IDF_VERSION_MAJOR 4 /** Minor version number (x.X.x) */ -#define ESP_IDF_VERSION_MINOR 2 +#define ESP_IDF_VERSION_MINOR 3 /** Patch version number (x.x.X) */ #define ESP_IDF_VERSION_PATCH 0 diff --git a/tools/sdk/esp32s2/include/esp_common/include/esp_private/system_internal.h b/tools/sdk/esp32s2/include/esp_common/include/esp_private/system_internal.h index 9b383cd6..4f5c90e8 100644 --- a/tools/sdk/esp32s2/include/esp_common/include/esp_private/system_internal.h +++ b/tools/sdk/esp32s2/include/esp_common/include/esp_private/system_internal.h @@ -61,6 +61,21 @@ void esp_reset_reason_set_hint(esp_reset_reason_t hint); */ esp_reset_reason_t esp_reset_reason_get_hint(void); + +/** + * @brief Get the time in microseconds since startup + * + * @returns time since startup in microseconds + */ +int64_t esp_system_get_time(void); + +/** + * @brief Get the resolution of the time returned by `esp_system_get_time`. + * + * @returns the resolution in microseconds + */ +uint32_t esp_system_get_time_resolution(void); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_phy.h b/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_phy.h index 4aedff11..b3aa39b4 100644 --- a/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_phy.h +++ b/tools/sdk/esp32s2/include/esp_eth/include/esp_eth_phy.h @@ -240,6 +240,17 @@ esp_eth_phy_t *esp_eth_phy_new_lan8720(const eth_phy_config_t *config); */ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config); +/** +* @brief Create a PHY instance of KSZ8041 +* +* @param[in] config: configuration of PHY +* +* @return +* - instance: create PHY instance successfully +* - NULL: create PHY instance failed because some error occurred +*/ +esp_eth_phy_t *esp_eth_phy_new_ksz8041(const eth_phy_config_t *config); + #if CONFIG_ETH_SPI_ETHERNET_DM9051 /** * @brief Create a PHY instance of DM9051 @@ -252,6 +263,7 @@ esp_eth_phy_t *esp_eth_phy_new_dp83848(const eth_phy_config_t *config); */ esp_eth_phy_t *esp_eth_phy_new_dm9051(const eth_phy_config_t *config); #endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_event/include/esp_event_legacy.h b/tools/sdk/esp32s2/include/esp_event/include/esp_event_legacy.h index 00d402c4..ba74ec77 100644 --- a/tools/sdk/esp32s2/include/esp_event/include/esp_event_legacy.h +++ b/tools/sdk/esp32s2/include/esp_event/include/esp_event_legacy.h @@ -80,6 +80,9 @@ typedef wifi_event_sta_authmode_change_t system_event_sta_authmode_change_t; /** Argument structure of SYSTEM_EVENT_STA_WPS_ER_PIN event */ typedef wifi_event_sta_wps_er_pin_t system_event_sta_wps_er_pin_t; +/** Argument structure of SYSTEM_EVENT_STA_WPS_ER_PIN event */ +typedef wifi_event_sta_wps_er_success_t system_event_sta_wps_er_success_t; + /** Argument structure of event */ typedef wifi_event_ap_staconnected_t system_event_ap_staconnected_t; @@ -107,6 +110,7 @@ typedef union { system_event_sta_got_ip_t got_ip; /*!< ESP32 station got IP, first time got IP or when IP is changed */ system_event_sta_wps_er_pin_t sta_er_pin; /*!< ESP32 station WPS enrollee mode PIN code received */ system_event_sta_wps_fail_reason_t sta_er_fail_reason; /*!< ESP32 station WPS enrollee mode failed reason code received */ + system_event_sta_wps_er_success_t sta_er_success; /*!< ESP32 station WPS enrollee success */ system_event_ap_staconnected_t sta_connected; /*!< a station connected to ESP32 soft-AP */ system_event_ap_stadisconnected_t sta_disconnected; /*!< a station disconnected to ESP32 soft-AP */ system_event_ap_probe_req_rx_t ap_probereqrecved; /*!< ESP32 soft-AP receive probe request packet */ diff --git a/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h b/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h index 15c64dcc..3ad04b49 100644 --- a/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h +++ b/tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h @@ -83,6 +83,13 @@ typedef enum { HTTP_METHOD_SUBSCRIBE, /*!< HTTP SUBSCRIBE Method */ HTTP_METHOD_UNSUBSCRIBE,/*!< HTTP UNSUBSCRIBE Method */ HTTP_METHOD_OPTIONS, /*!< HTTP OPTIONS Method */ + HTTP_METHOD_COPY, /*!< HTTP COPY Method */ + HTTP_METHOD_MOVE, /*!< HTTP MOVE Method */ + HTTP_METHOD_LOCK, /*!< HTTP LOCK Method */ + HTTP_METHOD_UNLOCK, /*!< HTTP UNLOCK Method */ + HTTP_METHOD_PROPFIND, /*!< HTTP PROPFIND Method */ + HTTP_METHOD_PROPPATCH, /*!< HTTP PROPPATCH Method */ + HTTP_METHOD_MKCOL, /*!< HTTP MKCOL Method */ HTTP_METHOD_MAX, } esp_http_client_method_t; @@ -113,7 +120,8 @@ typedef struct { esp_http_client_method_t method; /*!< HTTP Method */ int timeout_ms; /*!< Network timeout in milliseconds */ bool disable_auto_redirect; /*!< Disable HTTP automatic redirects */ - int max_redirection_count; /*!< Max redirection number, using default value if zero*/ + int max_redirection_count; /*!< Max number of redirections on receiving HTTP redirect status code, using default value if zero*/ + int max_authorization_retries; /*!< Max connection retries on receiving HTTP unauthorized status code, using default value if zero. Disables authorization retry if -1*/ http_event_handle_cb event_handler; /*!< HTTP Event Handle */ esp_http_client_transport_t transport_type; /*!< HTTP transport type, see `esp_http_client_transport_t` */ int buffer_size; /*!< HTTP receive buffer size */ @@ -134,7 +142,12 @@ typedef enum { HttpStatus_TemporaryRedirect = 307, /* 4xx - Client Error */ - HttpStatus_Unauthorized = 401 + HttpStatus_Unauthorized = 401, + HttpStatus_Forbidden = 403, + HttpStatus_NotFound = 404, + + /* 5xx - Server Error */ + HttpStatus_InternalError = 500 } HttpStatus_Code; #define ESP_ERR_HTTP_BASE (0x7000) /*!< Starting number of HTTP error codes */ diff --git a/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h b/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h index e1e5c288..0d936de8 100644 --- a/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h +++ b/tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h @@ -1047,7 +1047,7 @@ esp_err_t httpd_resp_send_chunk(httpd_req_t *r, const char *buf, ssize_t buf_len * - ESP_ERR_HTTPD_INVALID_REQ : Invalid request */ static inline esp_err_t httpd_resp_sendstr(httpd_req_t *r, const char *str) { - return httpd_resp_send(r, str, (str == NULL) ? 0 : strlen(str)); + return httpd_resp_send(r, str, (str == NULL) ? 0 : HTTPD_RESP_USE_STRLEN); } /** @@ -1068,7 +1068,7 @@ static inline esp_err_t httpd_resp_sendstr(httpd_req_t *r, const char *str) { * - ESP_ERR_HTTPD_INVALID_REQ : Invalid request */ static inline esp_err_t httpd_resp_sendstr_chunk(httpd_req_t *r, const char *str) { - return httpd_resp_send_chunk(r, str, (str == NULL) ? 0 : strlen(str)); + return httpd_resp_send_chunk(r, str, (str == NULL) ? 0 : HTTPD_RESP_USE_STRLEN); } /* Some commonly used status codes */ @@ -1292,6 +1292,53 @@ static inline esp_err_t httpd_resp_send_500(httpd_req_t *r) { */ int httpd_send(httpd_req_t *r, const char *buf, size_t buf_len); +/** + * A low level API to send data on a given socket + * + * @note This API is not recommended to be used in any request handler. + * Use this only for advanced use cases, wherein some asynchronous + * data is to be sent over a socket. + * + * This internally calls the default send function, or the function registered by + * httpd_sess_set_send_override(). + * + * @param[in] hd server instance + * @param[in] sockfd session socket file descriptor + * @param[in] buf buffer with bytes to send + * @param[in] buf_len data size + * @param[in] flags flags for the send() function + * @return + * - Bytes : The number of bytes sent successfully + * - HTTPD_SOCK_ERR_INVALID : Invalid arguments + * - HTTPD_SOCK_ERR_TIMEOUT : Timeout/interrupted while calling socket send() + * - HTTPD_SOCK_ERR_FAIL : Unrecoverable error while calling socket send() + */ +int httpd_socket_send(httpd_handle_t hd, int sockfd, const char *buf, size_t buf_len, int flags); + +/** + * A low level API to receive data from a given socket + * + * @note This API is not recommended to be used in any request handler. + * Use this only for advanced use cases, wherein some asynchronous + * communication is required. + * + * This internally calls the default recv function, or the function registered by + * httpd_sess_set_recv_override(). + * + * @param[in] hd server instance + * @param[in] sockfd session socket file descriptor + * @param[in] buf buffer with bytes to send + * @param[in] buf_len data size + * @param[in] flags flags for the send() function + * @return + * - Bytes : The number of bytes received successfully + * - 0 : Buffer length parameter is zero / connection closed by peer + * - HTTPD_SOCK_ERR_INVALID : Invalid arguments + * - HTTPD_SOCK_ERR_TIMEOUT : Timeout/interrupted while calling socket recv() + * - HTTPD_SOCK_ERR_FAIL : Unrecoverable error while calling socket recv() + */ +int httpd_socket_recv(httpd_handle_t hd, int sockfd, char *buf, size_t buf_len, int flags); + /** End of Request / Response * @} */ @@ -1483,7 +1530,15 @@ typedef enum { * @brief WebSocket frame format */ typedef struct httpd_ws_frame { - bool final; /*!< Final frame */ + bool final; /*!< Final frame: + For received frames this field indicates whether the `FIN` flag was set. + For frames to be transmitted, this field is only used if the `fragmented` + option is set as well. If `fragmented` is false, the `FIN` flag is set + by default, marking the ws_frame as a complete/unfragmented message + (esp_http_server doesn't automatically fragment messages) */ + bool fragmented; /*!< Indication that the frame allocated for transmission is a message fragment, + so the `FIN` flag is set manually according to the `final` option. + This flag is never set for received messages */ httpd_ws_type_t type; /*!< WebSocket frame type */ uint8_t *payload; /*!< Pre-allocated data buffer */ size_t len; /*!< Length of the WebSocket data */ diff --git a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h index a8df60e6..5cb6e802 100644 --- a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h +++ b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif.h @@ -815,6 +815,22 @@ esp_netif_t *esp_netif_next(esp_netif_t *esp_netif); */ size_t esp_netif_get_nr_of_ifs(void); +/** + * @brief increase the reference counter of net stack buffer + * + * @param[in] netstack_buf the net stack buffer + * + */ +void esp_netif_netstack_buf_ref(void *netstack_buf); + +/** + * @brief free the netstack buffer + * + * @param[in] netstack_buf the net stack buffer + * + */ +void esp_netif_netstack_buf_free(void *netstack_buf); + /** * @} */ diff --git a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_defaults.h b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_defaults.h index 3c41d9c2..f61d7294 100644 --- a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_defaults.h +++ b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_defaults.h @@ -70,7 +70,19 @@ extern "C" { .lost_ip_event = IP_EVENT_PPP_LOST_IP, \ .if_key = "PPP_DEF", \ .if_desc = "ppp", \ - .route_prio = 128 \ + .route_prio = 20 \ +}; + +#define ESP_NETIF_INHERENT_DEFAULT_SLIP() \ + { \ + .flags = ESP_NETIF_FLAG_IS_SLIP, \ + ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(mac) \ + ESP_COMPILER_DESIGNATED_INIT_AGGREGATE_TYPE_EMPTY(ip_info) \ + .get_ip_event = 0, \ + .lost_ip_event = 0, \ + .if_key = "SLP_DEF", \ + .if_desc = "slip", \ + .route_prio = 16 \ }; /** @@ -112,6 +124,18 @@ extern "C" { .driver = NULL, \ .stack = ESP_NETIF_NETSTACK_DEFAULT_PPP, \ } + +/** +* @brief Default configuration reference of SLIP client +*/ +#define ESP_NETIF_DEFAULT_SLIP() \ + { \ + .base = ESP_NETIF_BASE_DEFAULT_SLIP, \ + .driver = NULL, \ + .stack = ESP_NETIF_NETSTACK_DEFAULT_SLIP, \ + } + + /** * @brief Default base config (esp-netif inherent) of WIFI STA */ @@ -132,11 +156,18 @@ extern "C" { */ #define ESP_NETIF_BASE_DEFAULT_PPP &_g_esp_netif_inherent_ppp_config +/** + * @brief Default base config (esp-netif inherent) of slip interface + */ +#define ESP_NETIF_BASE_DEFAULT_SLIP &_g_esp_netif_inherent_slip_config + + #define ESP_NETIF_NETSTACK_DEFAULT_ETH _g_esp_netif_netstack_default_eth #define ESP_NETIF_NETSTACK_DEFAULT_WIFI_STA _g_esp_netif_netstack_default_wifi_sta #define ESP_NETIF_NETSTACK_DEFAULT_WIFI_AP _g_esp_netif_netstack_default_wifi_ap #define ESP_NETIF_NETSTACK_DEFAULT_PPP _g_esp_netif_netstack_default_ppp +#define ESP_NETIF_NETSTACK_DEFAULT_SLIP _g_esp_netif_netstack_default_slip // // Include default network stacks configs @@ -148,6 +179,7 @@ extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_eth; extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_wifi_sta; extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_wifi_ap; extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_ppp; +extern const esp_netif_netstack_config_t *_g_esp_netif_netstack_default_slip; // // Include default common configs inherent to esp-netif @@ -158,6 +190,7 @@ extern const esp_netif_inherent_config_t _g_esp_netif_inherent_sta_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_ap_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_eth_config; extern const esp_netif_inherent_config_t _g_esp_netif_inherent_ppp_config; +extern const esp_netif_inherent_config_t _g_esp_netif_inherent_slip_config; extern const esp_netif_ip_info_t _g_esp_netif_soft_ap_ip; diff --git a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_net_stack.h b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_net_stack.h index c38297a9..ab6d6a07 100644 --- a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_net_stack.h +++ b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_net_stack.h @@ -69,6 +69,20 @@ void* esp_netif_get_netif_impl(esp_netif_t *esp_netif); */ esp_err_t esp_netif_transmit(esp_netif_t *esp_netif, void* data, size_t len); +/** + * @brief Outputs packets from the TCP/IP stack to the media to be transmitted + * + * This function gets called from network stack to output packets to IO driver. + * + * @param[in] esp_netif Handle to esp-netif instance + * @param[in] data Data to be transmitted + * @param[in] len Length of the data frame + * @param[in] netstack_buf net stack buffer + * + * @return ESP_OK on success, an error passed from the I/O driver otherwise + */ +esp_err_t esp_netif_transmit_wrap(esp_netif_t *esp_netif, void *data, size_t len, void *netstack_buf); + /** * @brief Free the rx buffer allocated by the media driver * diff --git a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_slip.h b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_slip.h new file mode 100644 index 00000000..9cfafb97 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_slip.h @@ -0,0 +1,77 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +#ifndef _ESP_NETIF_SLIP_H_ +#define _ESP_NETIF_SLIP_H_ + +#include "esp_netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Configuration structure for SLIP network interface + * + */ +typedef struct esp_netif_slip_config { + esp_ip6_addr_t ip6_addr; /* Local IP6 address */ + +} esp_netif_slip_config_t; + + +/** @brief Sets common parameters for the supplied esp-netif. + * + * @param[in] esp_netif handle to slip esp-netif instance + * @param[in] config Pointer to SLIP netif configuration structure + * + * @return ESP_OK on success, ESP_ERR_ESP_NETIF_INVALID_PARAMS if netif null or not SLIP + */ +esp_err_t esp_netif_slip_set_params(esp_netif_t *netif, const esp_netif_slip_config_t *config); + +/** @brief Sets IPV6 address for the supplied esp-netif. + * + * @param[in] netif handle to slip esp-netif instance + * @param[in] ipv6 IPv6 address of the SLIP interface + * + * @return ESP_OK on success, ESP_ERR_ESP_NETIF_INVALID_PARAMS if netif null or not SLIP + */ +esp_err_t esp_netif_slip_set_ipv6(esp_netif_t *netif, const esp_ip6_addr_t *ipv6); + +/** + * @brief Data path API to write raw packet ous the SLIP interface + * + * This API is typically used when implementing user defined methods + * + * @param[in] esp_netif handle to slip esp-netif instance + * @param[in] buffer pointer to the outgoing data + * @param[in] len length of the data + * + * @return + * - ESP_OK on success + */ +void esp_netif_lwip_slip_raw_output(esp_netif_t *netif, void *buffer, size_t len); + +/** + * @brief Fetch IP6 address attached to the SLIP interface + * + * @param[in] esp_netif handle to slip esp-netif instance + * @param[in] address index (unused) + * + * @return + * - pointer to the internal ip6 address object + */ +const esp_ip6_addr_t *esp_slip_get_ip6(esp_netif_t *slip_netif); + +#endif diff --git a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_types.h b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_types.h index 0e361393..470839d1 100644 --- a/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_types.h +++ b/tools/sdk/esp32s2/include/esp_netif/include/esp_netif_types.h @@ -138,7 +138,8 @@ typedef enum esp_netif_flags { ESP_NETIF_FLAG_AUTOUP = 1 << 2, ESP_NETIF_FLAG_GARP = 1 << 3, ESP_NETIF_FLAG_EVENT_IP_MODIFIED = 1 << 4, - ESP_NETIF_FLAG_IS_PPP = 1 << 5 + ESP_NETIF_FLAG_IS_PPP = 1 << 5, + ESP_NETIF_FLAG_IS_SLIP = 1 << 6, } esp_netif_flags_t; typedef enum esp_netif_ip_event_type { @@ -163,7 +164,9 @@ typedef struct esp_netif_inherent_config { const char * if_key; /*!< string identifier of the interface */ const char * if_desc; /*!< textual description of the interface */ int route_prio; /*!< numeric priority of this interface to become a default - routing if (if other netifs are up) */ + routing if (if other netifs are up). + A higher value of route_prio indicates + a higher priority */ } esp_netif_inherent_config_t; typedef struct esp_netif_config esp_netif_config_t; @@ -184,6 +187,7 @@ typedef struct esp_netif_driver_base_s { struct esp_netif_driver_ifconfig { esp_netif_iodriver_handle handle; esp_err_t (*transmit)(void *h, void *buffer, size_t len); + esp_err_t (*transmit_wrap)(void *h, void *buffer, size_t len, void *netstack_buffer); void (*driver_free_rx_buffer)(void *h, void* buffer); }; diff --git a/tools/sdk/esp32s2/include/esp_ringbuf/include/freertos/ringbuf.h b/tools/sdk/esp32s2/include/esp_ringbuf/include/freertos/ringbuf.h index 1312723a..ef9c5322 100644 --- a/tools/sdk/esp32s2/include/esp_ringbuf/include/freertos/ringbuf.h +++ b/tools/sdk/esp32s2/include/esp_ringbuf/include/freertos/ringbuf.h @@ -255,6 +255,7 @@ void *xRingbufferReceive(RingbufHandle_t xRingbuffer, size_t *pxItemSize, TickTy * * @note A call to vRingbufferReturnItemFromISR() is required after this to free the item retrieved. * @note Byte buffers do not allow multiple retrievals before returning an item + * @note Two calls to RingbufferReceiveFromISR() are required if the bytes wrap around the end of the ring buffer. * * @return * - Pointer to the retrieved item on success; *pxItemSize filled with the length of the item. @@ -333,6 +334,7 @@ BaseType_t xRingbufferReceiveSplitFromISR(RingbufHandle_t xRingbuffer, * @note A call to vRingbufferReturnItem() is required after this to free up the data retrieved. * @note This function should only be called on byte buffers * @note Byte buffers do not allow multiple retrievals before returning an item + * @note Two calls to RingbufferReceiveUpTo() are required if the bytes wrap around the end of the ring buffer. * * @return * - Pointer to the retrieved item on success; *pxItemSize filled with diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/crc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/crc.h index a940b638..a5703611 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/crc.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/crc.h @@ -17,13 +17,6 @@ #include -#define ESP_ROM_HAS_CRC8LE 1 -#define ESP_ROM_HAS_CRC16LE 1 -#define ESP_ROM_HAS_CRC32LE 1 -#define ESP_ROM_HAS_CRC8BE 1 -#define ESP_ROM_HAS_CRC16BE 1 -#define ESP_ROM_HAS_CRC32BE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h index 04ffec0a..1ec326ca 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32/rom/secure_boot.h @@ -107,7 +107,7 @@ void ets_secure_boot_verify_boot_bootloader(void); * @return true if is Secure boot v2 has been enabled * False if Secure boot v2 has not been enabled. */ -bool ets_use_secure_boot_v2(); +bool ets_use_secure_boot_v2(void); #endif /* CONFIG_ESP32_REV_MIN_3 */ diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/cache.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/cache.h index 76ede22b..cc85512f 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/cache.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/cache.h @@ -50,10 +50,10 @@ typedef enum { typedef enum { CACHE_MEMORY_INVALID = 0, - CACHE_MEMORY_ICACHE_LOW = BIT(0), - CACHE_MEMORY_ICACHE_HIGH = BIT(1), - CACHE_MEMORY_DCACHE_LOW = BIT(2), - CACHE_MEMORY_DCACHE_HIGH = BIT(3), + CACHE_MEMORY_ICACHE_LOW = 1<<0, + CACHE_MEMORY_ICACHE_HIGH = 1<<1, + CACHE_MEMORY_DCACHE_LOW = 1<<2, + CACHE_MEMORY_DCACHE_HIGH = 1<<3, } cache_layout_t; #define CACHE_SIZE_8KB CACHE_SIZE_HALF diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/crc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/crc.h index f6a06871..0d139795 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/crc.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/crc.h @@ -17,10 +17,6 @@ #include -#define ESP_ROM_HAS_CRC8LE 1 -#define ESP_ROM_HAS_CRC16LE 1 -#define ESP_ROM_HAS_CRC32LE 1 - #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/queue.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/queue.h deleted file mode 100644 index 29ee6706..00000000 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/queue.h +++ /dev/null @@ -1,645 +0,0 @@ -/*- - * Copyright (c) 1991, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)queue.h 8.5 (Berkeley) 8/20/94 - * $FreeBSD$ - */ - -#ifndef _SYS_QUEUE_H_ -#define _SYS_QUEUE_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file defines four types of data structures: singly-linked lists, - * singly-linked tail queues, lists and tail queues. - * - * A singly-linked list is headed by a single forward pointer. The elements - * are singly linked for minimum space and pointer manipulation overhead at - * the expense of O(n) removal for arbitrary elements. New elements can be - * added to the list after an existing element or at the head of the list. - * Elements being removed from the head of the list should use the explicit - * macro for this purpose for optimum efficiency. A singly-linked list may - * only be traversed in the forward direction. Singly-linked lists are ideal - * for applications with large datasets and few or no removals or for - * implementing a LIFO queue. - * - * A singly-linked tail queue is headed by a pair of pointers, one to the - * head of the list and the other to the tail of the list. The elements are - * singly linked for minimum space and pointer manipulation overhead at the - * expense of O(n) removal for arbitrary elements. New elements can be added - * to the list after an existing element, at the head of the list, or at the - * end of the list. Elements being removed from the head of the tail queue - * should use the explicit macro for this purpose for optimum efficiency. - * A singly-linked tail queue may only be traversed in the forward direction. - * Singly-linked tail queues are ideal for applications with large datasets - * and few or no removals or for implementing a FIFO queue. - * - * A list is headed by a single forward pointer (or an array of forward - * pointers for a hash table header). The elements are doubly linked - * so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before - * or after an existing element or at the head of the list. A list - * may only be traversed in the forward direction. - * - * A tail queue is headed by a pair of pointers, one to the head of the - * list and the other to the tail of the list. The elements are doubly - * linked so that an arbitrary element can be removed without a need to - * traverse the list. New elements can be added to the list before or - * after an existing element, at the head of the list, or at the end of - * the list. A tail queue may be traversed in either direction. - * - * For details on the use of these macros, see the queue(3) manual page. - * - * - * SLIST LIST STAILQ TAILQ - * _HEAD + + + + - * _HEAD_INITIALIZER + + + + - * _ENTRY + + + + - * _INIT + + + + - * _EMPTY + + + + - * _FIRST + + + + - * _NEXT + + + + - * _PREV - - - + - * _LAST - - + + - * _FOREACH + + + + - * _FOREACH_SAFE + + + + - * _FOREACH_REVERSE - - - + - * _FOREACH_REVERSE_SAFE - - - + - * _INSERT_HEAD + + + + - * _INSERT_BEFORE - + - + - * _INSERT_AFTER + + + + - * _INSERT_TAIL - - + + - * _CONCAT - - + + - * _REMOVE_AFTER + - + - - * _REMOVE_HEAD + - + - - * _REMOVE + + + + - * - */ -#ifdef QUEUE_MACRO_DEBUG -/* Store the last 2 places the queue element or head was altered */ -struct qm_trace { - char * lastfile; - int lastline; - char * prevfile; - int prevline; -}; - -#define TRACEBUF struct qm_trace trace; -#define TRASHIT(x) do {(x) = (void *)-1;} while (0) -#define QMD_SAVELINK(name, link) void **name = (void *)&(link) - -#define QMD_TRACE_HEAD(head) do { \ - (head)->trace.prevline = (head)->trace.lastline; \ - (head)->trace.prevfile = (head)->trace.lastfile; \ - (head)->trace.lastline = __LINE__; \ - (head)->trace.lastfile = __FILE__; \ -} while (0) - -#define QMD_TRACE_ELEM(elem) do { \ - (elem)->trace.prevline = (elem)->trace.lastline; \ - (elem)->trace.prevfile = (elem)->trace.lastfile; \ - (elem)->trace.lastline = __LINE__; \ - (elem)->trace.lastfile = __FILE__; \ -} while (0) - -#else -#define QMD_TRACE_ELEM(elem) -#define QMD_TRACE_HEAD(head) -#define QMD_SAVELINK(name, link) -#define TRACEBUF -#define TRASHIT(x) -#endif /* QUEUE_MACRO_DEBUG */ - -/* - * Singly-linked List declarations. - */ -#define SLIST_HEAD(name, type) \ -struct name { \ - struct type *slh_first; /* first element */ \ -} - -#define SLIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define SLIST_ENTRY(type) \ -struct { \ - struct type *sle_next; /* next element */ \ -} - -/* - * Singly-linked List functions. - */ -#define SLIST_EMPTY(head) ((head)->slh_first == NULL) - -#define SLIST_FIRST(head) ((head)->slh_first) - -#define SLIST_FOREACH(var, head, field) \ - for ((var) = SLIST_FIRST((head)); \ - (var); \ - (var) = SLIST_NEXT((var), field)) - -#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = SLIST_FIRST((head)); \ - (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ - for ((varp) = &SLIST_FIRST((head)); \ - ((var) = *(varp)) != NULL; \ - (varp) = &SLIST_NEXT((var), field)) - -#define SLIST_INIT(head) do { \ - SLIST_FIRST((head)) = NULL; \ -} while (0) - -#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ - SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ - SLIST_NEXT((slistelm), field) = (elm); \ -} while (0) - -#define SLIST_INSERT_HEAD(head, elm, field) do { \ - SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ - SLIST_FIRST((head)) = (elm); \ -} while (0) - -#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) - -#define SLIST_REMOVE(head, elm, type, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.sle_next); \ - if (SLIST_FIRST((head)) == (elm)) { \ - SLIST_REMOVE_HEAD((head), field); \ - } \ - else { \ - struct type *curelm = SLIST_FIRST((head)); \ - while (SLIST_NEXT(curelm, field) != (elm)) \ - curelm = SLIST_NEXT(curelm, field); \ - SLIST_REMOVE_AFTER(curelm, field); \ - } \ - TRASHIT(*oldnext); \ -} while (0) - -#define SLIST_REMOVE_AFTER(elm, field) do { \ - SLIST_NEXT(elm, field) = \ - SLIST_NEXT(SLIST_NEXT(elm, field), field); \ -} while (0) - -#define SLIST_REMOVE_HEAD(head, field) do { \ - SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ -} while (0) - -/* - * Singly-linked Tail queue declarations. - */ -#define STAILQ_HEAD(name, type) \ -struct name { \ - struct type *stqh_first;/* first element */ \ - struct type **stqh_last;/* addr of last next element */ \ -} - -#define STAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).stqh_first } - -#define STAILQ_ENTRY(type) \ -struct { \ - struct type *stqe_next; /* next element */ \ -} - -/* - * Singly-linked Tail queue functions. - */ -#define STAILQ_CONCAT(head1, head2) do { \ - if (!STAILQ_EMPTY((head2))) { \ - *(head1)->stqh_last = (head2)->stqh_first; \ - (head1)->stqh_last = (head2)->stqh_last; \ - STAILQ_INIT((head2)); \ - } \ -} while (0) - -#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) - -#define STAILQ_FIRST(head) ((head)->stqh_first) - -#define STAILQ_FOREACH(var, head, field) \ - for((var) = STAILQ_FIRST((head)); \ - (var); \ - (var) = STAILQ_NEXT((var), field)) - - -#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = STAILQ_FIRST((head)); \ - (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define STAILQ_INIT(head) do { \ - STAILQ_FIRST((head)) = NULL; \ - (head)->stqh_last = &STAILQ_FIRST((head)); \ -} while (0) - -#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ - if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ - STAILQ_NEXT((tqelm), field) = (elm); \ -} while (0) - -#define STAILQ_INSERT_HEAD(head, elm, field) do { \ - if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ - STAILQ_FIRST((head)) = (elm); \ -} while (0) - -#define STAILQ_INSERT_TAIL(head, elm, field) do { \ - STAILQ_NEXT((elm), field) = NULL; \ - *(head)->stqh_last = (elm); \ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ -} while (0) - -#define STAILQ_LAST(head, type, field) \ - (STAILQ_EMPTY((head)) ? \ - NULL : \ - ((struct type *)(void *) \ - ((char *)((head)->stqh_last) - __offsetof(struct type, field)))) - -#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) - -#define STAILQ_REMOVE(head, elm, type, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.stqe_next); \ - if (STAILQ_FIRST((head)) == (elm)) { \ - STAILQ_REMOVE_HEAD((head), field); \ - } \ - else { \ - struct type *curelm = STAILQ_FIRST((head)); \ - while (STAILQ_NEXT(curelm, field) != (elm)) \ - curelm = STAILQ_NEXT(curelm, field); \ - STAILQ_REMOVE_AFTER(head, curelm, field); \ - } \ - TRASHIT(*oldnext); \ -} while (0) - -#define STAILQ_REMOVE_HEAD(head, field) do { \ - if ((STAILQ_FIRST((head)) = \ - STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ - (head)->stqh_last = &STAILQ_FIRST((head)); \ -} while (0) - -#define STAILQ_REMOVE_AFTER(head, elm, field) do { \ - if ((STAILQ_NEXT(elm, field) = \ - STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL) \ - (head)->stqh_last = &STAILQ_NEXT((elm), field); \ -} while (0) - -#define STAILQ_SWAP(head1, head2, type) do { \ - struct type *swap_first = STAILQ_FIRST(head1); \ - struct type **swap_last = (head1)->stqh_last; \ - STAILQ_FIRST(head1) = STAILQ_FIRST(head2); \ - (head1)->stqh_last = (head2)->stqh_last; \ - STAILQ_FIRST(head2) = swap_first; \ - (head2)->stqh_last = swap_last; \ - if (STAILQ_EMPTY(head1)) \ - (head1)->stqh_last = &STAILQ_FIRST(head1); \ - if (STAILQ_EMPTY(head2)) \ - (head2)->stqh_last = &STAILQ_FIRST(head2); \ -} while (0) - -#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do { \ - if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \ - (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field); \ - } \ - STAILQ_FIRST(head) = (elm_chead); \ -} while (0) - - -/* - * List declarations. - */ -#define LIST_HEAD(name, type) \ -struct name { \ - struct type *lh_first; /* first element */ \ -} - -#define LIST_HEAD_INITIALIZER(head) \ - { NULL } - -#define LIST_ENTRY(type) \ -struct { \ - struct type *le_next; /* next element */ \ - struct type **le_prev; /* address of previous next element */ \ -} - -/* - * List functions. - */ - -#if (defined(_KERNEL) && defined(INVARIANTS)) -#define QMD_LIST_CHECK_HEAD(head, field) do { \ - if (LIST_FIRST((head)) != NULL && \ - LIST_FIRST((head))->field.le_prev != \ - &LIST_FIRST((head))) \ - panic("Bad list head %p first->prev != head", (head)); \ -} while (0) - -#define QMD_LIST_CHECK_NEXT(elm, field) do { \ - if (LIST_NEXT((elm), field) != NULL && \ - LIST_NEXT((elm), field)->field.le_prev != \ - &((elm)->field.le_next)) \ - panic("Bad link elm %p next->prev != elm", (elm)); \ -} while (0) - -#define QMD_LIST_CHECK_PREV(elm, field) do { \ - if (*(elm)->field.le_prev != (elm)) \ - panic("Bad link elm %p prev->next != elm", (elm)); \ -} while (0) -#else -#define QMD_LIST_CHECK_HEAD(head, field) -#define QMD_LIST_CHECK_NEXT(elm, field) -#define QMD_LIST_CHECK_PREV(elm, field) -#endif /* (_KERNEL && INVARIANTS) */ - -#define LIST_EMPTY(head) ((head)->lh_first == NULL) - -#define LIST_FIRST(head) ((head)->lh_first) - -#define LIST_FOREACH(var, head, field) \ - for ((var) = LIST_FIRST((head)); \ - (var); \ - (var) = LIST_NEXT((var), field)) - -#define LIST_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = LIST_FIRST((head)); \ - (var) && ((tvar) = LIST_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define LIST_INIT(head) do { \ - LIST_FIRST((head)) = NULL; \ -} while (0) - -#define LIST_INSERT_AFTER(listelm, elm, field) do { \ - QMD_LIST_CHECK_NEXT(listelm, field); \ - if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ - LIST_NEXT((listelm), field)->field.le_prev = \ - &LIST_NEXT((elm), field); \ - LIST_NEXT((listelm), field) = (elm); \ - (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ -} while (0) - -#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ - QMD_LIST_CHECK_PREV(listelm, field); \ - (elm)->field.le_prev = (listelm)->field.le_prev; \ - LIST_NEXT((elm), field) = (listelm); \ - *(listelm)->field.le_prev = (elm); \ - (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ -} while (0) - -#define LIST_INSERT_HEAD(head, elm, field) do { \ - QMD_LIST_CHECK_HEAD((head), field); \ - if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ - LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ - LIST_FIRST((head)) = (elm); \ - (elm)->field.le_prev = &LIST_FIRST((head)); \ -} while (0) - -#define LIST_NEXT(elm, field) ((elm)->field.le_next) - -#define LIST_REMOVE(elm, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.le_next); \ - QMD_SAVELINK(oldprev, (elm)->field.le_prev); \ - QMD_LIST_CHECK_NEXT(elm, field); \ - QMD_LIST_CHECK_PREV(elm, field); \ - if (LIST_NEXT((elm), field) != NULL) \ - LIST_NEXT((elm), field)->field.le_prev = \ - (elm)->field.le_prev; \ - *(elm)->field.le_prev = LIST_NEXT((elm), field); \ - TRASHIT(*oldnext); \ - TRASHIT(*oldprev); \ -} while (0) - -#define LIST_SWAP(head1, head2, type, field) do { \ - struct type *swap_tmp = LIST_FIRST((head1)); \ - LIST_FIRST((head1)) = LIST_FIRST((head2)); \ - LIST_FIRST((head2)) = swap_tmp; \ - if ((swap_tmp = LIST_FIRST((head1))) != NULL) \ - swap_tmp->field.le_prev = &LIST_FIRST((head1)); \ - if ((swap_tmp = LIST_FIRST((head2))) != NULL) \ - swap_tmp->field.le_prev = &LIST_FIRST((head2)); \ -} while (0) - -/* - * Tail queue declarations. - */ -#define TAILQ_HEAD(name, type) \ -struct name { \ - struct type *tqh_first; /* first element */ \ - struct type **tqh_last; /* addr of last next element */ \ - TRACEBUF \ -} - -#define TAILQ_HEAD_INITIALIZER(head) \ - { NULL, &(head).tqh_first } - -#define TAILQ_ENTRY(type) \ -struct { \ - struct type *tqe_next; /* next element */ \ - struct type **tqe_prev; /* address of previous next element */ \ - TRACEBUF \ -} - -/* - * Tail queue functions. - */ -#if (defined(_KERNEL) && defined(INVARIANTS)) -#define QMD_TAILQ_CHECK_HEAD(head, field) do { \ - if (!TAILQ_EMPTY(head) && \ - TAILQ_FIRST((head))->field.tqe_prev != \ - &TAILQ_FIRST((head))) \ - panic("Bad tailq head %p first->prev != head", (head)); \ -} while (0) - -#define QMD_TAILQ_CHECK_TAIL(head, field) do { \ - if (*(head)->tqh_last != NULL) \ - panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \ -} while (0) - -#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \ - if (TAILQ_NEXT((elm), field) != NULL && \ - TAILQ_NEXT((elm), field)->field.tqe_prev != \ - &((elm)->field.tqe_next)) \ - panic("Bad link elm %p next->prev != elm", (elm)); \ -} while (0) - -#define QMD_TAILQ_CHECK_PREV(elm, field) do { \ - if (*(elm)->field.tqe_prev != (elm)) \ - panic("Bad link elm %p prev->next != elm", (elm)); \ -} while (0) -#else -#define QMD_TAILQ_CHECK_HEAD(head, field) -#define QMD_TAILQ_CHECK_TAIL(head, headname) -#define QMD_TAILQ_CHECK_NEXT(elm, field) -#define QMD_TAILQ_CHECK_PREV(elm, field) -#endif /* (_KERNEL && INVARIANTS) */ - -#define TAILQ_CONCAT(head1, head2, field) do { \ - if (!TAILQ_EMPTY(head2)) { \ - *(head1)->tqh_last = (head2)->tqh_first; \ - (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ - (head1)->tqh_last = (head2)->tqh_last; \ - TAILQ_INIT((head2)); \ - QMD_TRACE_HEAD(head1); \ - QMD_TRACE_HEAD(head2); \ - } \ -} while (0) - -#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) - -#define TAILQ_FIRST(head) ((head)->tqh_first) - -#define TAILQ_FOREACH(var, head, field) \ - for ((var) = TAILQ_FIRST((head)); \ - (var); \ - (var) = TAILQ_NEXT((var), field)) - -#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ - for ((var) = TAILQ_FIRST((head)); \ - (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ - (var) = (tvar)) - -#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ - for ((var) = TAILQ_LAST((head), headname); \ - (var); \ - (var) = TAILQ_PREV((var), headname, field)) - -#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ - for ((var) = TAILQ_LAST((head), headname); \ - (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ - (var) = (tvar)) - -#define TAILQ_INIT(head) do { \ - TAILQ_FIRST((head)) = NULL; \ - (head)->tqh_last = &TAILQ_FIRST((head)); \ - QMD_TRACE_HEAD(head); \ -} while (0) - -#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ - QMD_TAILQ_CHECK_NEXT(listelm, field); \ - if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ - TAILQ_NEXT((elm), field)->field.tqe_prev = \ - &TAILQ_NEXT((elm), field); \ - else { \ - (head)->tqh_last = &TAILQ_NEXT((elm), field); \ - QMD_TRACE_HEAD(head); \ - } \ - TAILQ_NEXT((listelm), field) = (elm); \ - (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ - QMD_TRACE_ELEM(&(elm)->field); \ - QMD_TRACE_ELEM(&listelm->field); \ -} while (0) - -#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ - QMD_TAILQ_CHECK_PREV(listelm, field); \ - (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ - TAILQ_NEXT((elm), field) = (listelm); \ - *(listelm)->field.tqe_prev = (elm); \ - (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ - QMD_TRACE_ELEM(&(elm)->field); \ - QMD_TRACE_ELEM(&listelm->field); \ -} while (0) - -#define TAILQ_INSERT_HEAD(head, elm, field) do { \ - QMD_TAILQ_CHECK_HEAD(head, field); \ - if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ - TAILQ_FIRST((head))->field.tqe_prev = \ - &TAILQ_NEXT((elm), field); \ - else \ - (head)->tqh_last = &TAILQ_NEXT((elm), field); \ - TAILQ_FIRST((head)) = (elm); \ - (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ - QMD_TRACE_HEAD(head); \ - QMD_TRACE_ELEM(&(elm)->field); \ -} while (0) - -#define TAILQ_INSERT_TAIL(head, elm, field) do { \ - QMD_TAILQ_CHECK_TAIL(head, field); \ - TAILQ_NEXT((elm), field) = NULL; \ - (elm)->field.tqe_prev = (head)->tqh_last; \ - *(head)->tqh_last = (elm); \ - (head)->tqh_last = &TAILQ_NEXT((elm), field); \ - QMD_TRACE_HEAD(head); \ - QMD_TRACE_ELEM(&(elm)->field); \ -} while (0) - -#define TAILQ_LAST(head, headname) \ - (*(((struct headname *)((head)->tqh_last))->tqh_last)) - -#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) - -#define TAILQ_PREV(elm, headname, field) \ - (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) - -#define TAILQ_REMOVE(head, elm, field) do { \ - QMD_SAVELINK(oldnext, (elm)->field.tqe_next); \ - QMD_SAVELINK(oldprev, (elm)->field.tqe_prev); \ - QMD_TAILQ_CHECK_NEXT(elm, field); \ - QMD_TAILQ_CHECK_PREV(elm, field); \ - if ((TAILQ_NEXT((elm), field)) != NULL) \ - TAILQ_NEXT((elm), field)->field.tqe_prev = \ - (elm)->field.tqe_prev; \ - else { \ - (head)->tqh_last = (elm)->field.tqe_prev; \ - QMD_TRACE_HEAD(head); \ - } \ - *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ - TRASHIT(*oldnext); \ - TRASHIT(*oldprev); \ - QMD_TRACE_ELEM(&(elm)->field); \ -} while (0) - -#define TAILQ_SWAP(head1, head2, type, field) do { \ - struct type *swap_first = (head1)->tqh_first; \ - struct type **swap_last = (head1)->tqh_last; \ - (head1)->tqh_first = (head2)->tqh_first; \ - (head1)->tqh_last = (head2)->tqh_last; \ - (head2)->tqh_first = swap_first; \ - (head2)->tqh_last = swap_last; \ - if ((swap_first = (head1)->tqh_first) != NULL) \ - swap_first->field.tqe_prev = &(head1)->tqh_first; \ - else \ - (head1)->tqh_last = &(head1)->tqh_first; \ - if ((swap_first = (head2)->tqh_first) != NULL) \ - swap_first->field.tqe_prev = &(head2)->tqh_first; \ - else \ - (head2)->tqh_last = &(head2)->tqh_first; \ -} while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* !_SYS_QUEUE_H_ */ diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rsa_pss.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rsa_pss.h index 6a70c578..bfbaeb6a 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rsa_pss.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rsa_pss.h @@ -16,7 +16,11 @@ #define _ROM_RSA_PSS_H_ #include -#include "rsa_pss.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif #define ETS_SIG_LEN 384 /* Bytes */ #define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ @@ -28,10 +32,14 @@ typedef struct { uint32_t mdash; } ets_rsa_pubkey_t; -bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest); +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest); void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); +#ifdef __cplusplus +} +#endif + #endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rtc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rtc.h index 593e8854..c91916fa 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rtc.h +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/rtc.h @@ -71,7 +71,6 @@ extern "C" { #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG - typedef enum { AWAKE = 0, // + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void cdc_acm_device; +extern cdc_acm_device *uart_acm_dev; + +#define ACM_BYTES_PER_TX 64 + +//ACM statuses are negative to distinguish from USB_DC_* status codes +#define ACM_STATUS_LINESTATE_CHANGED -1 +#define ACM_STATUS_LINECODING_CHANGED -2 +#define ACM_STATUS_TX -3 +#define ACM_STATUS_RX -4 + +typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status); + +/** + * @brief Get amount of received characters in buffer + * + * @returns character count + */ + +int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev); + + +/* + * @brief Poll the device for input. + * + * @return -ENOTSUP Since underlying USB device controller always uses + * interrupts, polled mode UART APIs are not implemented for the UART interface + * exported by CDC ACM driver. Apps should use fifo_read API instead. + */ + +int cdc_acm_poll_in(cdc_acm_device *dev, unsigned char *c); + +/* + * @brief Output a character in polled mode. + * + * The UART poll method for USB UART is simulated by waiting till + * we get the next BULK In upcall from the USB device controller or 100 ms. + * + * @return the same character which is sent + */ +unsigned char cdc_acm_poll_out(cdc_acm_device *dev, unsigned char c); + +/** + * @brief Fill FIFO with data + * + * @param dev CDC ACM device struct. + * @param tx_data Data to transmit. + * @param len Number of bytes to send. + * + * @return Number of bytes sent. + */ +int cdc_acm_fifo_fill(cdc_acm_device *dev, const uint8_t *tx_data, int len); + +/** + * @brief Read data from FIFO + * + * @param dev CDC ACM device struct. + * @param rx_data Pointer to data container. + * @param size Container size. + * + * @return Number of bytes read. + */ +int cdc_acm_fifo_read(cdc_acm_device *dev, uint8_t *rx_data, const int size); + +/** + * @brief Enable TX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_tx_enable(cdc_acm_device *dev); + +/** + * @brief Disable TX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_tx_disable(cdc_acm_device *dev); + +/** + * @brief Check if Tx IRQ has been raised + * + * @param dev CDC ACM device struct. + * + * @return 1 if a Tx IRQ is pending, 0 otherwise. + */ +int cdc_acm_irq_tx_ready(cdc_acm_device *dev); + +/** + * @brief Enable RX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A + */ +void cdc_acm_irq_rx_enable(cdc_acm_device *dev); + +/** + * @brief Disable RX interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_rx_disable(cdc_acm_device *dev); + +/** + * @brief Enable line state interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_state_enable(cdc_acm_device *dev); + +/** + * @brief Disable line state interrupt + * + * @param dev CDC ACM device struct. + * + * @return N/A. + */ +void cdc_acm_irq_state_disable(cdc_acm_device *dev); + + +/** + * @brief Check if Rx IRQ has been raised + * + * @param dev CDC ACM device struct. + * + * @return 1 if an IRQ is ready, 0 otherwise. + */ +int cdc_acm_irq_rx_ready(cdc_acm_device *dev); + +/** + * @brief Check if Tx or Rx IRQ is pending + * + * @param dev CDC ACM device struct. + * + * @return 1 if a Tx or Rx IRQ is pending, 0 otherwise. + */ +int cdc_acm_irq_is_pending(cdc_acm_device *dev); + +/** + * @brief Set the callback function pointer for IRQ. + * + * @param dev CDC ACM device struct. + * @param cb Callback function pointer. + * + * @return N/A + */ +void cdc_acm_irq_callback_set(cdc_acm_device *dev, uart_irq_callback_t cb); + +/** + * @brief Manipulate line control for UART. + * + * @param dev CDC ACM device struct + * @param ctrl The line control to be manipulated + * @param val Value to set the line control + * + * @return 0 if successful, failed otherwise. + */ +int cdc_acm_line_ctrl_set(cdc_acm_device *dev, uint32_t ctrl, uint32_t val); + +/** + * @brief Manipulate line control for UART. + * + * @param dev CDC ACM device struct + * @param ctrl The line control to be manipulated + * @param val Value to set the line control + * + * @return 0 if successful, failed otherwise. + */ +int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val); + + +/** + * @brief Initialize UART channel + * + * This routine is called to reset the chip in a quiescent state. + * It is assumed that this function is called only once per UART. + * + * @param mem_chunk Memory chunk to use for internal use + * @param mem_chunk_size Size of the memory chunk in bytes + * + * @return dev or NULL + */ +cdc_acm_device *cdc_acm_init(void *mem_chunk, int mem_chunk_size); + + +/** Common line controls for UART.*/ +#define LINE_CTRL_BAUD_RATE (1 << 0) +#define LINE_CTRL_RTS (1 << 1) +#define LINE_CTRL_DTR (1 << 2) +#define LINE_CTRL_DCD (1 << 3) +#define LINE_CTRL_DSR (1 << 4) + +/* Common communication errors for UART.*/ + +/** @brief Overrun error */ +#define UART_ERROR_OVERRUN (1 << 0) + +/** @brief Parity error */ +#define UART_ERROR_PARITY (1 << 1) + +/** @brief Framing error */ +#define UART_ERROR_FRAMING (1 << 2) + +/** + * @brief Break interrupt error: + * + * A break interrupt was received. This happens when the serial input is + * held at a logic '0' state for longer than the sum of start time + data bits + * + parity + stop bits. + */ +#define UART_ERROR_BREAK (1 << 3) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h new file mode 100644 index 00000000..a7c50643 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h @@ -0,0 +1,30 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int chip_usb_dw_init(void); +int chip_usb_dw_did_persist(void); +void chip_usb_dw_prepare_persist(void); +uint32_t chip_usb_get_persist_flags(void); +void chip_usb_set_persist_flags(uint32_t flags); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/cpio.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/cpio.h new file mode 100644 index 00000000..5603b3f5 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/cpio.h @@ -0,0 +1,180 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +/** + * Archive to parse cpio data in the newc and crc formats. Generate a cpio archive like that by e.g. + * find . | cpio -o -H newc > archive.cpio + */ + +#pragma once + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CPIO_MODE_FILETYPE_MASK 0xF000 +#define CPIO_MODE_FILETYPE_SOCKET 0xC000 +#define CPIO_MODE_FILETYPE_SYMLINK 0xA000 +#define CPIO_MODE_FILETYPE_REGULAR 0x8000 +#define CPIO_MODE_FILETYPE_BLOCKDEV 0x6000 +#define CPIO_MODE_FILETYPE_DIR 0x4000 +#define CPIO_MODE_FILETYPE_CHARDEV 0x2000 +#define CPIO_MODE_FILETYPE_FIFO 0x1000 +#define CPIO_MODE_SUID 0x0800 +#define CPIO_MODE_SGID 0x0400 +#define CPIO_MODE_STICKY 0x0200 + +typedef struct { + size_t filesize; + char *name; + uint32_t mode; + uint32_t check; +} cpio_file_t; + +typedef enum { + CPIO_RET_MORE = 0, + CPIO_RET_DONE, + CPIO_RET_ERR +} cpio_ret_t; + +typedef struct cpio_handle_data_t cpio_handle_data_t; +typedef cpio_handle_data_t *cpio_handle_t; + +typedef enum { + CPIO_RSN_FILE_ALL = 0, + CPIO_RSN_FILE_INITIAL, + CPIO_RSN_FILE_MORE, + CPIO_RSN_FILE_END +} cpio_callback_reason_t; + + +/** + * Callback for cpio file data. + * + * This callback will be called by the library to indicate data for a file is available. + * + * For files in the cpio archive that fit entirely in the internal buffer, or when no internal + * buffer is available, are entirely contained in the buffer fed to cpio_feed(), this callback + * is only called once, with reason=CPIO_RNS_FILE_ALL. fileinfo will contain the information + * for that specific file (name, size, ...), buff_offset will be 0, buff_len is the file + * size and buff contains all the information for the file. + * + * For files that do not fit in the buffer, this callback will be called multiple times. + * The initial time with reason=CPIO_RSN_FILE_INITIAL, when more data is available with + * CPIO_RSN_FILE_MORE and finally with CPIO_RSN_FILE_END. For these calls, fileinfo + * will again contain file information. buff will be the information contained in the + * file at offset buff_offset, and the lenght of this buffer will be in buff_len. + * + * The library guarantees to feed all file data to the callback consequitively, so + * within the same file, the buff_offset from a call will always be (buff_offset+buff_len) + * from the call before that. If cpio_start is + * + * The library also guarantees every file in the cpio archive will either generate a single + * callback call with CPIO_RSN_ALL, or multiple with in sequence CPIO_RSN_FILE_INITIAL, 0 or + * more CPIO_RSN_FILE_MORE and finally a CPIO_RSN_FILE_END. + * + * When a non-zero buffer size is passed to cpio_start, the library guarantees that all callback + * calls with a reason of CPIO_RSN_FILE_INITIAL and CPIO_RSN_FILE_MORE will have a buffer + * filled with exactly this amount of bytes. + * + */ +typedef void (*cpio_callback_t)(cpio_callback_reason_t reason, cpio_file_t *fileinfo, size_t buff_offset, size_t buff_len, char *buff, void *arg); + + +/** + * @brief Initialize a cpio handle. + * + * Call this to start parsing a cpio archive. You can set the callback that handles the + * files/data here. + * + * @param callback The callback that will handle the data of the files inside the cpio archive + * + * @param cbarg User-supplied argument. The callback will be called with this as an argument. + * + * @param buflen Length of internal buffer used. + * If this is zero, the callback will be called with data that lives in the data buffer + * supplied to the cpio library by whomever called cpio_feed(). Because this library has + * no power over that buffer, the callback can be passed as little as 1 and as many as + * INT_MAX bytes at a time. + * If this is non-zero, the library will allocate an internal buffer of this size. All + * cpio_feed()-calls will be rebuffered, and the callback is guaranteed to only be called + * with this many bytes in the buffer, given there's enough data in the file to fill it. + * + * @param memchunk Chunk of memory to allocate everything (handle, I/O buffer, filename buffer) in. Minimum size + * (estimate) is 160+buflen+sizeof(largest filename/path). + * @param memchunklen Size of the mem chunk + * + * @return + * - Success: A pointer to a cpio handle + * - Error: NULL + * + */ +cpio_handle_t cpio_start(cpio_callback_t callback, void *cbarg, size_t buflen, void *memchunk, int memchunklen); + +/** + * @brief Feed data from a cpio archive into the library + * + * This routine is used to feed consecutive data of the cpio archive into the library. While processing, + * the library can call the callback function one or more times if needed. + * + * @param cpio Handle obtained by calling cpio_start() + * + * @param buffer Pointer to buffer containing cpio archive data + * + * @param len Length of the buffer, in bytes + * + * @return + * - CPIO_RET_MORE: CPIO archive isn't done yet, please feed more data. + * - CPIO_RET_DONE: CPUI archive is finished. + * - CPIO_RET_ERR: Invalid CPIO archive data; decoding aborted. + * + */ +cpio_ret_t cpio_feed(cpio_handle_t cpio, char *buffer, int len); + +/** + * @brief Indicate there is no more cpio data to be fed into the archive + * + * This call is to be called when the source data is exhausted. Normally, the library can find the end of the + * cpio archive by looking for the end marker, + * + * @param timer_conf Pointer of LEDC timer configure struct + * + * + * @return + * - CPIO_RET_DONE on success + * - CPIO_RET_ERR when cpio archive is invalid + * + */ +cpio_ret_t cpio_done(cpio_handle_t cpio); + + +/** + * @brief Free the memory allocated for a cpio handle. + * + * @param cpio Handle obtained by calling cpio_start() + * + * @return + * - CPIO_RET_DONE on success + * + */ +cpio_ret_t cpio_destroy(cpio_handle_t cpio); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_cdc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_cdc.h new file mode 100644 index 00000000..c241bcfe --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_cdc.h @@ -0,0 +1,174 @@ +/* usb_cdc.h - USB CDC-ACM and CDC-ECM public header */ + +/* + * Copyright (c) 2017 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/** + * @file + * @brief USB Communications Device Class (CDC) public header + * + * Header follows the Class Definitions for + * Communications Devices Specification (CDC120-20101103-track.pdf), + * PSTN Devices Specification (PSTN120.pdf) and + * Ethernet Control Model Devices Specification (ECM120.pdf). + * Header is limited to ACM and ECM Subclasses. + */ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** CDC Specification release number in BCD format */ +#define CDC_SRN_1_20 0x0120 + +/** Communications Class Subclass Codes */ +#define ACM_SUBCLASS 0x02 +#define ECM_SUBCLASS 0x06 +#define EEM_SUBCLASS 0x0c + +/** Communications Class Protocol Codes */ +#define AT_CMD_V250_PROTOCOL 0x01 +#define EEM_PROTOCOL 0x07 + +/** + * @brief Data Class Interface Codes + * @note CDC120-20101103-track.pdf, 4.5, Table 6 + */ +#define DATA_INTERFACE_CLASS 0x0A + +/** + * @brief Values for the bDescriptorType Field + * @note CDC120-20101103-track.pdf, 5.2.3, Table 12 + */ +#define CS_INTERFACE 0x24 +#define CS_ENDPOINT 0x25 + +/** + * @brief bDescriptor SubType for Communications + * Class Functional Descriptors + * @note CDC120-20101103-track.pdf, 5.2.3, Table 13 + */ +#define HEADER_FUNC_DESC 0x00 +#define CALL_MANAGEMENT_FUNC_DESC 0x01 +#define ACM_FUNC_DESC 0x02 +#define UNION_FUNC_DESC 0x06 +#define ETHERNET_FUNC_DESC 0x0F + +/** + * @brief PSTN Subclass Specific Requests + * for ACM devices + * @note PSTN120.pdf, 6.3, Table 13 + */ +#define CDC_SEND_ENC_CMD 0x00 +#define CDC_GET_ENC_RSP 0x01 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/** UART State Bitmap Values */ +#define SERIAL_STATE_OVERRUN 0x40 +#define SERIAL_STATE_PARITY 0x20 +#define SERIAL_STATE_FRAMING 0x10 +#define SERIAL_STATE_RING 0x08 +#define SERIAL_STATE_BREAK 0x04 +#define SERIAL_STATE_TX_CARRIER 0x02 +#define SERIAL_STATE_RX_CARRIER 0x01 + +/** + * @brief Class-Specific Request Codes for Ethernet subclass + * @note ECM120.pdf, 6.2, Table 6 + */ +#define SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define SET_ETHERNET_PM_FILTER 0x41 +#define GET_ETHERNET_PM_FILTER 0x42 +#define SET_ETHERNET_PACKET_FILTER 0x43 +#define GET_ETHERNET_STATISTIC 0x44 + +/** Ethernet Packet Filter Bitmap */ +#define PACKET_TYPE_MULTICAST 0x10 +#define PACKET_TYPE_BROADCAST 0x08 +#define PACKET_TYPE_DIRECTED 0x04 +#define PACKET_TYPE_ALL_MULTICAST 0x02 +#define PACKET_TYPE_PROMISCUOUS 0x01 + +/** Header Functional Descriptor */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdCDC; +} __packed; + +/** Union Interface Functional Descriptor */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __packed; + +/** Call Management Functional Descriptor */ +struct cdc_cm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} __packed; + +/** Abstract Control Management Functional Descriptor */ +struct cdc_acm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} __packed; + + +/** Data structure for GET_LINE_CODING / SET_LINE_CODING class requests */ +struct cdc_acm_line_coding { + uint32_t dwDTERate; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} __packed; + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __packed; + +/** Ethernet Networking Functional Descriptor */ +struct cdc_ecm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __packed; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_common.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_common.h new file mode 100644 index 00000000..796a77bc --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_common.h @@ -0,0 +1,249 @@ +/*************************************************************************** + * + * + * Copyright(c) 2015,2016 Intel Corporation. + * Copyright(c) 2017 PHYTEC Messtechnik GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/** + * @file + * @brief useful constants and macros for the USB application + * + * This file contains useful constants and macros for the USB applications. + */ + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BCD(x) ((((x) / 10) << 4) | ((x) / 10)) + +/* Descriptor size in bytes */ +#define USB_DEVICE_DESC_SIZE 18 +#define USB_CONFIGURATION_DESC_SIZE 9 +#define USB_INTERFACE_DESC_SIZE 9 +#define USB_ENDPOINT_DESC_SIZE 7 +#define USB_STRING_DESC_SIZE 4 +#define USB_HID_DESC_SIZE 9 +#define USB_DFU_DESC_SIZE 9 +#define USB_DEVICE_QUAL_DESC_SIZE 10 +#define USB_INTERFACE_ASSOC_DESC_SIZE 8 + +/* Descriptor type */ +#define USB_DEVICE_DESC 0x01 +#define USB_CONFIGURATION_DESC 0x02 +#define USB_STRING_DESC 0x03 +#define USB_INTERFACE_DESC 0x04 +#define USB_ENDPOINT_DESC 0x05 +#define USB_DEVICE_QUAL_DESC 0x06 +#define USB_INTERFACE_ASSOC_DESC 0x0B +#define USB_DEVICE_CAPABILITY_DESC 0x10 +#define USB_HID_DESC 0x21 +#define USB_HID_REPORT_DESC 0x22 +#define USB_DFU_FUNCTIONAL_DESC 0x21 +#define USB_ASSOCIATION_DESC 0x0B +#define USB_BINARY_OBJECT_STORE_DESC 0x0F + +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 + +#define BCDDEVICE_RELNUM (BCD(KERNEL_VERSION_MAJOR) << 8 | \ + BCD(KERNEL_VERSION_MINOR)) + +/* 100mA max power, per 2mA units */ +/* USB 1.1 spec indicates 100mA(max) per unit load, up to 5 loads */ +#define MAX_LOW_POWER 0x32 +#define MAX_HIGH_POWER 0xFA + +/* bmAttributes: + * D7:Reserved, always 1, + * D6:Self-Powered -> 1, + * D5:Remote Wakeup -> 0, + * D4...0:Reserved -> 0 + */ +#define USB_CONFIGURATION_ATTRIBUTES 0xC0 + +/* Classes */ +#define COMMUNICATION_DEVICE_CLASS 0x02 +#define COMMUNICATION_DEVICE_CLASS_DATA 0x0A +#define HID_CLASS 0x03 +#define MASS_STORAGE_CLASS 0x08 +#define WIRELESS_DEVICE_CLASS 0xE0 +#define MISC_CLASS 0xEF +#define CUSTOM_CLASS 0xFF +#define DFU_DEVICE_CLASS 0xFE + +/* Sub-classes */ +#define CDC_NCM_SUBCLASS 0x0d +#define BOOT_INTERFACE_SUBCLASS 0x01 +#define SCSI_TRANSPARENT_SUBCLASS 0x06 +#define DFU_INTERFACE_SUBCLASS 0x01 +#define RF_SUBCLASS 0x01 +#define CUSTOM_SUBCLASS 0xFF +#define COMMON_SUBCLASS 0x02 +/* Misc subclasses */ +#define MISC_RNDIS_SUBCLASS 0x04 +#define CDC_ABSTRACT_CONTROL_MODEL 0x02 + +/* Protocols */ +#define V25TER_PROTOCOL 0x01 +#define MOUSE_PROTOCOL 0x02 +#define BULK_ONLY_PROTOCOL 0x50 +#define DFU_RUNTIME_PROTOCOL 0x01 +#define DFU_MODE_PROTOCOL 0x02 +#define BLUETOOTH_PROTOCOL 0x01 +/* CDC ACM protocols */ +#define ACM_VENDOR_PROTOCOL 0xFF +/* Misc protocols */ +#define MISC_ETHERNET_PROTOCOL 0x01 +#define IAD_PROTOCOL 0x01 + +/** Standard Device Descriptor */ +struct usb_device_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __packed; + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __packed; + +/** Association Descriptor */ +struct usb_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __packed; + +/** Standard Configuration Descriptor */ +struct usb_cfg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __packed; + +/** Standard Interface Descriptor */ +struct usb_if_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} __packed; + +/** Standard Endpoint Descriptor */ +struct usb_ep_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} __packed; + +struct string_descriptor_zero { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wBcdLang[]; +} __packed; + +struct string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString[]; +} __packed; + +#define ROM_MAX_CFG_DESC_CNT 1 + +struct rom_usb_descriptors { + const struct usb_device_descriptor *device_descr; + const void *config_descr[ROM_MAX_CFG_DESC_CNT]; + int string_count; // including string_descriptor_zero + const struct string_descriptor_zero *string0_descr; + const struct string_descriptor *string_descrs[]; +}; + +/* Descriptors defined in the ROM */ +extern struct usb_device_descriptor general_device_descr; +extern const void* acm_config_descr; +extern const void* dfu_config_descr; +extern const struct string_descriptor str_manu_descr; +extern const struct string_descriptor str_prod_descr; +extern const struct string_descriptor_zero string0_descr; +extern const struct rom_usb_descriptors acm_usb_descriptors; +extern const struct rom_usb_descriptors dfu_usb_descriptors; +extern const struct rom_usb_descriptors *rom_usb_curr_desc; + +/* ROM patch: set the ACM descriptor with the correct serial number. + * Only needed on ESP32-S2, on later chips the ROM descriptor is correct. + */ +void rom_usb_cdc_set_descriptor_patch(void); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_dc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_dc.h new file mode 100644 index 00000000..f20e897c --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_dc.h @@ -0,0 +1,392 @@ +/* usb_dc.h - USB device controller driver interface */ + +/* + * Copyright (c) 2016 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief USB device controller APIs + * + * This file contains the USB device controller APIs. All device controller + * drivers should implement the APIs described in this file. + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * USB endpoint direction and number. + */ + +#define USB_EP_DIR_MASK 0x80 +#define USB_EP_DIR_IN 0x80 +#define USB_EP_DIR_OUT 0x00 + +/** + * USB Driver Status Codes + */ +enum usb_dc_status_code { + USB_DC_ERROR, /* USB error reported by the controller */ + USB_DC_RESET, /* USB reset */ + /* USB connection established, hardware enumeration is completed */ + USB_DC_CONNECTED, + USB_DC_CONFIGURED, /* USB configuration done */ + USB_DC_DISCONNECTED, /* USB connection lost */ + USB_DC_SUSPEND, /* USB connection suspended by the HOST */ + USB_DC_RESUME, /* USB connection resumed by the HOST */ + USB_DC_INTERFACE, /* USB interface selected */ + USB_DC_SET_HALT, /* Set Feature ENDPOINT_HALT received */ + USB_DC_CLEAR_HALT, /* Clear Feature ENDPOINT_HALT received */ + USB_DC_UNKNOWN /* Initial USB connection status */ +}; + +/** + * USB Endpoint Callback Status Codes + */ +enum usb_dc_ep_cb_status_code { + USB_DC_EP_SETUP, /* SETUP received */ + /* Out transaction on this EP, data is available for read */ + USB_DC_EP_DATA_OUT, + USB_DC_EP_DATA_IN, /* In transaction done on this EP */ +}; + +/** + * USB Endpoint type + */ +enum usb_dc_ep_type { + USB_DC_EP_CONTROL = 0, /* Control type endpoint */ + USB_DC_EP_ISOCHRONOUS, /* Isochronous type endpoint */ + USB_DC_EP_BULK, /* Bulk type endpoint */ + USB_DC_EP_INTERRUPT /* Interrupt type endpoint */ +}; + +/** + * USB Endpoint Configuration. + */ +struct usb_dc_ep_cfg_data { + /** The number associated with the EP in the device + * configuration structure + * IN EP = 0x80 | \ + * OUT EP = 0x00 | \ + */ + uint8_t ep_addr; + uint16_t ep_mps; /** Endpoint max packet size */ + enum usb_dc_ep_type ep_type; /** Endpoint type */ +}; + +/** + * Callback function signature for the USB Endpoint status + */ +typedef void (*usb_dc_ep_callback)(uint8_t ep, + enum usb_dc_ep_cb_status_code cb_status); + +/** + * Callback function signature for the device + */ +typedef void (*usb_dc_status_callback)(enum usb_dc_status_code cb_status, + uint8_t *param); + +/** + * @brief attach USB for device connection + * + * Function to attach USB for device connection. Upon success, the USB PLL + * is enabled, and the USB device is now capable of transmitting and receiving + * on the USB bus and of generating interrupts. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_attach(void); + +/** + * @brief detach the USB device + * + * Function to detach the USB device. Upon success, the USB hardware PLL + * is powered down and USB communication is disabled. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_detach(void); + +/** + * @brief reset the USB device + * + * This function returns the USB device and firmware back to it's initial state. + * N.B. the USB PLL is handled by the usb_detach function + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_reset(void); + +/** + * @brief set USB device address + * + * @param[in] addr device address + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_set_address(const uint8_t addr); + +/** + * @brief set USB device controller status callback + * + * Function to set USB device controller status callback. The registered + * callback is used to report changes in the status of the device controller. + * + * @param[in] cb callback function + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_set_status_callback(const usb_dc_status_callback cb); + +/** + * @brief check endpoint capabilities + * + * Function to check capabilities of an endpoint. usb_dc_ep_cfg_data structure + * provides the endpoint configuration parameters: endpoint address, + * endpoint maximum packet size and endpoint type. + * The driver should check endpoint capabilities and return 0 if the + * endpoint configuration is possible. + * + * @param[in] cfg Endpoint config + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data *const cfg); + +/** + * @brief configure endpoint + * + * Function to configure an endpoint. usb_dc_ep_cfg_data structure provides + * the endpoint configuration parameters: endpoint address, endpoint maximum + * packet size and endpoint type. + * + * @param[in] cfg Endpoint config + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg); + +/** + * @brief set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_set_stall(const uint8_t ep); + +/** + * @brief clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_clear_stall(const uint8_t ep); + +/** + * @brief check if selected endpoint is stalled + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[out] stalled Endpoint stall status + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_is_stalled(const uint8_t ep, uint8_t *const stalled); + +/** + * @brief halt the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_halt(const uint8_t ep); + +/** + * @brief enable the selected endpoint + * + * Function to enable the selected endpoint. Upon success interrupts are + * enabled for the corresponding endpoint and the endpoint is ready for + * transmitting/receiving data. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_enable(const uint8_t ep); + +/** + * @brief disable the selected endpoint + * + * Function to disable the selected endpoint. Upon success interrupts are + * disabled for the corresponding endpoint and the endpoint is no longer able + * for transmitting/receiving data. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_disable(const uint8_t ep); + +/** + * @brief flush the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_flush(const uint8_t ep); + +/** + * @brief write data to the specified endpoint + * + * This function is called to write data to the specified endpoint. The supplied + * usb_ep_callback function will be called when data is transmitted out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data to write + * @param[in] data_len length of data requested to write. This may + * be zero for a zero length status packet. + * @param[out] ret_bytes bytes scheduled for transmission. This value + * may be NULL if the application expects all + * bytes to be written + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_write(const uint8_t ep, const uint8_t *const data, + const uint32_t data_len, uint32_t *const ret_bytes); + + + +/** + * @brief Indicate if the write to an IN endpoint (using usb_dc_ep_write) would block + * to wait until the endpoint has enoug space + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 when writable, 0 when not, negative errno code on fail. + */ +int usb_dc_ep_write_would_block(const uint8_t ep); + + +/** + * @brief read data from the specified endpoint + * + * This function is called by the Endpoint handler function, after an OUT + * interrupt has been received for that EP. The application must only call this + * function through the supplied usb_ep_callback function. This function clears + * the ENDPOINT NAK, if all data in the endpoint FIFO has been read, + * so as to accept more data from host. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read(const uint8_t ep, uint8_t *const data, + const uint32_t max_data_len, uint32_t *const read_bytes); + +/** + * @brief set callback function for the specified endpoint + * + * Function to set callback function for notification of data received and + * available to application or transmit done on the selected endpoint, + * NULL if callback not required by application code. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] cb callback function + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_set_callback(const uint8_t ep, const usb_dc_ep_callback cb); + +/** + * @brief read data from the specified endpoint + * + * This is similar to usb_dc_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_dc_ep_read_continue() do so. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len, + uint32_t *read_bytes); + + +/** + * @brief Continue reading data from the endpoint + * + * Clear the endpoint NAK and enable the endpoint to accept more data + * from the host. Usually called after usb_dc_ep_read_wait() when the consumer + * is fine to accept more data. Thus these calls together acts as flow control + * mechanism. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_dc_ep_read_continue(uint8_t ep); + +/** + * @brief Get endpoint max packet size + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return enpoint max packet size (mps) + */ +int usb_dc_ep_mps(uint8_t ep); + + + +//Hack - fake interrupts by pollinfg +void usb_dc_check_poll_for_interrupts(void); + + +//Prepare for USB persist. You should reboot after this. +int usb_dc_prepare_persist(void); + + +void usb_dw_isr_handler(void); + + +int usb_dc_ep_write_would_block(const uint8_t ep); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_descriptor.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_descriptor.h new file mode 100644 index 00000000..942a1968 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_descriptor.h @@ -0,0 +1,34 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define USB_DESCRIPTOR_TYPE_ACM 0 +#define USB_DESCRIPTOR_TYPE_DFU 1 + +void usb_set_current_descriptor(int descriptor_type); + +bool usb_get_descriptor(uint16_t type_index, uint16_t lang_id, + int32_t *len, uint8_t **data); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_device.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_device.h new file mode 100644 index 00000000..51801b5d --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_device.h @@ -0,0 +1,402 @@ +/* + * LPCUSB, an USB device driver for LPC microcontrollers + * Copyright (C) 2006 Bertrik Sikken (bertrik@sikken.nl) + * Copyright (c) 2016 Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file + * @brief USB device core layer APIs and structures + * + * This file contains the USB device core layer APIs and structures. + */ + +#pragma once + +#include +#include +#include "usb_dc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************************************************************* + * USB configuration + **************************************************************************/ + +#define MAX_PACKET_SIZE0 64 /**< maximum packet size for EP 0 */ +//Note: for FS this should be 8, 16, 32, 64 bytes. HS can go up to 512. + +/************************************************************************* + * USB application interface + **************************************************************************/ + +/** setup packet definitions */ +struct usb_setup_packet { + uint8_t bmRequestType; /**< characteristics of the specific request */ + uint8_t bRequest; /**< specific request */ + uint16_t wValue; /**< request specific parameter */ + uint16_t wIndex; /**< request specific parameter */ + uint16_t wLength; /**< length of data transferred in data phase */ +} __packed; + + +_Static_assert(sizeof(struct usb_setup_packet) == 8, "USB setup packet struct size error"); + +/** + * Callback function signature for the device + */ +typedef void (*usb_status_callback)(enum usb_dc_status_code status_code, + uint8_t *param); + +/** + * Callback function signature for the USB Endpoint status + */ +typedef void (*usb_ep_callback)(uint8_t ep, + enum usb_dc_ep_cb_status_code cb_status); + +/** + * Function which handles Class specific requests corresponding to an + * interface number specified in the device descriptor table + */ +typedef int (*usb_request_handler) (struct usb_setup_packet *detup, + int32_t *transfer_len, uint8_t **payload_data); + +/** + * Function for interface runtime configuration + */ +typedef void (*usb_interface_config)(uint8_t bInterfaceNumber); + +/* + * USB Endpoint Configuration + */ +struct usb_ep_cfg_data { + /** + * Callback function for notification of data received and + * available to application or transmit done, NULL if callback + * not required by application code + */ + usb_ep_callback ep_cb; + /** + * The number associated with the EP in the device configuration + * structure + * IN EP = 0x80 | \ + * OUT EP = 0x00 | \ + */ + uint8_t ep_addr; +}; + +/** + * USB Interface Configuration + */ +struct usb_interface_cfg_data { + /** Handler for USB Class specific Control (EP 0) communications */ + usb_request_handler class_handler; + /** Handler for USB Vendor specific commands */ + usb_request_handler vendor_handler; + /** + * The custom request handler gets a first chance at handling + * the request before it is handed over to the 'chapter 9' request + * handler + */ + usb_request_handler custom_handler; + /** + * This data area, allocated by the application, is used to store + * Class specific command data and must be large enough to store the + * largest payload associated with the largest supported Class' + * command set. This data area may be used for USB IN or OUT + * communications + */ + uint8_t *payload_data; + /** + * This data area, allocated by the application, is used to store + * Vendor specific payload + */ + uint8_t *vendor_data; +}; + +/* + * @brief USB device configuration + * + * The Application instantiates this with given parameters added + * using the "usb_set_config" function. Once this function is called + * changes to this structure will result in undefined behaviour. This structure + * may only be updated after calls to usb_deconfig + */ +struct usb_cfg_data { + /** + * USB device description, see + * http://www.beyondlogic.org/usbnutshell/usb5.shtml#DeviceDescriptors + */ + const uint8_t *usb_device_description; + /** Pointer to interface descriptor */ + const void *interface_descriptor; + /** Function for interface runtime configuration */ + usb_interface_config interface_config; + /** Callback to be notified on USB connection status change */ + usb_status_callback cb_usb_status; + /** USB interface (Class) handler and storage space */ + struct usb_interface_cfg_data interface; + /** Number of individual endpoints in the device configuration */ + uint8_t num_endpoints; + /** + * Pointer to an array of endpoint structs of length equal to the + * number of EP associated with the device description, + * not including control endpoints + */ + struct usb_ep_cfg_data *endpoint; +}; + +/* + * @brief configure USB controller + * + * Function to configure USB controller. + * Configuration parameters must be valid or an error is returned + * + * @param[in] config Pointer to configuration structure + * + * @return 0 on success, negative errno code on fail + */ +int usb_set_config(struct usb_cfg_data *config); + +/* + * @brief return the USB device to it's initial state + * + * @return 0 on success, negative errno code on fail + */ +int usb_deconfig(void); + +/* + * @brief enable USB for host/device connection + * + * Function to enable USB for host/device connection. + * Upon success, the USB module is no longer clock gated in hardware, + * it is now capable of transmitting and receiving on the USB bus and + * of generating interrupts. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_enable(struct usb_cfg_data *config); + +/* + * @brief disable the USB device. + * + * Function to disable the USB device. + * Upon success, the specified USB interface is clock gated in hardware, + * it is no longer capable of generating interrupts. + * + * @return 0 on success, negative errno code on fail + */ +int usb_disable(void); + +/* + * @brief Check if a write to an in ep would block until there is enough space + * in the fifo + * + * @param[in] ep Endpoint address corresponding to the one listed in the + * device configuration table + * + * @return 0 if free to write, 1 if a write would block, negative errno code on fail + */ +int usb_write_would_block(uint8_t ep); + +/* + * @brief write data to the specified endpoint + * + * Function to write data to the specified endpoint. The supplied + * usb_ep_callback will be called when transmission is done. + * + * @param[in] ep Endpoint address corresponding to the one listed in the + * device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of data requested to write. This may be zero for + * a zero length status packet. + * @param[out] bytes_ret Bytes written to the EP FIFO. This value may be NULL if + * the application expects all bytes to be written + * + * @return 0 on success, negative errno code on fail + */ +int usb_write(uint8_t ep, const uint8_t *data, uint32_t data_len, + uint32_t *bytes_ret); + +/* + * @brief read data from the specified endpoint + * + * This function is called by the Endpoint handler function, after an + * OUT interrupt has been received for that EP. The application must + * only call this function through the supplied usb_ep_callback function. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * @param[in] data Pointer to data buffer to write to + * @param[in] max_data_len Max length of data to read + * @param[out] ret_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes available + * for read is returned. + * + * @return 0 on success, negative errno code on fail + */ +int usb_read(uint8_t ep, uint8_t *data, uint32_t max_data_len, + uint32_t *ret_bytes); + +/* + * @brief set STALL condition on the specified endpoint + * + * This function is called by USB device class handler code to set stall + * conditionin on endpoint. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * + * @return 0 on success, negative errno code on fail + */ +int usb_ep_set_stall(uint8_t ep); + + +/* + * @brief clears STALL condition on the specified endpoint + * + * This function is called by USB device class handler code to clear stall + * conditionin on endpoint. + * + * @param[in] ep Endpoint address corresponding to the one listed in + * the device configuration table + * + * @return 0 on success, negative errno code on fail + */ +int usb_ep_clear_stall(uint8_t ep); + +/** + * @brief read data from the specified endpoint + * + * This is similar to usb_ep_read, the difference being that, it doesn't + * clear the endpoint NAKs so that the consumer is not bogged down by further + * upcalls till he is done with the processing of the data. The caller should + * reactivate ep by invoking usb_ep_read_continue() do so. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data pointer to data buffer to write to + * @param[in] max_data_len max length of data to read + * @param[out] read_bytes Number of bytes read. If data is NULL and + * max_data_len is 0 the number of bytes + * available for read should be returned. + * + * @return 0 on success, negative errno code on fail. + */ +int usb_ep_read_wait(uint8_t ep, uint8_t *data, uint32_t max_data_len, + uint32_t *read_bytes); + + +/** + * @brief Continue reading data from the endpoint + * + * Clear the endpoint NAK and enable the endpoint to accept more data + * from the host. Usually called after usb_ep_read_wait() when the consumer + * is fine to accept more data. Thus these calls together acts as flow control + * mechanism. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +int usb_ep_read_continue(uint8_t ep); + +/** + * Callback function signature for transfer completion. + */ +typedef void (*usb_transfer_callback)(uint8_t ep, int tsize, void *priv); + +/* USB transfer flags */ +#define USB_TRANS_READ BIT(0) /** Read transfer flag */ +#define USB_TRANS_WRITE BIT(1) /** Write transfer flag */ +#define USB_TRANS_NO_ZLP BIT(2) /** No zero-length packet flag */ + +/** + * @brief Transfer management endpoint callback + * + * If a USB class driver wants to use high-level transfer functions, driver + * needs to register this callback as usb endpoint callback. + */ +void usb_transfer_ep_callback(uint8_t ep, enum usb_dc_ep_cb_status_code); + +/** + * @brief Start a transfer + * + * Start a usb transfer to/from the data buffer. This function is asynchronous + * and can be executed in IRQ context. The provided callback will be called + * on transfer completion (or error) in thread context. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write-to/read-from + * @param[in] dlen Size of data buffer + * @param[in] flags Transfer flags (USB_TRANS_READ, USB_TRANS_WRITE...) + * @param[in] cb Function called on transfer completion/failure + * @param[in] priv Data passed back to the transfer completion callback + * + * @return 0 on success, negative errno code on fail. + */ +int usb_transfer(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags, + usb_transfer_callback cb, void *priv); + +/** + * @brief Start a transfer and block-wait for completion + * + * Synchronous version of usb_transfer, wait for transfer completion before + * returning. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data buffer to write-to/read-from + * @param[in] dlen Size of data buffer + * @param[in] flags Transfer flags + + * + * @return number of bytes transferred on success, negative errno code on fail. + */ +int usb_transfer_sync(uint8_t ep, uint8_t *data, size_t dlen, unsigned int flags); + +/** + * @brief Cancel any ongoing transfer on the specified endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return 0 on success, negative errno code on fail. + */ +void usb_cancel_transfer(uint8_t ep); + + +void usb_dev_resume(int configuration); +int usb_dev_get_configuration(void); + + +#ifdef __cplusplus +} +#endif + diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_dfu.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_dfu.h new file mode 100644 index 00000000..dec7ea93 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_dfu.h @@ -0,0 +1,147 @@ +/*************************************************************************** + * + * Copyright(c) 2015,2016 Intel Corporation. + * Copyright(c) 2017 PHYTEC Messtechnik GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/** + * @file + * @brief USB Device Firmware Upgrade (DFU) public header + * + * Header follows the Device Class Specification for + * Device Firmware Upgrade Version 1.1 + */ + +#pragma once + +#include +#include +#include "usb_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** DFU Class Subclass */ +#define DFU_SUBCLASS 0x01 + +/** DFU Class runtime Protocol */ +#define DFU_RT_PROTOCOL 0x01 + +/** DFU Class DFU mode Protocol */ +#define DFU_MODE_PROTOCOL 0x02 + +/** + * @brief DFU Class Specific Requests + */ +#define DFU_DETACH 0x00 +#define DFU_DNLOAD 0x01 +#define DFU_UPLOAD 0x02 +#define DFU_GETSTATUS 0x03 +#define DFU_CLRSTATUS 0x04 +#define DFU_GETSTATE 0x05 +#define DFU_ABORT 0x06 + +/** DFU FUNCTIONAL descriptor type */ +#define DFU_FUNC_DESC 0x21 + +/** DFU attributes DFU Functional Descriptor */ +#define DFU_ATTR_WILL_DETACH 0x08 +#define DFU_ATTR_MANIFESTATION_TOLERANT 0x04 +#define DFU_ATTR_CAN_UPLOAD 0x02 +#define DFU_ATTR_CAN_DNLOAD 0x01 + +/** DFU Specification release */ +#define DFU_VERSION 0x0110 + +/** Run-Time Functional Descriptor */ +struct dfu_runtime_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bmAttributes; + uint16_t wDetachTimeOut; + uint16_t wTransferSize; + uint16_t bcdDFUVersion; +} __packed; + +/** bStatus values for the DFU_GETSTATUS response */ +enum dfu_status { + statusOK, + errTARGET, + errFILE, + errWRITE, + errERASE, + errCHECK_ERASED, + errPROG, + errVERIFY, + errADDRESS, + errNOTDONE, + errFIRMWARE, + errVENDOR, + errUSB, + errPOR, + errUNKNOWN, + errSTALLEDPKT +}; + +/** bState values for the DFU_GETSTATUS response */ +enum dfu_state { + appIDLE, + appDETACH, + dfuIDLE, + dfuDNLOAD_SYNC, + dfuDNBUSY, + dfuDNLOAD_IDLE, + dfuMANIFEST_SYNC, + dfuMANIFEST, + dfuMANIFEST_WAIT_RST, + dfuUPLOAD_IDLE, + dfuERROR, +}; + +/* + These callbacks are made public so the ACM driver can call them to handle the switch to DFU. +*/ + +int dfu_class_handle_req(struct usb_setup_packet *pSetup, + int32_t *data_len, uint8_t **data); +void dfu_status_cb(enum usb_dc_status_code status, uint8_t *param); +int usb_dfu_init(void); +int dfu_custom_handle_req(struct usb_setup_packet *pSetup, + int32_t *data_len, uint8_t **data); + + +typedef void(*usb_dfu_detach_routine_t)(int delay); +void usb_dfu_set_detach_cb(usb_dfu_detach_routine_t cb); + + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h new file mode 100644 index 00000000..74d9b2a7 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h @@ -0,0 +1,40 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef void(*usb_osglue_intdisena_routine_t)(void); +typedef int(*usb_osglue_wait_routine_t)(int delay_us); + +typedef struct { + /* Disable USB interrupt */ + usb_osglue_intdisena_routine_t int_dis_proc; + /* Enable USB interrupt */ + usb_osglue_intdisena_routine_t int_ena_proc; + /* Wait for a set amount of uS. Return the amount actually waited. If delay_us is 0, just yield.*/ + usb_osglue_wait_routine_t wait_proc; +} usb_osglue_data_t; + +extern usb_osglue_data_t rom_usb_osglue; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_persist.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_persist.h new file mode 100644 index 00000000..bcf11b7c --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/usb/usb_persist.h @@ -0,0 +1,50 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// USB persistence flags. + +//This bit indicates persistence has been enabled, that is, the USB initialization routines should not +//reset the USB device as the device still is initialized and the host detected it with the same cdcacm/dfu +//descriptor as the ROM uses; we can just re-initialize the software side and have at 'er. +#define USBDC_PERSIST_ENA (1<<31) + +//This bit indicates to the ROM that we rebooted because of a request to go into DFU mode; the ROM should +//honour this request. +#define USBDC_BOOT_DFU (1<<30) + + +//This being non-0 indicates a memory location where a 'testament' is stored, aka a piece of text that should be output +//after a reboot. Can contain core dump info or something. +#define USBDC_TESTAMENT_LOC_MASK 0x7FFFF //bits 19-0; this is added to a base address of 0x3FF80000. + +//The testament is a FIFO. The ROM will output all data between textstart and textend; if textend is lower than textstart it will +//output everything from textstart to memend, then memstart to textend. +typedef struct { + char *memstart; //start of memory region + char *memend; //end of memory region + char *textstart; //start of text to output + char *textend; +} usbdc_testament_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h new file mode 100644 index 00000000..432c65ef --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/aes.h @@ -0,0 +1,55 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define AES_BLOCK_SIZE (16) + +enum AES_TYPE { + AES_ENC, + AES_DEC, +}; + +enum AES_BITS { + AES128, + AES192, + AES256 +}; + +void ets_aes_enable(void); + +void ets_aes_disable(void); + +void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap, + bool in_word_swap, bool in_byte_swap, + bool out_word_swap, bool out_byte_swap); + +int ets_aes_setkey(enum AES_TYPE type, const void *key, enum AES_BITS bits); + +int ets_aes_setkey_enc(const void *key, enum AES_BITS bits); + +int ets_aes_setkey_dec(const void *key, enum AES_BITS bits); + +void ets_aes_block(const void *input, void *output); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/bigint.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/bigint.h new file mode 100644 index 00000000..2ab022d8 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/bigint.h @@ -0,0 +1,40 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void ets_bigint_enable(void); + +void ets_bigint_disable(void); + +int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); + +int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); + +int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); + +void ets_bigint_wait_finish(void); + +int ets_bigint_getz(uint32_t *z, uint32_t len_words); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/cache.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/cache.h new file mode 100644 index 00000000..0ec6308f --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/cache.h @@ -0,0 +1,1097 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 32768 +#define MIN_DCACHE_SIZE 32768 +#define MAX_DCACHE_SIZE 65536 +#define MIN_ICACHE_WAYS 4 +#define MAX_ICACHE_WAYS 8 +#define MIN_DCACHE_WAYS 4 +#define MAX_DCACHE_WAYS 4 +#define MAX_CACHE_WAYS 8 +#define MIN_CACHE_LINE_SIZE 16 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 2 +#define MIN_DCACHE_BANK_NUM 1 +#define MAX_DCACHE_BANK_NUM 2 +#define CACHE_MEMORY_BANK_NUM 4 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 +#define CACHE_MEMORY_DBANK_SIZE 0x8000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) +#define MAX_DTAG_BANK_ITEMS (MAX_DCACHE_SIZE / MAX_DCACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_DTAG_BLOCK_ITEMS (MAX_DCACHE_SIZE / MAX_DCACHE_BANK_NUM / MAX_DCACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_DTAG_BANK_SIZE (MAX_DTAG_BANK_ITEMS * TAG_SIZE) +#define MAX_DTAG_BLOCK_SIZE (MAX_DTAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_DCACHE = 0, + CACHE_ICACHE0 = 1, + CACHE_ICACHE1 = 2, +} cache_t; + +typedef enum { + CACHE_MEMORY_INVALID = 0, + CACHE_MEMORY_IBANK0 = BIT(0), + CACHE_MEMORY_IBANK1 = BIT(1), + CACHE_MEMORY_IBANK2 = BIT(2), + CACHE_MEMORY_IBANK3 = BIT(3), + CACHE_MEMORY_DBANK0 = BIT(0), + CACHE_MEMORY_DBANK1 = BIT(1), + CACHE_MEMORY_DBANK2 = BIT(2), + CACHE_MEMORY_DBANK3 = BIT(3), +} cache_array_t; + +#define ICACHE_SIZE_16KB CACHE_SIZE_HALF +#define ICACHE_SIZE_32KB CACHE_SIZE_FULL +#define DCACHE_SIZE_32KB CACHE_SIZE_HALF +#define DCACHE_SIZE_64KB CACHE_SIZE_FULL + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid: 1; /*!< the tag item is valid or not */ + uint32_t lock: 1; /*!< the cache line is locked or not */ + uint32_t attr: 4; /*!< the attribute of the external memory physical address */ + uint32_t fifo_cnt: 3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag: 14; /*!< the tag is the high part of the cache address, however is only 64MB range, and without low part */ + uint32_t reserved: 9; +}; + +struct dcache_tag_item { + uint32_t dirty: 1; /*!< the cache line value is dirty or not */ + uint32_t valid: 1; /*!< the tag item is valid or not */ + uint32_t lock: 1; /*!< the cache line is locked or not */ + uint32_t occupy: 1; /*!< the cache line is occupied as internal sram */ + uint32_t attr: 4; /*!< the attribute of the external memory physical address */ + uint32_t fifo_cnt: 2; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag: 13; /*!< the tag is the high part of the cache address, however is only 64MB range, and without low part */ + uint32_t reserved: 9; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Count the pages in the bus room address which map to Flash. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus to count with. + * + * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. + * + * return uint32_t : the number of pages which map to Flash. + */ +uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t *page0_mapped); + +/** + * @brief Copy Instruction or rodata from Flash to SPIRAM, and remap to SPIRAM. + * Please do not call this function in your SDK application. + * + * @param uint32_t bus : the bus which need to copy to SPIRAM. + * + * @param uint32_t bus_start_addr : the start virtual address for the bus. + * + * @param uint32_t start_page : the start (64KB) page number in SPIRAM. + * + * @param uint32_t * page0_page : the flash page0 in SPIRAM page number, 0xffff for invalid. + * + * return uint32_t : the next start page number for SPIRAM not mapped. + */ +uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus, uint32_t bus_start_addr, uint32_t start_page, uint32_t *page0_page); + +/** + * @brief allocate memory to used by ICache. + * Please do not call this function in your SDK application. + * + * @param cache_array_t icache_low : the data array bank used by icache low part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1 + * + * @param cache_array_t icache_high : the data array bank used by icache high part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0, CACHE_MEMORY_IBANK1 only if icache_low and icache_high is not CACHE_MEMORY_INVALID + * + * return none + */ +void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low, cache_array_t icache_high); + +/** + * @brief allocate memory to used by DCache. + * Please do not call this function in your SDK application. + * + * @param cache_array_t dcache_low : the data array bank used by dcache low part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1 + * + * @param cache_array_t dcache1_high : the data array bank used by dcache high part, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_DBANK0, CACHE_MEMORY_DBANK1 only if dcache_low0 and dcache_low1 is not CACHE_MEMORY_INVALID + * + * return none + */ +void Cache_Occupy_DCache_MEMORY(cache_array_t dcache_low, cache_array_t dcache_high); + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode *mode); + +/** + * @brief set ICache modes: cache size, associate ways and cache line size. + * Please do not call this function in your SDK application. + * + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL + * + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B + * + * return none + */ +void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); + +/** + * @brief set DCache modes: cache size, associate ways and cache line size. + * Please do not call this function in your SDK application. + * + * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB + * + * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC + * + * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B + * + * return none + */ +void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); + +/** + * @brief check if the address is accessed through ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through ICache, 0 if not. + */ +uint32_t Cache_Address_Through_ICache(uint32_t addr); + +/** + * @brief check if the address is accessed through DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : the address to check. + * + * @return 1 if the address is accessed through DCache, 0 if not. + */ +uint32_t Cache_Address_Through_DCache(uint32_t addr); + +/** + * @brief Init mmu owner register to make i/d cache use half mmu entries. + * + * @param None + * + * @return None + */ +void Cache_Owner_Init(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Clean the dirty bit of cache Items of DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to Clean + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Clean_Items(uint32_t addr, uint32_t items); + +/** + * @brief Write back the cache items of DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to write back + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_WriteBack_Items(uint32_t addr, uint32_t items); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Clean the dirty bit of Cache items in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : cleaned region start address. + * + * @param uint32_t size : cleaned region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Clean_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Writeback the Cache items(also clean the dirty bit) in the region from DCache. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : writeback region start address. + * + * @param uint32_t size : writeback region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_WriteBack_Addr(uint32_t addr, uint32_t size); + + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_ICache_All(void); + +/** + * @brief Invalidate all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_DCache_All(void); + +/** + * @brief Clean the dirty bit of all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Clean_All(void); + +/** + * @brief WriteBack all cache items in DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_WriteBack_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief UnMask DRam0 bus through DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_UnMask_Dram0(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_ICache_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_ICache_Autoload(uint32_t autoload); + +/** + * @brief Suspend DCache auto preload operation, then you can resume it after some DCache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for DCache not auto preload before suspend. + */ +uint32_t Cache_Suspend_DCache_Autoload(void); + +/** + * @brief Resume DCache auto preload operation after some DCache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for DCache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_DCache_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_ICache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_ICache_Preload(uint32_t autoload); + +/** + * @brief Start an DCache manual preload, will suspend auto preload of DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of DCache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for DCache not auto preload before manual preload. + */ +uint32_t Cache_Start_DCache_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the DCache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for DCache manual preload not done. + */ +uint32_t Cache_DCache_Preload_Done(void); + +/** + * @brief End the DCache manual preload to resume auto preload of DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for DCache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_DCache_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_ICache_Autoload(const struct autoload_config *config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_ICache_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_ICache_Autoload(void); + +/** + * @brief Config autoload parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_DCache_Autoload(const struct autoload_config *config); + +/** + * @brief Enable auto preload for DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_DCache_Autoload(void); + +/** + * @brief Disable auto preload for DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_DCache_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_ICache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_ICache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Config a group of prelock parameters of DCache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ +void Cache_Enable_DCache_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for DCache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_DCache_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Lock_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Unlock the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to unlock + * + * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Unlock_DCache_Items(uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_ICache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_ICache(uint32_t autoload); + +/** + * @brief Disable DCache access for the cpu. + * This operation will make all DCache tag memory invalid, CPU can't access DCache, DCache will keep idle + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_DCache(void); + +/** + * @brief Enable DCache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : DCache will preload then. + * + * @return None + */ +void Cache_Enable_DCache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_ICache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_ICache(uint32_t autoload); + +/** + * @brief Suspend DCache access for the cpu. + * The ICache tag memory is still there, CPU can't access DCache, DCache will keep idle. + × Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_DCache(void); + +/** + * @brief Resume DCache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : DCache will preload then. + * + * @return None + */ +void Cache_Resume_DCache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_ICache_Line_Size(void); + +/** + * @brief Get DCache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_DCache_Line_Size(void); + +/** + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +void Cache_Set_Default_Mode(void); + +/** + * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. + * + * @param None + * + * @return None + */ +void Cache_Enable_Defalut_ICache_Mode(void); + +/** + * @brief Occupy the cache items for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of occupy region + * + * @param uint32_t items : cache lines to occupy, items * cache_line_size should not exceed the cache_size + * + * @return None + */ +void Cache_Occupy_Items(uint32_t addr, uint32_t items); + +/** + * @brief Occupy the cache addr for DCache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in DCache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of occupy region + * + * @param uint32_t size : size of occupy region, size should not exceed the cache_size + */ +int Cache_Occupy_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_ICache_Disable(void); + +/** + * @brief Enable freeze for DCache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for DCache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_DCache_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode *mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @brief Get cache memory block base address. + * Please do not call this function in your SDK application. + * + * @param uint32_t icache : 0 for dcache, other for icache. + * + * @param uint32_t bank_no : 0 ~ 3 bank. + * + * @return uint32_t : the cache memory block base address, 0 if the block not used. + */ +uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no); + +/** + * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); + +/** + * @brief Get the cache memory value by DRAM address. + * Please do not call this function in your SDK application. + * + * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Used by SPI flash mmap + * + */ +int flash2spiram_instruction_offset(void); +int flash2spiram_rodata_offset(void); +uint32_t flash_instr_rodata_start_page(uint32_t bus); +uint32_t flash_instr_rodata_end_page(uint32_t bus); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/crc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/crc.h new file mode 100644 index 00000000..e47a2ff5 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/crc.h @@ -0,0 +1,122 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup crc_apis, uart configuration and communication related apis + * @brief crc apis + */ + +/** @addtogroup crc_apis + * @{ + */ + +/* Standard CRC8/16/32 algorithms. */ +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/digital_signature.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/digital_signature.h new file mode 100644 index 00000000..36e71e7c --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/digital_signature.h @@ -0,0 +1,142 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ETS_DS_IV_LEN 16 + +/* Length of parameter 'C' stored in flash */ +#define ETS_DS_C_LEN (12672 / 8) + +/* Encrypted ETS data. Recommended to store in flash in this format. + */ +typedef struct { + /* RSA LENGTH register parameters + * (number of words in RSA key & operands, minus one). + * + * Max value 127 (for RSA 4096). + * + * This value must match the length field encrypted and stored in 'c', + * or invalid results will be returned. (The DS peripheral will + * always use the value in 'c', not this value, so an attacker can't + * alter the DS peripheral results this way, it will just truncate or + * extend the message and the resulting signature in software.) + */ + unsigned rsa_length; + + /* IV value used to encrypt 'c' */ + uint8_t iv[ETS_DS_IV_LEN]; + + /* Encrypted Digital Signature parameters. Result of AES-CBC encryption + of plaintext values. Includes an encrypted message digest. + */ + uint8_t c[ETS_DS_C_LEN]; +} ets_ds_data_t; + +typedef enum { + ETS_DS_OK, + ETS_DS_INVALID_PARAM, /* Supplied parameters are invalid */ + ETS_DS_INVALID_KEY, /* HMAC peripheral failed to supply key */ + ETS_DS_INVALID_PADDING, /* 'c' decrypted with invalid padding */ + ETS_DS_INVALID_DIGEST, /* 'c' decrypted with invalid digest */ +} ets_ds_result_t; + +void ets_ds_enable(void); + +void ets_ds_disable(void); + +/* + * @brief Start signing a message (or padded message digest) using the Digital Signature peripheral + * + * - @param message Pointer to message (or padded digest) containing the message to sign. Should be + * (data->rsa_length + 1)*4 bytes long. @param data Pointer to DS data. Can be a pointer to data + * in flash. + * + * Caller must have already called ets_ds_enable() and ets_hmac_calculate_downstream() before calling + * this function, and is responsible for calling ets_ds_finish_sign() and then + * ets_hmac_invalidate_downstream() afterwards. + * + * @return ETS_DS_OK if signature is in progress, ETS_DS_INVALID_PARAM if param is invalid, + * EST_DS_INVALID_KEY if key or HMAC peripheral is configured incorrectly. + */ +ets_ds_result_t ets_ds_start_sign(const void *message, const ets_ds_data_t *data); + + +/* + * @brief Returns true if the DS peripheral is busy following a call to ets_ds_start_sign() + * + * A result of false indicates that a call to ets_ds_finish_sign() will not block. + * + * Only valid if ets_ds_enable() has been called. + */ +bool ets_ds_is_busy(void); + + +/* @brief Finish signing a message using the Digital Signature peripheral + * + * Must be called after ets_ds_start_sign(). Can use ets_ds_busy() to wait until + * peripheral is no longer busy. + * + * - @param signature Pointer to buffer to contain the signature. Should be + * (data->rsa_length + 1)*4 bytes long. + * - @param data Should match the 'data' parameter passed to ets_ds_start_sign() + * + * @param ETS_DS_OK if signing succeeded, ETS_DS_INVALID_PARAM if param is invalid, + * ETS_DS_INVALID_DIGEST or ETS_DS_INVALID_PADDING if there is a problem with the + * encrypted data digest or padding bytes (in case of ETS_DS_INVALID_PADDING, a + * digest is produced anyhow.) + */ +ets_ds_result_t ets_ds_finish_sign(void *signature, const ets_ds_data_t *data); + + +/* Plaintext parameters used by Digital Signature. + + Not used for signing with DS peripheral, but can be encrypted + in-device by calling ets_ds_encrypt_params() +*/ +typedef struct { + uint32_t Y[4096 / 32]; + uint32_t M[4096 / 32]; + uint32_t Rb[4096 / 32]; + uint32_t M_prime; + uint32_t length; +} ets_ds_p_data_t; + +typedef enum { + ETS_DS_KEY_HMAC, /* The HMAC key (as stored in efuse) */ + ETS_DS_KEY_AES, /* The AES key (as derived from HMAC key by HMAC peripheral in downstream mode) */ +} ets_ds_key_t; + +/* @brief Encrypt DS parameters suitable for storing and later use with DS peripheral + * + * @param data Output buffer to store encrypted data, suitable for later use generating signatures. + * @param iv Pointer to 16 byte IV buffer, will be copied into 'data'. Should be randomly generated bytes each time. + * @param p_data Pointer to input plaintext key data. The expectation is this data will be deleted after this process is done and 'data' is stored. + * @param key Pointer to 32 bytes of key data. Type determined by key_type parameter. The expectation is the corresponding HMAC key will be stored to efuse and then permanently erased. + * @param key_type Type of key stored in 'key' (either the AES-256 DS key, or an HMAC DS key from which the AES DS key is derived using HMAC peripheral) + * + * @return ETS_DS_INVALID_PARAM if any parameter is invalid, or ETS_DS_OK if 'data' is successfully generated from the input parameters. + */ +ets_ds_result_t ets_ds_encrypt_params(ets_ds_data_t *data, const void *iv, const ets_ds_p_data_t *p_data, const void *key, ets_ds_key_t key_type); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/efuse.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/efuse.h new file mode 100644 index 00000000..cbe38e6a --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/efuse.h @@ -0,0 +1,391 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief set timing accroding the apb clock, so no read error or write error happens. + * + * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M. + * + * @return : 0 if success, others if clock not accepted + */ +int ets_efuse_set_timing(uint32_t clock); + +/** + * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again. + */ +void ets_efuse_start(void); + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read spi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - 1 for default HSPI pins. + * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK, + * EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * WP pin (for quad I/O modes) is not saved in efuse and not returned by this function. + */ +uint32_t ets_efuse_get_spiconfig(void); + +/** + * @brief Read spi flash wp pad from Efuse + * + * @return + * - 0x3f for invalid. + * - 0~46 is valid. + */ +uint32_t ets_efuse_get_wp_pad(void); + +/** + * @brief Read opi flash pads configuration from Efuse + * + * @return + * - 0 for default SPI pins. + * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for: + * DQS, D4, D5, D6, D7 accordingly. + */ +uint32_t ets_efuse_get_opiconfig(void); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if legacy spi flash boot mode disabled from Efuse + * + * @return + * - true for efuse disable legacy spi flash boot mode. + * - false for efuse doesn't disable legacy spi flash boot mode. + */ +bool ets_efuse_legacy_spi_boot_mode_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO46 is low when digital reset. + * 2 for uart print when GPIO46 is high when digital reset. + * 3 for uart force slient + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read which channel will used by ROM to print + * + * @return + * - 0 for UART0. + * - 1 for UART1. + */ +uint32_t ets_efuse_get_uart_print_channel(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if tiny basic mode disabled from Efuse + * + * @return + * - true for efuse disable tiny basic mode. + * - false for efuse doesn't disable tiny basic mode. + */ +bool ets_efuse_tiny_basic_mode_disabled(void); + +/** + * @brief Read if usb module disabled from Efuse + * + * @return + * - true for efuse disable usb module. + * - false for efuse doesn't disable usb module. + */ +bool ets_efuse_usb_module_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, PSRAM, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates an external phy needs to be used for USB + */ +bool ets_efuse_usb_use_ext_phy(void); + +/** + * @brief Return true if EFuse indicates USB device persistence is disabled + */ +bool ets_efuse_usb_force_nopersist(void); + +/** + * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU + */ +bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void); + +/** + * @brief Return true if EFuse indicates an opi flash is attached. + */ +bool ets_efuse_flash_opi_mode(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h new file mode 100644 index 00000000..edf9627c --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/ets_sys.h @@ -0,0 +1,654 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1 /**< return failed in ets*/ +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + +/** + * @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it. + * + * @param none + * + * @return none + */ +void ets_run(void); + +/** + * @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep. + * + * @param ets_idle_cb_t func : The callback function. + * + * @param void *arg : Argument of the callback. + * + * @return None + */ +void ets_set_idle_cb(ets_idle_cb_t func, void *arg); + +/** + * @brief Init a task with processer, priority, queue to receive Event, queue length. + * + * @param ETSTask task : The task processer. + * + * @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task. + * + * @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used. + * + * @param uint8_t qlen : Queue length. + * + * @return None + */ +void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen); + +/** + * @brief Post an event to an Task. + * + * @param uint8_t prio : Priority of the Task. + * + * @param ETSSignal sig : Event signal. + * + * @param ETSParam par : Event parameter + * + * @return ETS_OK : post successful + * @return ETS_FAILED : post failed + */ +ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par); + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code. + * When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run. + * + * @param uint32_t callback : the Startup code address value in uint32_t + * + * @return None : post successful + */ +void ets_set_startup_callback(uint32_t callback); + +/** + * @brief Set App cpu Entry code, code can be called in PRO CPU. + * When APP booting is completed, APP CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D. + * + * @return None + */ +void ets_set_appcpu_boot_addr(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Set the uart channel of ets_printf(uart_tx_one_char). + * ROM will set it base on the efuse and gpio setting, however, this can be changed after booting. + * + * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2. + * + * @return None + */ +void ets_set_printf_channel(uint8_t uart_no); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * + * @note This function only sets the tick rate for the current CPU. It is located in ROM, + * so the deep sleep stub can use it even if IRAM is not initialized yet. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if stored in efuse(not 0) + * clock = ets_efuse_get_xtal_freq() * 1000000; + * else if analog_8M in efuse + * clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock(); + * else clock = 40M. + */ +uint32_t ets_get_xtal_freq(void); + +/** + * @brief Get the apb divisor. The xtal frequency gets divided + * by this value to generate the APB clock. + * When any types of reset happens, the default value is 2. + * + * @param None + * + * @return uint32_t : 1 or 2. + */ +uint32_t ets_get_xtal_div(void); + + +/** + * @brief Modifies the apb divisor. The xtal frequency gets divided by this to + * generate the APB clock. + * + * @note The xtal frequency divisor is 2 by default as the glitch detector + * doesn't properly stop glitches when it is 1. Please do not set the + * divisor to 1 before the PLL is active without being aware that you + * may be introducing a security risk. + * + * @param div Divisor. 1 = xtal freq, 2 = 1/2th xtal freq. + */ +void ets_set_xtal_div(int div); + + +/** + * @brief Get apb_freq value, If value not stored in RTC_STORE5, than store. + * + * @param None + * + * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register. + * clock = (REG_READ(RTC_STORE5) & 0xffff) << 12; + * else store ets_get_detected_xtal_freq() in. + */ +uint32_t ets_get_apb_freq(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + +/** + * @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt). + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_waiti0(void); + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +#define _ETSTR(v) # v +#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ + __asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \ + : "=a" (__tmp) : : "memory" ); \ + }) + +#ifdef CONFIG_NONE_OS +#define ETS_INTR_LOCK() \ + ets_intr_lock() + +#define ETS_INTR_UNLOCK() \ + ets_intr_unlock() + +#define ETS_ISR_ATTACH \ + ets_isr_attach + +#define ETS_INTR_ENABLE(inum) \ + ets_isr_unmask((1< +#include +#include "soc/gpio_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +#define GPIO_FUNC_IN_HIGH 0x38 +#define GPIO_FUNC_IN_LOW 0x3C + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEDGE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + +#define GPIO_OUTPUT_SET(gpio_no, bit_value) \ + ((gpio_no < 32) ? gpio_output_set(bit_value<>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0)) + +/* GPIO interrupt handler, registered through gpio_intr_handler_register */ +typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg); + +/** + * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet + * to initialize "output enables" and pin configurations for each gpio pin. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_init(void); + +/** + * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask. + * + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32. + */ +uint32_t gpio_input_get_high(void); + +/** + * @brief Register an application-specific interrupt handler for GPIO pin interrupts. + * Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack. + * Please do not call this function in SDK. + * + * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler + * + * @param void *arg : gpio application-specific interrupt handler argument. + * + * @return None + */ +void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0. + */ +uint32_t gpio_intr_pending(void); + +/** + * @brief Get gpio interrupts which happens but not processed. + * Please do not call this function in SDK. + * + * @param None + * + * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32. + */ +uint32_t gpio_intr_pending_high(void); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0. + * + * @return None + */ +void gpio_intr_ack(uint32_t ack_mask); + +/** + * @brief Ack gpio interrupts to process pending interrupts. + * Please do not call this function in SDK. + * + * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32. + * + * @return None + */ +void gpio_intr_ack_high(uint32_t ack_mask); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~0x2f + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x100, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_select_gpio(uint32_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_pullup(uint32_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_pulldown(uint32_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~0x2f + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/hmac.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/hmac.h new file mode 100644 index 00000000..ac7ddf35 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/hmac.h @@ -0,0 +1,59 @@ +// Copyright 2018-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "efuse.h" + +void ets_hmac_enable(void); + +void ets_hmac_disable(void); + +/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP) + to digest a message. +*/ +int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac); + +/* Calculate a downstream HMAC message to temporarily enable JTAG, or + to generate a Digital Signature data decryption key. + + - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE + or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG + + - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6. + This efuse block must have the corresponding purpose set in "purpose", or + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL. + + The result of this HMAC calculation is only made available "downstream" to the + corresponding hardware module, and cannot be accessed by software. +*/ +int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose); + +/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream(). + * + * - purpose must match a previous call to ets_hmac_calculate_downstream(). + * + * After this function is called, the corresponding internal operation (JTAG or DS) will no longer + * have access to the generated key. + */ +int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/libc_stubs.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/libc_stubs.h new file mode 100644 index 00000000..9c9b0a21 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/libc_stubs.h @@ -0,0 +1,87 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ESP32-S3 ROM code contains implementations of some of C library functions. + * Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall + * implementation defined in the following struct. + * + * The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and + * `syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU) + * and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script. + * + * So, before using any of the C library functions (except for pure functions and memcpy/memset functions), + * application must allocate syscall table structure for each CPU being used, and populate it with pointers + * to actual implementations of corresponding syscalls. + * + */ +struct syscall_stub_table { + struct _reent *(*__getreent)(void); + void *(*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void *); + void *(*_realloc_r)(struct _reent *r, void *, size_t); + void *(*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char *); + int (*_rename_r)(struct _reent *r, const char *, const char *); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char *); + int (*_link_r)(struct _reent *r, const char *, const char *); + int (*_stat_r)(struct _reent *r, const char *, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void *(*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); + void (*_lock_init)(_lock_t *lock); + void (*_lock_init_recursive)(_lock_t *lock); + void (*_lock_close)(_lock_t *lock); + void (*_lock_close_recursive)(_lock_t *lock); + void (*_lock_acquire)(_lock_t *lock); + void (*_lock_acquire_recursive)(_lock_t *lock); + int (*_lock_try_acquire)(_lock_t *lock); + int (*_lock_try_acquire_recursive)(_lock_t *lock); + void (*_lock_release)(_lock_t *lock); + void (*_lock_release_recursive)(_lock_t *lock); + int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); +}; + +extern struct syscall_stub_table *syscall_table_ptr; +#define syscall_table_ptr_pro syscall_table_ptr +#define syscall_table_ptr_app syscall_table_ptr + +#ifdef __cplusplus +} // extern "C" +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/lldesc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/lldesc.h new file mode 100644 index 00000000..ebd02016 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/lldesc.h @@ -0,0 +1,173 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "sys/queue.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LLDESC_TX_MBLK_SIZE 268 /* */ +#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ +#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ +#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ +#ifdef ESP_MAC_5 +#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ +#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 +#else +#ifdef SBUF_RXTX +#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ +#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ +#endif +#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ + +#ifdef IEEE80211_RX_AMPDU +#define LLDESC_RX_MBLK_NUM 30 +#else +#define LLDESC_RX_MBLK_NUM 10 +#endif /*IEEE80211_RX_AMPDU*/ + +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 +#endif /* !ESP_MAC_5 */ +/* + * SLC2 DMA Desc struct, aka lldesc_t + * + * -------------------------------------------------------------- + * | own | EoF | sub_sof | 5'b0 | length [11:0] | size [11:0] | + * -------------------------------------------------------------- + * | buf_ptr [31:0] | + * -------------------------------------------------------------- + * | next_desc_ptr [31:0] | + * -------------------------------------------------------------- + */ + +/* this bitfield is start from the LSB!!! */ +typedef struct lldesc_s { + volatile uint32_t size : 12, + length: 12, + offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */ + sosf : 1, /* start of sub-frame */ + eof : 1, /* end of frame */ + owner : 1; /* hw or sw */ + volatile uint8_t *buf; /* point to buffer data */ + union { + volatile uint32_t empty; + STAILQ_ENTRY(lldesc_s) qe; /* pointing to the next desc */ + }; +} lldesc_t; + +typedef struct tx_ampdu_entry_s { + uint32_t sub_len : 12, + dili_num : 7, + : 1, + null_byte: 2, + data : 1, + enc : 1, + seq : 8; +} tx_ampdu_entry_t; + +typedef struct lldesc_chain_s { + lldesc_t *head; + lldesc_t *tail; +} lldesc_chain_t; + +#ifdef SBUF_RXTX +enum sbuf_mask_s { + SBUF_MOVE_NO = 0, + SBUF_MOVE_TX2RX, + SBUF_MOVE_RX2TX, +} ; + +#define SBUF_MOVE_STEP 8 +#endif +#define LLDESC_SIZE sizeof(struct lldesc_s) + +/* SLC Descriptor */ +#define LLDESC_OWNER_MASK 0x80000000 +#define LLDESC_OWNER_SHIFT 31 +#define LLDESC_SW_OWNED 0 +#define LLDESC_HW_OWNED 1 + +#define LLDESC_EOF_MASK 0x40000000 +#define LLDESC_EOF_SHIFT 30 + +#define LLDESC_SOSF_MASK 0x20000000 +#define LLDESC_SOSF_SHIFT 29 + +#define LLDESC_LENGTH_MASK 0x00fff000 +#define LLDESC_LENGTH_SHIFT 12 + +#define LLDESC_SIZE_MASK 0x00000fff +#define LLDESC_SIZE_SHIFT 0 + +#define LLDESC_ADDR_MASK 0x000fffff + +void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner, + lldesc_t **head, +#ifdef TO_HOST_RESTART + lldesc_t **one_before_tail, +#endif + lldesc_t **tail); + +lldesc_t *lldesc_num2link(lldesc_t *head, uint16_t nblks); + +lldesc_t *lldesc_set_owner(lldesc_t *head, uint16_t nblks, uint8_t owner); + +static inline uint32_t lldesc_get_chain_length(lldesc_t *head) +{ + lldesc_t *ds = head; + uint32_t len = 0; + + while (ds) { + len += ds->length; + ds = STAILQ_NEXT(ds, qe); + } + + return len; +} + +static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) +{ + ds->owner = owner; + ds->eof = eof; + ds->sosf = sosf; + ds->length = len; +} + +#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) \ + do { \ + (_desc)->owner = (_owner); \ + (_desc)->eof = (_eof); \ + (_desc)->sosf = (_sosf); \ + (_desc)->length = (_len); \ + } while(0) + +#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) + +#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/md5_hash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/md5_hash.h new file mode 100644 index 00000000..8676ace2 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/md5_hash.h @@ -0,0 +1,35 @@ +/* + * MD5 internal definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +}; + +void MD5Init(struct MD5Context *context); +void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *context); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/miniz.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/miniz.h new file mode 100644 index 00000000..75535113 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/miniz.h @@ -0,0 +1,757 @@ +#pragma once + +#include + +// Defines to completely disable specific portions of miniz.c: +// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl. + +// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O. +#define MINIZ_NO_STDIO + +// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or +// get/set file times, and the C run-time funcs that get/set times won't be called. +// The current downside is the times written to your archives will be from 1979. +#define MINIZ_NO_TIME + +// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's. +#define MINIZ_NO_ARCHIVE_APIS + +// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's. +#define MINIZ_NO_ARCHIVE_WRITING_APIS + +// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's. +#define MINIZ_NO_ZLIB_APIS + +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib. +#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc. +// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc +// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user +// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work. +#define MINIZ_NO_MALLOC + +#if defined(__TINYC__) && (defined(__linux) || defined(__linux__)) +// TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux +#define MINIZ_NO_TIME +#endif + +#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS) +#include +#endif + +//Hardcoded options for Xtensa - JD +#define MINIZ_X86_OR_X64_CPU 0 +#define MINIZ_LITTLE_ENDIAN 1 +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0 +#define MINIZ_HAS_64BIT_REGISTERS 0 +#define TINFL_USE_64BIT_BITBUF 0 + + +#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__) +// MINIZ_X86_OR_X64_CPU is only used to help set the below macros. +#define MINIZ_X86_OR_X64_CPU 1 +#endif + +#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU +// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian. +#define MINIZ_LITTLE_ENDIAN 1 +#endif + +#if MINIZ_X86_OR_X64_CPU +// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses. +#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1 +#endif + +#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__) +// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions). +#define MINIZ_HAS_64BIT_REGISTERS 1 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// ------------------- zlib-style API Definitions. + +// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits! +typedef unsigned long mz_ulong; + +// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap. +void mz_free(void *p); + +#define MZ_ADLER32_INIT (1) +// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL. +mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len); + +#define MZ_CRC32_INIT (0) +// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL. +mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len); + +// Compression strategies. +enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 }; + +// Method +#define MZ_DEFLATED 8 + +#ifndef MINIZ_NO_ZLIB_APIS + +// Heap allocation callbacks. +// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long. +typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size); +typedef void (*mz_free_func)(void *opaque, void *address); +typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size); + +#define MZ_VERSION "9.1.15" +#define MZ_VERNUM 0x91F0 +#define MZ_VER_MAJOR 9 +#define MZ_VER_MINOR 1 +#define MZ_VER_REVISION 15 +#define MZ_VER_SUBREVISION 0 + +// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs). +enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 }; + +// Return status codes. MZ_PARAM_ERROR is non-standard. +enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 }; + +// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL. +enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 }; + +// Window bits +#define MZ_DEFAULT_WINDOW_BITS 15 + +struct mz_internal_state; + +// Compression/decompression stream struct. +typedef struct mz_stream_s { + const unsigned char *next_in; // pointer to next byte to read + unsigned int avail_in; // number of bytes available at next_in + mz_ulong total_in; // total number of bytes consumed so far + + unsigned char *next_out; // pointer to next byte to write + unsigned int avail_out; // number of bytes that can be written to next_out + mz_ulong total_out; // total number of bytes produced so far + + char *msg; // error msg (unused) + struct mz_internal_state *state; // internal state, allocated by zalloc/zfree + + mz_alloc_func zalloc; // optional heap allocation function (defaults to malloc) + mz_free_func zfree; // optional heap free function (defaults to free) + void *opaque; // heap alloc function user pointer + + int data_type; // data_type (unused) + mz_ulong adler; // adler32 of the source or uncompressed data + mz_ulong reserved; // not used +} mz_stream; + +typedef mz_stream *mz_streamp; + +// Returns the version string of miniz.c. +const char *mz_version(void); + +// mz_deflateInit() initializes a compressor with default options: +// Parameters: +// pStream must point to an initialized mz_stream struct. +// level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION]. +// level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio. +// (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.) +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if the input parameters are bogus. +// MZ_MEM_ERROR on out of memory. +int mz_deflateInit(mz_streamp pStream, int level); + +// mz_deflateInit2() is like mz_deflate(), except with more control: +// Additional parameters: +// method must be MZ_DEFLATED +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer) +// mem_level must be between [1, 9] (it's checked but ignored by miniz.c) +int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy); + +// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2(). +int mz_deflateReset(mz_streamp pStream); + +// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH. +// Return values: +// MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full). +// MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.) +int mz_deflate(mz_streamp pStream, int flush); + +// mz_deflateEnd() deinitializes a compressor: +// Return values: +// MZ_OK on success. +// MZ_STREAM_ERROR if the stream is bogus. +int mz_deflateEnd(mz_streamp pStream); + +// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH. +mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len); + +// Single-call compression functions mz_compress() and mz_compress2(): +// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure. +int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); +int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level); + +// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress(). +mz_ulong mz_compressBound(mz_ulong source_len); + +// Initializes a decompressor. +int mz_inflateInit(mz_streamp pStream); + +// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer: +// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate). +int mz_inflateInit2(mz_streamp pStream, int window_bits); + +// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible. +// Parameters: +// pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members. +// flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH. +// On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster). +// MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data. +// Return values: +// MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full. +// MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified. +// MZ_STREAM_ERROR if the stream is bogus. +// MZ_DATA_ERROR if the deflate stream is invalid. +// MZ_PARAM_ERROR if one of the parameters is invalid. +// MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again +// with more input data, or with more room in the output buffer (except when using single call decompression, described above). +int mz_inflate(mz_streamp pStream, int flush); + +// Deinitializes a decompressor. +int mz_inflateEnd(mz_streamp pStream); + +// Single-call decompression. +// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure. +int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len); + +// Returns a string description of the specified error code, or NULL if the error code is invalid. +const char *mz_error(int err); + +// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports. +// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project. +#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES +typedef unsigned char Byte; +typedef unsigned int uInt; +typedef mz_ulong uLong; +typedef Byte Bytef; +typedef uInt uIntf; +typedef char charf; +typedef int intf; +typedef void *voidpf; +typedef uLong uLongf; +typedef void *voidp; +typedef void *const voidpc; +#define Z_NULL 0 +#define Z_NO_FLUSH MZ_NO_FLUSH +#define Z_PARTIAL_FLUSH MZ_PARTIAL_FLUSH +#define Z_SYNC_FLUSH MZ_SYNC_FLUSH +#define Z_FULL_FLUSH MZ_FULL_FLUSH +#define Z_FINISH MZ_FINISH +#define Z_BLOCK MZ_BLOCK +#define Z_OK MZ_OK +#define Z_STREAM_END MZ_STREAM_END +#define Z_NEED_DICT MZ_NEED_DICT +#define Z_ERRNO MZ_ERRNO +#define Z_STREAM_ERROR MZ_STREAM_ERROR +#define Z_DATA_ERROR MZ_DATA_ERROR +#define Z_MEM_ERROR MZ_MEM_ERROR +#define Z_BUF_ERROR MZ_BUF_ERROR +#define Z_VERSION_ERROR MZ_VERSION_ERROR +#define Z_PARAM_ERROR MZ_PARAM_ERROR +#define Z_NO_COMPRESSION MZ_NO_COMPRESSION +#define Z_BEST_SPEED MZ_BEST_SPEED +#define Z_BEST_COMPRESSION MZ_BEST_COMPRESSION +#define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION +#define Z_DEFAULT_STRATEGY MZ_DEFAULT_STRATEGY +#define Z_FILTERED MZ_FILTERED +#define Z_HUFFMAN_ONLY MZ_HUFFMAN_ONLY +#define Z_RLE MZ_RLE +#define Z_FIXED MZ_FIXED +#define Z_DEFLATED MZ_DEFLATED +#define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS +#define alloc_func mz_alloc_func +#define free_func mz_free_func +#define internal_state mz_internal_state +#define z_stream mz_stream +#define deflateInit mz_deflateInit +#define deflateInit2 mz_deflateInit2 +#define deflateReset mz_deflateReset +#define deflate mz_deflate +#define deflateEnd mz_deflateEnd +#define deflateBound mz_deflateBound +#define compress mz_compress +#define compress2 mz_compress2 +#define compressBound mz_compressBound +#define inflateInit mz_inflateInit +#define inflateInit2 mz_inflateInit2 +#define inflate mz_inflate +#define inflateEnd mz_inflateEnd +#define uncompress mz_uncompress +#define crc32 mz_crc32 +#define adler32 mz_adler32 +#define MAX_WBITS 15 +#define MAX_MEM_LEVEL 9 +#define zError mz_error +#define ZLIB_VERSION MZ_VERSION +#define ZLIB_VERNUM MZ_VERNUM +#define ZLIB_VER_MAJOR MZ_VER_MAJOR +#define ZLIB_VER_MINOR MZ_VER_MINOR +#define ZLIB_VER_REVISION MZ_VER_REVISION +#define ZLIB_VER_SUBREVISION MZ_VER_SUBREVISION +#define zlibVersion mz_version +#define zlib_version mz_version() +#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES + +#endif // MINIZ_NO_ZLIB_APIS + +// ------------------- Types and macros + +typedef unsigned char mz_uint8; +typedef signed short mz_int16; +typedef unsigned short mz_uint16; +typedef unsigned int mz_uint32; +typedef unsigned int mz_uint; +typedef long long mz_int64; +typedef unsigned long long mz_uint64; +typedef int mz_bool; + +#define MZ_FALSE (0) +#define MZ_TRUE (1) + +// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message. +#ifdef _MSC_VER +#define MZ_MACRO_END while (0, 0) +#else +#define MZ_MACRO_END while (0) +#endif + +// ------------------- ZIP archive reading/writing + +#ifndef MINIZ_NO_ARCHIVE_APIS + +enum { + MZ_ZIP_MAX_IO_BUF_SIZE = 64 * 1024, + MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260, + MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256 +}; + +typedef struct { + mz_uint32 m_file_index; + mz_uint32 m_central_dir_ofs; + mz_uint16 m_version_made_by; + mz_uint16 m_version_needed; + mz_uint16 m_bit_flag; + mz_uint16 m_method; +#ifndef MINIZ_NO_TIME + time_t m_time; +#endif + mz_uint32 m_crc32; + mz_uint64 m_comp_size; + mz_uint64 m_uncomp_size; + mz_uint16 m_internal_attr; + mz_uint32 m_external_attr; + mz_uint64 m_local_header_ofs; + mz_uint32 m_comment_size; + char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE]; + char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE]; +} mz_zip_archive_file_stat; + +typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n); +typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n); + +struct mz_zip_internal_state_tag; +typedef struct mz_zip_internal_state_tag mz_zip_internal_state; + +typedef enum { + MZ_ZIP_MODE_INVALID = 0, + MZ_ZIP_MODE_READING = 1, + MZ_ZIP_MODE_WRITING = 2, + MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3 +} mz_zip_mode; + +typedef struct mz_zip_archive_tag { + mz_uint64 m_archive_size; + mz_uint64 m_central_directory_file_ofs; + mz_uint m_total_files; + mz_zip_mode m_zip_mode; + + mz_uint m_file_offset_alignment; + + mz_alloc_func m_pAlloc; + mz_free_func m_pFree; + mz_realloc_func m_pRealloc; + void *m_pAlloc_opaque; + + mz_file_read_func m_pRead; + mz_file_write_func m_pWrite; + void *m_pIO_opaque; + + mz_zip_internal_state *m_pState; + +} mz_zip_archive; + +typedef enum { + MZ_ZIP_FLAG_CASE_SENSITIVE = 0x0100, + MZ_ZIP_FLAG_IGNORE_PATH = 0x0200, + MZ_ZIP_FLAG_COMPRESSED_DATA = 0x0400, + MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800 +} mz_zip_flags; + +// ZIP archive reading + +// Inits a ZIP archive reader. +// These functions read and validate the archive's central directory. +mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags); +mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags); +#endif + +// Returns the total number of files in the archive. +mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip); + +// Returns detailed information about an archive file entry. +mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat); + +// Determines if an archive file entry is a directory entry. +mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index); +mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index); + +// Retrieves the filename of an archive file entry. +// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename. +mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size); + +// Attempts to locates a file in the archive's central directory. +// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH +// Returns -1 if the file cannot be found. +int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags); + +// Extracts a archive file to a memory buffer using no memory allocation. +mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); +mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size); + +// Extracts a archive file to a memory buffer. +mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags); + +// Extracts a archive file to a dynamically allocated heap buffer. +void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags); +void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags); + +// Extracts a archive file using a callback function to output the file's data. +mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags); + +#ifndef MINIZ_NO_STDIO +// Extracts a archive file to a disk file and sets its last accessed and modified times. +// This function only extracts files, not archive directory records. +mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags); +mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags); +#endif + +// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used. +mz_bool mz_zip_reader_end(mz_zip_archive *pZip); + +// ZIP archive writing + +#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +// Inits a ZIP archive writer. +mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size); +mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size); + +#ifndef MINIZ_NO_STDIO +mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning); +#endif + +// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive. +// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called. +// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it). +// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL. +// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before +// the archive is finalized the file's central directory will be hosed. +mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename); + +// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive. +// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags); +mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32); + +#ifndef MINIZ_NO_STDIO +// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); +#endif + +// Adds a file to an archive by fully cloning the data from another archive. +// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields. +mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index); + +// Finalizes the archive by writing the central directory records followed by the end of central directory record. +// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end(). +// An archive must be manually finalized by calling this function for it to be valid. +mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip); +mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize); + +// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used. +// Note for the archive to be valid, it must have been finalized before ending. +mz_bool mz_zip_writer_end(mz_zip_archive *pZip); + +// Misc. high-level helper functions: + +// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive. +// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION. +mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags); + +// Reads a single file from an archive into a heap block. +// Returns NULL on failure. +void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags); + +#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS + +#endif // #ifndef MINIZ_NO_ARCHIVE_APIS + +// ------------------- Low-level Decompression API Definitions + +// Decompression flags used by tinfl_decompress(). +// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream. +// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input. +// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB). +// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes. +enum { + TINFL_FLAG_PARSE_ZLIB_HEADER = 1, + TINFL_FLAG_HAS_MORE_INPUT = 2, + TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4, + TINFL_FLAG_COMPUTE_ADLER32 = 8 +}; + +// High level decompression functions: +// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress. +// On return: +// Function returns a pointer to the decompressed data, or NULL on failure. +// *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must call mz_free() on the returned block when it's no longer needed. +void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory. +// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success. +#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1)) +size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer. +// Returns 1 on success or 0 on failure. +typedef int (*tinfl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser); +int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor; + +// Max size of LZ dictionary. +#define TINFL_LZ_DICT_SIZE 32768 + +// Return status. +typedef enum { + TINFL_STATUS_BAD_PARAM = -3, + TINFL_STATUS_ADLER32_MISMATCH = -2, + TINFL_STATUS_FAILED = -1, + TINFL_STATUS_DONE = 0, + TINFL_STATUS_NEEDS_MORE_INPUT = 1, + TINFL_STATUS_HAS_MORE_OUTPUT = 2 +} tinfl_status; + +// Initializes the decompressor to its initial state. +#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END +#define tinfl_get_adler32(r) (r)->m_check_adler32 + +// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability. +// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output. +tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags); + +// Internal/private bits follow. +enum { + TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19, + TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS +}; + +typedef struct { + mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0]; + mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2]; +} tinfl_huff_table; + +#if MINIZ_HAS_64BIT_REGISTERS +#define TINFL_USE_64BIT_BITBUF 1 +#endif + +#if TINFL_USE_64BIT_BITBUF +typedef mz_uint64 tinfl_bit_buf_t; +#define TINFL_BITBUF_SIZE (64) +#else +typedef mz_uint32 tinfl_bit_buf_t; +#define TINFL_BITBUF_SIZE (32) +#endif + +struct tinfl_decompressor_tag { + mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES]; + tinfl_bit_buf_t m_bit_buf; + size_t m_dist_from_out_buf_start; + tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES]; + mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137]; +}; + +// ------------------- Low-level Compression API Definitions + +// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently). +#define TDEFL_LESS_MEMORY 1 + +// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search): +// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression). +enum { + TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF +}; + +// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data. +// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers). +// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing. +// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory). +// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1) +// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled. +// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables. +// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks. +// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK). +enum { + TDEFL_WRITE_ZLIB_HEADER = 0x01000, + TDEFL_COMPUTE_ADLER32 = 0x02000, + TDEFL_GREEDY_PARSING_FLAG = 0x04000, + TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000, + TDEFL_RLE_MATCHES = 0x10000, + TDEFL_FILTER_MATCHES = 0x20000, + TDEFL_FORCE_ALL_STATIC_BLOCKS = 0x40000, + TDEFL_FORCE_ALL_RAW_BLOCKS = 0x80000 +}; + +// High level compression functions: +// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc(). +// On entry: +// pSrc_buf, src_buf_len: Pointer and size of source block to compress. +// flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression. +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data. +// The caller must free() the returned block when it's no longer needed. +void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags); + +// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory. +// Returns 0 on failure. +size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags); + +// Compresses an image to a compressed PNG file in memory. +// On entry: +// pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. +// The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory. +// level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL +// If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps). +// On return: +// Function returns a pointer to the compressed data, or NULL on failure. +// *pLen_out will be set to the size of the PNG image file. +// The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed. +void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip); +void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out); + +// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time. +typedef mz_bool (*tdefl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser); + +// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally. +mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 }; + +// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes). +#if TDEFL_LESS_MEMORY +enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#else +enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS }; +#endif + +// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions. +typedef enum { + TDEFL_STATUS_BAD_PARAM = -2, + TDEFL_STATUS_PUT_BUF_FAILED = -1, + TDEFL_STATUS_OKAY = 0, + TDEFL_STATUS_DONE = 1, +} tdefl_status; + +// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums +typedef enum { + TDEFL_NO_FLUSH = 0, + TDEFL_SYNC_FLUSH = 2, + TDEFL_FULL_FLUSH = 3, + TDEFL_FINISH = 4 +} tdefl_flush; + +// tdefl's compression state structure. +typedef struct { + tdefl_put_buf_func_ptr m_pPut_buf_func; + void *m_pPut_buf_user; + mz_uint m_flags, m_max_probes[2]; + int m_greedy_parsing; + mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size; + mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end; + mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer; + mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish; + tdefl_status m_prev_return_status; + const void *m_pIn_buf; + void *m_pOut_buf; + size_t *m_pIn_buf_size, *m_pOut_buf_size; + tdefl_flush m_flush; + const mz_uint8 *m_pSrc; + size_t m_src_buf_left, m_out_buf_ofs; + mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1]; + mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS]; + mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE]; + mz_uint16 m_next[TDEFL_LZ_DICT_SIZE]; + mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE]; + mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE]; +} tdefl_compressor; + +// Initializes the compressor. +// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory. +// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression. +// If pBut_buf_func is NULL the user should always call the tdefl_compress() API. +// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.) +tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags); + +// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible. +tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush); + +// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr. +// tdefl_compress_buffer() always consumes the entire input buffer. +tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush); + +tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d); +mz_uint32 tdefl_get_adler32(tdefl_compressor *d); + +// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros. +#ifndef MINIZ_NO_ZLIB_APIS +// Create tdefl_compress() flags given zlib-style compression parameters. +// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files) +// window_bits may be -15 (raw deflate) or 15 (zlib) +// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED +mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy); +#endif // #ifndef MINIZ_NO_ZLIB_APIS + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rsa_pss.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rsa_pss.h new file mode 100644 index 00000000..b9ced67a --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rsa_pss.h @@ -0,0 +1,43 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_SIG_LEN 384 /* Bytes */ +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef struct { + uint8_t n[384]; /* Public key modulus */ + uint32_t e; /* Public key exponent */ + uint8_t rinv[384]; + uint32_t mdash; +} ets_rsa_pubkey_t; + +bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest); + +void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask); + +bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h new file mode 100644 index 00000000..15adc528 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/rtc.h @@ -0,0 +1,213 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include "ets_sys.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * RTC Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP + * + * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * RTC_CNTL_STORE0_REG Reserved + * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value + * RTC_CNTL_STORE2_REG Boot time, low word + * RTC_CNTL_STORE3_REG Boot time, high word + * RTC_CNTL_STORE4_REG External XTAL frequency + * RTC_CNTL_STORE5_REG APB bus frequency + * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY + * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC + ************************************************************************************* + */ + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG + + +typedef enum { + AWAKE = 0, // +#include +#include "rsa_pss.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct ets_secure_boot_sig_block; +struct ets_secure_boot_signature_t; + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Verify bootloader image (reconfigures cache to map, + loads trusted key digests from efuse) + + If allow_key_revoke is true and aggressive revoke efuse is set, + any failed signature has its associated key revoked in efuse. + + If result is ETS_OK, the "simple hash" of the bootloader + is copied into verified_hash. +*/ +int ets_secure_boot_verify_bootloader(uint8_t *verified_hash, bool allow_key_revoke); + +/* Verify bootloader image (reconfigures cache to map), with + key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If result is ETS_OK, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +int ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access. +*/ +int ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL + + Returns 0 if at least one valid digest was found. +*/ +int ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block (up to 3 can be appended) */ +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +_Static_assert(sizeof(ets_secure_boot_sig_block_t) == 1216, "ets_secure_boot_sig_block_t should occupy 1216 Bytes in memory"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +_Static_assert(sizeof(ets_secure_boot_signature_t) == 4096, "ets_secure_boot_signature_t should occupy 4096 Bytes in memory"); + +struct ets_secure_boot_key_digests { + const void *key_digests[3]; + bool allow_key_revoke; +}; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/sha.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/sha.h new file mode 100644 index 00000000..4d8fe901 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/sha.h @@ -0,0 +1,63 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include "ets_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA2_384, + SHA2_512, + SHA2_512224, + SHA2_512256, + SHA2_512T, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h new file mode 100644 index 00000000..fb060c15 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/spi_flash.h @@ -0,0 +1,554 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup spi_flash_apis, spi flash operation related apis + * @brief spi_flash apis + */ + +/** @addtogroup spi_flash_apis + * @{ + */ + +/************************************************************* + * Note + ************************************************************* + * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is + * used as an SPI master to access Flash and ext-SRAM by + * Cache module. It will support Decryto read for Flash, + * read/write for ext-SRAM. And SPI1 is also used as an + * SPI master for Flash read/write and ext-SRAM read/write. + * It will support Encrypto write for Flash. + * 2. As an SPI master, SPI support Highest clock to 80M, + * however, Flash with 80M Clock should be configured + * for different Flash chips. If you want to use 80M + * clock We should use the SPI that is certified by + * Espressif. However, the certification is not started + * at the time, so please use 40M clock at the moment. + * 3. SPI Flash can use 2 lines or 4 lines mode. If you + * use 2 lines mode, you can save two pad SPIHD and + * SPIWP for gpio. ESP32 support configured SPI pad for + * Flash, the configuration is stored in efuse and flash. + * However, the configurations of pads should be certified + * by Espressif. If you use this function, please use 40M + * clock at the moment. + * 4. ESP32 support to use Common SPI command to configure + * Flash to QIO mode, if you failed to configure with fix + * command. With Common SPI Command, ESP32 can also provide + * a way to use same Common SPI command groups on different + * Flash chips. + * 5. This functions are not protected by packeting, Please use the + ************************************************************* + */ + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +//SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_ID_GD25LQ32C 0xC86016 + +typedef enum { + ESP_ROM_SPIFLASH_QIO_MODE = 0, + ESP_ROM_SPIFLASH_QOUT_MODE, + ESP_ROM_SPIFLASH_DIO_MODE, + ESP_ROM_SPIFLASH_DOUT_MODE, + ESP_ROM_SPIFLASH_FASTRD_MODE, + ESP_ROM_SPIFLASH_SLOWRD_MODE +} esp_rom_spiflash_read_mode_t; + +typedef enum { + ESP_ROM_SPIFLASH_RESULT_OK, + ESP_ROM_SPIFLASH_RESULT_ERR, + ESP_ROM_SPIFLASH_RESULT_TIMEOUT +} esp_rom_spiflash_result_t; + +typedef struct { + uint32_t device_id; + uint32_t chip_size; // chip size in bytes + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; +} esp_rom_spiflash_chip_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from falsh by rom code, function usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t legacy: In legacy mode, more SPI command is used in line. + * + * @return None + */ +void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Falsh status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +/** + * @brief Unlock SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief SPI write protect. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * @param uint32_t *data : The pointer to data which is to write. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/* TODO: figure out how to map these to their new names */ +typedef enum { + SPI_ENCRYPT_DESTINATION_FLASH, + SPI_ENCRYPT_DESTINATION_PSRAM, +} SpiEncryptDest; + +typedef esp_rom_spiflash_result_t SpiFlashOpResult; + +SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len); +SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len); +void SPI_Write_Encrypt_Enable(void); +void SPI_Write_Encrypt_Disable(void); + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions + * + */ +extern esp_rom_spiflash_chip_t g_rom_flashchip; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/tjpgd.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/tjpgd.h new file mode 100644 index 00000000..40340dea --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/tjpgd.h @@ -0,0 +1,97 @@ +/*----------------------------------------------------------------------------/ +/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012 +/----------------------------------------------------------------------------*/ +#ifndef _TJPGDEC +#define _TJPGDEC +/*---------------------------------------------------------------------------*/ +/* System Configurations */ + +#define JD_SZBUF 512 /* Size of stream input buffer */ +#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ +#define JD_USE_SCALE 1 /* Use descaling feature for output */ +#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ + +/*---------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + + +/* Error code */ +typedef enum { + JDR_OK = 0, /* 0: Succeeded */ + JDR_INTR, /* 1: Interrupted by output function */ + JDR_INP, /* 2: Device error or wrong termination of input stream */ + JDR_MEM1, /* 3: Insufficient memory pool for the image */ + JDR_MEM2, /* 4: Insufficient stream input buffer */ + JDR_PAR, /* 5: Parameter error */ + JDR_FMT1, /* 6: Data format error (may be damaged data) */ + JDR_FMT2, /* 7: Right format but not supported */ + JDR_FMT3 /* 8: Not supported JPEG standard */ +} JRESULT; + + + +/* Rectangular structure */ +typedef struct { + WORD left, right, top, bottom; +} JRECT; + + + +/* Decompressor object structure */ +typedef struct JDEC JDEC; +struct JDEC { + UINT dctr; /* Number of bytes available in the input buffer */ + BYTE *dptr; /* Current data read ptr */ + BYTE *inbuf; /* Bit stream input buffer */ + BYTE dmsk; /* Current bit in the current read byte */ + BYTE scale; /* Output scaling ratio */ + BYTE msx, msy; /* MCU size in unit of block (width, height) */ + BYTE qtid[3]; /* Quantization table ID of each component */ + SHORT dcv[3]; /* Previous DC element of each component */ + WORD nrst; /* Restart inverval */ + UINT width, height; /* Size of the input image (pixel) */ + BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ + WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */ + BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ + LONG *qttbl[4]; /* Dequaitizer tables [id] */ + void *workbuf; /* Working buffer for IDCT and RGB output */ + BYTE *mcubuf; /* Working buffer for the MCU */ + void *pool; /* Pointer to available memory pool */ + UINT sz_pool; /* Size of momory pool (bytes available) */ + UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */ + void *device; /* Pointer to I/O device identifiler for the session */ +}; + +/* TJpgDec API functions */ +JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *); +JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE); + + +#ifdef __cplusplus +} +#endif + +#endif /* _TJPGDEC */ diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h new file mode 100644 index 00000000..0c45e92c --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp32s3/rom/uart.h @@ -0,0 +1,436 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +#define RX_BUFF_SIZE 0x400 +#define TX_BUFF_SIZE 100 + +//uart int enalbe register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected; + * 1, two UART modules, hard to detect, detect and return. + * + * @return None + */ +int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Switch message exchange channel for UART download booting. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_buff_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t DataLen : the string length. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS SendMsg(uint8_t *pData, uint16_t DataLen); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *pData : the pointer to input string. + * + * @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return OK for successful. + * FAIL for failed. + */ +STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync); + +/** + * @brief Check if this UART is in download connection. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return ETS_NO_BOOT = 0 for no. + * SEL_UART_BOOT = BIT(1) for yes. + */ +uint8_t UartConnCheck(uint8_t uart_no); + +/** + * @brief Initialize the USB ACM UART + * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have. + * + * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code + * @param cdc_acm_work_mem_len Length of work mem + */ +void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); + + +/** + * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'. + */ +void uart_usb_enable_reset_on_rts(void); + + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_crc.h b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_crc.h new file mode 100644 index 00000000..39787ed1 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_crc.h @@ -0,0 +1,124 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** Notes about CRC API + * The ESP32 ROM include some CRC tables and CRC APIs to speed up CRC calculation. + * The CRC APIs include CRC8, CRC16, CRC32 algorithms for both little endian and big endian modes. + * Here are the polynomials for the algorithms: + * CRC-8 x8+x2+x1+1 0x07 + * CRC16-CCITT x16+x12+x5+1 0x1021 + * CRC32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1 0x04c11db7 + * + * These group of CRC APIs are designed to calculate the data in buffers either continuous or not. + * To make it easy, we had added a `~` at the beginning and the end of the functions. + * To calculate non-continuous buffers, we can write the code like this: + * init = ~init; + * crc = crc32_le(init, buf0, length0); + * crc = crc32_le(crc, buf1, length1); + * crc = ~crc; + * + * However, it is not easy to select which API to use and give the correct parameters. + * A specific CRC algorithm will include this parameters: width, polynomials, init, refin, refout, xorout + * refin and refout show the endian of the algorithm: + * if both of them are true, please use the little endian API. + * if both of them are false, please use the big endian API. + * xorout is the value which you need to be xored to the raw result. + * However, these group of APIs need one '~' before and after the APIs. + * + * Here are some examples for CRC16: + * CRC-16/CCITT, poly = 0x1021, init = 0x0000, refin = true, refout = true, xorout = 0x0000 + * crc = ~crc16_le((uint16_t)~0x0000, buf, length); + * + * CRC-16/CCITT-FALSE, poly = 0x1021, init = 0xffff, refin = false, refout = false, xorout = 0x0000 + * crc = ~crc16_be((uint16_t)~0xffff, buf, length); + * + * CRC-16/X25, poly = 0x1021, init = 0xffff, refin = true, refout = true, xorout = 0xffff + * crc = (~crc16_le((uint16_t)~(0xffff), buf, length))^0xffff; + * + * CRC-16/XMODEM, poly= 0x1021, init = 0x0000, refin = false, refout = false, xorout = 0x0000 + * crc = ~crc16_be((uint16_t)~0x0000, buf, length); + * + */ + +/** + * @brief CRC32 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC32 value + */ +uint32_t esp_rom_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC32 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC32 value + */ +uint32_t esp_rom_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC16 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC16 value + */ +uint16_t esp_rom_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC16 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC16 value + */ +uint16_t esp_rom_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC8 value in little endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC8 value + */ +uint8_t esp_rom_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief CRC8 value in big endian. + * + * @param crc: Initial CRC value (result of last calculation or 0 for the first time) + * @param buf: Data buffer that used to calculate the CRC value + * @param len: Length of the data buffer + * @return CRC8 value + */ +uint8_t esp_rom_crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_efuse.h b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_efuse.h new file mode 100644 index 00000000..907e175e --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_efuse.h @@ -0,0 +1,68 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0) +#define ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI (1) + +/** + * @brief A CRC8 algorithm used for MAC addresses stored in eFuse + * + * @param data Pointer to the original data + * @param len Data length in byte + * @return uint8_t CRC value + */ +uint8_t esp_rom_efuse_mac_address_crc8(const uint8_t *data, uint32_t len); + +/** + * @brief Get SPI Flash GPIO pin configurations from eFuse + * + * @return uint32_t + * - 0: default SPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) + * - 1: default HSPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) + * - Others: Customized pin configuration mask. Pins are encoded as per the + * EFUSE_SPICONFIG_RET_SPICLK, EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, + * EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros. + * + * @note WP pin (for quad I/O modes) is not saved in eFuse and not returned by this function. + */ +uint32_t esp_rom_efuse_get_flash_gpio_info(void); + +/** + * @brief Get SPI Flash WP pin information from eFuse + * + * @return uint32_t + * - 0x3F: invalid GPIO number + * - 0~46: valid GPIO number + */ +uint32_t esp_rom_efuse_get_flash_wp_gpio(void); + +/** + * @brief Read eFuse to check whether secure boot has been enabled or not + * + * @return true if secure boot is enabled, otherwise false + */ +bool esp_rom_efuse_is_secure_boot_enabled(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_gpio.h b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_gpio.h new file mode 100644 index 00000000..fc5f0d22 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_gpio.h @@ -0,0 +1,86 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @brief Configure IO Pad as General Purpose IO, + * so that it can be connected to internal Matrix, + * then combined with one or more peripheral signals. + * + * @param iopad_num IO Pad number + */ +void esp_rom_gpio_pad_select_gpio(uint32_t iopad_num); + +/** + * @brief Enable internal pull up, and disable internal pull down. + * + * @param iopad_num IO Pad number + */ +void esp_rom_gpio_pad_pullup_only(uint32_t iopad_num); + +/** + * @brief Unhold the IO Pad. + * @note When the Pad is set to hold, the state is latched at that moment and won't get changed. + * + * @param iopad_num IP Pad number + */ +void esp_rom_gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Set IO Pad current drive capability. + * + * @param iopad_num IO Pad number + * @param drv Numeric to indicate the capability of current drive + * - 0: 5mA + * - 1: 10mA + * - 2: 20mA + * - 3: 40mA + */ +void esp_rom_gpio_pad_set_drv(uint32_t iopad_num, uint32_t drv); + +/** + * @brief Combine a GPIO input with a peripheral signal, which tagged as input attribute. + * + * @note There's no limitation on the number of signals that a GPIO can combine with. + * + * @param gpio_num GPIO number, especially, `GPIO_MATRIX_CONST_ZERO_INPUT` means connect logic 0 to signal + * `GPIO_MATRIX_CONST_ONE_INPUT` means connect logic 1 to signal + * @param signal_idx Peripheral signal index (tagged as input attribute) + * @param inv Whether the GPIO input to be inverted or not + */ +void esp_rom_gpio_connect_in_signal(uint32_t gpio_num, uint32_t signal_idx, bool inv); + +/** + * @brief Combine a peripheral signal which tagged as output attribute with a GPIO. + * + * @note There's no limitation on the number of signals that a GPIO can combine with. + * + * @param gpio_num GPIO number + * @param signal_idx Peripheral signal index (tagged as output attribute) + * @param out_inv Whether to signal to be inverted or not + * @param oen_inv Whether the output enable control is inverted or not + */ +void esp_rom_gpio_connect_out_signal(uint32_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_md5.h b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_md5.h new file mode 100644 index 00000000..5bb71f3e --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_md5.h @@ -0,0 +1,63 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * The MD5 functions calculate a 128-bit cryptographic digest for any number of input bytes. + */ + +/** + * @brief Type defined for MD5 context + * + */ +typedef struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +} md5_context_t; + +/** + * @brief Initialize the MD5 context + * + * @param context Context object allocated by user + */ +void esp_rom_md5_init(md5_context_t *context); + +/** + * @brief Running MD5 algorithm over input data + * + * @param context MD5 context which has been initialized by `MD5Init` + * @param buf Input buffer + * @param len Buffer length + */ +void esp_rom_md5_update(md5_context_t *context, const uint8_t *buf, uint32_t len); + +/** + * @brief Extract the MD5 result, and erase the context + * + * @param digest Where to store the 128-bit digest value + * @param context MD5 context + */ +void esp_rom_md5_final(uint8_t digest[16], md5_context_t *context); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_sys.h b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_sys.h new file mode 100644 index 00000000..68a538b1 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_sys.h @@ -0,0 +1,56 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Print formated string to console device + * @note float and long long data are not supported! + * + * @param fmt Format string + * @param ... Additional arguments, depending on the format string + * @return int: Total number of characters written on success; A negative number on failure. + */ +int esp_rom_printf(const char *fmt, ...); + +/** + * @brief Pauses execution for us microseconds + * + * @param us Number of microseconds to pause + */ +void esp_rom_delay_us(uint32_t us); + +/** + * @brief esp_rom_printf can print message to different channels simultaneously. + * This function can help install the low level putc function for esp_rom_printf. + * + * @param channel Channel number (startting from 1) + * @param putc Function pointer to the putc implementation. Set NULL can disconnect esp_rom_printf with putc. + */ +void esp_rom_install_channel_putc(int channel, void (*putc)(char c)); + +/** + * @brief Disable logging from the ROM code. + */ +void esp_rom_disable_logging(void); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_uart.h b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_uart.h new file mode 100644 index 00000000..a944fc6b --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_rom/include/esp_rom_uart.h @@ -0,0 +1,109 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define ESP_ROM_CDC_ACM_WORK_BUF_MIN 128 + +typedef enum { + ESP_ROM_UART_0, + ESP_ROM_UART_1, + ESP_ROM_UART_USB +} esp_rom_uart_num_t; + +/** + * @brief Wait for UART TX FIFO is empty and all data has been sent out. + * + * @param uart_no UART port number + */ +void esp_rom_uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Set clock source and baud rate for UART. + * + * @param uart_no UART port number + * @param clock_hz Source clock (in Hz) + * @param baud_rate Baud rate to set + */ +void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate); + +/** + * @brief Wait until UART TX FIFO is empty (i.e. flush TX FIFO) + * + * @param uart_no UART port number + */ +void esp_rom_uart_flush_tx(uint8_t uart_no); + +/** + * @brief Transmit one character to the console channel. + * + * @param c Character to send + * @return + * - 0 on success + * - 1 on failure + */ +int esp_rom_uart_tx_one_char(uint8_t c); + +/** + * @brief Transmit one character to the console channel. + * @note This function is a wrapper over esp_rom_uart_tx_one_char, it can help handle line ending issue by replacing '\n' with '\r\n'. + * + * @param c Character to send + */ +void esp_rom_uart_putc(char c); + +/** + * @brief Get one character from the console channel. + * + * @param c Where to store the character + * @return + * - 0 on success + * - 1 on failure or no data available + */ +int esp_rom_uart_rx_one_char(uint8_t *c); + +/** + * @brief Get one line of string from console channel (line ending won't be stored in the buffer). + * + * @param str Where to store the string + * @param max_len Maximum length of the buffer (including the NULL delimiter) + * @return always return 0 when on success or wait in a loop for rx data + */ +int esp_rom_uart_rx_string(uint8_t *str, uint8_t max_len); + +/** + * @brief Set the UART port used by ets_printf. + * + * @param uart_no UART port number + */ +void esp_rom_uart_set_as_console(uint8_t uart_no); + +/** + * @brief Initialize the USB ACM UART + * @note The ACM working memroy should be at least 128 bytes (ESP_ROM_CDC_ACM_WORK_BUF_MIN) in size. + * + * @param cdc_acm_work_mem Pointer to the work memroy used for CDC-ACM + * @param cdc_acm_work_mem_len Length of work memory + */ +void esp_rom_uart_usb_acm_init(void *cdc_acm_work_mem, int cdc_acm_work_mem_len); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h b/tools/sdk/esp32s2/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h new file mode 100644 index 00000000..179fa555 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_serial_slave_link/include/esp_serial_slave_link/essl_spi.h @@ -0,0 +1,165 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_err.h" +#include "esp_serial_slave_link/essl.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +//////////////////////////////////////////////////////////////////////////////// +// Basic commands to communicate with the SPI Slave HD on ESP32-S2 +//////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Read the shared buffer from the slave. + * + * @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words + * by the DMA. When a byte is written, the remaining bytes in the same word will also be + * overwritten, even the ``len`` is shorter than a word. + * + * @param spi SPI device handle representing the slave + * @param out_data Buffer for read data, strongly suggested to be in the DRAM and align to 4 + * @param addr Address of the slave shared buffer + * @param len Length to read + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: on success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags); + +/** + * @brief Write the shared buffer of the slave. + * + * @note ``out_data`` should be prepared in words and in the DRAM. The buffer may be written in words + * by the DMA. When a byte is written, the remaining bytes in the same word will also be + * overwritten, even the ``len`` is shorter than a word. + * + * @param spi SPI device handle representing the slave + * @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4 + * @param addr Address of the slave shared buffer, + * @param len Length to write + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, int len, uint32_t flags); + +/** + * @brief Receive long buffer in segments from the slave through its DMA. + * + * @note This function combines several :cpp:func:`essl_spi_rddma_seg` and one + * :cpp:func:`essl_spi_rddma_done` at the end. Used when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param out_data Buffer to hold the received data, strongly suggested to be in the DRAM and align to 4 + * @param len Total length of data to receive. + * @param seg_len Length of each segment, which is not larger than the maximum transaction length + * allowed for the spi device. Suggested to be multiples of 4. When set < 0, means send + * all data in one segment (the ``rddma_done`` will still be sent.) + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rddma(spi_device_handle_t spi, uint8_t *out_data, int len, int seg_len, uint32_t flags); + +/** + * @brief Read one data segment from the slave through its DMA. + * + * @note To read long buffer, call :cpp:func:`essl_spi_rddma` instead. + * + * @param spi SPI device handle representing the slave + * @param out_data Buffer to hold the received data, strongly suggested to be in the DRAM and align to 4 + * @param seg_len Length of this segment + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg_len, uint32_t flags); + +/** + * @brief Send the ``rddma_done`` command to the slave. Upon receiving this command, the slave will + * stop sending the current buffer even there are data unsent, and maybe prepare the next buffer to + * send. + * + * @note This is required only when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags); + +/** + * @brief Send long buffer in segments to the slave through its DMA. + * + * @note This function combines several :cpp:func:`essl_spi_wrdma_seg` and one + * :cpp:func:`essl_spi_wrdma_done` at the end. Used when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4 + * @param len Total length of data to send. + * @param seg_len Length of each segment, which is not larger than the maximum transaction length + * allowed for the spi device. Suggested to be multiples of 4. When set < 0, means send + * all data in one segment (the ``wrdma_done`` will still be sent.) + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, int seg_len, uint32_t flags); + +/** + * @brief Send one data segment to the slave through its DMA. + * + * @note To send long buffer, call :cpp:func:`essl_spi_wrdma` instead. + * + * @param spi SPI device handle representing the slave + * @param data Buffer for data to send, strongly suggested to be in the DRAM and align to 4 + * @param seg_len Length of this segment + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int seg_len, uint32_t flags); + +/** + * @brief Send the ``wrdma_done`` command to the slave. Upon receiving this command, the slave will + * stop receiving, process the received data, and maybe prepare the next buffer to receive. + * + * @note This is required only when the slave is working in segment mode. + * + * @param spi SPI device handle representing the slave + * @param flags `SPI_TRANS_*` flags to control the transaction mode of the transaction to send. + * @return + * - ESP_OK: success + * - or other return value from :cpp:func:`spi_device_transmit`. + */ +esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags); + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h b/tools/sdk/esp32s2/include/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h new file mode 100644 index 00000000..d2856fd1 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h @@ -0,0 +1,38 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +#pragma once + +// NOTE: From the view of master +#define CMD_HD_WRBUF_REG 0x01 +#define CMD_HD_RDBUF_REG 0x02 +#define CMD_HD_WRDMA_REG 0x03 +#define CMD_HD_RDDMA_REG 0x04 + +#define CMD_HD_ONEBIT_MODE 0x00 +#define CMD_HD_DOUT_MODE 0x10 +#define CMD_HD_QOUT_MODE 0x20 +#define CMD_HD_DIO_MODE 0x50 +#define CMD_HD_QIO_MODE 0xA0 + +#define CMD_HD_SEG_END_REG 0x05 +#define CMD_HD_EN_QPI_REG 0x06 +#define CMD_HD_WR_END_REG 0x07 +#define CMD_HD_INT0_REG 0x08 +#define CMD_HD_INT1_REG 0x09 +#define CMD_HD_INT2_REG 0x0A +#define CMD_HD_EX_QPI_REG 0xDD + +#define SPI_SLAVE_HD_BUFFER_SIZE 72 \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/esp_system/include/esp_private/panic_internal.h b/tools/sdk/esp32s2/include/esp_system/include/esp_private/panic_internal.h new file mode 100644 index 00000000..583d3eba --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_private/panic_internal.h @@ -0,0 +1,77 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern bool g_panic_abort; + +// Function to print longer amounts of information such as the details +// and backtrace field of panic_info_t. These functions should limit themselves +// to printing to the console and should do other more involved processing, +// and must be aware that the main logic in panic.c has a watchdog timer active. +typedef void (*panic_info_dump_fn_t)(const void* frame); + +// Non architecture specific exceptions (generally valid for all targets). +// Can be used to convey to the main logic what exception is being +// dealt with to perform some actions, without knowing the underlying +// architecture/chip-specific exception. +typedef enum { + PANIC_EXCEPTION_DEBUG, + PANIC_EXCEPTION_IWDT, + PANIC_EXCEPTION_TWDT, + PANIC_EXCEPTION_ABORT, + PANIC_EXCEPTION_FAULT, // catch-all for all types of faults +} panic_exception_t; + +typedef struct { + int core; // core which triggered panic + panic_exception_t exception; // non-architecture-specific exception code + const char* reason; // exception string + const char* description; // short description of the exception + panic_info_dump_fn_t details; // more details on the exception + panic_info_dump_fn_t state; // processor state, usually the contents of the registers + const void* addr; // instruction address that triggered the exception + const void* frame; // reference to the frame + bool pseudo_excause; // flag indicating that exception cause has special meaning +} panic_info_t; + +#define PANIC_INFO_DUMP(info, dump_fn) {if ((info)->dump_fn) (*(info)->dump_fn)((info->frame));} + +// Create own print functions, since printf might be broken, and can be silenced +// when CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT +#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT +void panic_print_char(char c); +void panic_print_str(const char *str); +void panic_print_dec(int d); +void panic_print_hex(int h); +#else +#define panic_print_char(c) +#define panic_print_str(str) +#define panic_print_dec(d) +#define panic_print_hex(h) +#endif + +void __attribute__((noreturn)) panic_abort(const char *details); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/esp_system/include/esp_private/startup_internal.h b/tools/sdk/esp32s2/include/esp_system/include/esp_private/startup_internal.h new file mode 100644 index 00000000..fc91b0fa --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_private/startup_internal.h @@ -0,0 +1,74 @@ +// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_attr.h" + +#include "soc/soc_caps.h" +#include "hal/cpu_hal.h" + +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern bool g_spiram_ok; // [refactor-todo] better way to communicate this from port layer to common startup code + +// Port layer defines the entry point. It then transfer control to a `sys_startup_fn_t`, stored in this +// array, one per core. +typedef void (*sys_startup_fn_t)(void); + +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE +extern sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM]; +#else +extern sys_startup_fn_t g_startup_fn[1]; +#endif + +// Utility to execute `sys_startup_fn_t` for the current core. +#define SYS_STARTUP_FN() ((*g_startup_fn[(cpu_hal_get_core_id())])()) + +#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE +void startup_resume_other_cores(void); +#endif + +typedef struct { + void (*fn)(void); + uint32_t cores; +} esp_system_init_fn_t; + +/* + * Declare an component initialization function that will execute on the specified cores (ex. if BIT0 == 1, will execute + * on CORE0, CORE1 if BIT1 and so on). + * + * @note Initialization functions should be placed in a compilation unit where at least one other + * symbol is referenced 'meaningfully' in another compilation unit, otherwise this gets discarded during linking. (By + * 'meaningfully' we mean the reference should not itself get optimized out by the compiler/discarded by the linker). + */ +#define ESP_SYSTEM_INIT_FN(f, c, ...) \ +static void __attribute__((used)) __VA_ARGS__ __esp_system_init_fn_##f(void); \ +static __attribute__((used)) esp_system_init_fn_t _SECTION_ATTR_IMPL(".esp_system_init_fn", f) \ + esp_system_init_fn_##f = { .fn = ( __esp_system_init_fn_##f), .cores = (c) }; \ +static __attribute__((used)) __VA_ARGS__ void __esp_system_init_fn_##f(void) // [refactor-todo] this can be made public API if we allow components to declare init functions, + // instead of calling them explicitly + +extern uint64_t g_startup_time; // Startup time that serves as the point of origin for system time. Should be set by the entry + // function in the port layer. May be 0 as well if this is not backed by a persistent counter, in which case + // startup time = system time = 0 at the point the entry function sets this variable. + +#ifdef __cplusplus +} +#endif + diff --git a/tools/sdk/esp32s2/include/esp_system/include/esp_private/usb_console.h b/tools/sdk/esp32s2/include/esp_system/include/esp_private/usb_console.h new file mode 100644 index 00000000..1e9536f4 --- /dev/null +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_private/usb_console.h @@ -0,0 +1,73 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file usb_console.h + * This file contains definitions of low-level USB console functions. + * These functions are not considered to be a public interface and + * should not be called by applications directly. + * Application interface to the USB console is provided either by + * "cdcacm" VFS driver, or by the USB CDC driver in TinyUSB. + */ + + +/** + * RX/TX callback function type + * @param arg callback-specific context pointer + */ +typedef void (*esp_usb_console_cb_t)(void* arg); + +/** + * Initialize USB console output using ROM USB CDC driver. + * This function is called by the early startup code if USB CDC is + * selected as the console output option. + * @return + * - ESP_OK on success + * - ESP_ERR_NO_MEM + * - other error codes from the interrupt allocator + */ +esp_err_t esp_usb_console_init(void); + +/** + * Write a buffer to USB CDC + * @param buf data to write + * @param size size of the data, in bytes + * @return -1 on error, otherwise the number of bytes + */ +ssize_t esp_usb_console_write_buf(const char* buf, size_t size); + +ssize_t esp_usb_console_flush(void); + +ssize_t esp_usb_console_read_buf(char* buf, size_t buf_size); + +bool esp_usb_console_read_available(void); + +bool esp_usb_console_write_available(void); + +esp_err_t esp_usb_console_set_cb(esp_usb_console_cb_t rx_cb, esp_usb_console_cb_t tx_cb, void* arg); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32/include/esp32/include/esp_sleep.h b/tools/sdk/esp32s2/include/esp_system/include/esp_sleep.h similarity index 93% rename from tools/sdk/esp32/include/esp32/include/esp_sleep.h rename to tools/sdk/esp32s2/include/esp_system/include/esp_sleep.h index a1d912b5..e423e6df 100644 --- a/tools/sdk/esp32/include/esp32/include/esp_sleep.h +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_sleep.h @@ -16,8 +16,9 @@ #include #include "esp_err.h" -#include "driver/gpio.h" -#include "driver/touch_pad.h" + +#include "hal/touch_sensor_types.h" +#include "hal/gpio_types.h" #ifdef __cplusplus extern "C" { @@ -64,6 +65,9 @@ typedef enum { ESP_SLEEP_WAKEUP_ULP, //!< Wakeup caused by ULP program ESP_SLEEP_WAKEUP_GPIO, //!< Wakeup caused by GPIO (light sleep only) ESP_SLEEP_WAKEUP_UART, //!< Wakeup caused by UART (light sleep only) + ESP_SLEEP_WAKEUP_WIFI, //!< Wakeup caused by WIFI (light sleep only) + ESP_SLEEP_WAKEUP_COCPU, //!< Wakeup caused by COCPU int + ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG, //!< Wakeup caused by COCPU crash } esp_sleep_source_t; /* Leave this type define for compatibility */ @@ -89,7 +93,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source); /** * @brief Enable wakeup by ULP coprocessor - * @note ULP wakeup source cannot be used when RTC_PERIPH power domain is forced + * @note On ESP32, ULP wakeup source cannot be used when RTC_PERIPH power domain is forced * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup source is used. * @return * - ESP_OK on success @@ -110,9 +114,8 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us); /** * @brief Enable wakeup by touch sensor * - * @note Touch wakeup source cannot be used when RTC_PERIPH power domain is forced - * to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup - * source is used. + * @note In revisions 0 and 1 of the ESP32, touch wakeup source + * can not be used when RTC_PERIPH power domain is forced * * @note The FSM mode of the touch button should be configured * as the timer trigger mode. @@ -145,7 +148,8 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void); * @note This function does not modify pin configuration. The pin is * configured in esp_sleep_start, immediately before entering sleep mode. * - * @note ext0 wakeup source cannot be used together with touch or ULP wakeup sources. + * @note In revisions 0 and 1 of the ESP32, ext0 wakeup source + * can not be used together with touch or ULP wakeup sources. * * @param gpio_num GPIO number used as wakeup source. Only GPIOs which are have RTC * functionality can be used: 0,2,4,12-15,25-27,32-39. @@ -202,7 +206,8 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode * wakeup level, for each GPIO which is used for wakeup. * Then call this function to enable wakeup feature. * - * @note GPIO wakeup source cannot be used together with touch or ULP wakeup sources. + * @note In revisions 0 and 1 of the ESP32, GPIO wakeup source + * can not be used together with touch or ULP wakeup sources. * * @return * - ESP_OK on success @@ -227,6 +232,14 @@ esp_err_t esp_sleep_enable_gpio_wakeup(void); */ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num); +/** + * @brief Enable wakeup by WiFi MAC + * @return + * - ESP_OK on success + */ +esp_err_t esp_sleep_enable_wifi_wakeup(void); + + /** * @brief Get the bit mask of GPIOs which caused wakeup (ext1) * diff --git a/tools/sdk/esp32s2/include/esp_system/include/esp_system.h b/tools/sdk/esp32s2/include/esp_system/include/esp_system.h index 9b0abf43..9be72c3e 100644 --- a/tools/sdk/esp32s2/include/esp_system/include/esp_system.h +++ b/tools/sdk/esp32s2/include/esp_system/include/esp_system.h @@ -117,6 +117,16 @@ esp_reset_reason_t esp_reset_reason(void); */ uint32_t esp_get_free_heap_size(void); +/** + * @brief Get the size of available internal heap. + * + * Note that the returned value may be larger than the maximum contiguous block + * which can be allocated. + * + * @return Available internal heap size, in bytes. + */ +uint32_t esp_get_free_internal_heap_size(void); + /** * @brief Get the minimum heap that has ever been available * @@ -251,6 +261,7 @@ void __attribute__((noreturn)) esp_system_abort(const char* details); typedef enum { CHIP_ESP32 = 1, //!< ESP32 CHIP_ESP32S2 = 2, //!< ESP32-S2 + CHIP_ESP32S3 = 4, //!< ESP32-S3 } esp_chip_model_t; /* Chip feature flags, used in esp_chip_info_t */ @@ -275,6 +286,18 @@ typedef struct { */ void esp_chip_info(esp_chip_info_t* out_info); + +#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX +/** + * @brief Cache lock bug exists or not + * + * @return + * - ture : bug exists + * - false : bug not exists + */ +bool soc_has_cache_lock_bug(void); +#endif + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_timer/include/esp_timer.h b/tools/sdk/esp32s2/include/esp_timer/include/esp_timer.h index 1a39ef0a..79766d61 100644 --- a/tools/sdk/esp32s2/include/esp_timer/include/esp_timer.h +++ b/tools/sdk/esp32s2/include/esp_timer/include/esp_timer.h @@ -178,7 +178,7 @@ esp_err_t esp_timer_stop(esp_timer_handle_t timer); * @param timer timer handle allocated using esp_timer_create * @return * - ESP_OK on success - * - ESP_ERR_INVALID_STATE if the timer is not running + * - ESP_ERR_INVALID_STATE if the timer is running */ esp_err_t esp_timer_delete(esp_timer_handle_t timer); diff --git a/tools/sdk/esp32s2/include/esp_websocket_client/include/esp_websocket_client.h b/tools/sdk/esp32s2/include/esp_websocket_client/include/esp_websocket_client.h index ae8cc8a4..5a0e52e0 100644 --- a/tools/sdk/esp32s2/include/esp_websocket_client/include/esp_websocket_client.h +++ b/tools/sdk/esp32s2/include/esp_websocket_client/include/esp_websocket_client.h @@ -85,6 +85,9 @@ typedef struct { char *subprotocol; /*!< Websocket subprotocol */ char *user_agent; /*!< Websocket user-agent */ char *headers; /*!< Websocket additional headers */ + int pingpong_timeout_sec; /*!< Period before connection is aborted due to no PONGs received */ + bool disable_pingpong_discon; /*!< Disable auto-disconnect due to no PONG received within pingpong_timeout_sec */ + } esp_websocket_client_config_t; /** @@ -185,7 +188,7 @@ int esp_websocket_client_send_bin(esp_websocket_client_handle_t client, const ch int esp_websocket_client_send_text(esp_websocket_client_handle_t client, const char *data, int len, TickType_t timeout); /** - * @brief Check the WebSocket connection status + * @brief Check the WebSocket client connection state * * @param[in] client The client handle * diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi.h index 8d21c64e..04a306fb 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi.h @@ -119,15 +119,6 @@ esp_err_t esp_wifi_init_internal(const wifi_init_config_t *config); */ esp_err_t esp_wifi_deinit_internal(void); -/** - * @brief get whether the wifi driver is allowed to transmit data or not - * - * @return - * - true : upper layer should stop to transmit data to wifi driver - * - false : upper layer can transmit data to wifi driver - */ -bool esp_wifi_internal_tx_is_stop(void); - /** * @brief free the rx buffer which allocated by wifi driver * @@ -138,18 +129,79 @@ void esp_wifi_internal_free_rx_buffer(void* buffer); /** * @brief transmit the buffer via wifi driver * + * This API makes a copy of the input buffer and then forwards the buffer + * copy to WiFi driver. + * * @param wifi_interface_t wifi_if : wifi interface id * @param void *buffer : the buffer to be tansmit * @param uint16_t len : the length of buffer * * @return - * - ERR_OK : Successfully transmit the buffer to wifi driver - * - ERR_MEM : Out of memory - * - ERR_IF : WiFi driver error - * - ERR_ARG : Invalid argument + * - ESP_OK : Successfully transmit the buffer to wifi driver + * - ESP_ERR_NO_MEM: out of memory + * - ESP_ERR_WIFI_ARG: invalid argument + * - ESP_ERR_WIFI_IF : WiFi interface is invalid + * - ESP_ERR_WIFI_CONN : WiFi interface is not created, e.g. send the data to STA while WiFi mode is AP mode + * - ESP_ERR_WIFI_NOT_STARTED : WiFi is not started + * - ESP_ERR_WIFI_STATE : WiFi internal state is not ready, e.g. WiFi is not started + * - ESP_ERR_WIFI_NOT_ASSOC : WiFi is not associated + * - ESP_ERR_WIFI_TX_DISALLOW : WiFi TX is disallowed, e.g. WiFi hasn't pass the authentication + * - ESP_ERR_WIFI_POST : caller fails to post event to WiFi task */ int esp_wifi_internal_tx(wifi_interface_t wifi_if, void *buffer, uint16_t len); +/** + * @brief The net stack buffer reference counter callback function + * + */ +typedef void (*wifi_netstack_buf_ref_cb_t)(void *netstack_buf); + +/** + * @brief The net stack buffer free callback function + * + */ +typedef void (*wifi_netstack_buf_free_cb_t)(void *netstack_buf); + +/** + * @brief transmit the buffer by reference via wifi driver + * + * This API firstly increases the reference counter of the input buffer and + * then forwards the buffer to WiFi driver. The WiFi driver will free the buffer + * after processing it. Use esp_wifi_internal_tx() if the uplayer buffer doesn't + * supports reference counter. + * + * @param wifi_if : wifi interface id + * @param buffer : the buffer to be tansmit + * @param len : the length of buffer + * @param netstack_buf : the netstack buffer related to bufffer + * + * @return + * - ESP_OK : Successfully transmit the buffer to wifi driver + * - ESP_ERR_NO_MEM: out of memory + * - ESP_ERR_WIFI_ARG: invalid argument + * - ESP_ERR_WIFI_IF : WiFi interface is invalid + * - ESP_ERR_WIFI_CONN : WiFi interface is not created, e.g. send the data to STA while WiFi mode is AP mode + * - ESP_ERR_WIFI_NOT_STARTED : WiFi is not started + * - ESP_ERR_WIFI_STATE : WiFi internal state is not ready, e.g. WiFi is not started + * - ESP_ERR_WIFI_NOT_ASSOC : WiFi is not associated + * - ESP_ERR_WIFI_TX_DISALLOW : WiFi TX is disallowed, e.g. WiFi hasn't pass the authentication + * - ESP_ERR_WIFI_POST : caller fails to post event to WiFi task + */ +esp_err_t esp_wifi_internal_tx_by_ref(wifi_interface_t ifx, void *buffer, size_t len, void *netstack_buf); + +/** + * @brief register the net stack buffer reference increasing and free callback + * + * @param ref : net stack buffer reference callback + * @param free: net stack buffer free callback + * + * @return + * - ESP_OK : Successfully transmit the buffer to wifi driver + * - others : failed to register the callback + */ +esp_err_t esp_wifi_internal_reg_netstack_buf_cb(wifi_netstack_buf_ref_cb_t ref, wifi_netstack_buf_free_cb_t free); + + /** * @brief The WiFi RX callback function * diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi_os_adapter.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi_os_adapter.h index f005b315..ad4245b7 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi_os_adapter.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi_os_adapter.h @@ -21,7 +21,7 @@ extern "C" { #endif -#define ESP_WIFI_OS_ADAPTER_VERSION 0x00000006 +#define ESP_WIFI_OS_ADAPTER_VERSION 0x00000007 #define ESP_WIFI_OS_ADAPTER_MAGIC 0xDEADBEAF #define OSI_FUNCS_TIME_BLOCKING 0xffffffff @@ -133,6 +133,7 @@ typedef struct { void (* _coex_condition_set)(uint32_t type, bool dissatisfy); int32_t (* _coex_wifi_request)(uint32_t event, uint32_t latency, uint32_t duration); int32_t (* _coex_wifi_release)(uint32_t event); + bool (* _is_from_isr)(void); int32_t _magic; } wifi_osi_funcs_t; diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h index 891a8de6..4dad75b9 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi.h @@ -88,6 +88,8 @@ extern "C" { #define ESP_ERR_WIFI_POST (ESP_ERR_WIFI_BASE + 18) /*!< Failed to post the event to WiFi task */ #define ESP_ERR_WIFI_INIT_STATE (ESP_ERR_WIFI_BASE + 19) /*!< Invalod WiFi state when init/deinit is called */ #define ESP_ERR_WIFI_STOP_STATE (ESP_ERR_WIFI_BASE + 20) /*!< Returned when WiFi is stopping */ +#define ESP_ERR_WIFI_NOT_ASSOC (ESP_ERR_WIFI_BASE + 21) /*!< The WiFi connection is not associated */ +#define ESP_ERR_WIFI_TX_DISALLOW (ESP_ERR_WIFI_BASE + 22) /*!< The WiFi TX is disallowed */ /** * @brief WiFi stack configuration parameters passed to esp_wifi_init call. @@ -101,12 +103,12 @@ typedef struct { int tx_buf_type; /**< WiFi TX buffer type */ int static_tx_buf_num; /**< WiFi static TX buffer number */ int dynamic_tx_buf_num; /**< WiFi dynamic TX buffer number */ + int cache_tx_buf_num; /**< WiFi TX cache buffer number */ int csi_enable; /**< WiFi channel state information enable flag */ int ampdu_rx_enable; /**< WiFi AMPDU RX feature enable flag */ int ampdu_tx_enable; /**< WiFi AMPDU TX feature enable flag */ int nvs_enable; /**< WiFi NVS flash enable flag */ int nano_enable; /**< Nano option for printf/scan family enable flag */ - int tx_ba_win; /**< WiFi Block Ack TX window size */ int rx_ba_win; /**< WiFi Block Ack RX window size */ int wifi_task_core_id; /**< WiFi Task Core ID */ int beacon_max_len; /**< WiFi softAP maximum length of the beacon */ @@ -121,6 +123,12 @@ typedef struct { #define WIFI_STATIC_TX_BUFFER_NUM 0 #endif +#if (CONFIG_ESP32_SPIRAM_SUPPORT | CONFIG_ESP32S2_SPIRAM_SUPPORT) +#define WIFI_CACHE_TX_BUFFER_NUM CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM +#else +#define WIFI_CACHE_TX_BUFFER_NUM 0 +#endif + #ifdef CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM #define WIFI_DYNAMIC_TX_BUFFER_NUM CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM #else @@ -162,12 +170,6 @@ extern uint64_t g_wifi_feature_caps; #define WIFI_INIT_CONFIG_MAGIC 0x1F2F3F4F -#ifdef CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED -#define WIFI_DEFAULT_TX_BA_WIN CONFIG_ESP32_WIFI_TX_BA_WIN -#else -#define WIFI_DEFAULT_TX_BA_WIN 0 /* unused if ampdu_tx_enable == false */ -#endif - #ifdef CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED #define WIFI_DEFAULT_RX_BA_WIN CONFIG_ESP32_WIFI_RX_BA_WIN #else @@ -193,6 +195,7 @@ extern uint64_t g_wifi_feature_caps; #endif #define CONFIG_FEATURE_WPA3_SAE_BIT (1<<0) +#define CONFIG_FEATURE_CACHE_TX_BUF_BIT (1<<1) #define WIFI_INIT_CONFIG_DEFAULT() { \ .event_handler = &esp_event_send_internal, \ @@ -203,12 +206,12 @@ extern uint64_t g_wifi_feature_caps; .tx_buf_type = CONFIG_ESP32_WIFI_TX_BUFFER_TYPE,\ .static_tx_buf_num = WIFI_STATIC_TX_BUFFER_NUM,\ .dynamic_tx_buf_num = WIFI_DYNAMIC_TX_BUFFER_NUM,\ + .cache_tx_buf_num = WIFI_CACHE_TX_BUFFER_NUM,\ .csi_enable = WIFI_CSI_ENABLED,\ .ampdu_rx_enable = WIFI_AMPDU_RX_ENABLED,\ .ampdu_tx_enable = WIFI_AMPDU_TX_ENABLED,\ .nvs_enable = WIFI_NVS_ENABLED,\ .nano_enable = WIFI_NANO_FORMAT_ENABLED,\ - .tx_ba_win = WIFI_DEFAULT_TX_BA_WIN,\ .rx_ba_win = WIFI_DEFAULT_RX_BA_WIN,\ .wifi_task_core_id = WIFI_TASK_CORE_ID,\ .beacon_max_len = WIFI_SOFTAP_BEACON_MAX_LEN, \ @@ -1093,6 +1096,63 @@ esp_err_t esp_wifi_set_ant(const wifi_ant_config_t *config); */ esp_err_t esp_wifi_get_ant(wifi_ant_config_t *config); +/** + * @brief Get the TSF time + * In Station mode or SoftAP+Station mode if station is not connected or station doesn't receive at least + * one beacon after connected, will return 0 + * + * @attention Enabling power save may cause the return value inaccurate, except WiFi modem sleep + * + * @param interface The interface whose tsf_time is to be retrieved. + * + * @return 0 or the TSF time + */ +int64_t esp_wifi_get_tsf_time(wifi_interface_t interface); + +/** + * @brief Set the inactive time of the ESP32 STA or AP + * + * @attention 1. For Station, If the station does not receive a beacon frame from the connected SoftAP during the inactive time, + * disconnect from SoftAP. Default 6s. + * @attention 2. For SoftAP, If the softAP doesn't receive any data from the connected STA during inactive time, + * the softAP will force deauth the STA. Default is 300s. + * @attention 3. The inactive time configuration is not stored into flash + * + * @param ifx interface to be configured. + * @param sec Inactive time. Unit seconds. + * + * @return + * - ESP_OK: succeed + * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start + * - ESP_ERR_WIFI_ARG: invalid argument, For Station, if sec is less than 3. For SoftAP, if sec is less than 10. + */ +esp_err_t esp_wifi_set_inactive_time(wifi_interface_t ifx, uint16_t sec); + +/** + * @brief Get inactive time of specified interface + * + * @param ifx Interface to be configured. + * @param sec Inactive time. Unit seconds. + * + * @return + * - ESP_OK: succeed + * - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init + * - ESP_ERR_WIFI_ARG: invalid argument + */ +esp_err_t esp_wifi_get_inactive_time(wifi_interface_t ifx, uint16_t *sec); + +/** + * @brief Dump WiFi statistics + * + * @param modules statistic modules to be dumped + * + * @return + * - ESP_OK: succeed + * - others: failed + */ +esp_err_t esp_wifi_statis_dump(uint32_t modules); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h index cc7dc02a..af3c8569 100644 --- a/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h +++ b/tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_types.h @@ -94,7 +94,7 @@ typedef enum { WIFI_REASON_ASSOC_FAIL = 203, WIFI_REASON_HANDSHAKE_TIMEOUT = 204, WIFI_REASON_CONNECTION_FAIL = 205, - WIFI_REASON_AUTH_CHANGED = 206, + WIFI_REASON_AP_TSF_RESET = 206, } wifi_err_reason_t; typedef enum { @@ -581,6 +581,19 @@ typedef enum { WPS_FAIL_REASON_MAX } wifi_event_sta_wps_fail_reason_t; +#define MAX_SSID_LEN 32 +#define MAX_PASSPHRASE_LEN 64 +#define MAX_WPS_AP_CRED 3 + +/** Argument structure for WIFI_EVENT_STA_WPS_ER_SUCCESS event */ +typedef struct { + uint8_t ap_cred_cnt; /**< Number of AP credentials received */ + struct { + uint8_t ssid[MAX_SSID_LEN]; /**< SSID of AP */ + uint8_t passphrase[MAX_PASSPHRASE_LEN]; /**< Passphrase for the AP */ + } ap_cred[MAX_WPS_AP_CRED]; /**< All AP credentials received from WPS handshake */ +} wifi_event_sta_wps_er_success_t; + /** Argument structure for WIFI_EVENT_AP_STACONNECTED event */ typedef struct { uint8_t mac[6]; /**< MAC address of the station connected to ESP32 soft-AP */ @@ -599,6 +612,12 @@ typedef struct { uint8_t mac[6]; /**< MAC address of the station which send probe request */ } wifi_event_ap_probe_req_rx_t; +#define WIFI_STATIS_BUFFER (1<<0) +#define WIFI_STATIS_RXTX (1<<1) +#define WIFI_STATIS_HW (1<<2) +#define WIFI_STATIS_DIAG (1<<3) +#define WIFI_STATIS_ALL (-1) + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/espcoredump/include/esp_core_dump.h b/tools/sdk/esp32s2/include/espcoredump/include/esp_core_dump.h index 7d8d56c5..2a6c1093 100644 --- a/tools/sdk/esp32s2/include/espcoredump/include/esp_core_dump.h +++ b/tools/sdk/esp32s2/include/espcoredump/include/esp_core_dump.h @@ -17,6 +17,7 @@ #include #include "esp_err.h" #include "freertos/xtensa_context.h" +#include "esp_private/panic_internal.h" /**************************************************************************************/ /******************************** EXCEPTION MODE API **********************************/ @@ -46,7 +47,7 @@ void esp_core_dump_init(void); * The structure of core dump data is described below in details. * 1) Core dump starts with header: * 1.1) TOTAL_LEN is total length of core dump data in flash including CRC. Size is 4 bytes. - * 1.2) VERSION field keeps 4 byte version of core dump. + * 1.2) VERSION field keeps 4 byte version of core dump. * 1.2) TASKS_NUM is the number of tasks for which data are stored. Size is 4 bytes. * 1.3) TCB_SIZE is the size of task's TCB structure. Size is 4 bytes. * 2) Core dump header is followed by the data for every task in the system. @@ -58,7 +59,7 @@ void esp_core_dump_init(void); * 4) Task's stack is placed after TCB data. Size is (STACK_END - STACK_TOP) bytes. * 5) CRC is placed at the end of the data. */ -void esp_core_dump_to_flash(XtExcFrame *frame); +void esp_core_dump_to_flash(panic_info_t *info); /** * @brief Print base64-encoded core dump to UART. @@ -68,7 +69,7 @@ void esp_core_dump_to_flash(XtExcFrame *frame); * 2) Since CRC is omitted TOTAL_LEN does not include its size. * 3) Printed base64 data are surrounded with special messages to help user recognize the start and end of actual data. */ -void esp_core_dump_to_uart(XtExcFrame *frame); +void esp_core_dump_to_uart(panic_info_t *info); /**************************************************************************************/ /*********************************** USER MODE API ************************************/ diff --git a/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_common.h b/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_common.h index b44296b3..b6836ba7 100644 --- a/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_common.h +++ b/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_common.h @@ -23,7 +23,7 @@ extern "C" { #endif #define MB_CONTROLLER_STACK_SIZE (CONFIG_FMB_CONTROLLER_STACK_SIZE) // Stack size for Modbus controller -#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_SERIAL_TASK_PRIO - 1) // priority of MB controller task +#define MB_CONTROLLER_PRIORITY (CONFIG_FMB_PORT_TASK_PRIO - 1) // priority of MB controller task // Default port defines #define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus @@ -67,8 +67,9 @@ typedef enum MB_PORT_SERIAL_MASTER = 0x00, /*!< Modbus port type serial master. */ MB_PORT_SERIAL_SLAVE, /*!< Modbus port type serial slave. */ MB_PORT_TCP_MASTER, /*!< Modbus port type TCP master. */ - MB_PORT_TCP_SLAVE, /*!< Modbus port type TCP slave. */ - MB_PORT_COUNT /*!< Modbus port count. */ + MB_PORT_TCP_SLAVE, /*!< Modbus port type TCP slave. */ + MB_PORT_COUNT, /*!< Modbus port count. */ + MB_PORT_INACTIVE = 0xFF } mb_port_type_t; /** @@ -104,8 +105,17 @@ typedef enum { typedef enum { MB_MODE_RTU, /*!< RTU transmission mode. */ MB_MODE_ASCII, /*!< ASCII transmission mode. */ - MB_MODE_TCP /*!< TCP mode. */ -} mb_mode_type_t; // Todo: This is common type leave it here for now + MB_MODE_TCP, /*!< TCP communication mode. */ + MB_MODE_UDP /*!< UDP communication mode. */ +} mb_mode_type_t; + +/*! + * \brief Modbus TCP type of address. + */ +typedef enum { + MB_IPV4 = 0, /*!< TCP IPV4 addressing */ + MB_IPV6 = 1 /*!< TCP IPV6 addressing */ +} mb_tcp_addr_type_t; /** * @brief Device communication structure to setup Modbus controller @@ -120,27 +130,27 @@ typedef union { uart_parity_t parity; /*!< Modbus UART parity settings */ uint16_t dummy_port; /*!< Dummy field, unused */ }; - // Tcp communication structure + // TCP/UDP communication structure struct { - mb_mode_type_t tcp_mode; /*!< Modbus communication mode */ - uint8_t dummy_addr; /*!< Modbus slave address field (dummy for master) */ - uart_port_t dummy_uart_port; /*!< Modbus communication port (UART) number */ - uint32_t dummy_baudrate; /*!< Modbus baudrate */ - uart_parity_t dummy_parity; /*!< Modbus UART parity settings */ - uint16_t tcp_port; /*!< Modbus TCP port */ + mb_mode_type_t ip_mode; /*!< Modbus communication mode */ + uint16_t ip_port; /*!< Modbus port */ + mb_tcp_addr_type_t ip_addr_type; /*!< Modbus address type */ + void* ip_addr; /*!< Modbus address table for connection */ + void* ip_netif_ptr; /*!< Modbus network interface */ }; } mb_communication_info_t; /** * common interface method types */ -typedef esp_err_t (*iface_init)(mb_port_type_t, void**); /*!< Interface method init */ -typedef esp_err_t (*iface_destroy)(void); /*!< Interface method destroy */ -typedef esp_err_t (*iface_setup)(void*); /*!< Interface method setup */ -typedef esp_err_t (*iface_start)(void); /*!< Interface method start */ +typedef esp_err_t (*iface_init)(void**); /*!< Interface method init */ +typedef esp_err_t (*iface_destroy)(void); /*!< Interface method destroy */ +typedef esp_err_t (*iface_setup)(void*); /*!< Interface method setup */ +typedef esp_err_t (*iface_start)(void); /*!< Interface method start */ #ifdef __cplusplus } #endif #endif // _MB_IFACE_COMMON_H + diff --git a/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_master.h b/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_master.h index 7b87ffaa..bb7dc7a0 100644 --- a/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_master.h +++ b/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_master.h @@ -107,18 +107,39 @@ typedef struct { uint16_t reg_size; /*!< Modbus number of registers */ } mb_param_request_t; -// Master interface public functions /** - * @brief Initialize Modbus controller and stack + * @brief Initialize Modbus controller and stack for TCP port * * @param[out] handler handler(pointer) to master data structure - * @param[in] port_type the type of port * @return - * - ESP_OK Success - * - ESP_ERR_NO_MEM Parameter error + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure + */ +esp_err_t mbc_master_init_tcp(void** handler); + +/** + * @brief Initialize Modbus Master controller and stack for Serial port + * + * @param[out] handler handler(pointer) to master data structure + * @param[in] port_type type of stack + * @return + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure */ esp_err_t mbc_master_init(mb_port_type_t port_type, void** handler); +/** + * @brief Initialize Modbus Master controller interface handle + * + * @param[in] handler - pointer to master data structure + * @return None + */ +void mbc_master_init_iface(void* handler); + /** * @brief Destroy Modbus controller and stack * diff --git a/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_slave.h b/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_slave.h index 1f911450..ed6a12ed 100644 --- a/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_slave.h +++ b/tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_slave.h @@ -50,17 +50,38 @@ typedef struct { } mb_register_area_descriptor_t; /** - * @brief Initialize Modbus controller and stack + * @brief Initialize Modbus Slave controller and stack for TCP port * * @param[out] handler handler(pointer) to master data structure - * @param[in] port_type type of stack * @return - * - ESP_OK Success - * - ESP_ERR_NO_MEM Parameter error + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure + */ +esp_err_t mbc_slave_init_tcp(void** handler); + +/** + * @brief Initialize Modbus Slave controller and stack for Serial port + * + * @param[out] handler handler(pointer) to master data structure + * @param[in] port_type the type of port + * @return + * - ESP_OK Success + * - ESP_ERR_NO_MEM Parameter error + * - ESP_ERR_NOT_SUPPORTED Port type not supported + * - ESP_ERR_INVALID_STATE Initialization failure */ -//esp_err_t mbc_slave_init(mb_port_type_t port_type, void** handler); esp_err_t mbc_slave_init(mb_port_type_t port_type, void** handler); +/** + * @brief Initialize Modbus Slave controller interface handle + * + * @param[in] handler - pointer to slave interface data structure + * @return None + */ +void mbc_slave_init_iface(void* handler); + /** * @brief Destroy Modbus controller and stack * diff --git a/tools/sdk/esp32s2/include/freemodbus/common/include/mbcontroller.h b/tools/sdk/esp32s2/include/freemodbus/common/include/mbcontroller.h index 3b73d676..08b3c183 100644 --- a/tools/sdk/esp32s2/include/freemodbus/common/include/mbcontroller.h +++ b/tools/sdk/esp32s2/include/freemodbus/common/include/mbcontroller.h @@ -30,4 +30,3 @@ #include "esp_modbus_slave.h" #endif - diff --git a/tools/sdk/esp32s2/include/freertos/include/freertos/task.h b/tools/sdk/esp32s2/include/freertos/include/freertos/task.h index 46863304..cfea1f0a 100644 --- a/tools/sdk/esp32s2/include/freertos/include/freertos/task.h +++ b/tools/sdk/esp32s2/include/freertos/include/freertos/task.h @@ -199,8 +199,6 @@ typedef struct xTASK_SNAPSHOT StackType_t *pxTopOfStack; /*!< Points to the location of the last item placed on the tasks stack. */ StackType_t *pxEndOfStack; /*!< Points to the end of the stack. pxTopOfStack < pxEndOfStack, stack grows hi2lo pxTopOfStack > pxEndOfStack, stack grows lo2hi*/ - eTaskState eState; /*!< Current state of the task. Can be running or suspended */ - BaseType_t xCpuId; /*!< CPU where this task was running */ } TaskSnapshot_t; /** diff --git a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h index 51cbcbce..6e589c67 100644 --- a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h +++ b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/FreeRTOSConfig.h @@ -120,8 +120,9 @@ int xt_clock_freq(void) __attribute__((deprecated)); /* configASSERT behaviour */ #ifndef __ASSEMBLER__ #include /* for abort() */ +#include "esp_rom_sys.h" #if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" +#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" #endif @@ -129,20 +130,20 @@ int xt_clock_freq(void) __attribute__((deprecated)); #if defined(CONFIG_FREERTOS_ASSERT_DISABLE) #define configASSERT(a) /* assertions disabled */ #elif defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE) -#define configASSERT(a) if (unlikely(!(a))) { \ - ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ - __FUNCTION__); \ +#define configASSERT(a) if (unlikely(!(a))) { \ + esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__); \ } #else /* CONFIG_FREERTOS_ASSERT_FAIL_ABORT */ -#define configASSERT(a) if (unlikely(!(a))) { \ - ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ - __FUNCTION__); \ - abort(); \ +#define configASSERT(a) if (unlikely(!(a))) { \ + esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \ + __FUNCTION__); \ + abort(); \ } #endif #if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION -#define UNTESTED_FUNCTION() { ets_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0) +#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0) #else #define UNTESTED_FUNCTION() #endif @@ -181,21 +182,30 @@ int xt_clock_freq(void) __attribute__((deprecated)); #define configMAX_PRIORITIES ( 25 ) #endif -#ifndef CONFIG_APPTRACE_ENABLE -#define configMINIMAL_STACK_SIZE 768 -#else +#if defined(CONFIG_APPTRACE_ENABLE) /* apptrace module requires at least 2KB of stack per task */ #define configMINIMAL_STACK_SIZE 2048 +#elif defined(CONFIG_COMPILER_OPTIMIZATION_NONE) +/* with optimizations disabled, scheduler uses additional stack */ +#define configMINIMAL_STACK_SIZE 1024 +#else +#define configMINIMAL_STACK_SIZE 768 #endif #ifndef configIDLE_TASK_STACK_SIZE #define configIDLE_TASK_STACK_SIZE CONFIG_FREERTOS_IDLE_TASK_STACKSIZE #endif -/* The Xtensa port uses a separate interrupt stack. Adjust the stack size */ -/* to suit the needs of your specific application. */ +/* Stack alignment, architecture specifc. Must be a power of two. */ +#define configSTACK_ALIGNMENT 16 + +/* The Xtensa port uses a separate interrupt stack. Adjust the stack size + * to suit the needs of your specific application. + * Size needs to be aligned to the stack increment, since the location of + * the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE. + */ #ifndef configISR_STACK_SIZE -#define configISR_STACK_SIZE CONFIG_FREERTOS_ISR_STACKSIZE +#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1))) #endif /* Minimal heap size to make sure examples can run on memory limited diff --git a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/portmacro.h b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/portmacro.h index 979ffeca..9c00fa16 100644 --- a/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/portmacro.h +++ b/tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/portmacro.h @@ -84,7 +84,7 @@ extern "C" { #include "esp_timer.h" /* required for FreeRTOS run time stats */ #include "soc/spinlock.h" #include - +#include "esp_rom_sys.h" #include "sdkconfig.h" #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS @@ -225,22 +225,22 @@ static inline void __attribute__((always_inline)) vPortEnterCriticalCompliance(p { if(!xPortInIsrContext()) { vPortEnterCritical(mux); - } else { - ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, - __FUNCTION__); - abort(); - } + } else { + esp_rom_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", + __FILE__, __LINE__, __FUNCTION__); + abort(); + } } static inline void __attribute__((always_inline)) vPortExitCriticalCompliance(portMUX_TYPE *mux) { if(!xPortInIsrContext()) { vPortExitCritical(mux); - } else { - ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__, - __FUNCTION__); - abort(); - } + } else { + esp_rom_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", + __FILE__, __LINE__, __FUNCTION__); + abort(); + } } #ifdef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE diff --git a/tools/sdk/esp32s2/include/idf_test/include/esp32/idf_performance_target.h b/tools/sdk/esp32s2/include/idf_test/include/esp32/idf_performance_target.h index 92173862..2e906b02 100644 --- a/tools/sdk/esp32s2/include/idf_test/include/esp32/idf_performance_target.h +++ b/tools/sdk/esp32s2/include/idf_test/include/esp32/idf_performance_target.h @@ -18,6 +18,18 @@ #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 30 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 27 +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (359*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 76600 +#endif + // floating point instructions per divide and per sqrt (configured for worst-case with PSRAM workaround) #define IDF_PERFORMANCE_MAX_CYCLES_PER_DIV 70 #define IDF_PERFORMANCE_MAX_CYCLES_PER_SQRT 140 diff --git a/tools/sdk/esp32s2/include/idf_test/include/esp32s2/idf_performance_target.h b/tools/sdk/esp32s2/include/idf_test/include/esp32s2/idf_performance_target.h index 64ba9293..ba29e146 100644 --- a/tools/sdk/esp32s2/include/idf_test/include/esp32s2/idf_performance_target.h +++ b/tools/sdk/esp32s2/include/idf_test/include/esp32s2/idf_performance_target.h @@ -7,7 +7,7 @@ #define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 90.0 // esp_sha() time to process 32KB of input data from RAM #define IDF_PERFORMANCE_MAX_TIME_SHA1_32KB 900 -#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 800 +#define IDF_PERFORMANCE_MAX_TIME_SHA512_32KB 900 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 13500 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 130000 @@ -16,3 +16,15 @@ #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 32 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 30 + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (309*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1504*1000) +#endif + +#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 52200 +#endif diff --git a/tools/sdk/esp32s2/include/idf_test/include/idf_performance.h b/tools/sdk/esp32s2/include/idf_test/include/idf_performance.h index 57d35ff3..4fb6364b 100644 --- a/tools/sdk/esp32s2/include/idf_test/include/idf_performance.h +++ b/tools/sdk/esp32s2/include/idf_test/include/idf_performance.h @@ -102,8 +102,9 @@ #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_RD_2KB (7088*1000) #endif +//This value is usually around 44K, but there are some chips with such low performance.... #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE 52200 +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_LEGACY_ERASE 12000 #endif #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B @@ -113,7 +114,7 @@ #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B 53600 #endif #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB (1015*1000) +#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_2KB (694*1000) #endif #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_2KB (7797*1000) @@ -142,18 +143,12 @@ #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_4B 68900 #endif -#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B (359*1000) -#endif +// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_4B in target file #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_WR_2KB (475*1000) #endif -#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB (1697*1000) -#endif -#ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE -#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE 81300 -#endif +// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_RD_2KB in target file +// IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_EXT_ERASE in target file //time to perform the task selection plus context switch (from task) #ifndef IDF_PERFORMANCE_MAX_SCHEDULING_TIME diff --git a/tools/sdk/esp32s2/include/log/include/esp_log.h b/tools/sdk/esp32s2/include/log/include/esp_log.h index cdbe74f6..1abc70c1 100644 --- a/tools/sdk/esp32s2/include/log/include/esp_log.h +++ b/tools/sdk/esp32s2/include/log/include/esp_log.h @@ -17,9 +17,10 @@ #include #include +#include "esp_rom_sys.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" +#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" #endif @@ -285,9 +286,9 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format, /// macro to output logs in startup code at ``ESP_LOG_VERBOSE`` level. @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf`` #define ESP_EARLY_LOGV( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__) -#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ - if (LOG_LOCAL_LEVEL >= log_level) { \ - ets_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \ +#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ + if (LOG_LOCAL_LEVEL >= log_level) { \ + esp_rom_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \ }} while(0) #ifndef BOOTLOADER_BUILD @@ -361,24 +362,24 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format, * * @note Placing log strings in DRAM reduces available DRAM, so only use when absolutely essential. * - * @see ``ets_printf``,``ESP_LOGE`` + * @see ``esp_rom_printf``,``ESP_LOGE`` */ #define ESP_DRAM_LOGE( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_ERROR, E, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_WARN`` level. @see ``ESP_DRAM_LOGW``,``ESP_LOGW``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_WARN`` level. @see ``ESP_DRAM_LOGW``,``ESP_LOGW``, ``esp_rom_printf`` #define ESP_DRAM_LOGW( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_WARN, W, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_INFO`` level. @see ``ESP_DRAM_LOGI``,``ESP_LOGI``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_INFO`` level. @see ``ESP_DRAM_LOGI``,``ESP_LOGI``, ``esp_rom_printf`` #define ESP_DRAM_LOGI( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_INFO, I, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_DEBUG`` level. @see ``ESP_DRAM_LOGD``,``ESP_LOGD``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_DEBUG`` level. @see ``ESP_DRAM_LOGD``,``ESP_LOGD``, ``esp_rom_printf`` #define ESP_DRAM_LOGD( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_DEBUG, D, ##__VA_ARGS__) -/// macro to output logs when the cache is disabled at ``ESP_LOG_VERBOSE`` level. @see ``ESP_DRAM_LOGV``,``ESP_LOGV``, ``ets_printf`` +/// macro to output logs when the cache is disabled at ``ESP_LOG_VERBOSE`` level. @see ``ESP_DRAM_LOGV``,``ESP_LOGV``, ``esp_rom_printf`` #define ESP_DRAM_LOGV( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__) /** @cond */ #define _ESP_LOG_DRAM_LOG_FORMAT(letter, format) DRAM_STR(#letter " %s: " format "\n") -#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ - if (LOG_LOCAL_LEVEL >= log_level) { \ - ets_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \ +#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \ + if (LOG_LOCAL_LEVEL >= log_level) { \ + esp_rom_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \ }} while(0) /** @endcond */ diff --git a/tools/sdk/esp32s2/include/lwip/include/apps/ping/ping_sock.h b/tools/sdk/esp32s2/include/lwip/include/apps/ping/ping_sock.h index ef1189e8..f2581fdb 100644 --- a/tools/sdk/esp32s2/include/lwip/include/apps/ping/ping_sock.h +++ b/tools/sdk/esp32s2/include/lwip/include/apps/ping/ping_sock.h @@ -82,7 +82,7 @@ typedef struct { .count = 5, \ .interval_ms = 1000, \ .timeout_ms = 1000, \ - .data_size = 56, \ + .data_size = 64, \ .tos = 0, \ .target_addr = ip_addr_any_type, \ .task_stack_size = 2048, \ diff --git a/tools/sdk/esp32s2/include/lwip/lwip/src/include/lwip/opt.h b/tools/sdk/esp32s2/include/lwip/lwip/src/include/lwip/opt.h index 3a338d5a..cdd7044c 100644 --- a/tools/sdk/esp32s2/include/lwip/lwip/src/include/lwip/opt.h +++ b/tools/sdk/esp32s2/include/lwip/lwip/src/include/lwip/opt.h @@ -1534,6 +1534,11 @@ #define LWIP_ALTCP_TLS 0 #endif +#if ESP_LWIP +#if !defined LWIP_TCP_RTO_TIME || defined __DOXYGEN__ +#define LWIP_TCP_RTO_TIME 3000 +#endif +#endif /** * @} */ @@ -2585,6 +2590,14 @@ #define LWIP_ND6_QUEUEING LWIP_IPV6 #endif +/** + * ESP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address + * is being resolved. + */ +#if !defined ESP_ND6_QUEUEING || defined __DOXYGEN__ +#define ESP_ND6_QUEUEING LWIP_IPV6 +#endif + /** * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. */ diff --git a/tools/sdk/esp32s2/include/lwip/port/esp32/include/lwipopts.h b/tools/sdk/esp32s2/include/lwip/port/esp32/include/lwipopts.h index 978857d6..5e178a20 100644 --- a/tools/sdk/esp32s2/include/lwip/port/esp32/include/lwipopts.h +++ b/tools/sdk/esp32s2/include/lwip/port/esp32/include/lwipopts.h @@ -157,18 +157,32 @@ -------------------------------- */ /** - * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP4 packets. Note that * this option does not affect outgoing packet sizes, which can be controlled * via IP_FRAG. */ -#define IP_REASSEMBLY CONFIG_LWIP_IP_REASSEMBLY +#define IP_REASSEMBLY CONFIG_LWIP_IP4_REASSEMBLY /** - * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * LWIP_IPV6_REASS==1: reassemble incoming IP6 packets that fragmented. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via LWIP_IPV6_FRAG. + */ +#define LWIP_IPV6_REASS CONFIG_LWIP_IP6_REASSEMBLY + +/** + * IP_FRAG==1: Fragment outgoing IP4 packets if their size exceeds MTU. Note * that this option does not affect incoming packet sizes, which can be * controlled via IP_REASSEMBLY. */ -#define IP_FRAG CONFIG_LWIP_IP_FRAG +#define IP_FRAG CONFIG_LWIP_IP4_FRAG + +/** + * LWIP_IPV6_FRAG==1: Fragment outgoing IP6 packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#define LWIP_IPV6_FRAG CONFIG_LWIP_IP6_FRAG /** * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) @@ -400,6 +414,12 @@ #define TCP_RCV_SCALE CONFIG_LWIP_TCP_RCV_SCALE #endif +/** + * LWIP_TCP_RTO_TIME: TCP rto time. + * Default is 3 second. + */ +#define LWIP_TCP_RTO_TIME CONFIG_LWIP_TCP_RTO_TIME + /* ---------------------------------- ---------- Pbuf options ---------- @@ -454,6 +474,34 @@ ------------------------------------ */ +#ifdef CONFIG_LWIP_SLIP_SUPPORT + +/** + * Enable SLIP receive from ISR functions and disable Rx thread + * + * This is the only supported mode of lwIP SLIP interface, so that + * - incoming packets are queued into pbufs + * - no thread is created from lwIP + * meaning it is the application responsibility to read data + * from IO driver and feed them to the slip interface + */ +#define SLIP_RX_FROM_ISR 1 +#define SLIP_USE_RX_THREAD 0 + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#define SLIP_DEBUG_ON CONFIG_LWIP_SLIP_DEBUG_ON + +#if SLIP_DEBUG_ON +#define SLIP_DEBUG LWIP_DBG_ON +#else +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + + +#endif + /* ------------------------------------ ---------- Thread options ---------- @@ -704,6 +752,16 @@ */ #define LWIP_IPV6 1 +/** + * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. + */ +#define MEMP_NUM_ND6_QUEUE CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE + +/** + * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache + */ +#define LWIP_ND6_NUM_NEIGHBORS CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS + /* --------------------------------------- ---------- Hook options --------------- @@ -718,37 +776,82 @@ /** * ETHARP_DEBUG: Enable debugging in etharp.c. */ -#define ETHARP_DEBUG LWIP_DBG_OFF +#ifdef CONFIG_LWIP_ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_ON +#else +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + /** * NETIF_DEBUG: Enable debugging in netif.c. */ +#ifdef CONFIG_LWIP_NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_ON +#else #define NETIF_DEBUG LWIP_DBG_OFF +#endif /** * PBUF_DEBUG: Enable debugging in pbuf.c. */ -#define PBUF_DEBUG LWIP_DBG_OFF +#ifdef CONFIG_LWIP_PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_ON +#else +#define PBUF_DEBUG LWIP_DBG_OFF +#endif /** * API_LIB_DEBUG: Enable debugging in api_lib.c. */ -#define API_LIB_DEBUG LWIP_DBG_OFF +#ifdef CONFIG_LWIP_API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_ON +#else +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + /** * SOCKETS_DEBUG: Enable debugging in sockets.c. */ +#ifdef CONFIG_LWIP_SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_ON +#else #define SOCKETS_DEBUG LWIP_DBG_OFF +#endif /** * ICMP_DEBUG: Enable debugging in icmp.c. */ +#ifdef CONFIG_LWIP_ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_ON +#else #define ICMP_DEBUG LWIP_DBG_OFF +#endif + +#ifdef CONFIG_LWIP_ICMP6_DEBUG +#define ICMP6_DEBUG LWIP_DBG_ON +#else +#define ICMP6_DEBUG LWIP_DBG_OFF +#endif /** * IP_DEBUG: Enable debugging for IP. */ +#ifdef CONFIG_LWIP_IP_DEBUG +#define IP_DEBUG LWIP_DBG_ON +#else #define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifdef CONFIG_LWIP_IP6_DEBUG +#define IP6_DEBUG LWIP_DBG_ON +#else +#define IP6_DEBUG LWIP_DBG_OFF +#endif /** * MEMP_DEBUG: Enable debugging in memp.c. diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aes.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aes.h index 94e7282d..d20cdbd6 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aes.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aes.h @@ -20,8 +20,15 @@ * . */ -/* Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. - * SPDX-License-Identifier: Apache-2.0 +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -35,6 +42,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aesni.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aesni.h index a4ca012f..91a4e0f1 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aesni.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aesni.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_AESNI_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/arc4.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/arc4.h index fb044d5b..ecaf3101 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/arc4.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/arc4.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) * */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aria.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aria.h index 1e8956ed..66f2668b 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aria.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/aria.h @@ -9,8 +9,15 @@ * Korean, but see http://210.104.33.10/ARIA/index-e.html in English) * and also described by the IETF in RFC 5794. */ -/* Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 +/* + * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -24,6 +31,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1.h index 96c1c9a8..c64038cd 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ASN1_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1write.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1write.h index a1942436..4fed5937 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1write.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/asn1write.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ASN1_WRITE_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/base64.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/base64.h index 0d024164..215255e6 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/base64.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/base64.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BASE64_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bignum.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bignum.h index 1fb3dd7b..1e41d702 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bignum.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bignum.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BIGNUM_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/blowfish.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/blowfish.h index f01573dc..d2a1ebdb 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/blowfish.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/blowfish.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_BLOWFISH_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h index 748975ea..42339b7b 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/bn_mul.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ /* diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/camellia.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/camellia.h index 3eeb6636..41d6f955 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/camellia.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/camellia.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CAMELLIA_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ccm.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ccm.h index f03e3b58..3647d509 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ccm.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ccm.h @@ -29,7 +29,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -43,6 +49,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/certs.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/certs.h index 179ebbba..2a645ad0 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/certs.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/certs.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CERTS_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chacha20.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chacha20.h index 2ae5e6e5..e2950e1a 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chacha20.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chacha20.h @@ -12,8 +12,15 @@ * \author Daniel King */ -/* Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. - * SPDX-License-Identifier: Apache-2.0 +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -27,6 +34,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chachapoly.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chachapoly.h index 49e615d2..bee5a3ab 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chachapoly.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/chachapoly.h @@ -12,8 +12,15 @@ * \author Daniel King */ -/* Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. - * SPDX-License-Identifier: Apache-2.0 +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -27,6 +34,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/check_config.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/check_config.h index d076c235..8ce73cef 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/check_config.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/check_config.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ @@ -140,6 +167,16 @@ #error "MBEDTLS_ECP_C defined, but not all prerequisites" #endif +#if defined(MBEDTLS_ECP_C) && !( \ + defined(MBEDTLS_ECP_ALT) || \ + defined(MBEDTLS_CTR_DRBG_C) || \ + defined(MBEDTLS_HMAC_DRBG_C) || \ + defined(MBEDTLS_SHA512_C) || \ + defined(MBEDTLS_SHA256_C) || \ + defined(MBEDTLS_ECP_NO_INTERNAL_RNG)) +#error "MBEDTLS_ECP_C requires a DRBG or SHA-2 module unless MBEDTLS_ECP_NO_INTERNAL_RNG is defined or an alternative implementation is used" +#endif + #if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_ASN1_PARSE_C) #error "MBEDTLS_PK_PARSE_C defined, but not all prerequesites" #endif @@ -546,6 +583,23 @@ #error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites" #endif +#if (defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2)) && \ + !(defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) ) +#error "One or more versions of the TLS protocol are enabled " \ + "but no key exchange methods defined with MBEDTLS_KEY_EXCHANGE_xxxx" +#endif + #if defined(MBEDTLS_SSL_PROTO_DTLS) && \ !defined(MBEDTLS_SSL_PROTO_TLS1_1) && \ !defined(MBEDTLS_SSL_PROTO_TLS1_2) @@ -669,6 +723,10 @@ #error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites" #endif +#if defined(MBEDTLS_CERTS_C) && !defined(MBEDTLS_X509_USE_C) +#error "MBEDTLS_CERTS_C defined, but not all prerequisites" +#endif + #if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) #error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites" #endif diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher.h index 082a6917..8672dd2b 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher_internal.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher_internal.h index c6def0be..558be52a 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher_internal.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cipher_internal.h @@ -7,7 +7,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -21,6 +27,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_CIPHER_WRAP_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cmac.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cmac.h index 9d42b3f2..20747475 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cmac.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/cmac.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2015-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/compat-1.3.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/compat-1.3.h index a58b4724..71cc4f4d 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/compat-1.3.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/compat-1.3.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/config.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/config.h index 834cced8..f7e55aef 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/config.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/config.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ @@ -780,6 +807,28 @@ */ #define MBEDTLS_ECP_NIST_OPTIM +/** + * \def MBEDTLS_ECP_NO_INTERNAL_RNG + * + * When this option is disabled, mbedtls_ecp_mul() will make use of an + * internal RNG when called with a NULL \c f_rng argument, in order to protect + * against some side-channel attacks. + * + * This protection introduces a dependency of the ECP module on one of the + * DRBG or SHA modules (HMAC-DRBG, CTR-DRBG, SHA-512 or SHA-256.) For very + * constrained applications that don't require this protection (for example, + * because you're only doing signature verification, so not manipulating any + * secret, or because local/physical side-channel attacks are outside your + * threat model), it might be desirable to get rid of that dependency. + * + * \warning Enabling this option makes some uses of ECP vulnerable to some + * side-channel attacks. Only enable it if you know that's not a problem for + * your use case. + * + * Uncomment this macro to disable some counter-measures in ECP. + */ +//#define MBEDTLS_ECP_NO_INTERNAL_RNG + /** * \def MBEDTLS_ECP_RESTARTABLE * diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h index e0b5ed9c..894fa171 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ctr_drbg.h @@ -39,7 +39,13 @@ */ /* * Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -53,6 +59,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/debug.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/debug.h index 736444bb..11928e98 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/debug.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/debug.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_DEBUG_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/des.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/des.h index 54e6b789..4c6441d7 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/des.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/des.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) * */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/dhm.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/dhm.h index 2909f5fb..5c04ed19 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/dhm.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/dhm.h @@ -45,7 +45,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -59,6 +65,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdh.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdh.h index 4479a1d4..a0052df4 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdh.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdh.h @@ -14,7 +14,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -28,6 +34,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h index 932acc6d..bc219dca 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecdsa.h @@ -12,7 +12,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -26,6 +32,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecjpake.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecjpake.h index 3d8d02ae..1b6c6ac2 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecjpake.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecjpake.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ECJPAKE_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp.h index 065a4cc0..8db20606 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp.h @@ -16,7 +16,13 @@ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -30,6 +36,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ @@ -813,6 +840,9 @@ int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, * intermediate results to prevent potential timing attacks * targeting these results. We recommend always providing * a non-NULL \p f_rng. The overhead is negligible. + * Note: unless #MBEDTLS_ECP_NO_INTERNAL_RNG is defined, when + * \p f_rng is NULL, an internal RNG (seeded from the value + * of \p m) will be used instead. * * \param grp The ECP group to use. * This must be initialized and have group parameters diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp_internal.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp_internal.h index 7625ed48..4e9445ae 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp_internal.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ecp_internal.h @@ -6,7 +6,13 @@ */ /* * Copyright (C) 2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -20,6 +26,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy.h index ca06dc3c..fd70cd7e 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ENTROPY_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy_poll.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy_poll.h index 94dd657e..9843a9e4 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy_poll.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/entropy_poll.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ENTROPY_POLL_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/error.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/error.h index bee0fe48..3ee7bbba 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/error.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/error.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_ERROR_H @@ -100,6 +127,7 @@ * ECP 4 10 (Started from top) * MD 5 5 * HKDF 5 1 (Started from top) + * SSL 5 1 (Started from 0x5E80) * CIPHER 6 8 * SSL 6 23 (Started from top) * SSL 7 32 diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/gcm.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/gcm.h index fd130abd..52d03b0c 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/gcm.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/gcm.h @@ -13,7 +13,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -27,6 +33,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/havege.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/havege.h index 4c1c8608..75ab3cb9 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/havege.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/havege.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HAVEGE_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hkdf.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hkdf.h index bcafe425..a8db554d 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hkdf.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hkdf.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2016-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HKDF_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h index 7931c228..231fb459 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/hmac_drbg.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2019, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_HMAC_DRBG_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md.h index 8bcf766a..6a21f059 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md.h @@ -7,7 +7,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -21,6 +27,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ @@ -98,6 +125,8 @@ typedef struct mbedtls_md_context_t * \brief This function returns the list of digests supported by the * generic digest module. * + * \note The list starts with the strongest available hashes. + * * \return A statically allocated array of digests. Each element * in the returned list is an integer belonging to the * message-digest enumeration #mbedtls_md_type_t. diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md2.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md2.h index fe97cf08..6d563b41 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md2.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md2.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) * */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md4.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md4.h index ce703c0b..3f4bcdc6 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md4.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md4.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) * */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md5.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md5.h index 6eed6cc8..34279c72 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md5.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md5.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MD5_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md_internal.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md_internal.h index 04de4829..154b8bbc 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md_internal.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/md_internal.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MD_WRAP_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/memory_buffer_alloc.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/memory_buffer_alloc.h index 705f9a63..c1e0926b 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/memory_buffer_alloc.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/memory_buffer_alloc.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_MEMORY_BUFFER_ALLOC_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net.h index 8cead58e..bba4a359 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net.h @@ -7,7 +7,13 @@ */ /* * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -21,6 +27,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #if !defined(MBEDTLS_CONFIG_FILE) diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net_sockets.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net_sockets.h index 4c7ef00f..d4d23fe9 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net_sockets.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/net_sockets.h @@ -21,7 +21,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -35,6 +41,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_NET_SOCKETS_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/nist_kw.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/nist_kw.h index 3b67b59c..f2b9cebf 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/nist_kw.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/nist_kw.h @@ -17,7 +17,13 @@ */ /* * Copyright (C) 2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -31,6 +37,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/oid.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/oid.h index 6fbd018a..7fe4b386 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/oid.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/oid.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_OID_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/padlock.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/padlock.h index 721a5d49..bd476f5f 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/padlock.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/padlock.h @@ -9,7 +9,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -23,6 +29,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PADLOCK_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pem.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pem.h index a29e9ce3..16b61014 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pem.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pem.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PEM_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk.h index 13642750..408f7bae 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk_internal.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk_internal.h index 48b7a5f7..1cd05943 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk_internal.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pk_internal.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs11.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs11.h index 02427ddc..e1446120 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs11.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs11.h @@ -7,7 +7,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -21,6 +27,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PKCS11_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs12.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs12.h index d441357b..c418e8f2 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs12.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs12.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PKCS12_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs5.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs5.h index c92185f7..c3f645af 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs5.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/pkcs5.h @@ -7,7 +7,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -21,6 +27,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PKCS5_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform.h index 89fe8a7b..dcb5a88e 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform.h @@ -14,7 +14,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -28,6 +34,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_time.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_time.h index 2ed36f56..a45870c3 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_time.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_time.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_TIME_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_util.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_util.h index 09d09651..f10574af 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_util.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/platform_util.h @@ -6,7 +6,13 @@ */ /* * Copyright (C) 2018, Arm Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -20,6 +26,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_PLATFORM_UTIL_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/poly1305.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/poly1305.h index f0ec44c9..6e45b2c2 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/poly1305.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/poly1305.h @@ -12,8 +12,15 @@ * \author Daniel King */ -/* Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. - * SPDX-License-Identifier: Apache-2.0 +/* + * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved. + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -27,6 +34,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ripemd160.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ripemd160.h index b42f6d2a..505c3925 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ripemd160.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ripemd160.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_RIPEMD160_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa.h index 35bacd87..cd22fc4c 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa.h @@ -11,7 +11,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -25,6 +31,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_RSA_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa_internal.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa_internal.h index 53abd3c5..2464e6b0 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa_internal.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/rsa_internal.h @@ -36,7 +36,13 @@ */ /* * Copyright (C) 2006-2017, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -50,6 +56,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) * */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha1.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha1.h index bb6ecf05..e69db8a1 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha1.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha1.h @@ -12,7 +12,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -26,6 +32,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SHA1_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha256.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha256.h index d6473982..5b03bc31 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha256.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha256.h @@ -8,7 +8,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -22,6 +28,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SHA256_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha512.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha512.h index c06ceed1..2fbc69f8 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha512.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/sha512.h @@ -7,7 +7,13 @@ */ /* * Copyright (C) 2006-2018, Arm Limited (or its affiliates), All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -21,6 +27,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of Mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SHA512_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl.h index 1adf9608..6f569835 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_H @@ -123,6 +150,7 @@ #define MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS -0x6500 /**< The asynchronous operation is not completed yet. */ #define MBEDTLS_ERR_SSL_EARLY_MESSAGE -0x6480 /**< Internal-only message signaling that a message arrived early. */ #define MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS -0x7000 /**< A cryptographic operation is in progress. Try again later. */ +#define MBEDTLS_ERR_SSL_BAD_CONFIG -0x5E80 /**< Invalid value in SSL config */ /* * Various constants @@ -137,6 +165,9 @@ #define MBEDTLS_SSL_TRANSPORT_DATAGRAM 1 /*!< DTLS */ #define MBEDTLS_SSL_MAX_HOST_NAME_LEN 255 /*!< Maximum host name defined in RFC 1035 */ +#define MBEDTLS_SSL_MAX_ALPN_NAME_LEN 255 /*!< Maximum size in bytes of a protocol name in alpn ext., RFC 7301 */ + +#define MBEDTLS_SSL_MAX_ALPN_LIST_LEN 65535 /*!< Maximum size in bytes of list in alpn ext., RFC 7301 */ /* RFC 6066 section 4, see also mfl_code_to_length in ssl_tls.c * NONE must be zero so that memset()ing structure to zero works */ diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cache.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cache.h index 52ba0948..e987c29e 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cache.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cache.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_CACHE_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ciphersuites.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ciphersuites.h index 71053e5b..89691411 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ciphersuites.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ciphersuites.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_CIPHERSUITES_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cookie.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cookie.h index e34760ae..71e05678 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cookie.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_cookie.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_COOKIE_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_internal.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_internal.h index bd5ad94d..b371094f 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_internal.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_internal.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_INTERNAL_H @@ -182,6 +209,12 @@ : ( MBEDTLS_SSL_IN_CONTENT_LEN ) \ ) +/* Maximum size in bytes of list in sig-hash algorithm ext., RFC 5246 */ +#define MBEDTLS_SSL_MAX_SIG_HASH_ALG_LIST_LEN 65534 + +/* Maximum size in bytes of list in supported elliptic curve ext., RFC 4492 */ +#define MBEDTLS_SSL_MAX_CURVE_LIST_LEN 65535 + /* * Check that we obey the standard's message size bounds */ @@ -236,6 +269,41 @@ #define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT (1 << 0) #define MBEDTLS_TLS_EXT_ECJPAKE_KKPP_OK (1 << 1) +/** + * \brief This function checks if the remaining size in a buffer is + * greater or equal than a needed space. + * + * \param cur Pointer to the current position in the buffer. + * \param end Pointer to one past the end of the buffer. + * \param need Needed space in bytes. + * + * \return Zero if the needed space is available in the buffer, non-zero + * otherwise. + */ +static inline int mbedtls_ssl_chk_buf_ptr( const uint8_t *cur, + const uint8_t *end, size_t need ) +{ + return( ( cur > end ) || ( need > (size_t)( end - cur ) ) ); +} + +/** + * \brief This macro checks if the remaining size in a buffer is + * greater or equal than a needed space. If it is not the case, + * it returns an SSL_BUFFER_TOO_SMALL error. + * + * \param cur Pointer to the current position in the buffer. + * \param end Pointer to one past the end of the buffer. + * \param need Needed space in bytes. + * + */ +#define MBEDTLS_SSL_CHK_BUF_PTR( cur, end, need ) \ + do { \ + if( mbedtls_ssl_chk_buf_ptr( ( cur ), ( end ), ( need ) ) != 0 ) \ + { \ + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); \ + } \ + } while( 0 ) + #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h index 774a007a..ac3be043 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/ssl_ticket.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_SSL_TICKET_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/threading.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/threading.h index 92e6e6b9..b6ec4df8 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/threading.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/threading.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_THREADING_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/timing.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/timing.h index a965fe0d..149ccfb6 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/timing.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/timing.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_TIMING_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/version.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/version.h index 8e2ce03c..2bff31d5 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/version.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/version.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ /* @@ -40,16 +67,16 @@ */ #define MBEDTLS_VERSION_MAJOR 2 #define MBEDTLS_VERSION_MINOR 16 -#define MBEDTLS_VERSION_PATCH 5 +#define MBEDTLS_VERSION_PATCH 7 /** * The single version number has the following structure: * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x02100500 -#define MBEDTLS_VERSION_STRING "2.16.5" -#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.5" +#define MBEDTLS_VERSION_NUMBER 0x02100700 +#define MBEDTLS_VERSION_STRING "2.16.7" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.16.7" #if defined(MBEDTLS_VERSION_C) diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509.h index 63aae32d..e9f2fc60 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h index fa838d68..0e37f65e 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crl.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CRL_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crt.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crt.h index 670bd10d..4aae923e 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crt.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_crt.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CRT_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_csr.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_csr.h index a3c28048..8ba2cda0 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_csr.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/x509_csr.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_X509_CSR_H diff --git a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/xtea.h b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/xtea.h index b47f5535..d3721102 100644 --- a/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/xtea.h +++ b/tools/sdk/esp32s2/include/mbedtls/mbedtls/include/mbedtls/xtea.h @@ -5,7 +5,13 @@ */ /* * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + * + * This file is provided under the Apache License 2.0, or the + * GNU General Public License v2.0 or later. + * + * ********** + * Apache License 2.0: * * Licensed under the Apache License, Version 2.0 (the "License"); you may * not use this file except in compliance with the License. @@ -19,6 +25,27 @@ * See the License for the specific language governing permissions and * limitations under the License. * + * ********** + * + * ********** + * GNU General Public License v2.0 or later: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * ********** + * * This file is part of mbed TLS (https://tls.mbed.org) */ #ifndef MBEDTLS_XTEA_H diff --git a/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h b/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h index 93c8ce28..60826e6c 100644 --- a/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h +++ b/tools/sdk/esp32s2/include/mbedtls/port/include/mbedtls/esp_config.h @@ -976,6 +976,8 @@ */ #ifdef CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 #define MBEDTLS_SSL_PROTO_TLS1_1 +#else +#undef MBEDTLS_SSL_PROTO_TLS1_1 #endif /** diff --git a/tools/sdk/esp32s2/include/newlib/platform_include/esp_newlib.h b/tools/sdk/esp32s2/include/newlib/platform_include/esp_newlib.h index 11658776..c43d6ec2 100644 --- a/tools/sdk/esp32s2/include/newlib/platform_include/esp_newlib.h +++ b/tools/sdk/esp32s2/include/newlib/platform_include/esp_newlib.h @@ -17,6 +17,11 @@ #include +/* + * Initialize newlib time functions + */ +void esp_newlib_time_init(void); + /** * Replacement for newlib's _REENT_INIT_PTR and __sinit. * diff --git a/tools/sdk/esp32s2/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h b/tools/sdk/esp32s2/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h index 1c74b35c..9be6eea5 100644 --- a/tools/sdk/esp32s2/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h +++ b/tools/sdk/esp32s2/include/nghttp/nghttp2/lib/includes/nghttp2/nghttp2.h @@ -28,7 +28,12 @@ /* Define WIN32 when build target is Win32 API (borrowed from libcurl) */ #if (defined(_WIN32) || defined(__WIN32__)) && !defined(WIN32) -#define WIN32 +# define WIN32 +#endif + +/* Compatibility for non-Clang compilers */ +#ifndef __has_declspec_attribute +# define __has_declspec_attribute(x) 0 #endif #ifdef __cplusplus @@ -40,9 +45,9 @@ extern "C" { /* MSVC < 2013 does not have inttypes.h because it is not C99 compliant. See compiler macros and version number in https://sourceforge.net/p/predef/wiki/Compilers/ */ -#include +# include #else /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */ -#include +# include #endif /* !defined(_MSC_VER) || (_MSC_VER >= 1800) */ #include #include @@ -50,20 +55,21 @@ extern "C" { #include #ifdef NGHTTP2_STATICLIB -#define NGHTTP2_EXTERN -#elif defined(WIN32) -#ifdef BUILDING_NGHTTP2 -#define NGHTTP2_EXTERN __declspec(dllexport) -#else /* !BUILDING_NGHTTP2 */ -#define NGHTTP2_EXTERN __declspec(dllimport) -#endif /* !BUILDING_NGHTTP2 */ -#else /* !defined(WIN32) */ -#ifdef BUILDING_NGHTTP2 -#define NGHTTP2_EXTERN __attribute__((visibility("default"))) -#else /* !BUILDING_NGHTTP2 */ -#define NGHTTP2_EXTERN -#endif /* !BUILDING_NGHTTP2 */ -#endif /* !defined(WIN32) */ +# define NGHTTP2_EXTERN +#elif defined(WIN32) || (__has_declspec_attribute(dllexport) && \ + __has_declspec_attribute(dllimport)) +# ifdef BUILDING_NGHTTP2 +# define NGHTTP2_EXTERN __declspec(dllexport) +# else /* !BUILDING_NGHTTP2 */ +# define NGHTTP2_EXTERN __declspec(dllimport) +# endif /* !BUILDING_NGHTTP2 */ +#else /* !defined(WIN32) */ +# ifdef BUILDING_NGHTTP2 +# define NGHTTP2_EXTERN __attribute__((visibility("default"))) +# else /* !BUILDING_NGHTTP2 */ +# define NGHTTP2_EXTERN +# endif /* !BUILDING_NGHTTP2 */ +#endif /* !defined(WIN32) */ /** * @macro @@ -222,6 +228,13 @@ typedef struct { */ #define NGHTTP2_CLIENT_MAGIC_LEN 24 +/** + * @macro + * + * The default max number of settings per SETTINGS frame + */ +#define NGHTTP2_DEFAULT_MAX_SETTINGS 32 + /** * @enum * @@ -387,6 +400,16 @@ typedef enum { * Indicates that a processing was canceled. */ NGHTTP2_ERR_CANCEL = -535, + /** + * When a local endpoint expects to receive SETTINGS frame, it + * receives an other type of frame. + */ + NGHTTP2_ERR_SETTINGS_EXPECTED = -536, + /** + * When a local endpoint receives too many settings entries + * in a single SETTINGS frame. + */ + NGHTTP2_ERR_TOO_MANY_SETTINGS = -537, /** * The errors < :enum:`NGHTTP2_ERR_FATAL` mean that the library is * under unexpected condition and processing was terminated (e.g., @@ -469,6 +492,15 @@ NGHTTP2_EXTERN void nghttp2_rcbuf_decref(nghttp2_rcbuf *rcbuf); */ NGHTTP2_EXTERN nghttp2_vec nghttp2_rcbuf_get_buf(nghttp2_rcbuf *rcbuf); +/** + * @function + * + * Returns nonzero if the underlying buffer is statically allocated, + * and 0 otherwise. This can be useful for language bindings that wish + * to avoid creating duplicate strings for these buffers. + */ +NGHTTP2_EXTERN int nghttp2_rcbuf_is_static(const nghttp2_rcbuf *rcbuf); + /** * @enum * @@ -597,7 +629,12 @@ typedef enum { * The ALTSVC frame, which is defined in `RFC 7383 * `_. */ - NGHTTP2_ALTSVC = 0x0a + NGHTTP2_ALTSVC = 0x0a, + /** + * The ORIGIN frame, which is defined by `RFC 8336 + * `_. + */ + NGHTTP2_ORIGIN = 0x0c } nghttp2_frame_type; /** @@ -661,7 +698,12 @@ typedef enum { /** * SETTINGS_MAX_HEADER_LIST_SIZE */ - NGHTTP2_SETTINGS_MAX_HEADER_LIST_SIZE = 0x06 + NGHTTP2_SETTINGS_MAX_HEADER_LIST_SIZE = 0x06, + /** + * SETTINGS_ENABLE_CONNECT_PROTOCOL + * (`RFC 8441 `_) + */ + NGHTTP2_SETTINGS_ENABLE_CONNECT_PROTOCOL = 0x08 } nghttp2_settings_id; /* Note: If we add SETTINGS, update the capacity of NGHTTP2_INBOUND_NUM_IV as well */ @@ -1978,6 +2020,9 @@ typedef ssize_t (*nghttp2_pack_extension_callback)(nghttp2_session *session, * of length |len|. |len| does not include the sentinel NULL * character. * + * This function is deprecated. The new application should use + * :type:`nghttp2_error_callback2`. + * * The format of error message may change between nghttp2 library * versions. The application should not depend on the particular * format. @@ -1994,6 +2039,33 @@ typedef ssize_t (*nghttp2_pack_extension_callback)(nghttp2_session *session, typedef int (*nghttp2_error_callback)(nghttp2_session *session, const char *msg, size_t len, void *user_data); +/** + * @functypedef + * + * Callback function invoked when library provides the error code, and + * message. This callback is solely for debugging purpose. + * |lib_error_code| is one of error code defined in + * :enum:`nghttp2_error`. The |msg| is typically NULL-terminated + * string of length |len|, and intended for human consumption. |len| + * does not include the sentinel NULL character. + * + * The format of error message may change between nghttp2 library + * versions. The application should not depend on the particular + * format. + * + * Normally, application should return 0 from this callback. If fatal + * error occurred while doing something in this callback, application + * should return :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`. In this case, + * library will return immediately with return value + * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`. Currently, if nonzero value + * is returned from this callback, they are treated as + * :enum:`NGHTTP2_ERR_CALLBACK_FAILURE`, but application should not + * rely on this details. + */ +typedef int (*nghttp2_error_callback2)(nghttp2_session *session, + int lib_error_code, const char *msg, + size_t len, void *user_data); + struct nghttp2_session_callbacks; /** @@ -2258,10 +2330,30 @@ nghttp2_session_callbacks_set_on_extension_chunk_recv_callback( * * Sets callback function invoked when library tells error message to * the application. + * + * This function is deprecated. The new application should use + * `nghttp2_session_callbacks_set_error_callback2()`. + * + * If both :type:`nghttp2_error_callback` and + * :type:`nghttp2_error_callback2` are set, the latter takes + * precedence. */ NGHTTP2_EXTERN void nghttp2_session_callbacks_set_error_callback( nghttp2_session_callbacks *cbs, nghttp2_error_callback error_callback); +/** + * @function + * + * Sets callback function invoked when library tells error code, and + * message to the application. + * + * If both :type:`nghttp2_error_callback` and + * :type:`nghttp2_error_callback2` are set, the latter takes + * precedence. + */ +NGHTTP2_EXTERN void nghttp2_session_callbacks_set_error_callback2( + nghttp2_session_callbacks *cbs, nghttp2_error_callback2 error_callback2); + /** * @functypedef * @@ -2409,15 +2501,15 @@ nghttp2_option_set_no_auto_window_update(nghttp2_option *option, int val); * * This option sets the SETTINGS_MAX_CONCURRENT_STREAMS value of * remote endpoint as if it is received in SETTINGS frame. Without - * specifying this option, before the local endpoint receives - * SETTINGS_MAX_CONCURRENT_STREAMS in SETTINGS frame from remote - * endpoint, SETTINGS_MAX_CONCURRENT_STREAMS is unlimited. This may - * cause problem if local endpoint submits lots of requests initially - * and sending them at once to the remote peer may lead to the - * rejection of some requests. Specifying this option to the sensible - * value, say 100, may avoid this kind of issue. This value will be - * overwritten if the local endpoint receives - * SETTINGS_MAX_CONCURRENT_STREAMS from the remote endpoint. + * specifying this option, the maximum number of outgoing concurrent + * streams is initially limited to 100 to avoid issues when the local + * endpoint submits lots of requests before receiving initial SETTINGS + * frame from the remote endpoint, since sending them at once to the + * remote endpoint could lead to rejection of some of the requests. + * This value will be overwritten when the local endpoint receives + * initial SETTINGS frame from the remote endpoint, either to the + * value advertised in SETTINGS_MAX_CONCURRENT_STREAMS or to the + * default value (unlimited) if none was advertised. */ NGHTTP2_EXTERN void nghttp2_option_set_peer_max_concurrent_streams(nghttp2_option *option, @@ -2568,6 +2660,28 @@ nghttp2_option_set_max_deflate_dynamic_table_size(nghttp2_option *option, NGHTTP2_EXTERN void nghttp2_option_set_no_closed_streams(nghttp2_option *option, int val); +/** + * @function + * + * This function sets the maximum number of outgoing SETTINGS ACK and + * PING ACK frames retained in :type:`nghttp2_session` object. If + * more than those frames are retained, the peer is considered to be + * misbehaving and session will be closed. The default value is 1000. + */ +NGHTTP2_EXTERN void nghttp2_option_set_max_outbound_ack(nghttp2_option *option, + size_t val); + +/** + * @function + * + * This function sets the maximum number of SETTINGS entries per + * SETTINGS frame that will be accepted. If more than those entries + * are received, the peer is considered to be misbehaving and session + * will be closed. The default value is 32. + */ +NGHTTP2_EXTERN void nghttp2_option_set_max_settings(nghttp2_option *option, + size_t val); + /** * @function * @@ -3017,6 +3131,16 @@ NGHTTP2_EXTERN int nghttp2_session_set_stream_user_data(nghttp2_session *session, int32_t stream_id, void *stream_user_data); +/** + * @function + * + * Sets |user_data| to |session|, overwriting the existing user data + * specified in `nghttp2_session_client_new()`, or + * `nghttp2_session_server_new()`. + */ +NGHTTP2_EXTERN void nghttp2_session_set_user_data(nghttp2_session *session, + void *user_data); + /** * @function * @@ -3723,10 +3847,13 @@ nghttp2_priority_spec_check_default(const nghttp2_priority_spec *pri_spec); * .. warning:: * * This function returns assigned stream ID if it succeeds. But - * that stream is not opened yet. The application must not submit + * that stream is not created yet. The application must not submit * frame to that stream ID before * :type:`nghttp2_before_frame_send_callback` is called for this - * frame. + * frame. This means `nghttp2_session_get_stream_user_data()` does + * not work before the callback. But + * `nghttp2_session_set_stream_user_data()` handles this situation + * specially, and it can set data to a stream during this period. * */ NGHTTP2_EXTERN int32_t nghttp2_submit_request( @@ -4442,8 +4569,7 @@ typedef struct { * Submits ALTSVC frame. * * ALTSVC frame is a non-critical extension to HTTP/2, and defined in - * is defined in `RFC 7383 - * `_. + * `RFC 7383 `_. * * The |flags| is currently ignored and should be * :enum:`NGHTTP2_FLAG_NONE`. @@ -4477,6 +4603,81 @@ NGHTTP2_EXTERN int nghttp2_submit_altsvc(nghttp2_session *session, const uint8_t *field_value, size_t field_value_len); +/** + * @struct + * + * The single entry of an origin. + */ +typedef struct { + /** + * The pointer to origin. No validation is made against this field + * by the library. This is not necessarily NULL-terminated. + */ + uint8_t *origin; + /** + * The length of the |origin|. + */ + size_t origin_len; +} nghttp2_origin_entry; + +/** + * @struct + * + * The payload of ORIGIN frame. ORIGIN frame is a non-critical + * extension to HTTP/2 and defined by `RFC 8336 + * `_. + * + * If this frame is received, and + * `nghttp2_option_set_user_recv_extension_type()` is not set, and + * `nghttp2_option_set_builtin_recv_extension_type()` is set for + * :enum:`NGHTTP2_ORIGIN`, ``nghttp2_extension.payload`` will point to + * this struct. + * + * It has the following members: + */ +typedef struct { + /** + * The number of origins contained in |ov|. + */ + size_t nov; + /** + * The pointer to the array of origins contained in ORIGIN frame. + */ + nghttp2_origin_entry *ov; +} nghttp2_ext_origin; + +/** + * @function + * + * Submits ORIGIN frame. + * + * ORIGIN frame is a non-critical extension to HTTP/2 and defined by + * `RFC 8336 `_. + * + * The |flags| is currently ignored and should be + * :enum:`NGHTTP2_FLAG_NONE`. + * + * The |ov| points to the array of origins. The |nov| specifies the + * number of origins included in |ov|. This function creates copies + * of all elements in |ov|. + * + * The ORIGIN frame is only usable by a server. If this function is + * invoked with client side session, this function returns + * :enum:`NGHTTP2_ERR_INVALID_STATE`. + * + * :enum:`NGHTTP2_ERR_NOMEM` + * Out of memory + * :enum:`NGHTTP2_ERR_INVALID_STATE` + * The function is called from client side session. + * :enum:`NGHTTP2_ERR_INVALID_ARGUMENT` + * There are too many origins, or an origin is too large to fit + * into a default frame payload. + */ +NGHTTP2_EXTERN int nghttp2_submit_origin(nghttp2_session *session, + uint8_t flags, + const nghttp2_origin_entry *ov, + size_t nov); + /** * @function * @@ -4591,6 +4792,19 @@ NGHTTP2_EXTERN int nghttp2_check_header_name(const uint8_t *name, size_t len); */ NGHTTP2_EXTERN int nghttp2_check_header_value(const uint8_t *value, size_t len); +/** + * @function + * + * Returns nonzero if the |value| which is supposed to the value of + * :authority or host header field is valid according to + * https://tools.ietf.org/html/rfc3986#section-3.2 + * + * |value| is valid if it merely consists of the allowed characters. + * In particular, it does not check whether |value| follows the syntax + * of authority. + */ +NGHTTP2_EXTERN int nghttp2_check_authority(const uint8_t *value, size_t len); + /* HPACK API */ struct nghttp2_hd_deflater; @@ -4693,8 +4907,8 @@ nghttp2_hd_deflate_change_table_size(nghttp2_hd_deflater *deflater, * * After this function returns, it is safe to delete the |nva|. * - * This function returns 0 if it succeeds, or one of the following - * negative error codes: + * This function returns the number of bytes written to |buf| if it + * succeeds, or one of the following negative error codes: * * :enum:`NGHTTP2_ERR_NOMEM` * Out of memory. @@ -4725,8 +4939,8 @@ NGHTTP2_EXTERN ssize_t nghttp2_hd_deflate_hd(nghttp2_hd_deflater *deflater, * * After this function returns, it is safe to delete the |nva|. * - * This function returns 0 if it succeeds, or one of the following - * negative error codes: + * This function returns the number of bytes written to |vec| if it + * succeeds, or one of the following negative error codes: * * :enum:`NGHTTP2_ERR_NOMEM` * Out of memory. diff --git a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_code.h b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_code.h index 80fdbb20..18e687e5 100644 --- a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_code.h +++ b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_code.h @@ -23,6 +23,10 @@ #include "tls1.h" #include "x509_vfy.h" +/* Used in SSL_set_mode() -- supported mode when using BIO */ +#define SSL_MODE_ENABLE_PARTIAL_WRITE 0x00000001L +#define SSL_MODE_ACCEPT_MOVING_WRITE_BUFFER 0x00000002L + /* Used in SSL_set_shutdown()/SSL_get_shutdown(); */ # define SSL_SENT_SHUTDOWN 1 # define SSL_RECEIVED_SHUTDOWN 2 diff --git a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_pkey.h b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_pkey.h index e790fcc9..0f361288 100644 --- a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_pkey.h +++ b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_pkey.h @@ -55,6 +55,52 @@ EVP_PKEY* d2i_PrivateKey(int type, const unsigned char **pp, long length); +/** + * @brief decodes and load a buffer BIO into a EVP key context. If '*a' is pointed to the + * private key, then load key into it. Or create a new private key object + * + * @param bp BIO object containing the key + * @param a Pointer to an existing EVP_KEY or NULL if a new key shall be created + * + * @return Created or updated EVP_PKEY + */ +EVP_PKEY *d2i_PrivateKey_bio(BIO *bp, EVP_PKEY **a); + +/** + * @brief Same as d2i_PrivateKey_bio + * + * @param bp BIO object containing the key + * @param a Pointer to an existing EVP_KEY or NULL if a new key shall be created + * + * @return Created or updated EVP_PKEY + */ +RSA *d2i_RSAPrivateKey_bio(BIO *bp,RSA **rsa); + +/** + * @brief loads a private key in PEM format from BIO object + * + * @param bp BIO object containing the key + * @param x Pointer to an existent PKEY or NULL if a new key shall be created + * @param cb Password callback (not used) + * @param u User context (not used) + * + * @return Created or updated EVP_PKEY + */ +EVP_PKEY *PEM_read_bio_PrivateKey(BIO *bp, EVP_PKEY **x, pem_password_cb *cb, void *u); + +/** + * @brief RSA key in PEM format from BIO object + * + * @param bp BIO object containing the key + * @param x Pointer to an existent PKEY or NULL if a new key shall be created + * @param cb Password callback (not used) + * @param u User context (not used) + * + * @return Created or updated EVP_PKEY + */ + +RSA *PEM_read_bio_RSAPrivateKey(BIO *bp, RSA **rsa, pem_password_cb *cb, void *u); + /** * @brief free a private key object * diff --git a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_stack.h b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_stack.h index 7a7051a0..f1efa579 100644 --- a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_stack.h +++ b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_stack.h @@ -17,6 +17,49 @@ } \ #define DEFINE_STACK_OF(t) SKM_DEFINE_STACK_OF(t, t, t) +typedef struct asn1_string_st ASN1_OCTET_STRING; + +struct stack_st_GENERAL_NAME; +typedef struct GENERAL_NAME_st { + int type; + union { + char *ptr; + struct asn1_string_st* dNSName; + ASN1_OCTET_STRING* iPAddress; + } d; +} GENERAL_NAME; + +typedef struct asn1_string_st ASN1_OCTET_STRING; +typedef struct X509_name_st X509_NAME; +typedef struct asn1_string_st ASN1_STRING; +typedef struct X509_name_entry_st X509_NAME_ENTRY; + +typedef struct asn1_string_st { + int type; + int length; + void *data; +} ASN1_IA5STRING; + +typedef STACK_OF(GENERAL_NAME) GENERAL_NAMES; + +/** + * @brief get nr of stack items + * + * @param sk Stack structure pointer + * + * @return number of items in the stack + */ +size_t sk_GENERAL_NAME_num(const struct stack_st_GENERAL_NAME *sk); + +/** + * @brief get GENERAL_NAME value from the stack + * + * @param sk Stack structure pointer + * @param i Index to stack item + * + * @return GENERAL_NAME object pointer + */ +GENERAL_NAME *sk_GENERAL_NAME_value(const struct stack_st_GENERAL_NAME *sk, size_t i); /** * @brief create a openssl stack object diff --git a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_types.h b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_types.h index 21ba69f4..2871d3a8 100644 --- a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_types.h +++ b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_types.h @@ -20,6 +20,8 @@ #endif #include "ssl_code.h" +#include +#include typedef void SSL_CIPHER; @@ -30,6 +32,8 @@ typedef void RSA; typedef void STACK; +typedef void DH; + #define ossl_inline inline #define SSL_METHOD_CALL(f, s, ...) s->method->func->ssl_##f(s, ##__VA_ARGS__) @@ -37,7 +41,7 @@ typedef void STACK; #define EVP_PKEY_METHOD_CALL(f, k, ...) k->method->pkey_##f(k, ##__VA_ARGS__) typedef int (*OPENSSL_sk_compfunc)(const void *, const void *); - +typedef int (*openssl_verify_callback)(int, X509_STORE_CTX *); struct stack_st; typedef struct stack_st OPENSSL_STACK; @@ -100,6 +104,8 @@ struct evp_pkey_st { void *pkey_pm; const PKEY_METHOD *method; + + int ref_counter; }; struct x509_st { @@ -152,8 +158,16 @@ struct X509_VERIFY_PARAM_st { }; struct bio_st { - const unsigned char * data; + + unsigned char * data; int dlen; + BIO* peer; + size_t offset; + size_t roffset; + size_t size; + size_t flags; + size_t type; + }; typedef enum { ALPN_INIT, ALPN_ENABLE, ALPN_DISABLE, ALPN_ERROR } ALPN_STATUS; @@ -166,6 +180,9 @@ struct ssl_alpn_st { const char *alpn_list[ALPN_LIST_MAX]; }; +typedef int pem_password_cb(char *buf, int size, int rwflag, void *userdata); + + struct ssl_ctx_st { int version; @@ -193,6 +210,16 @@ struct ssl_ctx_st int read_buffer_len; X509_VERIFY_PARAM param; + + void *default_passwd_callback_userdata; + + pem_password_cb *default_passwd_callback; + + struct stack_st_X509 *extra_certs; + + int max_version; + int min_version; + }; struct ssl_st @@ -230,12 +257,13 @@ struct ssl_st X509_VERIFY_PARAM param; - int err; + uint32_t mode; void (*info_callback) (const SSL *ssl, int type, int val); /* SSL low-level system arch point */ void *ssl_pm; + void *bio; }; struct ssl_method_st { @@ -299,6 +327,13 @@ struct pkey_method_st { int (*pkey_load)(EVP_PKEY *pkey, const unsigned char *buf, int len); }; +struct bio_method_st { + + unsigned type; + + unsigned size; +}; + typedef int (*next_proto_cb)(SSL *ssl, unsigned char **out, unsigned char *outlen, const unsigned char *in, diff --git a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_x509.h b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_x509.h index e5843972..88e46e2e 100644 --- a/tools/sdk/esp32s2/include/openssl/include/internal/ssl_x509.h +++ b/tools/sdk/esp32s2/include/openssl/include/internal/ssl_x509.h @@ -114,23 +114,6 @@ int SSL_use_certificate_ASN1(SSL *ssl, int len, const unsigned char *d); */ int X509_STORE_add_cert(X509_STORE *store, X509 *x); -/** - * @brief load data in BIO - * - * Normally BIO_write should append data but that doesn't happen here, and - * 'data' cannot be freed after the function is called, it should remain valid - * until BIO object is in use. - * - * @param b - pointer to BIO - * @param data - pointer to data - * @param dlen - data bytes - * - * @return result - * 0 : failed - * 1 : OK - */ -int BIO_write(BIO *b, const void *data, int dlen); - /** * @brief load a character certification context into system context. * @@ -145,28 +128,22 @@ int BIO_write(BIO *b, const void *data, int dlen); * * @return X509 certification object point */ -X509 * PEM_read_bio_X509(BIO *bp, X509 **x, void *cb, void *u); +X509 * PEM_read_bio_X509(BIO *bp, X509 **x, pem_password_cb cb, void *u); /** - * @brief create a BIO object - * - * @param method - pointer to BIO_METHOD + * @brief load a character certification context into system context. * - * @return pointer to BIO object - */ -BIO *BIO_new(void * method); - -/** - * @brief get the memory BIO method function - */ -void *BIO_s_mem(void); - -/** - * @brief free a BIO object + * Current implementation directly calls PEM_read_bio_X509 * - * @param x - pointer to BIO object + * @param bp - pointer to BIO + * @param buffer - pointer to the certification context memory + * @param cb - pointer to the callback (not implemented) + * @param u - pointer to arbitrary data (not implemented) + * + * @return X509 certification object point */ -void BIO_free(BIO *b); +X509 *PEM_read_bio_X509_AUX(BIO *bp, X509 **cert, pem_password_cb *cb, void *u); + #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/openssl/include/openssl/bio.h b/tools/sdk/esp32s2/include/openssl/include/openssl/bio.h new file mode 100644 index 00000000..1fc049b6 --- /dev/null +++ b/tools/sdk/esp32s2/include/openssl/include/openssl/bio.h @@ -0,0 +1,179 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _OPENSSL_BIO_H +#define _OPENSSL_BIO_H + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* These are the 'types' of BIOs */ +#define BIO_TYPE_NONE 0 +#define BIO_TYPE_MEM (1 | 0x0400) +#define BIO_TYPE_BIO (19 | 0x0400) /* (half a) BIO pair */ + +/* Bio object flags */ +#define BIO_FLAGS_READ 0x01 +#define BIO_FLAGS_WRITE 0x02 + +#define BIO_should_read(a) BIO_test_flags(a, BIO_FLAGS_READ) +#define BIO_should_write(a) BIO_test_flags(a, BIO_FLAGS_WRITE) + +typedef struct bio_st BIO; +typedef struct bio_method_st BIO_METHOD; + +/** + * @brief Create a BIO object as a file type + * Current implementation return NULL as file types are discouraged on ESP platform + * + * @param filename Filename + * @param mode Mode + * + * @return BIO object + */ +BIO *BIO_new_file(const char *filename, const char *mode); + +/** + * @brief Create a BIO object as a membuf type + * Current implementation takes a shallow copy of the buffer + * + * @param buf Pointer to the buffer + * @param len Length of the buffer + * + * @return BIO object + */ +BIO *BIO_new_mem_buf(void *buf, int len); + +/** + * @brief create a BIO object + * + * @param method - pointer to BIO_METHOD + * + * @return pointer to BIO object + */ +BIO *BIO_new(BIO_METHOD * method); + +/** + * @brief get the memory BIO method function + */ +void *BIO_s_mem(void); + +/** + * @brief free a BIO object + * + * @param x - pointer to BIO object + */ +void BIO_free(BIO *b); + +/** + * @brief Create a connected pair of BIOs bio1, bio2 with write buffer sizes writebuf1 and writebuf2 + * + * @param out1 pointer to BIO1 + * @param writebuf1 write size of BIO1 (0 means default size will be used) + * @param out2 pointer to BIO2 + * @param writebuf2 write size of BIO2 (0 means default size will be used) + * + * @return result + * 0 : failed + * 1 : OK + */ +int BIO_new_bio_pair(BIO **out1, size_t writebuf1, BIO **out2, size_t writebuf2); + +/** + * @brief Write data to BIO + * + * BIO_TYPE_BIO behaves the same way as OpenSSL bio object, other BIO types mock + * this functionality to avoid excessive allocation/copy, so the 'data' cannot + * be freed after the function is called, it should remain valid until BIO object is in use. + * + * @param b - pointer to BIO + * @param data - pointer to data + * @param dlen - data bytes + * + * @return result + * -1, 0 : failed + * 1 : OK + */ +int BIO_write(BIO *b, const void *data, int dlen); + +/** + * @brief Read data from BIO + * + * BIO_TYPE_BIO behaves the same way as OpenSSL bio object. + * Other types just hold pointer + * + * @param b - pointer to BIO + * @param data - pointer to data + * @param dlen - data bytes + * + * @return result + * -1, 0 : failed + * 1 : OK + */ +int BIO_read(BIO *bio, void *data, int len); + +/** + * @brief Get number of pending characters in the BIOs write buffers. + * + * @param b Pointer to BIO + * + * @return Amount of pending data + */ +size_t BIO_wpending(const BIO *bio); + +/** + * @brief Get number of pending characters in the BIOs read buffers. + * + * @param b Pointer to BIO + * + * @return Amount of pending data + */ +size_t BIO_ctrl_pending(const BIO *bio); + +/** + * @brief Get the maximum length of data that can be currently written to the BIO + * + * @param b Pointer to BIO + * + * @return Max length of writable data + */ +size_t BIO_ctrl_get_write_guarantee(BIO *bio); + +/** + * @brief Returns the type of a BIO. + * + * @param b Pointer to BIO + * + * @return Type of the BIO object + */ +int BIO_method_type(const BIO *b); + +/** + * @brief Test flags of a BIO. + * + * @param b Pointer to BIO + * @param flags Flags + * + * @return BIO object flags masked with the supplied flags + */ +int BIO_test_flags(const BIO *b, int flags); + +#ifdef __cplusplus +} +#endif + +#endif //_OPENSSL_BIO_H diff --git a/tools/sdk/esp32s2/include/openssl/include/openssl/err.h b/tools/sdk/esp32s2/include/openssl/include/openssl/err.h new file mode 100644 index 00000000..f4247a4a --- /dev/null +++ b/tools/sdk/esp32s2/include/openssl/include/openssl/err.h @@ -0,0 +1,228 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _OPENSSL_ERR_H +#define _OPENSSL_ERR_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @note This file contains a very simple implementation of error stack + * for ESP APIs stubs to OpenSSL + */ + +#define OPENSSL_PUT_SYSTEM_ERROR() \ + ERR_put_error(ERR_LIB_SYS, 0, 0, __FILE__, __LINE__); + +#define OPENSSL_PUT_LIB_ERROR(lib, code) \ + ERR_put_error(lib, 0, code, __FILE__, __LINE__); + +#define ERR_GET_LIB(packed_error) ((int)(((packed_error) >> 24) & 0xff)) +#define ERR_GET_REASON(packed_error) ((int)((packed_error) & 0xffff)) +#define ERR_R_PEM_LIB ERR_LIB_PEM +/* inherent openssl errors */ +# define ERR_R_FATAL 64 +# define ERR_R_MALLOC_FAILURE (1|ERR_R_FATAL) +# define ERR_R_SHOULD_NOT_HAVE_BEEN_CALLED (2|ERR_R_FATAL) +# define ERR_R_PASSED_NULL_PARAMETER (3|ERR_R_FATAL) +# define ERR_R_INTERNAL_ERROR (4|ERR_R_FATAL) +# define ERR_R_DISABLED (5|ERR_R_FATAL) +# define ERR_R_INIT_FAIL (6|ERR_R_FATAL) +# define ERR_R_PASSED_INVALID_ARGUMENT (7) +# define ERR_R_OPERATION_FAIL (8|ERR_R_FATAL) +# define ERR_R_INVALID_PROVIDER_FUNCTIONS (9|ERR_R_FATAL) +# define ERR_R_INTERRUPTED_OR_CANCELLED (10) + +enum { + ERR_LIB_NONE = 1, + ERR_LIB_SYS, + ERR_LIB_BN, + ERR_LIB_RSA, + ERR_LIB_DH, + ERR_LIB_EVP, + ERR_LIB_BUF, + ERR_LIB_OBJ, + ERR_LIB_PEM, + ERR_LIB_DSA, + ERR_LIB_X509, + ERR_LIB_ASN1, + ERR_LIB_CONF, + ERR_LIB_CRYPTO, + ERR_LIB_EC, + ERR_LIB_SSL, + ERR_LIB_BIO, + ERR_LIB_PKCS7, + ERR_LIB_PKCS8, + ERR_LIB_X509V3, + ERR_LIB_RAND, + ERR_LIB_ENGINE, + ERR_LIB_OCSP, + ERR_LIB_UI, + ERR_LIB_COMP, + ERR_LIB_ECDSA, + ERR_LIB_ECDH, + ERR_LIB_HMAC, + ERR_LIB_DIGEST, + ERR_LIB_CIPHER, + ERR_LIB_HKDF, + ERR_LIB_USER, + ERR_NUM_LIBS +}; + +/** + * @brief clear the SSL error code + * + * @param none + * + * @return none + */ +void ERR_clear_error(void); + +/** + * @brief get the current SSL error code + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_get_error(void); + +/** + * @brief peek the current SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_error(void); + +/** + * @brief peek the last SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_last_error(void); + +/** + * @brief register the SSL error strings + * + * @param none + * + * @return none + */ +void ERR_load_SSL_strings(void); + +/** + * @brief clear the SSL error code + * + * @param none + * + * @return none + */ +void ERR_clear_error(void); + +/** + * @brief peek the current SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_error(void); + +/** + * @brief peek the last SSL error code, not clearing it + * + * @param none + * + * @return current SSL error number + */ +uint32_t ERR_peek_last_error(void); + +/** + * @brief capture the current error to the error structure + * + * @param library Related library + * @param unused Not used (used for compliant function prototype) + * @param reason The actual error code + * @param file File name of the error report + * @param line Line number of the error report + * + */ +void ERR_put_error(int library, int unused, int reason, const char *file, unsigned line); + +/** + * @brief Peek the current SSL error, not clearing it + * + * @param file file name of the reported error + * @param line line number of the reported error + * @param data Associated data to the reported error + * @param flags Flags associated to the error + * + * @return current SSL error number + */ +uint32_t ERR_peek_error_line_data(const char **file, int *line, + const char **data, int *flags); + +/** + * @brief Get the current SSL error + * + * @param file file name of the reported error + * @param line line number of the reported error + * @param data Associated data to the reported error + * @param flags Flags associated to the error + * + * @return current SSL error number + */ +uint32_t ERR_get_error_line_data(const char **file, int *line, + const char **data, int *flags); + +/** + * @brief API provided as a declaration only + * + */ +void SSL_load_error_strings(void); + +/** + * @brief API provided as a declaration only + * + */ +void ERR_free_strings(void); + +/** + * @brief API provided as a declaration only + * + */ +void ERR_remove_state(unsigned long pid); + +/** + * @brief Returns error string -- Not implemented + * + * @param packed_error Packed error code + * + * @return NULL + */ +const char *ERR_reason_error_string(uint32_t packed_error); + +#ifdef __cplusplus +} +#endif + +#endif // _OPENSSL_ERR_H diff --git a/tools/sdk/esp32s2/include/openssl/include/openssl/ssl.h b/tools/sdk/esp32s2/include/openssl/include/openssl/ssl.h index 88d7bca6..4a3376c0 100644 --- a/tools/sdk/esp32s2/include/openssl/include/openssl/ssl.h +++ b/tools/sdk/esp32s2/include/openssl/include/openssl/ssl.h @@ -21,6 +21,8 @@ #include "internal/ssl_x509.h" #include "internal/ssl_pkey.h" +#include "openssl/bio.h" +#include "openssl/err.h" /* { @@ -297,6 +299,67 @@ const SSL_METHOD* SSLv3_server_method(void); */ const SSL_METHOD* TLS_server_method(void); +/** + * @brief create the target SSL context method + * + * @return the TLS any version SSL context method + */ +const SSL_METHOD* TLS_method(void); + +/** + * @brief create the target SSL context method + * + * @return the TLS1.2 version SSL context method + */ +const SSL_METHOD* TLSv1_2_method(void); + +/** + * @brief create the target SSL context method + * + * @return the TLS1.1 version SSL context method + */ +const SSL_METHOD* TLSv1_1_method(void); + +/** + * @brief create the target SSL context method + * + * @return the TLS1.0 version SSL context method + */ +const SSL_METHOD* TLSv1_method(void); + +/** + * @brief create the target SSL context method + * + * @return the SSLV3.0 version SSL context method + */ +const SSL_METHOD* SSLv3_method(void); + +/** + * @brief create the target SSL context method + * + * @param none + * + * @return the SSLV2.3 version SSL context method + */ +const SSL_METHOD* SSLv23_method(void); + +/** + * @brief Set minimum protocol version for defined context + * + * @param ctx SSL context + * + * @return 1 on success + */ +int SSL_CTX_set_min_proto_version(SSL_CTX *ctx, int version); + +/** + * @brief Set maximum protocol version for defined context + * + * @param ctx SSL context + * + * @return 1 on success + */ +int SSL_CTX_set_max_proto_version(SSL_CTX *ctx, int version); /** * @brief set the SSL context ALPN select callback function @@ -348,43 +411,6 @@ void SSL_CTX_set_next_proto_select_cb(SSL_CTX *ctx, void *arg), void *arg); -/** - * @brief get SSL error code - * - * @param ssl - SSL point - * @param ret_code - SSL return code - * - * @return SSL error number - */ -int SSL_get_error(const SSL *ssl, int ret_code); - -/** - * @brief clear the SSL error code - * - * @param none - * - * @return none - */ -void ERR_clear_error(void); - -/** - * @brief get the current SSL error code - * - * @param none - * - * @return current SSL error number - */ -int ERR_get_error(void); - -/** - * @brief register the SSL error strings - * - * @param none - * - * @return none - */ -void ERR_load_SSL_strings(void); - /** * @brief initialize the SSL library * @@ -1399,7 +1425,17 @@ SSL_CTX *SSL_get_SSL_CTX(const SSL *ssl); * * @return application data */ -char *SSL_get_app_data(SSL *ssl); +void *SSL_get_app_data(SSL *ssl); + +/** + * @brief get SSL error code + * + * @param ssl - SSL point + * @param ret_code - SSL return code + * + * @return SSL error number + */ +int SSL_get_error(const SSL *ssl, int ret_code); /** * @brief get SSL cipher bits @@ -1667,7 +1703,7 @@ void SSL_set_accept_state(SSL *ssl); * * @return none */ -void SSL_set_app_data(SSL *ssl, char *arg); +void SSL_set_app_data(SSL *ssl, void *arg); /** * @brief set SSL BIO @@ -1756,7 +1792,7 @@ void SSL_set_timeout(SSL *ssl, long t); * * @return SSL statement string */ -char *SSL_state_string(const SSL *ssl); +const char *SSL_state_string(const SSL *ssl); /** * @brief get SSL statement long string @@ -1815,6 +1851,52 @@ const char *SSL_get_psk_identity_hint(SSL *ssl); */ const char *SSL_get_psk_identity(SSL *ssl); +/** + * @brief set the SSL verify depth of the SSL + * + * @param ssl - SSL context + * @param depth - Depth level to verify + * + */ +void SSL_set_verify_depth(SSL *ssl, int depth); + +/** + * @brief Get default verify callback + * + * @param ctx - SSL context + * @return verify_callback - verifying callback function + * + */ +openssl_verify_callback SSL_CTX_get_verify_callback(const SSL_CTX *ctx); + +/** + * @brief Get default verify callback + * + * @param ctx - SSL context + * @return verify_callback - verifying callback function + * + */ +openssl_verify_callback SSL_get_verify_callback(const SSL *s); + +/** + * @brief Frees RSA object + * + * Current implementation calls directly EVP_PKEY free + * + * @param r RSA object + * + */ +void RSA_free(RSA *r); + +/** + * @brief Sets SSL mode, partially implemented + * + * @param ssl SSL context + * + * @return the new mode bitmask after adding mode + */ +uint32_t SSL_set_mode(SSL *ssl, uint32_t mode); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/pthread/include/esp_pthread.h b/tools/sdk/esp32s2/include/pthread/include/esp_pthread.h index cdff0519..95e182c1 100644 --- a/tools/sdk/esp32s2/include/pthread/include/esp_pthread.h +++ b/tools/sdk/esp32s2/include/pthread/include/esp_pthread.h @@ -82,6 +82,11 @@ esp_err_t esp_pthread_set_cfg(const esp_pthread_cfg_t *cfg); */ esp_err_t esp_pthread_get_cfg(esp_pthread_cfg_t *p); +/** + * @brief Initialize pthread library + */ +esp_err_t esp_pthread_init(void); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h b/tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h index 621b23d1..e497149e 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h @@ -168,6 +168,20 @@ int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value); */ #define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en) +/** + * Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @note ESP32 only supports output of ADC2's internal reference voltage. + * @param[in] adc ADC unit select + * @param[in] channel ADC2 channel number + * @param[in] en Enable/disable the reference voltage output + */ +#define adc_hal_vref_output(adc, channel, en) adc_ll_vref_output(adc, channel, en) + /*--------------------------------------------------------------- Digital controller setting ---------------------------------------------------------------*/ diff --git a/tools/sdk/esp32s2/include/soc/include/hal/adc_types.h b/tools/sdk/esp32s2/include/soc/include/hal/adc_types.h index 1305d276..5f3d5a13 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/adc_types.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/adc_types.h @@ -1,8 +1,22 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. #pragma once -#include "soc/adc_caps.h" -#include "sdkconfig.h" #include +#include +#include "sdkconfig.h" +#include "soc/adc_caps.h" /** * @brief ADC units selected handle. @@ -69,7 +83,7 @@ typedef enum { ADC_WIDTH_BIT_10 = 1, /*!< ADC capture width is 10Bit. Only ESP32 is supported. */ ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */ ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */ -#ifdef CONFIG_IDF_TARGET_ESP32S2 +#if !CONFIG_IDF_TARGET_ESP32 ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32S2 is supported. */ #endif ADC_WIDTH_MAX, @@ -108,11 +122,11 @@ typedef struct { If (channel > ADC_CHANNEL_MAX), The data is invalid. */ uint16_t unit: 1; /*! #include +#include "esp_err.h" + #include "soc/soc_caps.h" #include "hal/cpu_hal.h" #include "hal/soc_ll.h" -#include "esp_err.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_hal.h b/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_hal.h index 6992daf6..ffc1a22f 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_hal.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_hal.h @@ -37,20 +37,22 @@ * implementations that also use the SPI peripheral. */ typedef struct { + spi_flash_host_inst_t inst; ///< Host instance, containing host data and function pointer table. May update with the host (hardware version). spi_dev_t *spi; ///< Pointer to SPI peripheral registers (SP1, SPI2 or SPI3). Set before initialisation. int cs_num; ///< Which cs pin is used, 0-2. - int extra_dummy; - spi_flash_ll_clock_reg_t clock_conf; -} spi_flash_memspi_data_t; + int extra_dummy; ///< Pre-calculated extra dummy used for compensation + spi_flash_ll_clock_reg_t clock_conf; ///< Pre-calculated clock configuration value + uint32_t reserved_config[2]; ///< The ROM has reserved some memory for configurations with one set of driver code. (e.g. QPI mode, 64-bit address mode, etc.) +} spi_flash_hal_context_t; /// Configuration structure for the SPI driver. typedef struct { spi_host_device_t host_id; ///< SPI peripheral ID. - int cs_num; ///< Which cs pin is used, 0-2. + int cs_num; ///< Which cs pin is used, 0-(SOC_SPI_PERIPH_CS_NUM-1). bool iomux; ///< Whether the IOMUX is used, used for timing compensation. int input_delay_ns; ///< Input delay on the MISO pin after the launch clock， used for timing compensation. esp_flash_speed_t speed;///< SPI flash clock speed to work at. -} spi_flash_memspi_config_t; +} spi_flash_hal_config_t; /** * Configure SPI flash hal settings. @@ -62,16 +64,16 @@ typedef struct { * - ESP_OK: success * - ESP_ERR_INVALID_ARG: the data buffer is not in the DRAM. */ -esp_err_t spi_flash_hal_init(spi_flash_memspi_data_t *data_out, const spi_flash_memspi_config_t *cfg); +esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg); /** * Configure the device-related register before transactions. * - * @param driver The driver context. + * @param host The driver context. * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver); +esp_err_t spi_flash_hal_device_config(spi_flash_host_inst_t *host); /** * Send an user-defined spi transaction to the device. @@ -80,60 +82,60 @@ esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *driver); * particular commands. Since this function supports timing compensation, it is * also used to receive some data when the frequency is high. * - * @param driver The driver context. + * @param host The driver context. * @param trans The transaction to send, also holds the received data. * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *driver, spi_flash_trans_t *trans); +esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans); /** * Erase whole flash chip by using the erase chip (C7h) command. * - * @param driver The driver context. + * @param host The driver context. */ -void spi_flash_hal_erase_chip(spi_flash_host_driver_t *driver); +void spi_flash_hal_erase_chip(spi_flash_host_inst_t *host); /** * Erase a specific sector by its start address through the sector erase (20h) * command. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Start address of the sector to erase. */ -void spi_flash_hal_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address); +void spi_flash_hal_erase_sector(spi_flash_host_inst_t *host, uint32_t start_address); /** * Erase a specific 64KB block by its start address through the 64KB block * erase (D8h) command. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Start address of the block to erase. */ -void spi_flash_hal_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address); +void spi_flash_hal_erase_block(spi_flash_host_inst_t *host, uint32_t start_address); /** * Program a page of the flash using the page program (02h) command. * - * @param driver The driver context. + * @param host The driver context. * @param address Address of the page to program * @param buffer Data to program * @param length Size of the buffer in bytes, no larger than ``SPI_FLASH_HAL_MAX_WRITE_BYTES`` (64) bytes. */ -void spi_flash_hal_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length); +void spi_flash_hal_program_page(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length); /** * Read from the flash. Call ``spi_flash_hal_configure_host_read_mode`` to * configure the read command before calling this function. * - * @param driver The driver context. + * @param host The driver context. * @param buffer Buffer to store the read data * @param address Address to read * @param length Length to read, no larger than ``SPI_FLASH_HAL_MAX_READ_BYTES`` (64) bytes. * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len); +esp_err_t spi_flash_hal_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len); /** * @brief Send the write enable (06h) or write disable (04h) command to the flash chip. @@ -143,16 +145,16 @@ esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *driver, void *buffer, uint * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *chip_drv, bool wp); +esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_inst_t *host, bool wp); /** * Check whether the SPI host is idle and can perform other operations. * - * @param driver The driver context. + * @param host The driver context. * * @return ture if idle, otherwise false. */ -bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver); +bool spi_flash_hal_host_idle(spi_flash_host_inst_t *host); /** * @brief Configure the SPI host hardware registers for the specified io mode. @@ -177,7 +179,7 @@ bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver); * - Common write: set command value, address value (or length to 0 if not * used), disable dummy phase, and set output data. * - * @param driver The driver context + * @param host The driver context * @param io_mode The HW read mode to use * @param addr_bitlen Length of the address phase, in bits * @param dummy_cyclelen_base Base cycles of the dummy phase, some extra dummy cycles may be appended to compensate the timing. @@ -185,34 +187,34 @@ bool spi_flash_hal_host_idle(spi_flash_host_driver_t *driver); * * @return always return ESP_OK. */ -esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_driver_t *driver, uint32_t command, uint32_t addr_bitlen, +esp_err_t spi_flash_hal_configure_host_io_mode(spi_flash_host_inst_t *host, uint32_t command, uint32_t addr_bitlen, int dummy_cyclelen_base, esp_flash_io_mode_t io_mode); /** * Poll until the last operation is done. * - * @param driver The driver context. + * @param host The driver context. */ -void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *driver); +void spi_flash_hal_poll_cmd_done(spi_flash_host_inst_t *host); /** * Check whether the given buffer can be used as the write buffer directly. If 'chip' is connected to the main SPI bus, we can only write directly from * regions that are accessible ith cache disabled. * * - * @param driver The driver context + * @param host The driver context * @param p The buffer holding data to send. * * @return True if the buffer can be used to send data, otherwise false. */ -bool spi_flash_hal_supports_direct_write(spi_flash_host_driver_t *driver, const void *p); +bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p); /** * Check whether the given buffer can be used as the read buffer directly. If 'chip' is connected to the main SPI bus, we can only read directly from * regions that are accessible ith cache disabled. * * - * @param driver The driver context + * @param host The driver context * @param p The buffer to hold the received data. * * @return True if the buffer can be used to receive data, otherwise false. */ -bool spi_flash_hal_supports_direct_read(spi_flash_host_driver_t *driver, const void *p); +bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p); diff --git a/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_types.h b/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_types.h index 0a468c60..d2efe3e8 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_types.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/spi_flash_types.h @@ -68,84 +68,105 @@ typedef enum { ///Slowest io mode supported by ESP32, currently SlowRd #define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD -struct spi_flash_host_driver_t; -typedef struct spi_flash_host_driver_t spi_flash_host_driver_t; +struct spi_flash_host_driver_s; +typedef struct spi_flash_host_driver_s spi_flash_host_driver_t; + +/** SPI Flash Host driver instance */ +typedef struct { + const struct spi_flash_host_driver_s* driver; ///< Pointer to the implementation function table + // Implementations can wrap this structure into their own ones, and append other data here +} spi_flash_host_inst_t ; + /** Host driver configuration and context structure. */ -struct spi_flash_host_driver_t { - /** - * Configuration and static data used by the specific host driver. The type - * is determined by the host driver. - */ - void *driver_data; +struct spi_flash_host_driver_s { /** * Configure the device-related register before transactions. This saves * some time to re-configure those registers when we send continuously */ - esp_err_t (*dev_config)(spi_flash_host_driver_t *driver); + esp_err_t (*dev_config)(spi_flash_host_inst_t *host); /** * Send an user-defined spi transaction to the device. */ - esp_err_t (*common_command)(spi_flash_host_driver_t *driver, spi_flash_trans_t *t); + esp_err_t (*common_command)(spi_flash_host_inst_t *host, spi_flash_trans_t *t); /** * Read flash ID. */ - esp_err_t (*read_id)(spi_flash_host_driver_t *driver, uint32_t *id); + esp_err_t (*read_id)(spi_flash_host_inst_t *host, uint32_t *id); /** * Erase whole flash chip. */ - void (*erase_chip)(spi_flash_host_driver_t *driver); + void (*erase_chip)(spi_flash_host_inst_t *host); /** * Erase a specific sector by its start address. */ - void (*erase_sector)(spi_flash_host_driver_t *driver, uint32_t start_address); + void (*erase_sector)(spi_flash_host_inst_t *host, uint32_t start_address); /** * Erase a specific block by its start address. */ - void (*erase_block)(spi_flash_host_driver_t *driver, uint32_t start_address); + void (*erase_block)(spi_flash_host_inst_t *host, uint32_t start_address); /** * Read the status of the flash chip. */ - esp_err_t (*read_status)(spi_flash_host_driver_t *driver, uint8_t *out_sr); + esp_err_t (*read_status)(spi_flash_host_inst_t *host, uint8_t *out_sr); /** * Disable write protection. */ - esp_err_t (*set_write_protect)(spi_flash_host_driver_t *driver, bool wp); + esp_err_t (*set_write_protect)(spi_flash_host_inst_t *host, bool wp); /** * Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length. */ - void (*program_page)(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length); - /** Check whether need to allocate new buffer to write */ - bool (*supports_direct_write)(spi_flash_host_driver_t *driver, const void *p); - /** Check whether need to allocate new buffer to read */ - bool (*supports_direct_read)(spi_flash_host_driver_t *driver, const void *p); - /** maximum length of program_page */ - int max_write_bytes; + void (*program_page)(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length); + /** Check whether given buffer can be directly used to write */ + bool (*supports_direct_write)(spi_flash_host_inst_t *host, const void *p); + /** + * Slicer for write data. The `program_page` should be called iteratively with the return value + * of this function. + * + * @param address Beginning flash address to write + * @param len Length request to write + * @param align_addr Output of the aligned address to write to + * @param page_size Physical page size of the flash chip + * @return Length that can be actually written in one `program_page` call + */ + int (*write_data_slicer)(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_addr, + uint32_t page_size); /** * Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length. */ - esp_err_t (*read)(spi_flash_host_driver_t *driver, void *buffer, uint32_t address, uint32_t read_len); - /** maximum length of read */ - int max_read_bytes; + esp_err_t (*read)(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len); + /** Check whether given buffer can be directly used to read */ + bool (*supports_direct_read)(spi_flash_host_inst_t *host, const void *p); + /** + * Slicer for read data. The `read` should be called iteratively with the return value + * of this function. + * + * @param address Beginning flash address to read + * @param len Length request to read + * @param align_addr Output of the aligned address to read + * @param page_size Physical page size of the flash chip + * @return Length that can be actually read in one `read` call + */ + int (*read_data_slicer)(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_addr, uint32_t page_size); /** * Check whether the host is idle to perform new operations. */ - bool (*host_idle)(spi_flash_host_driver_t *driver); + bool (*host_idle)(spi_flash_host_inst_t *host); /** * Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode. */ - esp_err_t (*configure_host_io_mode)(spi_flash_host_driver_t *driver, uint32_t command, + esp_err_t (*configure_host_io_mode)(spi_flash_host_inst_t *host, uint32_t command, uint32_t addr_bitlen, int dummy_bitlen_base, esp_flash_io_mode_t io_mode); /** * Internal use, poll the HW until the last operation is done. */ - void (*poll_cmd_done)(spi_flash_host_driver_t *driver); + void (*poll_cmd_done)(spi_flash_host_inst_t *host); /** * For some host (SPI1), they are shared with a cache. When the data is * modified, the cache needs to be flushed. Left NULL if not supported. */ - esp_err_t (*flush_cache)(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size); + esp_err_t (*flush_cache)(spi_flash_host_inst_t* host, uint32_t addr, uint32_t size); }; #ifdef __cplusplus diff --git a/tools/sdk/esp32s2/include/soc/include/hal/spi_slave_hd_hal.h b/tools/sdk/esp32s2/include/soc/include/hal/spi_slave_hd_hal.h new file mode 100644 index 00000000..c9e3684d --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/include/hal/spi_slave_hd_hal.h @@ -0,0 +1,212 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +/* + * The HAL layer for SPI Slave HD mode, currently only segment mode is supported + * + * Usage: + * - Firstly, initialize the slave with `slave_hd_hal_init` + * + * - Event handling: + * - (Optional) Call ``spi_slave_hd_hal_enable_event_intr`` to enable the used interrupts + * - (Basic) Call ``spi_slave_hd_hal_check_clear_event`` to check whether an event happen, and also + * clear its interrupt. For events: SPI_EV_BUF_TX, SPI_EV_BUF_RX, SPI_EV_BUF_RX, SPI_EV_CMD9, + * SPI_EV_CMDA. + * - (Advanced) Call ``spi_slave_hd_hal_check_disable_event`` to disable the interrupt of an event, + * so that the task can call ``spi_slave_hd_hal_invoke_event_intr`` later to manually invoke the + * ISR. For SPI_EV_SEND, SPI_EV_RECV. + * + * - TXDMA: + * - To send data through DMA, call `spi_slave_hd_hal_txdma` + * - When the operation is done, SPI_EV_SEND will be triggered. + * + * - RXDMA: + * - To receive data through DMA, call `spi_slave_hd_hal_rxdma` + * - When the operation is done, SPI_EV_RECV will be triggered. + * - Call ``spi_slave_hd_hal_rxdma_get_len`` to get the received length + * + * - Shared buffer: + * - Call ``spi_slave_hd_hal_write_buffer`` to write the shared register buffer. When the buffer is + * read by the master (regardless of the read address), SPI_EV_BUF_TX will be triggered + * - Call ``spi_slave_hd_hal_read_buffer`` to read the shared register buffer. When the buffer is + * written by the master (regardless of the written address), SPI_EV_BUF_RX will be triggered. + */ + +#pragma once + +#include +#include "esp_err.h" +#include "hal/spi_ll.h" +#include "hal/spi_types.h" + + +/// Configuration of the HAL +typedef struct { + int host_id; ///< Host ID of the spi peripheral + int spics_io_num; ///< CS GPIO pin for this device + uint8_t mode; ///< SPI mode (0-3) + int command_bits; ///< command field bits, multiples of 8 and at least 8. + int address_bits; ///< address field bits, multiples of 8 and at least 8. + int dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. + + struct { + uint32_t tx_lsbfirst : 1;///< Whether TX data should be sent with LSB first. + uint32_t rx_lsbfirst : 1;///< Whether RX data should be read with LSB first. + }; + int dma_chan; ///< The dma channel used. +} spi_slave_hd_hal_config_t; + +/// Context of the HAL, initialized by :cpp:func:`slave_hd_hal_init`. +typedef struct { + spi_dev_t* dev; ///< Beginning address of the peripheral registers. + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + + /* Internal status used by the HAL implementation, initialized as 0. */ + uint32_t intr_not_triggered; +} spi_slave_hd_hal_context_t; + + +/** + * @brief Initialize the hardware and part of the context + * + * @param hal Context of the HAL layer + * @param config Configuration of the HAL + */ +void slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *config); + +/** + * @brief Check and clear signal of one event + * + * @param hal Context of the HAL layer + * @param ev Event to check + * @return true if event triggered, otherwise false + */ +bool spi_slave_hd_hal_check_clear_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +/** + * @brief Check and clear the interrupt of one event. + * + * @note The event source will be kept, so that the interrupt can be invoked by + * :cpp:func:`spi_slave_hd_hal_invoke_event_intr`. If event not triggered, its interrupt source + * will not be disabled either. + * + * @param hal Context of the HAL layer + * @param ev Event to check and disable + * @return true if event triggered, otherwise false + */ +bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +/** + * @brief Enable to invole the ISR of corresponding event. + * + * @note The function, compared with :cpp:func:`spi_slave_hd_hal_enable_event_intr`, contains a + * workaround to force trigger the interrupt, even if the interrupt source cannot be initialized + * correctly. + * + * @param hal Context of the HAL layer + * @param ev Event (reason) to invoke the ISR + */ +void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +/** + * @brief Enable the interrupt source of corresponding event. + * + * @param hal Context of the HAL layer + * @param ev Event whose corresponding interrupt source should be enabled. + */ +void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev); + +//////////////////////////////////////////////////////////////////////////////// +// RX DMA +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Start the RX DMA operation to the specified buffer. + * + * @param hal Context of the HAL layer + * @param[out] out_buf Buffer to receive the data + * @param len Maximul length to receive + */ +void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len); + +/** + * @brief Get the length of total received data + * + * @param hal Context of the HAL layer + * @return The received length + */ +int spi_slave_hd_hal_rxdma_get_len(spi_slave_hd_hal_context_t *hal); + +//////////////////////////////////////////////////////////////////////////////// +// TX DMA +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Start the TX DMA operation with the specified buffer + * + * @param hal Context of the HAL layer + * @param data Buffer of data to send + * @param len Size of the buffer, also the maximum length to send + */ +void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len); + +//////////////////////////////////////////////////////////////////////////////// +// Shared buffer +//////////////////////////////////////////////////////////////////////////////// +/** + * @brief Read from the shared register buffer + * + * @param hal Context of the HAL layer + * @param addr Address of the shared regsiter to read + * @param out_data Buffer to store the read data + * @param len Length to read from the shared buffer + */ +void spi_slave_hd_hal_read_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *out_data, size_t len); + +/** + * @brief Write the shared register buffer + * + * @param hal Context of the HAL layer + * @param addr Address of the shared register to write + * @param data Buffer of the data to write + * @param len Length to write into the shared buffer + */ +void spi_slave_hd_hal_write_buffer(spi_slave_hd_hal_context_t *hal, int addr, uint8_t *data, size_t len); + +/** + * @brief Get the length of previous transaction. + * + * @param hal Context of the HAL layer + * @return The length of previous transaction + */ +int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal); + +/** + * @brief Get the address of last transaction + * + * @param hal Context of the HAL layer + * @return The address of last transaction + */ +int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal); diff --git a/tools/sdk/esp32s2/include/soc/include/hal/spi_types.h b/tools/sdk/esp32s2/include/soc/include/hal/spi_types.h index 379f1398..b2fef1c3 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/spi_types.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/spi_types.h @@ -15,7 +15,9 @@ #pragma once #include "soc/spi_caps.h" +#include "esp_attr.h" #include "sdkconfig.h" +#include /** * @brief Enum with the three SPI peripherals that are software-accessible in it @@ -27,6 +29,19 @@ typedef enum { SPI3_HOST=2, ///< SPI3 } spi_host_device_t; +/// SPI Events +typedef enum { + SPI_EV_BUF_TX = BIT(0), ///< The buffer has sent data to master, Slave HD only + SPI_EV_BUF_RX = BIT(1), ///< The buffer has received data from master, Slave HD only + SPI_EV_SEND = BIT(2), ///< Has sent data to master through RDDMA, Slave HD only + SPI_EV_RECV = BIT(3), ///< Has received data from master through WRDMA, Slave HD only + SPI_EV_CMD9 = BIT(4), ///< Received CMD9 from master, Slave HD only + SPI_EV_CMDA = BIT(5), ///< Received CMDA from master, Slave HD only + SPI_EV_TRANS = BIT(6), ///< A transaction has done +} spi_event_t; +FLAG_ATTR(spi_event_t) + + /** @cond */ //Doxy command to hide preprocessor definitions from docs */ //alias for different chips @@ -34,7 +49,7 @@ typedef enum { #define SPI_HOST SPI1_HOST #define HSPI_HOST SPI2_HOST #define VSPI_HOST SPI3_HOST -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 #define SPI_HOST SPI1_HOST #define FSPI_HOST SPI2_HOST diff --git a/tools/sdk/esp32s2/include/soc/include/hal/systimer_hal.h b/tools/sdk/esp32s2/include/soc/include/hal/systimer_hal.h index a26ffdde..e070f686 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/systimer_hal.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/systimer_hal.h @@ -71,6 +71,11 @@ void systimer_hal_counter_value_advance(systimer_counter_id_t counter_id, int64_ */ void systimer_hal_init(void); +/** + * @brief connect alarm unit to selected counter + */ +void systimer_hal_connect_alarm_counter(systimer_alarm_id_t alarm_id, systimer_counter_id_t counter_id); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/soc/include/hal/systimer_types.h b/tools/sdk/esp32s2/include/soc/include/hal/systimer_types.h index ebe5fb4e..2ae7c4a2 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/systimer_types.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/systimer_types.h @@ -46,7 +46,7 @@ _Static_assert(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t typedef enum { SYSTIMER_COUNTER_0, /*!< systimer counter 0 */ #if SOC_SYSTIMER_COUNTER_NUM > 1 - SYSTIEMR_COUNTER_1, /*!< systimer counter 1 */ + SYSTIMER_COUNTER_1, /*!< systimer counter 1 */ #endif } systimer_counter_id_t; diff --git a/tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_types.h b/tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_types.h index 3de534a3..d2ddf33e 100644 --- a/tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_types.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_types.h @@ -14,6 +14,9 @@ #pragma once +#include + +#include "soc/soc.h" #include "soc/touch_sensor_caps.h" #include "sdkconfig.h" #include "esp_attr.h" @@ -129,7 +132,7 @@ typedef enum { #define TOUCH_TRIGGER_MODE_DEFAULT (TOUCH_TRIGGER_BELOW) /*! (touch threshold + hysteresis), the touch channel be touched. - If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released. - Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 1/32; 3: OFF */ - uint32_t noise_thr; /*! (noise), the baseline stop updating. - If (raw data - baseline) < (noise), the baseline start updating. + uint32_t noise_thr; /*! (negative noise), the baseline restart reset process(refer to `baseline_reset`). - If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`). - Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1/8; */ - uint32_t neg_noise_limit; /*! #include -#include "hal/can_types.h" -#include "hal/can_ll.h" +#include "hal/twai_types.h" +#include "hal/twai_ll.h" /* ------------------------- Defines and Typedefs --------------------------- */ //Error active interrupt related -#define CAN_HAL_EVENT_BUS_OFF (1 << 0) -#define CAN_HAL_EVENT_BUS_RECOV_CPLT (1 << 1) -#define CAN_HAL_EVENT_BUS_RECOV_PROGRESS (1 << 2) -#define CAN_HAL_EVENT_ABOVE_EWL (1 << 3) -#define CAN_HAL_EVENT_BELOW_EWL (1 << 4) -#define CAN_HAL_EVENT_ERROR_PASSIVE (1 << 5) -#define CAN_HAL_EVENT_ERROR_ACTIVE (1 << 6) -#define CAN_HAL_EVENT_BUS_ERR (1 << 7) -#define CAN_HAL_EVENT_ARB_LOST (1 << 8) -#define CAN_HAL_EVENT_RX_BUFF_FRAME (1 << 9) -#define CAN_HAL_EVENT_TX_BUFF_FREE (1 << 10) +#define TWAI_HAL_EVENT_BUS_OFF (1 << 0) +#define TWAI_HAL_EVENT_BUS_RECOV_CPLT (1 << 1) +#define TWAI_HAL_EVENT_BUS_RECOV_PROGRESS (1 << 2) +#define TWAI_HAL_EVENT_ABOVE_EWL (1 << 3) +#define TWAI_HAL_EVENT_BELOW_EWL (1 << 4) +#define TWAI_HAL_EVENT_ERROR_PASSIVE (1 << 5) +#define TWAI_HAL_EVENT_ERROR_ACTIVE (1 << 6) +#define TWAI_HAL_EVENT_BUS_ERR (1 << 7) +#define TWAI_HAL_EVENT_ARB_LOST (1 << 8) +#define TWAI_HAL_EVENT_RX_BUFF_FRAME (1 << 9) +#define TWAI_HAL_EVENT_TX_BUFF_FREE (1 << 10) typedef struct { - can_dev_t *dev; -} can_hal_context_t; + twai_dev_t *dev; +} twai_hal_context_t; -typedef can_ll_frame_buffer_t can_hal_frame_t; +typedef twai_ll_frame_buffer_t twai_hal_frame_t; /* ---------------------------- Init and Config ----------------------------- */ /** - * @brief Initialize CAN peripheral and HAL context + * @brief Initialize TWAI peripheral and HAL context * - * Sets HAL context, puts CAN peripheral into reset mode, then sets some + * Sets HAL context, puts TWAI peripheral into reset mode, then sets some * registers with default values. * * @param hal_ctx Context of the HAL layer * @return True if successfully initialized, false otherwise. */ -bool can_hal_init(can_hal_context_t *hal_ctx); +bool twai_hal_init(twai_hal_context_t *hal_ctx); /** - * @brief Deinitialize the CAN peripheral and HAL context + * @brief Deinitialize the TWAI peripheral and HAL context * * Clears any unhandled interrupts and unsets HAL context * * @param hal_ctx Context of the HAL layer */ -void can_hal_deinit(can_hal_context_t *hal_ctx); +void twai_hal_deinit(twai_hal_context_t *hal_ctx); /** - * @brief Configure the CAN peripheral + * @brief Configure the TWAI peripheral * * @param hal_ctx Context of the HAL layer * @param t_config Pointer to timing configuration structure @@ -81,32 +81,32 @@ void can_hal_deinit(can_hal_context_t *hal_ctx); * @param intr_mask Mask of interrupts to enable * @param clkout_divider Clock divider value for CLKOUT. Set to -1 to disable CLKOUT */ -void can_hal_configure(can_hal_context_t *hal_ctx, const can_timing_config_t *t_config, const can_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider); +void twai_hal_configure(twai_hal_context_t *hal_ctx, const twai_timing_config_t *t_config, const twai_filter_config_t *f_config, uint32_t intr_mask, uint32_t clkout_divider); /* -------------------------------- Actions --------------------------------- */ /** - * @brief Start the CAN peripheral + * @brief Start the TWAI peripheral * - * Start the CAN peripheral by configuring its operating mode, then exiting - * reset mode so that the CAN peripheral can participate in bus activities. + * Start the TWAI peripheral by configuring its operating mode, then exiting + * reset mode so that the TWAI peripheral can participate in bus activities. * * @param hal_ctx Context of the HAL layer * @param mode Operating mode * @return True if successfully started, false otherwise. */ -bool can_hal_start(can_hal_context_t *hal_ctx, can_mode_t mode); +bool twai_hal_start(twai_hal_context_t *hal_ctx, twai_mode_t mode); /** - * @brief Stop the CAN peripheral + * @brief Stop the TWAI peripheral * - * Stop the CAN peripheral by entering reset mode to stop any bus activity, then + * Stop the TWAI peripheral by entering reset mode to stop any bus activity, then * setting the operating mode to Listen Only so that REC is frozen. * * @param hal_ctx Context of the HAL layer * @return True if successfully stopped, false otherwise. */ -bool can_hal_stop(can_hal_context_t *hal_ctx); +bool twai_hal_stop(twai_hal_context_t *hal_ctx); /** * @brief Start bus recovery @@ -114,9 +114,9 @@ bool can_hal_stop(can_hal_context_t *hal_ctx); * @param hal_ctx Context of the HAL layer * @return True if successfully started bus recovery, false otherwise. */ -static inline bool can_hal_start_bus_recovery(can_hal_context_t *hal_ctx) +static inline bool twai_hal_start_bus_recovery(twai_hal_context_t *hal_ctx) { - return can_ll_exit_reset_mode(hal_ctx->dev); + return twai_ll_exit_reset_mode(hal_ctx->dev); } /** @@ -125,9 +125,9 @@ static inline bool can_hal_start_bus_recovery(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return TX Error Counter Value */ -static inline uint32_t can_hal_get_tec(can_hal_context_t *hal_ctx) +static inline uint32_t twai_hal_get_tec(twai_hal_context_t *hal_ctx) { - return can_ll_get_tec((hal_ctx)->dev); + return twai_ll_get_tec((hal_ctx)->dev); } /** @@ -136,9 +136,9 @@ static inline uint32_t can_hal_get_tec(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return RX Error Counter Value */ -static inline uint32_t can_hal_get_rec(can_hal_context_t *hal_ctx) +static inline uint32_t twai_hal_get_rec(twai_hal_context_t *hal_ctx) { - return can_ll_get_rec((hal_ctx)->dev); + return twai_ll_get_rec((hal_ctx)->dev); } /** @@ -147,9 +147,9 @@ static inline uint32_t can_hal_get_rec(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return RX message count */ -static inline uint32_t can_hal_get_rx_msg_count(can_hal_context_t *hal_ctx) +static inline uint32_t twai_hal_get_rx_msg_count(twai_hal_context_t *hal_ctx) { - return can_ll_get_rx_msg_count((hal_ctx)->dev); + return twai_ll_get_rx_msg_count((hal_ctx)->dev); } /** @@ -158,9 +158,9 @@ static inline uint32_t can_hal_get_rx_msg_count(can_hal_context_t *hal_ctx) * @param hal_ctx Context of the HAL layer * @return True if successful */ -static inline bool can_hal_check_last_tx_successful(can_hal_context_t *hal_ctx) +static inline bool twai_hal_check_last_tx_successful(twai_hal_context_t *hal_ctx) { - return can_ll_is_last_tx_successful((hal_ctx)->dev); + return twai_ll_is_last_tx_successful((hal_ctx)->dev); } /* ----------------------------- Event Handling ----------------------------- */ @@ -168,15 +168,15 @@ static inline bool can_hal_check_last_tx_successful(can_hal_context_t *hal_ctx) /** * @brief Decode current events that triggered an interrupt * - * This function should be called on every CAN interrupt. It will read (and + * This function should be called on every TWAI interrupt. It will read (and * thereby clear) the interrupt register, then determine what events have * occurred to trigger the interrupt. * * @param hal_ctx Context of the HAL layer - * @param bus_recovering Whether the CAN peripheral was previous undergoing bus recovery + * @param bus_recovering Whether the TWAI peripheral was previous undergoing bus recovery * @return Bit mask of events that have occurred */ -uint32_t can_hal_decode_interrupt_events(can_hal_context_t *hal_ctx, bool bus_recovering); +uint32_t twai_hal_decode_interrupt_events(twai_hal_context_t *hal_ctx, bool bus_recovering); /** * @brief Handle bus recovery complete @@ -187,9 +187,9 @@ uint32_t can_hal_decode_interrupt_events(can_hal_context_t *hal_ctx, bool bus_re * @param hal_ctx Context of the HAL layer * @return True if successfully handled bus recovery completion, false otherwise. */ -static inline bool can_hal_handle_bus_recov_cplt(can_hal_context_t *hal_ctx) +static inline bool twai_hal_handle_bus_recov_cplt(twai_hal_context_t *hal_ctx) { - return can_ll_enter_reset_mode((hal_ctx)->dev); + return twai_ll_enter_reset_mode((hal_ctx)->dev); } /** @@ -200,9 +200,9 @@ static inline bool can_hal_handle_bus_recov_cplt(can_hal_context_t *hal_ctx) * * @param hal_ctx Context of the HAL layer */ -static inline void can_hal_handle_arb_lost(can_hal_context_t *hal_ctx) +static inline void twai_hal_handle_arb_lost(twai_hal_context_t *hal_ctx) { - can_ll_clear_arb_lost_cap((hal_ctx)->dev); + twai_ll_clear_arb_lost_cap((hal_ctx)->dev); } /** @@ -213,9 +213,9 @@ static inline void can_hal_handle_arb_lost(can_hal_context_t *hal_ctx) * * @param hal_ctx Context of the HAL layer */ -static inline void can_hal_handle_bus_error(can_hal_context_t *hal_ctx) +static inline void twai_hal_handle_bus_error(twai_hal_context_t *hal_ctx) { - can_ll_clear_err_code_cap((hal_ctx)->dev); + twai_ll_clear_err_code_cap((hal_ctx)->dev); } /** @@ -226,42 +226,42 @@ static inline void can_hal_handle_bus_error(can_hal_context_t *hal_ctx) * * @param hal_ctx Context of the HAL layer */ -static inline void can_hal_handle_bus_off(can_hal_context_t *hal_ctx) +static inline void twai_hal_handle_bus_off(twai_hal_context_t *hal_ctx) { - can_ll_set_mode((hal_ctx)->dev, CAN_MODE_LISTEN_ONLY); + twai_ll_set_mode((hal_ctx)->dev, TWAI_MODE_LISTEN_ONLY); } /* ------------------------------- TX and RX -------------------------------- */ /** - * @brief Format a CAN Frame + * @brief Format a TWAI Frame * - * This function takes a CAN message structure (containing ID, DLC, data, and + * This function takes a TWAI message structure (containing ID, DLC, data, and * flags) and formats it to match the layout of the TX frame buffer. * - * @param message Pointer to CAN message + * @param message Pointer to TWAI message * @param frame Pointer to empty frame structure */ -static inline void can_hal_format_frame(const can_message_t *message, can_hal_frame_t *frame) +static inline void twai_hal_format_frame(const twai_message_t *message, twai_hal_frame_t *frame) { //Direct call to ll function - can_ll_format_frame_buffer(message->identifier, message->data_length_code, message->data, + twai_ll_format_frame_buffer(message->identifier, message->data_length_code, message->data, message->flags, frame); } /** - * @brief Parse a CAN Frame + * @brief Parse a TWAI Frame * - * This function takes a CAN frame (in the format of the RX frame buffer) and - * parses it to a CAN message (containing ID, DLC, data and flags). + * This function takes a TWAI frame (in the format of the RX frame buffer) and + * parses it to a TWAI message (containing ID, DLC, data and flags). * * @param frame Pointer to frame structure * @param message Pointer to empty message structure */ -static inline void can_hal_parse_frame(can_hal_frame_t *frame, can_message_t *message) +static inline void twai_hal_parse_frame(twai_hal_frame_t *frame, twai_message_t *message) { //Direct call to ll function - can_ll_prase_frame_buffer(frame, &message->identifier, &message->data_length_code, + twai_ll_prase_frame_buffer(frame, &message->identifier, &message->data_length_code, message->data, &message->flags); } @@ -275,7 +275,7 @@ static inline void can_hal_parse_frame(can_hal_frame_t *frame, can_message_t *me * @param hal_ctx Context of the HAL layer * @param tx_frame Pointer to structure containing formatted TX frame */ -void can_hal_set_tx_buffer_and_transmit(can_hal_context_t *hal_ctx, can_hal_frame_t *tx_frame); +void twai_hal_set_tx_buffer_and_transmit(twai_hal_context_t *hal_ctx, twai_hal_frame_t *tx_frame); /** * @brief Copy a frame from the RX buffer and release @@ -286,10 +286,10 @@ void can_hal_set_tx_buffer_and_transmit(can_hal_context_t *hal_ctx, can_hal_fram * @param hal_ctx Context of the HAL layer * @param rx_frame Pointer to structure to store RX frame */ -static inline void can_hal_read_rx_buffer_and_clear(can_hal_context_t *hal_ctx, can_hal_frame_t *rx_frame) +static inline void twai_hal_read_rx_buffer_and_clear(twai_hal_context_t *hal_ctx, twai_hal_frame_t *rx_frame) { - can_ll_get_rx_buffer(hal_ctx->dev, rx_frame); - can_ll_set_cmd_release_rx_buffer(hal_ctx->dev); + twai_ll_get_rx_buffer(hal_ctx->dev, rx_frame); + twai_ll_set_cmd_release_rx_buffer(hal_ctx->dev); /* * Todo: Support overrun handling by: * - Check overrun status bit. Return false if overrun diff --git a/tools/sdk/esp32/include/soc/include/hal/can_types.h b/tools/sdk/esp32s2/include/soc/include/hal/twai_types.h similarity index 55% rename from tools/sdk/esp32/include/soc/include/hal/can_types.h rename to tools/sdk/esp32s2/include/soc/include/hal/twai_types.h index d7947e65..1e6fc7ed 100644 --- a/tools/sdk/esp32/include/soc/include/hal/can_types.h +++ b/tools/sdk/esp32s2/include/soc/include/hal/twai_types.h @@ -20,72 +20,78 @@ extern "C" { #include #include +#include "sdkconfig.h" /** - * @brief CAN2.0B Constants + * @brief TWAI Constants */ -#define CAN_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */ -#define CAN_STD_ID_MASK 0x7FF /**< Bit mask for 11 bit Standard Frame Format ID */ -#define CAN_FRAME_MAX_DLC 8 /**< Max data bytes allowed in CAN2.0 */ -#define CAN_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */ -#define CAN_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */ -#define CAN_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */ +#define TWAI_EXTD_ID_MASK 0x1FFFFFFF /**< Bit mask for 29 bit Extended Frame Format ID */ +#define TWAI_STD_ID_MASK 0x7FF /**< Bit mask for 11 bit Standard Frame Format ID */ +#define TWAI_FRAME_MAX_DLC 8 /**< Max data bytes allowed in TWAI */ +#define TWAI_FRAME_EXTD_ID_LEN_BYTES 4 /**< EFF ID requires 4 bytes (29bit) */ +#define TWAI_FRAME_STD_ID_LEN_BYTES 2 /**< SFF ID requires 2 bytes (11bit) */ +#define TWAI_ERR_PASS_THRESH 128 /**< Error counter threshold for error passive */ /** @cond */ //Doxy command to hide preprocessor definitions from docs /** - * @brief CAN Message flags + * @brief TWAI Message flags * * The message flags are used to indicate the type of message transmitted/received. * Some flags also specify the type of transmission. */ -#define CAN_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */ -#define CAN_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */ -#define CAN_MSG_FLAG_RTR 0x02 /**< Message is a Remote Transmit Request */ -#define CAN_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */ -#define CAN_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */ -#define CAN_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B */ +#define TWAI_MSG_FLAG_NONE 0x00 /**< No message flags (Standard Frame Format) */ +#define TWAI_MSG_FLAG_EXTD 0x01 /**< Extended Frame Format (29bit ID) */ +#define TWAI_MSG_FLAG_RTR 0x02 /**< Message is a Remote Frame */ +#define TWAI_MSG_FLAG_SS 0x04 /**< Transmit as a Single Shot Transmission. Unused for received. */ +#define TWAI_MSG_FLAG_SELF 0x08 /**< Transmit as a Self Reception Request. Unused for received. */ +#define TWAI_MSG_FLAG_DLC_NON_COMP 0x10 /**< Message's Data length code is larger than 8. This will break compliance with TWAI */ /** * @brief Initializer macros for timing configuration structure * - * The following initializer macros offer commonly found bit rates. + * The following initializer macros offer commonly found bit rates. These macros + * place the sample point at 80% or 67% of a bit time. * * @note These timing values are based on the assumption APB clock is at 80MHz - * @note The 20K, 16K and 12.5K bit rates are only available from ESP32 Revision 2 onwards + * @note The available bit rates are dependent on the chip target and revision. */ -#ifdef CAN_BRP_DIV_SUPPORTED -#define CAN_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#if (TWAI_BRP_MAX > 256) +#define TWAI_TIMING_CONFIG_1KBITS() {.brp = 4000, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_5KBITS() {.brp = 800, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_10KBITS() {.brp = 400, .tseg_1 = 15, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} #endif -#define CAN_TIMING_CONFIG_25KBITS() {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_50KBITS() {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_100KBITS() {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_125KBITS() {.brp = 32, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_250KBITS() {.brp = 16, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_500KBITS() {.brp = 8, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_800KBITS() {.brp = 4, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} -#define CAN_TIMING_CONFIG_1MBITS() {.brp = 4, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#if (TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2) +#define TWAI_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#endif +#define TWAI_TIMING_CONFIG_25KBITS() {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_50KBITS() {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_100KBITS() {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_125KBITS() {.brp = 32, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_250KBITS() {.brp = 16, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_500KBITS() {.brp = 8, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_800KBITS() {.brp = 4, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false} +#define TWAI_TIMING_CONFIG_1MBITS() {.brp = 4, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false} /** * @brief Initializer macro for filter configuration to accept all IDs */ -#define CAN_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true} +#define TWAI_FILTER_CONFIG_ACCEPT_ALL() {.acceptance_code = 0, .acceptance_mask = 0xFFFFFFFF, .single_filter = true} /** @endcond */ /** - * @brief CAN Controller operating modes + * @brief TWAI Controller operating modes */ typedef enum { - CAN_MODE_NORMAL, /**< Normal operating mode where CAN controller can send/receive/acknowledge messages */ - CAN_MODE_NO_ACK, /**< Transmission does not require acknowledgment. Use this mode for self testing */ - CAN_MODE_LISTEN_ONLY, /**< The CAN controller will not influence the bus (No transmissions or acknowledgments) but can receive messages */ -} can_mode_t; + TWAI_MODE_NORMAL, /**< Normal operating mode where TWAI controller can send/receive/acknowledge messages */ + TWAI_MODE_NO_ACK, /**< Transmission does not require acknowledgment. Use this mode for self testing */ + TWAI_MODE_LISTEN_ONLY, /**< The TWAI controller will not influence the bus (No transmissions or acknowledgments) but can receive messages */ +} twai_mode_t; /** - * @brief Structure to store a CAN message + * @brief Structure to store a TWAI message * - * @note * @note The flags member is deprecated */ typedef struct { @@ -93,36 +99,36 @@ typedef struct { struct { //The order of these bits must match deprecated message flags for compatibility reasons uint32_t extd: 1; /**< Extended Frame Format (29bit ID) */ - uint32_t rtr: 1; /**< Message is a Remote Transmit Request */ + uint32_t rtr: 1; /**< Message is a Remote Frame */ uint32_t ss: 1; /**< Transmit as a Single Shot Transmission. Unused for received. */ uint32_t self: 1; /**< Transmit as a Self Reception Request. Unused for received. */ - uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with CAN2.0B. */ + uint32_t dlc_non_comp: 1; /**< Message's Data length code is larger than 8. This will break compliance with ISO 11898-1 */ uint32_t reserved: 27; /**< Reserved bits */ }; //Todo: Deprecate flags - uint32_t flags; /**< Alternate way to set message flags using message flag macros (see documentation) */ + uint32_t flags; /**< Deprecated: Alternate way to set bits using message flags */ }; uint32_t identifier; /**< 11 or 29 bit identifier */ uint8_t data_length_code; /**< Data length code */ - uint8_t data[CAN_FRAME_MAX_DLC]; /**< Data bytes (not relevant in RTR frame) */ -} can_message_t; + uint8_t data[TWAI_FRAME_MAX_DLC]; /**< Data bytes (not relevant in RTR frame) */ +} twai_message_t; /** - * @brief Structure for bit timing configuration of the CAN driver + * @brief Structure for bit timing configuration of the TWAI driver * * @note Macro initializers are available for this structure */ typedef struct { - uint32_t brp; /**< Baudrate prescaler (i.e., APB clock divider) can be any even number from 2 to 128. + uint32_t brp; /**< Baudrate prescaler (i.e., APB clock divider). Any even number from 2 to 128 for ESP32, 2 to 32768 for ESP32S2. For ESP32 Rev 2 or later, multiples of 4 from 132 to 256 are also supported */ uint8_t tseg_1; /**< Timing segment 1 (Number of time quanta, between 1 to 16) */ uint8_t tseg_2; /**< Timing segment 2 (Number of time quanta, 1 to 8) */ uint8_t sjw; /**< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4) */ - bool triple_sampling; /**< Enables triple sampling when the CAN controller samples a bit */ -} can_timing_config_t; + bool triple_sampling; /**< Enables triple sampling when the TWAI controller samples a bit */ +} twai_timing_config_t; /** - * @brief Structure for acceptance filter configuration of the CAN driver (see documentation) + * @brief Structure for acceptance filter configuration of the TWAI driver (see documentation) * * @note Macro initializers are available for this structure */ @@ -130,7 +136,7 @@ typedef struct { uint32_t acceptance_code; /**< 32-bit acceptance code */ uint32_t acceptance_mask; /**< 32-bit acceptance mask */ bool single_filter; /**< Use Single Filter Mode (see documentation) */ -} can_filter_config_t; +} twai_filter_config_t; #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/soc/include/soc/lldesc.h b/tools/sdk/esp32s2/include/soc/include/soc/lldesc.h index 541fa1b7..a991a95d 100644 --- a/tools/sdk/esp32s2/include/soc/include/soc/lldesc.h +++ b/tools/sdk/esp32s2/include/soc/include/soc/lldesc.h @@ -20,6 +20,8 @@ #include "esp32/rom/lldesc.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/lldesc.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/lldesc.h" #endif //the size field has 12 bits, but 0 not for 4096. @@ -33,13 +35,23 @@ * The caller should ensure there is enough size to hold the array, by calling * ``lldesc_get_required_num``. * - * @param out_desc_array Output of a descriptor array, the head should be fed to the DMA. + * @param[out] out_desc_array Output of a descriptor array, the head should be fed to the DMA. * @param buffer Buffer for the descriptors to point to. * @param size Size (or length for TX) of the buffer * @param isrx The RX DMA may require the buffer to be word-aligned, set to true for a RX link, otherwise false. */ void lldesc_setup_link(lldesc_t *out_desc_array, const void *buffer, int size, bool isrx); +/** + * @brief Get the received length of a linked list, until end of the link or eof. + * + * @param head The head of the linked list. + * @param[out] out_next Output of the next descriptor of the EOF descriptor. Return NULL if there's no + * EOF. Can be set to NULL if next descriptor is not needed. + * @return The accumulation of the `len` field of all descriptors until EOF or the end of the link. + */ +int lldesc_get_received_len(lldesc_t* head, lldesc_t** out_next); + /** * Get the number of descriptors required for a given buffer size. * diff --git a/tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h b/tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h index 00f69aec..01b13c51 100644 --- a/tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h +++ b/tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h @@ -211,10 +211,10 @@ inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) { } inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) { -#if !CONFIG_FREERTOS_UNICORE || CONFIG_IDF_TARGET_ESP32S2 - return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH); -#else +#if CONFIG_IDF_TARGET_ESP32 && CONFIG_FREERTOS_UNICORE return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH); +#else + return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH); #endif } diff --git a/tools/sdk/esp32s2/include/soc/include/soc_log.h b/tools/sdk/esp32s2/include/soc/include/soc_log.h index a3f955d8..2934eb0c 100644 --- a/tools/sdk/esp32s2/include/soc/include/soc_log.h +++ b/tools/sdk/esp32s2/include/soc/include/soc_log.h @@ -13,7 +13,7 @@ // limitations under the License. #pragma once - +#include "esp_rom_sys.h" /** * @file soc_log.h * @brief SOC library logging functions @@ -33,14 +33,16 @@ #else #include "sdkconfig.h" #ifdef CONFIG_IDF_TARGET_ESP32 -#include "esp32/rom/ets_sys.h" +#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0 #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/ets_sys.h" #endif -#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) -#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGW(tag, fmt, ...) esp_rom_printf("%s(warn): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGI(tag, fmt, ...) esp_rom_printf("%s(info): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGD(tag, fmt, ...) esp_rom_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__) +#define SOC_LOGV(tag, fmt, ...) esp_rom_printf("%s: " fmt, tag, ##__VA_ARGS__) #endif //ESP_PLATFORM diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_caps.h new file mode 100644 index 00000000..e3a7b1a1 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_caps.h @@ -0,0 +1,25 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_reg.h new file mode 100644 index 00000000..ee785b47 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_reg.h @@ -0,0 +1,698 @@ +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CP_DMA_INT_RAW_REG register + * Raw interrupt status + */ +#define CP_DMA_INT_RAW_REG (DR_REG_CP_BASE + 0x0) +/** CP_DMA_IN_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * This is the interrupt raw bit. Triggered when the last data of frame is received or + * the receive buffer is full indicated by inlink descriptor. + */ +#define CP_DMA_IN_DONE_INT_RAW (BIT(0)) +#define CP_DMA_IN_DONE_INT_RAW_M (CP_DMA_IN_DONE_INT_RAW_V << CP_DMA_IN_DONE_INT_RAW_S) +#define CP_DMA_IN_DONE_INT_RAW_V 0x00000001 +#define CP_DMA_IN_DONE_INT_RAW_S 0 +/** CP_DMA_IN_SUC_EOF_INT_RAW : RO; bitpos: [1]; default: 0; + * This is the interrupt raw bit. Triggered when the last data of one frame is + * received. + */ +#define CP_DMA_IN_SUC_EOF_INT_RAW (BIT(1)) +#define CP_DMA_IN_SUC_EOF_INT_RAW_M (CP_DMA_IN_SUC_EOF_INT_RAW_V << CP_DMA_IN_SUC_EOF_INT_RAW_S) +#define CP_DMA_IN_SUC_EOF_INT_RAW_V 0x00000001 +#define CP_DMA_IN_SUC_EOF_INT_RAW_S 1 +/** CP_DMA_OUT_DONE_INT_RAW : RO; bitpos: [2]; default: 0; + * This is the interrupt raw bit. Triggered when all data indicated by one outlink + * descriptor has been pushed into Tx FIFO. + */ +#define CP_DMA_OUT_DONE_INT_RAW (BIT(2)) +#define CP_DMA_OUT_DONE_INT_RAW_M (CP_DMA_OUT_DONE_INT_RAW_V << CP_DMA_OUT_DONE_INT_RAW_S) +#define CP_DMA_OUT_DONE_INT_RAW_V 0x00000001 +#define CP_DMA_OUT_DONE_INT_RAW_S 2 +/** CP_DMA_OUT_EOF_INT_RAW : RO; bitpos: [3]; default: 0; + * This is the interrupt raw bit. Triggered when the last data with EOF flag has been + * pushed into Tx FIFO. + */ +#define CP_DMA_OUT_EOF_INT_RAW (BIT(3)) +#define CP_DMA_OUT_EOF_INT_RAW_M (CP_DMA_OUT_EOF_INT_RAW_V << CP_DMA_OUT_EOF_INT_RAW_S) +#define CP_DMA_OUT_EOF_INT_RAW_V 0x00000001 +#define CP_DMA_OUT_EOF_INT_RAW_S 3 +/** CP_DMA_IN_DSCR_ERR_INT_RAW : RO; bitpos: [4]; default: 0; + * This is the interrupt raw bit. Triggered when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor. + */ +#define CP_DMA_IN_DSCR_ERR_INT_RAW (BIT(4)) +#define CP_DMA_IN_DSCR_ERR_INT_RAW_M (CP_DMA_IN_DSCR_ERR_INT_RAW_V << CP_DMA_IN_DSCR_ERR_INT_RAW_S) +#define CP_DMA_IN_DSCR_ERR_INT_RAW_V 0x00000001 +#define CP_DMA_IN_DSCR_ERR_INT_RAW_S 4 +/** CP_DMA_OUT_DSCR_ERR_INT_RAW : RO; bitpos: [5]; default: 0; + * This is the interrupt raw bit. Triggered when detecting outlink descriptor error, + * including owner error, the second and third word error of outlink descriptor. + */ +#define CP_DMA_OUT_DSCR_ERR_INT_RAW (BIT(5)) +#define CP_DMA_OUT_DSCR_ERR_INT_RAW_M (CP_DMA_OUT_DSCR_ERR_INT_RAW_V << CP_DMA_OUT_DSCR_ERR_INT_RAW_S) +#define CP_DMA_OUT_DSCR_ERR_INT_RAW_V 0x00000001 +#define CP_DMA_OUT_DSCR_ERR_INT_RAW_S 5 +/** CP_DMA_IN_DSCR_EMPTY_INT_RAW : RO; bitpos: [6]; default: 0; + * This is the interrupt raw bit. Triggered when receiving data is completed and no + * more inlink descriptor. + */ +#define CP_DMA_IN_DSCR_EMPTY_INT_RAW (BIT(6)) +#define CP_DMA_IN_DSCR_EMPTY_INT_RAW_M (CP_DMA_IN_DSCR_EMPTY_INT_RAW_V << CP_DMA_IN_DSCR_EMPTY_INT_RAW_S) +#define CP_DMA_IN_DSCR_EMPTY_INT_RAW_V 0x00000001 +#define CP_DMA_IN_DSCR_EMPTY_INT_RAW_S 6 +/** CP_DMA_OUT_TOTAL_EOF_INT_RAW : RO; bitpos: [7]; default: 0; + * This is the interrupt raw bit. Triggered when data corresponding to all outlink + * descriptor and the last descriptor with valid EOF is transmitted out. + */ +#define CP_DMA_OUT_TOTAL_EOF_INT_RAW (BIT(7)) +#define CP_DMA_OUT_TOTAL_EOF_INT_RAW_M (CP_DMA_OUT_TOTAL_EOF_INT_RAW_V << CP_DMA_OUT_TOTAL_EOF_INT_RAW_S) +#define CP_DMA_OUT_TOTAL_EOF_INT_RAW_V 0x00000001 +#define CP_DMA_OUT_TOTAL_EOF_INT_RAW_S 7 +/** CP_DMA_CRC_DONE_INT_RAW : RO; bitpos: [8]; default: 0; + * This is the interrupt raw bit. Triggered when crc calculation is done. + */ +#define CP_DMA_CRC_DONE_INT_RAW (BIT(8)) +#define CP_DMA_CRC_DONE_INT_RAW_M (CP_DMA_CRC_DONE_INT_RAW_V << CP_DMA_CRC_DONE_INT_RAW_S) +#define CP_DMA_CRC_DONE_INT_RAW_V 0x00000001 +#define CP_DMA_CRC_DONE_INT_RAW_S 8 + +/** CP_DMA_INT_ST_REG register + * Masked interrupt status + */ +#define CP_DMA_INT_ST_REG (DR_REG_CP_BASE + 0x4) +/** CP_DMA_IN_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * This is the masked interrupt bit for cp_in_done_int interrupt when + * cp_in_done_int_ena is set to 1. + */ +#define CP_DMA_IN_DONE_INT_ST (BIT(0)) +#define CP_DMA_IN_DONE_INT_ST_M (CP_DMA_IN_DONE_INT_ST_V << CP_DMA_IN_DONE_INT_ST_S) +#define CP_DMA_IN_DONE_INT_ST_V 0x00000001 +#define CP_DMA_IN_DONE_INT_ST_S 0 +/** CP_DMA_IN_SUC_EOF_INT_ST : RO; bitpos: [1]; default: 0; + * This is the masked interrupt bit for cp_in_suc_eof_int interrupt when + * cp_in_suc_eof_int_ena is set to 1. + */ +#define CP_DMA_IN_SUC_EOF_INT_ST (BIT(1)) +#define CP_DMA_IN_SUC_EOF_INT_ST_M (CP_DMA_IN_SUC_EOF_INT_ST_V << CP_DMA_IN_SUC_EOF_INT_ST_S) +#define CP_DMA_IN_SUC_EOF_INT_ST_V 0x00000001 +#define CP_DMA_IN_SUC_EOF_INT_ST_S 1 +/** CP_DMA_OUT_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * This is the masked interrupt bit for cp_out_done_int interrupt when + * cp_out_done_int_ena is set to 1. + */ +#define CP_DMA_OUT_DONE_INT_ST (BIT(2)) +#define CP_DMA_OUT_DONE_INT_ST_M (CP_DMA_OUT_DONE_INT_ST_V << CP_DMA_OUT_DONE_INT_ST_S) +#define CP_DMA_OUT_DONE_INT_ST_V 0x00000001 +#define CP_DMA_OUT_DONE_INT_ST_S 2 +/** CP_DMA_OUT_EOF_INT_ST : RO; bitpos: [3]; default: 0; + * This is the masked interrupt bit for cp_out_eof_int interrupt when + * cp_out_eof_int_ena is set to 1. + */ +#define CP_DMA_OUT_EOF_INT_ST (BIT(3)) +#define CP_DMA_OUT_EOF_INT_ST_M (CP_DMA_OUT_EOF_INT_ST_V << CP_DMA_OUT_EOF_INT_ST_S) +#define CP_DMA_OUT_EOF_INT_ST_V 0x00000001 +#define CP_DMA_OUT_EOF_INT_ST_S 3 +/** CP_DMA_IN_DSCR_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * This is the masked interrupt bit for cp_in_dscr_err_int interrupt when + * cp_in_dscr_err_int_ena is set to 1. + */ +#define CP_DMA_IN_DSCR_ERR_INT_ST (BIT(4)) +#define CP_DMA_IN_DSCR_ERR_INT_ST_M (CP_DMA_IN_DSCR_ERR_INT_ST_V << CP_DMA_IN_DSCR_ERR_INT_ST_S) +#define CP_DMA_IN_DSCR_ERR_INT_ST_V 0x00000001 +#define CP_DMA_IN_DSCR_ERR_INT_ST_S 4 +/** CP_DMA_OUT_DSCR_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * This is the masked interrupt bit for cp_out_dscr_err_int interrupt when + * cp_out_dscr_err_int_ena is set to 1. + */ +#define CP_DMA_OUT_DSCR_ERR_INT_ST (BIT(5)) +#define CP_DMA_OUT_DSCR_ERR_INT_ST_M (CP_DMA_OUT_DSCR_ERR_INT_ST_V << CP_DMA_OUT_DSCR_ERR_INT_ST_S) +#define CP_DMA_OUT_DSCR_ERR_INT_ST_V 0x00000001 +#define CP_DMA_OUT_DSCR_ERR_INT_ST_S 5 +/** CP_DMA_IN_DSCR_EMPTY_INT_ST : RO; bitpos: [6]; default: 0; + * This is the masked interrupt bit for cp_in_dscr_empty_int interrupt when + * cp_in_dscr_empty_int_ena is set to 1. + */ +#define CP_DMA_IN_DSCR_EMPTY_INT_ST (BIT(6)) +#define CP_DMA_IN_DSCR_EMPTY_INT_ST_M (CP_DMA_IN_DSCR_EMPTY_INT_ST_V << CP_DMA_IN_DSCR_EMPTY_INT_ST_S) +#define CP_DMA_IN_DSCR_EMPTY_INT_ST_V 0x00000001 +#define CP_DMA_IN_DSCR_EMPTY_INT_ST_S 6 +/** CP_DMA_OUT_TOTAL_EOF_INT_ST : RO; bitpos: [7]; default: 0; + * This is the masked interrupt bit for cp_out_total_eof_int interrupt when + * cp_out_total_eof_int_ena is set to 1. + */ +#define CP_DMA_OUT_TOTAL_EOF_INT_ST (BIT(7)) +#define CP_DMA_OUT_TOTAL_EOF_INT_ST_M (CP_DMA_OUT_TOTAL_EOF_INT_ST_V << CP_DMA_OUT_TOTAL_EOF_INT_ST_S) +#define CP_DMA_OUT_TOTAL_EOF_INT_ST_V 0x00000001 +#define CP_DMA_OUT_TOTAL_EOF_INT_ST_S 7 +/** CP_DMA_CRC_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * This is the masked interrupt bit for cp_crc_done_int interrupt when + * cp_crc_done_int_ena is set to 1. + */ +#define CP_DMA_CRC_DONE_INT_ST (BIT(8)) +#define CP_DMA_CRC_DONE_INT_ST_M (CP_DMA_CRC_DONE_INT_ST_V << CP_DMA_CRC_DONE_INT_ST_S) +#define CP_DMA_CRC_DONE_INT_ST_V 0x00000001 +#define CP_DMA_CRC_DONE_INT_ST_S 8 + +/** CP_DMA_INT_ENA_REG register + * Interrupt enable bits + */ +#define CP_DMA_INT_ENA_REG (DR_REG_CP_BASE + 0x8) +/** CP_DMA_IN_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the interrupt enable bit for cp_in_done_int interrupt. + */ +#define CP_DMA_IN_DONE_INT_ENA (BIT(0)) +#define CP_DMA_IN_DONE_INT_ENA_M (CP_DMA_IN_DONE_INT_ENA_V << CP_DMA_IN_DONE_INT_ENA_S) +#define CP_DMA_IN_DONE_INT_ENA_V 0x00000001 +#define CP_DMA_IN_DONE_INT_ENA_S 0 +/** CP_DMA_IN_SUC_EOF_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the interrupt enable bit for cp_in_suc_eof_int interrupt. + */ +#define CP_DMA_IN_SUC_EOF_INT_ENA (BIT(1)) +#define CP_DMA_IN_SUC_EOF_INT_ENA_M (CP_DMA_IN_SUC_EOF_INT_ENA_V << CP_DMA_IN_SUC_EOF_INT_ENA_S) +#define CP_DMA_IN_SUC_EOF_INT_ENA_V 0x00000001 +#define CP_DMA_IN_SUC_EOF_INT_ENA_S 1 +/** CP_DMA_OUT_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the interrupt enable bit for cp_out_done_int interrupt. + */ +#define CP_DMA_OUT_DONE_INT_ENA (BIT(2)) +#define CP_DMA_OUT_DONE_INT_ENA_M (CP_DMA_OUT_DONE_INT_ENA_V << CP_DMA_OUT_DONE_INT_ENA_S) +#define CP_DMA_OUT_DONE_INT_ENA_V 0x00000001 +#define CP_DMA_OUT_DONE_INT_ENA_S 2 +/** CP_DMA_OUT_EOF_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the interrupt enable bit for cp_out_eof_int interrupt. + */ +#define CP_DMA_OUT_EOF_INT_ENA (BIT(3)) +#define CP_DMA_OUT_EOF_INT_ENA_M (CP_DMA_OUT_EOF_INT_ENA_V << CP_DMA_OUT_EOF_INT_ENA_S) +#define CP_DMA_OUT_EOF_INT_ENA_V 0x00000001 +#define CP_DMA_OUT_EOF_INT_ENA_S 3 +/** CP_DMA_IN_DSCR_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the interrupt enable bit for cp_in_dscr_err_int interrupt. + */ +#define CP_DMA_IN_DSCR_ERR_INT_ENA (BIT(4)) +#define CP_DMA_IN_DSCR_ERR_INT_ENA_M (CP_DMA_IN_DSCR_ERR_INT_ENA_V << CP_DMA_IN_DSCR_ERR_INT_ENA_S) +#define CP_DMA_IN_DSCR_ERR_INT_ENA_V 0x00000001 +#define CP_DMA_IN_DSCR_ERR_INT_ENA_S 4 +/** CP_DMA_OUT_DSCR_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the interrupt enable bit for cp_out_dscr_err_int interrupt. + */ +#define CP_DMA_OUT_DSCR_ERR_INT_ENA (BIT(5)) +#define CP_DMA_OUT_DSCR_ERR_INT_ENA_M (CP_DMA_OUT_DSCR_ERR_INT_ENA_V << CP_DMA_OUT_DSCR_ERR_INT_ENA_S) +#define CP_DMA_OUT_DSCR_ERR_INT_ENA_V 0x00000001 +#define CP_DMA_OUT_DSCR_ERR_INT_ENA_S 5 +/** CP_DMA_IN_DSCR_EMPTY_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the interrupt enable bit for cp_in_dscr_empty_int interrupt. + */ +#define CP_DMA_IN_DSCR_EMPTY_INT_ENA (BIT(6)) +#define CP_DMA_IN_DSCR_EMPTY_INT_ENA_M (CP_DMA_IN_DSCR_EMPTY_INT_ENA_V << CP_DMA_IN_DSCR_EMPTY_INT_ENA_S) +#define CP_DMA_IN_DSCR_EMPTY_INT_ENA_V 0x00000001 +#define CP_DMA_IN_DSCR_EMPTY_INT_ENA_S 6 +/** CP_DMA_OUT_TOTAL_EOF_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the interrupt enable bit for cp_out_total_eof_int interrupt. + */ +#define CP_DMA_OUT_TOTAL_EOF_INT_ENA (BIT(7)) +#define CP_DMA_OUT_TOTAL_EOF_INT_ENA_M (CP_DMA_OUT_TOTAL_EOF_INT_ENA_V << CP_DMA_OUT_TOTAL_EOF_INT_ENA_S) +#define CP_DMA_OUT_TOTAL_EOF_INT_ENA_V 0x00000001 +#define CP_DMA_OUT_TOTAL_EOF_INT_ENA_S 7 +/** CP_DMA_CRC_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the interrupt enable bit for cp_crc_done_int interrupt. + */ +#define CP_DMA_CRC_DONE_INT_ENA (BIT(8)) +#define CP_DMA_CRC_DONE_INT_ENA_M (CP_DMA_CRC_DONE_INT_ENA_V << CP_DMA_CRC_DONE_INT_ENA_S) +#define CP_DMA_CRC_DONE_INT_ENA_V 0x00000001 +#define CP_DMA_CRC_DONE_INT_ENA_S 8 + +/** CP_DMA_INT_CLR_REG register + * Interrupt clear bits + */ +#define CP_DMA_INT_CLR_REG (DR_REG_CP_BASE + 0xc) +/** CP_DMA_IN_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear cp_in_done_int interrupt. + */ +#define CP_DMA_IN_DONE_INT_CLR (BIT(0)) +#define CP_DMA_IN_DONE_INT_CLR_M (CP_DMA_IN_DONE_INT_CLR_V << CP_DMA_IN_DONE_INT_CLR_S) +#define CP_DMA_IN_DONE_INT_CLR_V 0x00000001 +#define CP_DMA_IN_DONE_INT_CLR_S 0 +/** CP_DMA_IN_SUC_EOF_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear cp_in_suc_eof_int interrupt. + */ +#define CP_DMA_IN_SUC_EOF_INT_CLR (BIT(1)) +#define CP_DMA_IN_SUC_EOF_INT_CLR_M (CP_DMA_IN_SUC_EOF_INT_CLR_V << CP_DMA_IN_SUC_EOF_INT_CLR_S) +#define CP_DMA_IN_SUC_EOF_INT_CLR_V 0x00000001 +#define CP_DMA_IN_SUC_EOF_INT_CLR_S 1 +/** CP_DMA_OUT_DONE_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear cp_out_done_int interrupt. + */ +#define CP_DMA_OUT_DONE_INT_CLR (BIT(2)) +#define CP_DMA_OUT_DONE_INT_CLR_M (CP_DMA_OUT_DONE_INT_CLR_V << CP_DMA_OUT_DONE_INT_CLR_S) +#define CP_DMA_OUT_DONE_INT_CLR_V 0x00000001 +#define CP_DMA_OUT_DONE_INT_CLR_S 2 +/** CP_DMA_OUT_EOF_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear cp_out_eof_int interrupt. + */ +#define CP_DMA_OUT_EOF_INT_CLR (BIT(3)) +#define CP_DMA_OUT_EOF_INT_CLR_M (CP_DMA_OUT_EOF_INT_CLR_V << CP_DMA_OUT_EOF_INT_CLR_S) +#define CP_DMA_OUT_EOF_INT_CLR_V 0x00000001 +#define CP_DMA_OUT_EOF_INT_CLR_S 3 +/** CP_DMA_IN_DSCR_ERR_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear cp_in_dscr_err_int interrupt. + */ +#define CP_DMA_IN_DSCR_ERR_INT_CLR (BIT(4)) +#define CP_DMA_IN_DSCR_ERR_INT_CLR_M (CP_DMA_IN_DSCR_ERR_INT_CLR_V << CP_DMA_IN_DSCR_ERR_INT_CLR_S) +#define CP_DMA_IN_DSCR_ERR_INT_CLR_V 0x00000001 +#define CP_DMA_IN_DSCR_ERR_INT_CLR_S 4 +/** CP_DMA_OUT_DSCR_ERR_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear cp_out_dscr_err_int interrupt. + */ +#define CP_DMA_OUT_DSCR_ERR_INT_CLR (BIT(5)) +#define CP_DMA_OUT_DSCR_ERR_INT_CLR_M (CP_DMA_OUT_DSCR_ERR_INT_CLR_V << CP_DMA_OUT_DSCR_ERR_INT_CLR_S) +#define CP_DMA_OUT_DSCR_ERR_INT_CLR_V 0x00000001 +#define CP_DMA_OUT_DSCR_ERR_INT_CLR_S 5 +/** CP_DMA_IN_DSCR_EMPTY_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear cp_in_dscr_empty_int interrupt. + */ +#define CP_DMA_IN_DSCR_EMPTY_INT_CLR (BIT(6)) +#define CP_DMA_IN_DSCR_EMPTY_INT_CLR_M (CP_DMA_IN_DSCR_EMPTY_INT_CLR_V << CP_DMA_IN_DSCR_EMPTY_INT_CLR_S) +#define CP_DMA_IN_DSCR_EMPTY_INT_CLR_V 0x00000001 +#define CP_DMA_IN_DSCR_EMPTY_INT_CLR_S 6 +/** CP_DMA_OUT_TOTAL_EOF_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear cp_out_total_eof_int interrupt. + */ +#define CP_DMA_OUT_TOTAL_EOF_INT_CLR (BIT(7)) +#define CP_DMA_OUT_TOTAL_EOF_INT_CLR_M (CP_DMA_OUT_TOTAL_EOF_INT_CLR_V << CP_DMA_OUT_TOTAL_EOF_INT_CLR_S) +#define CP_DMA_OUT_TOTAL_EOF_INT_CLR_V 0x00000001 +#define CP_DMA_OUT_TOTAL_EOF_INT_CLR_S 7 +/** CP_DMA_CRC_DONE_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear cp_crc_done_int interrupt. + */ +#define CP_DMA_CRC_DONE_INT_CLR (BIT(8)) +#define CP_DMA_CRC_DONE_INT_CLR_M (CP_DMA_CRC_DONE_INT_CLR_V << CP_DMA_CRC_DONE_INT_CLR_S) +#define CP_DMA_CRC_DONE_INT_CLR_V 0x00000001 +#define CP_DMA_CRC_DONE_INT_CLR_S 8 + +/** CP_DMA_OUT_LINK_REG register + * Link descriptor address and control + */ +#define CP_DMA_OUT_LINK_REG (DR_REG_CP_BASE + 0x10) +/** CP_DMA_OUTLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * This register is used to specify the least significant 20 bits of the first outlink + * descriptor's address. + */ +#define CP_DMA_OUTLINK_ADDR 0x000FFFFF +#define CP_DMA_OUTLINK_ADDR_M (CP_DMA_OUTLINK_ADDR_V << CP_DMA_OUTLINK_ADDR_S) +#define CP_DMA_OUTLINK_ADDR_V 0x000FFFFF +#define CP_DMA_OUTLINK_ADDR_S 0 +/** CP_DMA_OUTLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set this bit to stop dealing with the outlink descriptor. + */ +#define CP_DMA_OUTLINK_STOP (BIT(28)) +#define CP_DMA_OUTLINK_STOP_M (CP_DMA_OUTLINK_STOP_V << CP_DMA_OUTLINK_STOP_S) +#define CP_DMA_OUTLINK_STOP_V 0x00000001 +#define CP_DMA_OUTLINK_STOP_S 28 +/** CP_DMA_OUTLINK_START : R/W; bitpos: [29]; default: 0; + * Set this bit to start a new outlink descriptor. + */ +#define CP_DMA_OUTLINK_START (BIT(29)) +#define CP_DMA_OUTLINK_START_M (CP_DMA_OUTLINK_START_V << CP_DMA_OUTLINK_START_S) +#define CP_DMA_OUTLINK_START_V 0x00000001 +#define CP_DMA_OUTLINK_START_S 29 +/** CP_DMA_OUTLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set this bit to restart the outlink descriptpr from the last address. + */ +#define CP_DMA_OUTLINK_RESTART (BIT(30)) +#define CP_DMA_OUTLINK_RESTART_M (CP_DMA_OUTLINK_RESTART_V << CP_DMA_OUTLINK_RESTART_S) +#define CP_DMA_OUTLINK_RESTART_V 0x00000001 +#define CP_DMA_OUTLINK_RESTART_S 30 +/** CP_DMA_OUTLINK_PARK : RO; bitpos: [31]; default: 0; + * 1: the outlink descriptor's FSM is in idle state. + * 0: the outlink descriptor's FSM is working. + */ +#define CP_DMA_OUTLINK_PARK (BIT(31)) +#define CP_DMA_OUTLINK_PARK_M (CP_DMA_OUTLINK_PARK_V << CP_DMA_OUTLINK_PARK_S) +#define CP_DMA_OUTLINK_PARK_V 0x00000001 +#define CP_DMA_OUTLINK_PARK_S 31 + +/** CP_DMA_IN_LINK_REG register + * Link descriptor address and control + */ +#define CP_DMA_IN_LINK_REG (DR_REG_CP_BASE + 0x14) +/** CP_DMA_INLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * This register is used to specify the least significant 20 bits of the first inlink + * descriptor's address. + */ +#define CP_DMA_INLINK_ADDR 0x000FFFFF +#define CP_DMA_INLINK_ADDR_M (CP_DMA_INLINK_ADDR_V << CP_DMA_INLINK_ADDR_S) +#define CP_DMA_INLINK_ADDR_V 0x000FFFFF +#define CP_DMA_INLINK_ADDR_S 0 +/** CP_DMA_INLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ +#define CP_DMA_INLINK_STOP (BIT(28)) +#define CP_DMA_INLINK_STOP_M (CP_DMA_INLINK_STOP_V << CP_DMA_INLINK_STOP_S) +#define CP_DMA_INLINK_STOP_V 0x00000001 +#define CP_DMA_INLINK_STOP_S 28 +/** CP_DMA_INLINK_START : R/W; bitpos: [29]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ +#define CP_DMA_INLINK_START (BIT(29)) +#define CP_DMA_INLINK_START_M (CP_DMA_INLINK_START_V << CP_DMA_INLINK_START_S) +#define CP_DMA_INLINK_START_V 0x00000001 +#define CP_DMA_INLINK_START_S 29 +/** CP_DMA_INLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set this bit to restart new inlink descriptors. + */ +#define CP_DMA_INLINK_RESTART (BIT(30)) +#define CP_DMA_INLINK_RESTART_M (CP_DMA_INLINK_RESTART_V << CP_DMA_INLINK_RESTART_S) +#define CP_DMA_INLINK_RESTART_V 0x00000001 +#define CP_DMA_INLINK_RESTART_S 30 +/** CP_DMA_INLINK_PARK : RO; bitpos: [31]; default: 0; + * 1: the inlink descriptor's FSM is in idle state. + * 0: the inlink descriptor's FSM is working. + */ +#define CP_DMA_INLINK_PARK (BIT(31)) +#define CP_DMA_INLINK_PARK_M (CP_DMA_INLINK_PARK_V << CP_DMA_INLINK_PARK_S) +#define CP_DMA_INLINK_PARK_V 0x00000001 +#define CP_DMA_INLINK_PARK_S 31 + +/** CP_DMA_OUT_EOF_DES_ADDR_REG register + * Outlink descriptor address when EOF occurs + */ +#define CP_DMA_OUT_EOF_DES_ADDR_REG (DR_REG_CP_BASE + 0x18) +/** CP_DMA_OUT_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ +#define CP_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define CP_DMA_OUT_EOF_DES_ADDR_M (CP_DMA_OUT_EOF_DES_ADDR_V << CP_DMA_OUT_EOF_DES_ADDR_S) +#define CP_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define CP_DMA_OUT_EOF_DES_ADDR_S 0 + +/** CP_DMA_IN_EOF_DES_ADDR_REG register + * Inlink descriptor address when EOF occurs + */ +#define CP_DMA_IN_EOF_DES_ADDR_REG (DR_REG_CP_BASE + 0x1c) +/** CP_DMA_IN_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when received successful + * EOF. + */ +#define CP_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define CP_DMA_IN_SUC_EOF_DES_ADDR_M (CP_DMA_IN_SUC_EOF_DES_ADDR_V << CP_DMA_IN_SUC_EOF_DES_ADDR_S) +#define CP_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define CP_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +/** CP_DMA_OUT_EOF_BFR_DES_ADDR_REG register + * Outlink descriptor address before the last outlink descriptor + */ +#define CP_DMA_OUT_EOF_BFR_DES_ADDR_REG (DR_REG_CP_BASE + 0x20) +/** CP_DMA_OUT_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ +#define CP_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define CP_DMA_OUT_EOF_BFR_DES_ADDR_M (CP_DMA_OUT_EOF_BFR_DES_ADDR_V << CP_DMA_OUT_EOF_BFR_DES_ADDR_S) +#define CP_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define CP_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +/** CP_DMA_INLINK_DSCR_REG register + * Address of current inlink descriptor + */ +#define CP_DMA_INLINK_DSCR_REG (DR_REG_CP_BASE + 0x24) +/** CP_DMA_INLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ +#define CP_DMA_INLINK_DSCR 0xFFFFFFFF +#define CP_DMA_INLINK_DSCR_M (CP_DMA_INLINK_DSCR_V << CP_DMA_INLINK_DSCR_S) +#define CP_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define CP_DMA_INLINK_DSCR_S 0 + +/** CP_DMA_INLINK_DSCR_BF0_REG register + * Address of last inlink descriptor + */ +#define CP_DMA_INLINK_DSCR_BF0_REG (DR_REG_CP_BASE + 0x28) +/** CP_DMA_INLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ +#define CP_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define CP_DMA_INLINK_DSCR_BF0_M (CP_DMA_INLINK_DSCR_BF0_V << CP_DMA_INLINK_DSCR_BF0_S) +#define CP_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define CP_DMA_INLINK_DSCR_BF0_S 0 + +/** CP_DMA_INLINK_DSCR_BF1_REG register + * Address of the second-to-last inlink descriptor + */ +#define CP_DMA_INLINK_DSCR_BF1_REG (DR_REG_CP_BASE + 0x2c) +/** CP_DMA_INLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ +#define CP_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define CP_DMA_INLINK_DSCR_BF1_M (CP_DMA_INLINK_DSCR_BF1_V << CP_DMA_INLINK_DSCR_BF1_S) +#define CP_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define CP_DMA_INLINK_DSCR_BF1_S 0 + +/** CP_DMA_OUTLINK_DSCR_REG register + * Address of current outlink descriptor + */ +#define CP_DMA_OUTLINK_DSCR_REG (DR_REG_CP_BASE + 0x30) +/** CP_DMA_OUTLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ +#define CP_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define CP_DMA_OUTLINK_DSCR_M (CP_DMA_OUTLINK_DSCR_V << CP_DMA_OUTLINK_DSCR_S) +#define CP_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define CP_DMA_OUTLINK_DSCR_S 0 + +/** CP_DMA_OUTLINK_DSCR_BF0_REG register + * Address of last outlink descriptor + */ +#define CP_DMA_OUTLINK_DSCR_BF0_REG (DR_REG_CP_BASE + 0x34) +/** CP_DMA_OUTLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ +#define CP_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define CP_DMA_OUTLINK_DSCR_BF0_M (CP_DMA_OUTLINK_DSCR_BF0_V << CP_DMA_OUTLINK_DSCR_BF0_S) +#define CP_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define CP_DMA_OUTLINK_DSCR_BF0_S 0 + +/** CP_DMA_OUTLINK_DSCR_BF1_REG register + * Address of the second-to-last outlink descriptor + */ +#define CP_DMA_OUTLINK_DSCR_BF1_REG (DR_REG_CP_BASE + 0x38) +/** CP_DMA_OUTLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last outlink descriptor y-2. + */ +#define CP_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define CP_DMA_OUTLINK_DSCR_BF1_M (CP_DMA_OUTLINK_DSCR_BF1_V << CP_DMA_OUTLINK_DSCR_BF1_S) +#define CP_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define CP_DMA_OUTLINK_DSCR_BF1_S 0 + +/** CP_DMA_CONF_REG register + * Copy DMA configuration register + */ +#define CP_DMA_CONF_REG (DR_REG_CP_BASE + 0x3c) +/** CP_DMA_IN_RST : R/W; bitpos: [0]; default: 0; + * Set this bit to reset in_inf state machine. + */ +#define CP_DMA_IN_RST (BIT(0)) +#define CP_DMA_IN_RST_M (CP_DMA_IN_RST_V << CP_DMA_IN_RST_S) +#define CP_DMA_IN_RST_V 0x00000001 +#define CP_DMA_IN_RST_S 0 +/** CP_DMA_OUT_RST : R/W; bitpos: [1]; default: 0; + * Set this bit to reset out_inf state machine. + */ +#define CP_DMA_OUT_RST (BIT(1)) +#define CP_DMA_OUT_RST_M (CP_DMA_OUT_RST_V << CP_DMA_OUT_RST_S) +#define CP_DMA_OUT_RST_V 0x00000001 +#define CP_DMA_OUT_RST_S 1 +/** CP_DMA_CMDFIFO_RST : R/W; bitpos: [2]; default: 0; + * Set this bit to reset in_cmd fifo and out_cmd fifo. + */ +#define CP_DMA_CMDFIFO_RST (BIT(2)) +#define CP_DMA_CMDFIFO_RST_M (CP_DMA_CMDFIFO_RST_V << CP_DMA_CMDFIFO_RST_S) +#define CP_DMA_CMDFIFO_RST_V 0x00000001 +#define CP_DMA_CMDFIFO_RST_S 2 +/** CP_DMA_FIFO_RST : R/W; bitpos: [3]; default: 0; + * Set this bit to reset data in receive FIFO. + */ +#define CP_DMA_FIFO_RST (BIT(3)) +#define CP_DMA_FIFO_RST_M (CP_DMA_FIFO_RST_V << CP_DMA_FIFO_RST_S) +#define CP_DMA_FIFO_RST_V 0x00000001 +#define CP_DMA_FIFO_RST_S 3 +/** CP_DMA_OUT_OWNER : R/W; bitpos: [4]; default: 0; + * This is used to configure the owner bit in OUT descriptor. This is effective only + * when you set reg_out_auto_wrback. + */ +#define CP_DMA_OUT_OWNER (BIT(4)) +#define CP_DMA_OUT_OWNER_M (CP_DMA_OUT_OWNER_V << CP_DMA_OUT_OWNER_S) +#define CP_DMA_OUT_OWNER_V 0x00000001 +#define CP_DMA_OUT_OWNER_S 4 +/** CP_DMA_IN_OWNER : R/W; bitpos: [5]; default: 0; + * This is used to configure the owner bit in IN descriptor. + */ +#define CP_DMA_IN_OWNER (BIT(5)) +#define CP_DMA_IN_OWNER_M (CP_DMA_IN_OWNER_V << CP_DMA_IN_OWNER_S) +#define CP_DMA_IN_OWNER_V 0x00000001 +#define CP_DMA_IN_OWNER_S 5 +/** CP_DMA_OUT_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * This bit is used to write back out descriptor when hardware has already used this + * descriptor. + */ +#define CP_DMA_OUT_AUTO_WRBACK (BIT(6)) +#define CP_DMA_OUT_AUTO_WRBACK_M (CP_DMA_OUT_AUTO_WRBACK_V << CP_DMA_OUT_AUTO_WRBACK_S) +#define CP_DMA_OUT_AUTO_WRBACK_V 0x00000001 +#define CP_DMA_OUT_AUTO_WRBACK_S 6 +/** CP_DMA_CHECK_OWNER : R/W; bitpos: [7]; default: 0; + * Set this bit to enable owner bit check in descriptor. + */ +#define CP_DMA_CHECK_OWNER (BIT(7)) +#define CP_DMA_CHECK_OWNER_M (CP_DMA_CHECK_OWNER_V << CP_DMA_CHECK_OWNER_S) +#define CP_DMA_CHECK_OWNER_V 0x00000001 +#define CP_DMA_CHECK_OWNER_S 7 +/** CP_DMA_CRC_CAL_RESET : R/W; bitpos: [8]; default: 0; + * Set this bit to reset crc calculation. + */ +#define CP_DMA_CRC_CAL_RESET (BIT(8)) +#define CP_DMA_CRC_CAL_RESET_M (CP_DMA_CRC_CAL_RESET_V << CP_DMA_CRC_CAL_RESET_S) +#define CP_DMA_CRC_CAL_RESET_V 0x00000001 +#define CP_DMA_CRC_CAL_RESET_S 8 +/** CP_DMA_CRC_CAL_EN : R/W; bitpos: [9]; default: 0; + * Set this bit enable crc calculation function. + */ +#define CP_DMA_CRC_CAL_EN (BIT(9)) +#define CP_DMA_CRC_CAL_EN_M (CP_DMA_CRC_CAL_EN_V << CP_DMA_CRC_CAL_EN_S) +#define CP_DMA_CRC_CAL_EN_V 0x00000001 +#define CP_DMA_CRC_CAL_EN_S 9 +/** CP_DMA_CRC_BIG_ENDIAN_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to reorder the bit of data which will be send to excute crc. + */ +#define CP_DMA_CRC_BIG_ENDIAN_EN (BIT(10)) +#define CP_DMA_CRC_BIG_ENDIAN_EN_M (CP_DMA_CRC_BIG_ENDIAN_EN_V << CP_DMA_CRC_BIG_ENDIAN_EN_S) +#define CP_DMA_CRC_BIG_ENDIAN_EN_V 0x00000001 +#define CP_DMA_CRC_BIG_ENDIAN_EN_S 10 +/** CP_DMA_CRC_OUT_REVERSE_EN : R/W; bitpos: [11]; default: 0; + * Set this bit to reverse the crc calculation result. + */ +#define CP_DMA_CRC_OUT_REVERSE_EN (BIT(11)) +#define CP_DMA_CRC_OUT_REVERSE_EN_M (CP_DMA_CRC_OUT_REVERSE_EN_V << CP_DMA_CRC_OUT_REVERSE_EN_S) +#define CP_DMA_CRC_OUT_REVERSE_EN_V 0x00000001 +#define CP_DMA_CRC_OUT_REVERSE_EN_S 11 +/** CP_DMA_CLK_EN : R/W; bitpos: [31]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ +#define CP_DMA_CLK_EN (BIT(31)) +#define CP_DMA_CLK_EN_M (CP_DMA_CLK_EN_V << CP_DMA_CLK_EN_S) +#define CP_DMA_CLK_EN_V 0x00000001 +#define CP_DMA_CLK_EN_S 31 + +/** CP_DMA_IN_ST_REG register + * Status register of receiving data + */ +#define CP_DMA_IN_ST_REG (DR_REG_CP_BASE + 0x40) +/** CP_DMA_INLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ +#define CP_DMA_INLINK_DSCR_ADDR 0x0003FFFF +#define CP_DMA_INLINK_DSCR_ADDR_M (CP_DMA_INLINK_DSCR_ADDR_V << CP_DMA_INLINK_DSCR_ADDR_S) +#define CP_DMA_INLINK_DSCR_ADDR_V 0x0003FFFF +#define CP_DMA_INLINK_DSCR_ADDR_S 0 +/** CP_DMA_IN_DSCR_STATE : RO; bitpos: [19:18]; default: 0; + * Reserved. + */ +#define CP_DMA_IN_DSCR_STATE 0x00000003 +#define CP_DMA_IN_DSCR_STATE_M (CP_DMA_IN_DSCR_STATE_V << CP_DMA_IN_DSCR_STATE_S) +#define CP_DMA_IN_DSCR_STATE_V 0x00000003 +#define CP_DMA_IN_DSCR_STATE_S 18 +/** CP_DMA_IN_STATE : RO; bitpos: [22:20]; default: 0; + * Reserved. + */ +#define CP_DMA_IN_STATE 0x00000007 +#define CP_DMA_IN_STATE_M (CP_DMA_IN_STATE_V << CP_DMA_IN_STATE_S) +#define CP_DMA_IN_STATE_V 0x00000007 +#define CP_DMA_IN_STATE_S 20 +/** CP_DMA_FIFO_EMPTY : RO; bitpos: [23]; default: 0; + * Copy DMA FIFO empty signal. + */ +#define CP_DMA_FIFO_EMPTY (BIT(23)) +#define CP_DMA_FIFO_EMPTY_M (CP_DMA_FIFO_EMPTY_V << CP_DMA_FIFO_EMPTY_S) +#define CP_DMA_FIFO_EMPTY_V 0x00000001 +#define CP_DMA_FIFO_EMPTY_S 23 + +/** CP_DMA_OUT_ST_REG register + * Status register of trasmitting data + */ +#define CP_DMA_OUT_ST_REG (DR_REG_CP_BASE + 0x44) +/** CP_DMA_OUTLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ +#define CP_DMA_OUTLINK_DSCR_ADDR 0x0003FFFF +#define CP_DMA_OUTLINK_DSCR_ADDR_M (CP_DMA_OUTLINK_DSCR_ADDR_V << CP_DMA_OUTLINK_DSCR_ADDR_S) +#define CP_DMA_OUTLINK_DSCR_ADDR_V 0x0003FFFF +#define CP_DMA_OUTLINK_DSCR_ADDR_S 0 +/** CP_DMA_OUT_DSCR_STATE : RO; bitpos: [19:18]; default: 0; + * Reserved. + */ +#define CP_DMA_OUT_DSCR_STATE 0x00000003 +#define CP_DMA_OUT_DSCR_STATE_M (CP_DMA_OUT_DSCR_STATE_V << CP_DMA_OUT_DSCR_STATE_S) +#define CP_DMA_OUT_DSCR_STATE_V 0x00000003 +#define CP_DMA_OUT_DSCR_STATE_S 18 +/** CP_DMA_OUT_STATE : RO; bitpos: [22:20]; default: 0; + * Reserved. + */ +#define CP_DMA_OUT_STATE 0x00000007 +#define CP_DMA_OUT_STATE_M (CP_DMA_OUT_STATE_V << CP_DMA_OUT_STATE_S) +#define CP_DMA_OUT_STATE_V 0x00000007 +#define CP_DMA_OUT_STATE_S 20 +/** CP_DMA_FIFO_FULL : RO; bitpos: [23]; default: 0; + * Copy DMA FIFO full signal. + */ +#define CP_DMA_FIFO_FULL (BIT(23)) +#define CP_DMA_FIFO_FULL_M (CP_DMA_FIFO_FULL_V << CP_DMA_FIFO_FULL_S) +#define CP_DMA_FIFO_FULL_V 0x00000001 +#define CP_DMA_FIFO_FULL_S 23 + +/** CP_DMA_CRC_OUT_REG register + * CRC result register + */ +#define CP_DMA_CRC_OUT_REG (DR_REG_CP_BASE + 0x48) +/** CP_DMA_CRC_RESULT : RO; bitpos: [31:0]; default: 0; + * This register stores the result of CRC. + */ +#define CP_DMA_CRC_RESULT 0xFFFFFFFF +#define CP_DMA_CRC_RESULT_M (CP_DMA_CRC_RESULT_V << CP_DMA_CRC_RESULT_S) +#define CP_DMA_CRC_RESULT_V 0xFFFFFFFF +#define CP_DMA_CRC_RESULT_S 0 + +/** CP_DMA_DATE_REG register + * Copy DMA version register + */ +#define CP_DMA_DATE_REG (DR_REG_CP_BASE + 0xfc) +/** CP_DMA_DMA_DATE : R/W; bitpos: [31:0]; default: 403185664; + * This is the version register. + */ +#define CP_DMA_DMA_DATE 0xFFFFFFFF +#define CP_DMA_DMA_DATE_M (CP_DMA_DMA_DATE_V << CP_DMA_DMA_DATE_S) +#define CP_DMA_DMA_DATE_V 0xFFFFFFFF +#define CP_DMA_DMA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_struct.h new file mode 100644 index 00000000..208c8293 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/cp_dma_struct.h @@ -0,0 +1,623 @@ +/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Interrupt Registers */ +/** Type of dma_int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** dma_in_done_int_raw : RO; bitpos: [0]; default: 0; + * This is the interrupt raw bit. Triggered when the last data of frame is received or + * the receive buffer is full indicated by inlink descriptor. + */ + uint32_t dma_in_done_int_raw: 1; + /** dma_in_suc_eof_int_raw : RO; bitpos: [1]; default: 0; + * This is the interrupt raw bit. Triggered when the last data of one frame is + * received. + */ + uint32_t dma_in_suc_eof_int_raw: 1; + /** dma_out_done_int_raw : RO; bitpos: [2]; default: 0; + * This is the interrupt raw bit. Triggered when all data indicated by one outlink + * descriptor has been pushed into Tx FIFO. + */ + uint32_t dma_out_done_int_raw: 1; + /** dma_out_eof_int_raw : RO; bitpos: [3]; default: 0; + * This is the interrupt raw bit. Triggered when the last data with EOF flag has been + * pushed into Tx FIFO. + */ + uint32_t dma_out_eof_int_raw: 1; + /** dma_in_dscr_err_int_raw : RO; bitpos: [4]; default: 0; + * This is the interrupt raw bit. Triggered when detecting inlink descriptor error, + * including owner error, the second and third word error of inlink descriptor. + */ + uint32_t dma_in_dscr_err_int_raw: 1; + /** dma_out_dscr_err_int_raw : RO; bitpos: [5]; default: 0; + * This is the interrupt raw bit. Triggered when detecting outlink descriptor error, + * including owner error, the second and third word error of outlink descriptor. + */ + uint32_t dma_out_dscr_err_int_raw: 1; + /** dma_in_dscr_empty_int_raw : RO; bitpos: [6]; default: 0; + * This is the interrupt raw bit. Triggered when receiving data is completed and no + * more inlink descriptor. + */ + uint32_t dma_in_dscr_empty_int_raw: 1; + /** dma_out_total_eof_int_raw : RO; bitpos: [7]; default: 0; + * This is the interrupt raw bit. Triggered when data corresponding to all outlink + * descriptor and the last descriptor with valid EOF is transmitted out. + */ + uint32_t dma_out_total_eof_int_raw: 1; + /** dma_crc_done_int_raw : RO; bitpos: [8]; default: 0; + * This is the interrupt raw bit. Triggered when crc calculation is done. + */ + uint32_t dma_crc_done_int_raw: 1; + }; + uint32_t val; +} cp_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** dma_in_done_int_st : RO; bitpos: [0]; default: 0; + * This is the masked interrupt bit for cp_in_done_int interrupt when + * cp_in_done_int_ena is set to 1. + */ + uint32_t dma_in_done_int_st: 1; + /** dma_in_suc_eof_int_st : RO; bitpos: [1]; default: 0; + * This is the masked interrupt bit for cp_in_suc_eof_int interrupt when + * cp_in_suc_eof_int_ena is set to 1. + */ + uint32_t dma_in_suc_eof_int_st: 1; + /** dma_out_done_int_st : RO; bitpos: [2]; default: 0; + * This is the masked interrupt bit for cp_out_done_int interrupt when + * cp_out_done_int_ena is set to 1. + */ + uint32_t dma_out_done_int_st: 1; + /** dma_out_eof_int_st : RO; bitpos: [3]; default: 0; + * This is the masked interrupt bit for cp_out_eof_int interrupt when + * cp_out_eof_int_ena is set to 1. + */ + uint32_t dma_out_eof_int_st: 1; + /** dma_in_dscr_err_int_st : RO; bitpos: [4]; default: 0; + * This is the masked interrupt bit for cp_in_dscr_err_int interrupt when + * cp_in_dscr_err_int_ena is set to 1. + */ + uint32_t dma_in_dscr_err_int_st: 1; + /** dma_out_dscr_err_int_st : RO; bitpos: [5]; default: 0; + * This is the masked interrupt bit for cp_out_dscr_err_int interrupt when + * cp_out_dscr_err_int_ena is set to 1. + */ + uint32_t dma_out_dscr_err_int_st: 1; + /** dma_in_dscr_empty_int_st : RO; bitpos: [6]; default: 0; + * This is the masked interrupt bit for cp_in_dscr_empty_int interrupt when + * cp_in_dscr_empty_int_ena is set to 1. + */ + uint32_t dma_in_dscr_empty_int_st: 1; + /** dma_out_total_eof_int_st : RO; bitpos: [7]; default: 0; + * This is the masked interrupt bit for cp_out_total_eof_int interrupt when + * cp_out_total_eof_int_ena is set to 1. + */ + uint32_t dma_out_total_eof_int_st: 1; + /** dma_crc_done_int_st : RO; bitpos: [8]; default: 0; + * This is the masked interrupt bit for cp_crc_done_int interrupt when + * cp_crc_done_int_ena is set to 1. + */ + uint32_t dma_crc_done_int_st: 1; + }; + uint32_t val; +} cp_dma_int_st_reg_t; + +/** Type of dma_int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** dma_in_done_int_ena : R/W; bitpos: [0]; default: 0; + * This is the interrupt enable bit for cp_in_done_int interrupt. + */ + uint32_t dma_in_done_int_ena: 1; + /** dma_in_suc_eof_int_ena : R/W; bitpos: [1]; default: 0; + * This is the interrupt enable bit for cp_in_suc_eof_int interrupt. + */ + uint32_t dma_in_suc_eof_int_ena: 1; + /** dma_out_done_int_ena : R/W; bitpos: [2]; default: 0; + * This is the interrupt enable bit for cp_out_done_int interrupt. + */ + uint32_t dma_out_done_int_ena: 1; + /** dma_out_eof_int_ena : R/W; bitpos: [3]; default: 0; + * This is the interrupt enable bit for cp_out_eof_int interrupt. + */ + uint32_t dma_out_eof_int_ena: 1; + /** dma_in_dscr_err_int_ena : R/W; bitpos: [4]; default: 0; + * This is the interrupt enable bit for cp_in_dscr_err_int interrupt. + */ + uint32_t dma_in_dscr_err_int_ena: 1; + /** dma_out_dscr_err_int_ena : R/W; bitpos: [5]; default: 0; + * This is the interrupt enable bit for cp_out_dscr_err_int interrupt. + */ + uint32_t dma_out_dscr_err_int_ena: 1; + /** dma_in_dscr_empty_int_ena : R/W; bitpos: [6]; default: 0; + * This is the interrupt enable bit for cp_in_dscr_empty_int interrupt. + */ + uint32_t dma_in_dscr_empty_int_ena: 1; + /** dma_out_total_eof_int_ena : R/W; bitpos: [7]; default: 0; + * This is the interrupt enable bit for cp_out_total_eof_int interrupt. + */ + uint32_t dma_out_total_eof_int_ena: 1; + /** dma_crc_done_int_ena : R/W; bitpos: [8]; default: 0; + * This is the interrupt enable bit for cp_crc_done_int interrupt. + */ + uint32_t dma_crc_done_int_ena: 1; + }; + uint32_t val; +} cp_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** dma_in_done_int_clr : WO; bitpos: [0]; default: 0; + * Set this bit to clear cp_in_done_int interrupt. + */ + uint32_t dma_in_done_int_clr: 1; + /** dma_in_suc_eof_int_clr : WO; bitpos: [1]; default: 0; + * Set this bit to clear cp_in_suc_eof_int interrupt. + */ + uint32_t dma_in_suc_eof_int_clr: 1; + /** dma_out_done_int_clr : WO; bitpos: [2]; default: 0; + * Set this bit to clear cp_out_done_int interrupt. + */ + uint32_t dma_out_done_int_clr: 1; + /** dma_out_eof_int_clr : WO; bitpos: [3]; default: 0; + * Set this bit to clear cp_out_eof_int interrupt. + */ + uint32_t dma_out_eof_int_clr: 1; + /** dma_in_dscr_err_int_clr : WO; bitpos: [4]; default: 0; + * Set this bit to clear cp_in_dscr_err_int interrupt. + */ + uint32_t dma_in_dscr_err_int_clr: 1; + /** dma_out_dscr_err_int_clr : WO; bitpos: [5]; default: 0; + * Set this bit to clear cp_out_dscr_err_int interrupt. + */ + uint32_t dma_out_dscr_err_int_clr: 1; + /** dma_in_dscr_empty_int_clr : WO; bitpos: [6]; default: 0; + * Set this bit to clear cp_in_dscr_empty_int interrupt. + */ + uint32_t dma_in_dscr_empty_int_clr: 1; + /** dma_out_total_eof_int_clr : WO; bitpos: [7]; default: 0; + * Set this bit to clear cp_out_total_eof_int interrupt. + */ + uint32_t dma_out_total_eof_int_clr: 1; + /** dma_crc_done_int_clr : WO; bitpos: [8]; default: 0; + * Set this bit to clear cp_crc_done_int interrupt. + */ + uint32_t dma_crc_done_int_clr: 1; + }; + uint32_t val; +} cp_dma_int_clr_reg_t; + + +/** Configuration Registers */ +/** Type of dma_out_link register + * Link descriptor address and control + */ +typedef union { + struct { + /** dma_outlink_addr : R/W; bitpos: [19:0]; default: 0; + * This register is used to specify the least significant 20 bits of the first outlink + * descriptor's address. + */ + uint32_t dma_outlink_addr: 20; + uint32_t reserved_20: 8; + /** dma_outlink_stop : R/W; bitpos: [28]; default: 0; + * Set this bit to stop dealing with the outlink descriptor. + */ + uint32_t dma_outlink_stop: 1; + /** dma_outlink_start : R/W; bitpos: [29]; default: 0; + * Set this bit to start a new outlink descriptor. + */ + uint32_t dma_outlink_start: 1; + /** dma_outlink_restart : R/W; bitpos: [30]; default: 0; + * Set this bit to restart the outlink descriptpr from the last address. + */ + uint32_t dma_outlink_restart: 1; + /** dma_outlink_park : RO; bitpos: [31]; default: 0; + * 1: the outlink descriptor's FSM is in idle state. + * 0: the outlink descriptor's FSM is working. + */ + uint32_t dma_outlink_park: 1; + }; + uint32_t val; +} cp_dma_out_link_reg_t; + +/** Type of dma_in_link register + * Link descriptor address and control + */ +typedef union { + struct { + /** dma_inlink_addr : R/W; bitpos: [19:0]; default: 0; + * This register is used to specify the least significant 20 bits of the first inlink + * descriptor's address. + */ + uint32_t dma_inlink_addr: 20; + uint32_t reserved_20: 8; + /** dma_inlink_stop : R/W; bitpos: [28]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + uint32_t dma_inlink_stop: 1; + /** dma_inlink_start : R/W; bitpos: [29]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + uint32_t dma_inlink_start: 1; + /** dma_inlink_restart : R/W; bitpos: [30]; default: 0; + * Set this bit to restart new inlink descriptors. + */ + uint32_t dma_inlink_restart: 1; + /** dma_inlink_park : RO; bitpos: [31]; default: 0; + * 1: the inlink descriptor's FSM is in idle state. + * 0: the inlink descriptor's FSM is working. + */ + uint32_t dma_inlink_park: 1; + }; + uint32_t val; +} cp_dma_in_link_reg_t; + +/** Type of dma_conf register + * Copy DMA configuration register + */ +typedef union { + struct { + /** dma_in_rst : R/W; bitpos: [0]; default: 0; + * Set this bit to reset in_inf state machine. + */ + uint32_t dma_in_rst: 1; + /** dma_out_rst : R/W; bitpos: [1]; default: 0; + * Set this bit to reset out_inf state machine. + */ + uint32_t dma_out_rst: 1; + /** dma_cmdfifo_rst : R/W; bitpos: [2]; default: 0; + * Set this bit to reset in_cmd fifo and out_cmd fifo. + */ + uint32_t dma_cmdfifo_rst: 1; + /** dma_fifo_rst : R/W; bitpos: [3]; default: 0; + * Set this bit to reset data in receive FIFO. + */ + uint32_t dma_fifo_rst: 1; + /** dma_out_owner : R/W; bitpos: [4]; default: 0; + * This is used to configure the owner bit in OUT descriptor. This is effective only + * when you set reg_out_auto_wrback. + */ + uint32_t dma_out_owner: 1; + /** dma_in_owner : R/W; bitpos: [5]; default: 0; + * This is used to configure the owner bit in IN descriptor. + */ + uint32_t dma_in_owner: 1; + /** dma_out_auto_wrback : R/W; bitpos: [6]; default: 0; + * This bit is used to write back out descriptor when hardware has already used this + * descriptor. + */ + uint32_t dma_out_auto_wrback: 1; + /** dma_check_owner : R/W; bitpos: [7]; default: 0; + * Set this bit to enable owner bit check in descriptor. + */ + uint32_t dma_check_owner: 1; + /** dma_crc_cal_reset : R/W; bitpos: [8]; default: 0; + * Set this bit to reset crc calculation. + */ + uint32_t dma_crc_cal_reset: 1; + /** dma_crc_cal_en : R/W; bitpos: [9]; default: 0; + * Set this bit enable crc calculation function. + */ + uint32_t dma_crc_cal_en: 1; + /** dma_crc_big_endian_en : R/W; bitpos: [10]; default: 0; + * Set this bit to reorder the bit of data which will be send to excute crc. + */ + uint32_t dma_crc_big_endian_en: 1; + /** dma_crc_out_reverse_en : R/W; bitpos: [11]; default: 0; + * Set this bit to reverse the crc calculation result. + */ + uint32_t dma_crc_out_reverse_en: 1; + uint32_t reserved_12: 19; + /** dma_clk_en : R/W; bitpos: [31]; default: 0; + * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes + * registers. + */ + uint32_t dma_clk_en: 1; + }; + uint32_t val; +} cp_dma_conf_reg_t; + + +/** Status Registers */ +/** Type of dma_out_eof_des_addr register + * Outlink descriptor address when EOF occurs + */ +typedef union { + struct { + /** dma_out_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t dma_out_eof_des_addr: 32; + }; + uint32_t val; +} cp_dma_out_eof_des_addr_reg_t; + +/** Type of dma_in_eof_des_addr register + * Inlink descriptor address when EOF occurs + */ +typedef union { + struct { + /** dma_in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when received successful + * EOF. + */ + uint32_t dma_in_suc_eof_des_addr: 32; + }; + uint32_t val; +} cp_dma_in_eof_des_addr_reg_t; + +/** Type of dma_out_eof_bfr_des_addr register + * Outlink descriptor address before the last outlink descriptor + */ +typedef union { + struct { + /** dma_out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the last outlink + * descriptor. + */ + uint32_t dma_out_eof_bfr_des_addr: 32; + }; + uint32_t val; +} cp_dma_out_eof_bfr_des_addr_reg_t; + +/** Type of dma_inlink_dscr register + * Address of current inlink descriptor + */ +typedef union { + struct { + /** dma_inlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + uint32_t dma_inlink_dscr: 32; + }; + uint32_t val; +} cp_dma_inlink_dscr_reg_t; + +/** Type of dma_inlink_dscr_bf0 register + * Address of last inlink descriptor + */ +typedef union { + struct { + /** dma_inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + uint32_t dma_inlink_dscr_bf0: 32; + }; + uint32_t val; +} cp_dma_inlink_dscr_bf0_reg_t; + +/** Type of dma_inlink_dscr_bf1 register + * Address of the second-to-last inlink descriptor + */ +typedef union { + struct { + /** dma_inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + uint32_t dma_inlink_dscr_bf1: 32; + }; + uint32_t val; +} cp_dma_inlink_dscr_bf1_reg_t; + +/** Type of dma_outlink_dscr register + * Address of current outlink descriptor + */ +typedef union { + struct { + /** dma_outlink_dscr : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + uint32_t dma_outlink_dscr: 32; + }; + uint32_t val; +} cp_dma_outlink_dscr_reg_t; + +/** Type of dma_outlink_dscr_bf0 register + * Address of last outlink descriptor + */ +typedef union { + struct { + /** dma_outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + uint32_t dma_outlink_dscr_bf0: 32; + }; + uint32_t val; +} cp_dma_outlink_dscr_bf0_reg_t; + +/** Type of dma_outlink_dscr_bf1 register + * Address of the second-to-last outlink descriptor + */ +typedef union { + struct { + /** dma_outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last outlink descriptor y-2. + */ + uint32_t dma_outlink_dscr_bf1: 32; + }; + uint32_t val; +} cp_dma_outlink_dscr_bf1_reg_t; + +/** Type of dma_in_st register + * Status register of receiving data + */ +typedef union { + struct { + /** dma_inlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + uint32_t dma_inlink_dscr_addr: 18; + /** dma_in_dscr_state : RO; bitpos: [19:18]; default: 0; + * Reserved. + */ + uint32_t dma_in_dscr_state: 2; + /** dma_in_state : RO; bitpos: [22:20]; default: 0; + * Reserved. + */ + uint32_t dma_in_state: 3; + /** dma_fifo_empty : RO; bitpos: [23]; default: 0; + * Copy DMA FIFO empty signal. + */ + uint32_t dma_fifo_empty: 1; + }; + uint32_t val; +} cp_dma_in_st_reg_t; + +/** Type of dma_out_st register + * Status register of transmitting data + */ +typedef union { + struct { + /** dma_outlink_dscr_addr : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + uint32_t dma_outlink_dscr_addr: 18; + /** dma_out_dscr_state : RO; bitpos: [19:18]; default: 0; + * Reserved. + */ + uint32_t dma_out_dscr_state: 2; + /** dma_out_state : RO; bitpos: [22:20]; default: 0; + * Reserved. + */ + uint32_t dma_out_state: 3; + /** dma_fifo_full : RO; bitpos: [23]; default: 0; + * Copy DMA FIFO full signal. + */ + uint32_t dma_fifo_full: 1; + }; + uint32_t val; +} cp_dma_out_st_reg_t; + +/** Type of dma_crc_out register + * CRC result register + */ +typedef union { + struct { + /** dma_crc_result : RO; bitpos: [31:0]; default: 0; + * This register stores the result of CRC. + */ + uint32_t dma_crc_result: 32; + }; + uint32_t val; +} cp_dma_crc_out_reg_t; + +/** Type of dma_date register + * Copy DMA version register + */ +typedef union { + struct { + /** dma_dma_date : R/W; bitpos: [31:0]; default: 403185664; + * This is the version register. + */ + uint32_t dma_dma_date: 32; + }; + uint32_t val; +} cp_dma_date_reg_t; + + +typedef struct { + volatile cp_dma_int_raw_reg_t dma_int_raw; + volatile cp_dma_int_st_reg_t dma_int_st; + volatile cp_dma_int_ena_reg_t dma_int_ena; + volatile cp_dma_int_clr_reg_t dma_int_clr; + volatile cp_dma_out_link_reg_t dma_out_link; + volatile cp_dma_in_link_reg_t dma_in_link; + volatile cp_dma_out_eof_des_addr_reg_t dma_out_eof_des_addr; + volatile cp_dma_in_eof_des_addr_reg_t dma_in_eof_des_addr; + volatile cp_dma_out_eof_bfr_des_addr_reg_t dma_out_eof_bfr_des_addr; + volatile cp_dma_inlink_dscr_reg_t dma_inlink_dscr; + volatile cp_dma_inlink_dscr_bf0_reg_t dma_inlink_dscr_bf0; + volatile cp_dma_inlink_dscr_bf1_reg_t dma_inlink_dscr_bf1; + volatile cp_dma_outlink_dscr_reg_t dma_outlink_dscr; + volatile cp_dma_outlink_dscr_bf0_reg_t dma_outlink_dscr_bf0; + volatile cp_dma_outlink_dscr_bf1_reg_t dma_outlink_dscr_bf1; + volatile cp_dma_conf_reg_t dma_conf; + volatile cp_dma_in_st_reg_t dma_in_st; + volatile cp_dma_out_st_reg_t dma_out_st; + volatile cp_dma_crc_out_reg_t dma_crc_out; + uint32_t reserved_04c; + uint32_t reserved_050; + uint32_t reserved_054; + uint32_t reserved_058; + uint32_t reserved_05c; + uint32_t reserved_060; + uint32_t reserved_064; + uint32_t reserved_068; + uint32_t reserved_06c; + uint32_t reserved_070; + uint32_t reserved_074; + uint32_t reserved_078; + uint32_t reserved_07c; + uint32_t reserved_080; + uint32_t reserved_084; + uint32_t reserved_088; + uint32_t reserved_08c; + uint32_t reserved_090; + uint32_t reserved_094; + uint32_t reserved_098; + uint32_t reserved_09c; + uint32_t reserved_0a0; + uint32_t reserved_0a4; + uint32_t reserved_0a8; + uint32_t reserved_0ac; + uint32_t reserved_0b0; + uint32_t reserved_0b4; + uint32_t reserved_0b8; + uint32_t reserved_0bc; + uint32_t reserved_0c0; + uint32_t reserved_0c4; + uint32_t reserved_0c8; + uint32_t reserved_0cc; + uint32_t reserved_0d0; + uint32_t reserved_0d4; + uint32_t reserved_0d8; + uint32_t reserved_0dc; + uint32_t reserved_0e0; + uint32_t reserved_0e4; + uint32_t reserved_0e8; + uint32_t reserved_0ec; + uint32_t reserved_0f0; + uint32_t reserved_0f4; + uint32_t reserved_0f8; + volatile cp_dma_date_reg_t dma_date; +} cp_dma_dev_t; + +_Static_assert(sizeof(cp_dma_dev_t) == 0x100, "cp_dma_dev_t should occupy 0x100 bytes in memory"); + +extern cp_dma_dev_t CP_DMA; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_caps.h index 8039602a..9fa5936a 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_caps.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_caps.h @@ -40,6 +40,9 @@ extern "C" { #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */ #define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */ +#define GPIO_MATRIX_CONST_ONE_INPUT (0x38) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C) + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sig_map.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sig_map.h index 8247a422..5b7e9e8c 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sig_map.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/gpio_sig_map.h @@ -188,10 +188,10 @@ #define FSPICS3_OUT_IDX 120 #define FSPICS4_OUT_IDX 121 #define FSPICS5_OUT_IDX 122 -#define CAN_RX_IDX 123 -#define CAN_TX_IDX 123 -#define CAN_BUS_OFF_ON_IDX 124 -#define CAN_CLKOUT_IDX 125 +#define TWAI_RX_IDX 123 +#define TWAI_TX_IDX 123 +#define TWAI_BUS_OFF_ON_IDX 124 +#define TWAI_CLKOUT_IDX 125 #define SUBSPICLK_OUT_MUX_IDX 126 #define SUBSPIQ_IN_IDX 127 #define SUBSPIQ_OUT_IDX 127 diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_reg.h deleted file mode 100644 index aad35786..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_reg.h +++ /dev/null @@ -1,248 +0,0 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_HINF_REG_H_ -#define _SOC_HINF_REG_H_ - - -#include "soc.h" -#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) -/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */ -/*description: */ -#define HINF_DEVICE_ID_FN1 0x0000FFFF -#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S)) -#define HINF_DEVICE_ID_FN1_V 0xFFFF -#define HINF_DEVICE_ID_FN1_S 16 -/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */ -/*description: */ -#define HINF_USER_ID_FN1 0x0000FFFF -#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S)) -#define HINF_USER_ID_FN1_V 0xFFFF -#define HINF_USER_ID_FN1_S 0 - -#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) -/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */ -/*description: */ -#define HINF_SDIO20_CONF1 0x00000007 -#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S)) -#define HINF_SDIO20_CONF1_V 0x7 -#define HINF_SDIO20_CONF1_S 29 -/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define HINF_FUNC2_EPS (BIT(28)) -#define HINF_FUNC2_EPS_M (BIT(28)) -#define HINF_FUNC2_EPS_V 0x1 -#define HINF_FUNC2_EPS_S 28 -/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */ -/*description: */ -#define HINF_SDIO_VER 0x00000FFF -#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S)) -#define HINF_SDIO_VER_V 0xFFF -#define HINF_SDIO_VER_S 16 -/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */ -/*description: */ -#define HINF_SDIO20_CONF0 0x0000000F -#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S)) -#define HINF_SDIO20_CONF0_V 0xF -#define HINF_SDIO20_CONF0_S 12 -/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HINF_IOENABLE1 (BIT(11)) -#define HINF_IOENABLE1_M (BIT(11)) -#define HINF_IOENABLE1_V 0x1 -#define HINF_IOENABLE1_S 11 -/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HINF_EMP (BIT(10)) -#define HINF_EMP_M (BIT(10)) -#define HINF_EMP_V 0x1 -#define HINF_EMP_S 10 -/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HINF_FUNC1_EPS (BIT(9)) -#define HINF_FUNC1_EPS_M (BIT(9)) -#define HINF_FUNC1_EPS_V 0x1 -#define HINF_FUNC1_EPS_S 9 -/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HINF_CD_DISABLE (BIT(8)) -#define HINF_CD_DISABLE_M (BIT(8)) -#define HINF_CD_DISABLE_V 0x1 -#define HINF_CD_DISABLE_S 8 -/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HINF_IOENABLE2 (BIT(7)) -#define HINF_IOENABLE2_M (BIT(7)) -#define HINF_IOENABLE2_V 0x1 -#define HINF_IOENABLE2_S 7 -/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HINF_SDIO_INT_MASK (BIT(6)) -#define HINF_SDIO_INT_MASK_M (BIT(6)) -#define HINF_SDIO_INT_MASK_V 0x1 -#define HINF_SDIO_INT_MASK_S 6 -/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HINF_SDIO_IOREADY2 (BIT(5)) -#define HINF_SDIO_IOREADY2_M (BIT(5)) -#define HINF_SDIO_IOREADY2_V 0x1 -#define HINF_SDIO_IOREADY2_S 5 -/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define HINF_SDIO_CD_ENABLE (BIT(4)) -#define HINF_SDIO_CD_ENABLE_M (BIT(4)) -#define HINF_SDIO_CD_ENABLE_V 0x1 -#define HINF_SDIO_CD_ENABLE_S 4 -/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HINF_HIGHSPEED_MODE (BIT(3)) -#define HINF_HIGHSPEED_MODE_M (BIT(3)) -#define HINF_HIGHSPEED_MODE_V 0x1 -#define HINF_HIGHSPEED_MODE_S 3 -/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HINF_HIGHSPEED_ENABLE (BIT(2)) -#define HINF_HIGHSPEED_ENABLE_M (BIT(2)) -#define HINF_HIGHSPEED_ENABLE_V 0x1 -#define HINF_HIGHSPEED_ENABLE_S 2 -/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HINF_SDIO_IOREADY1 (BIT(1)) -#define HINF_SDIO_IOREADY1_M (BIT(1)) -#define HINF_SDIO_IOREADY1_V 0x1 -#define HINF_SDIO_IOREADY1_S 1 -/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define HINF_SDIO_ENABLE (BIT(0)) -#define HINF_SDIO_ENABLE_M (BIT(0)) -#define HINF_SDIO_ENABLE_V 0x1 -#define HINF_SDIO_ENABLE_S 0 - -#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C) -/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */ -/*description: */ -#define HINF_SDIO_IOREADY0 (BIT(17)) -#define HINF_SDIO_IOREADY0_M (BIT(17)) -#define HINF_SDIO_IOREADY0_V 0x1 -#define HINF_SDIO_IOREADY0_S 17 -/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HINF_SDIO_RST (BIT(16)) -#define HINF_SDIO_RST_M (BIT(16)) -#define HINF_SDIO_RST_V 0x1 -#define HINF_SDIO_RST_S 16 -/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ -/*description: */ -#define HINF_CHIP_STATE 0x000000FF -#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S)) -#define HINF_CHIP_STATE_V 0xFF -#define HINF_CHIP_STATE_S 8 -/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: */ -#define HINF_PIN_STATE 0x000000FF -#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S)) -#define HINF_PIN_STATE_V 0xFF -#define HINF_PIN_STATE_S 0 - -#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20) -/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W0 0xFFFFFFFF -#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S)) -#define HINF_CIS_CONF_W0_V 0xFFFFFFFF -#define HINF_CIS_CONF_W0_S 0 - -#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24) -/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W1 0xFFFFFFFF -#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S)) -#define HINF_CIS_CONF_W1_V 0xFFFFFFFF -#define HINF_CIS_CONF_W1_S 0 - -#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28) -/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W2 0xFFFFFFFF -#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S)) -#define HINF_CIS_CONF_W2_V 0xFFFFFFFF -#define HINF_CIS_CONF_W2_S 0 - -#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C) -/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W3 0xFFFFFFFF -#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S)) -#define HINF_CIS_CONF_W3_V 0xFFFFFFFF -#define HINF_CIS_CONF_W3_S 0 - -#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30) -/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W4 0xFFFFFFFF -#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S)) -#define HINF_CIS_CONF_W4_V 0xFFFFFFFF -#define HINF_CIS_CONF_W4_S 0 - -#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34) -/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W5 0xFFFFFFFF -#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S)) -#define HINF_CIS_CONF_W5_V 0xFFFFFFFF -#define HINF_CIS_CONF_W5_S 0 - -#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38) -/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W6 0xFFFFFFFF -#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S)) -#define HINF_CIS_CONF_W6_V 0xFFFFFFFF -#define HINF_CIS_CONF_W6_S 0 - -#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C) -/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: */ -#define HINF_CIS_CONF_W7 0xFFFFFFFF -#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S)) -#define HINF_CIS_CONF_W7_V 0xFFFFFFFF -#define HINF_CIS_CONF_W7_S 0 - -#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) -/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */ -/*description: */ -#define HINF_DEVICE_ID_FN2 0x0000FFFF -#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S)) -#define HINF_DEVICE_ID_FN2_V 0xFFFF -#define HINF_DEVICE_ID_FN2_S 16 -/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */ -/*description: */ -#define HINF_USER_ID_FN2 0x0000FFFF -#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S)) -#define HINF_USER_ID_FN2_V 0xFFFF -#define HINF_USER_ID_FN2_S 0 - -#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC) -/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */ -/*description: */ -#define HINF_SDIO_DATE 0xFFFFFFFF -#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S)) -#define HINF_SDIO_DATE_V 0xFFFFFFFF -#define HINF_SDIO_DATE_S 0 - - - - -#endif /*_SOC_HINF_REG_H_ */ - - diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_struct.h deleted file mode 100644 index 1c2d9e3b..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/hinf_struct.h +++ /dev/null @@ -1,134 +0,0 @@ -// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_HINF_STRUCT_H_ -#define _SOC_HINF_STRUCT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t user_id_fn1: 16; - uint32_t device_id_fn1:16; - }; - uint32_t val; - } cfg_data0; - union { - struct { - uint32_t sdio_enable: 1; - uint32_t sdio_ioready1: 1; - uint32_t highspeed_enable: 1; - uint32_t highspeed_mode: 1; - uint32_t sdio_cd_enable: 1; - uint32_t sdio_ioready2: 1; - uint32_t sdio_int_mask: 1; - uint32_t ioenable2: 1; - uint32_t cd_disable: 1; - uint32_t func1_eps: 1; - uint32_t emp: 1; - uint32_t ioenable1: 1; - uint32_t sdio20_conf0: 4; - uint32_t sdio_ver: 12; - uint32_t func2_eps: 1; - uint32_t sdio20_conf1: 3; - }; - uint32_t val; - } cfg_data1; - uint32_t reserved_8; - uint32_t reserved_c; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - union { - struct { - uint32_t pin_state: 8; - uint32_t chip_state: 8; - uint32_t sdio_rst: 1; - uint32_t sdio_ioready0: 1; - uint32_t reserved18: 14; - }; - uint32_t val; - } cfg_data7; - uint32_t cis_conf0; /**/ - uint32_t cis_conf1; /**/ - uint32_t cis_conf2; /**/ - uint32_t cis_conf3; /**/ - uint32_t cis_conf4; /**/ - uint32_t cis_conf5; /**/ - uint32_t cis_conf6; /**/ - uint32_t cis_conf7; /**/ - union { - struct { - uint32_t user_id_fn2: 16; - uint32_t device_id_fn2:16; - }; - uint32_t val; - } cfg_data16; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t date; /**/ -} hinf_dev_t; -extern hinf_dev_t HINF; - -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_HINF_STRUCT_H_ */ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_reg.h deleted file mode 100644 index 37aa6214..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_reg.h +++ /dev/null @@ -1,1806 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_HOST_REG_H_ -#define _SOC_HOST_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20) -/* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: */ -#define HOST_SLC_FUNC1_MDSTAT (BIT(0)) -#define HOST_SLC_FUNC1_MDSTAT_M (BIT(0)) -#define HOST_SLC_FUNC1_MDSTAT_V 0x1 -#define HOST_SLC_FUNC1_MDSTAT_S 0 - -#define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34) -/* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT0 0xFFFFFFFF -#define HOST_GPIO_SDIO_INT0_M ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S)) -#define HOST_GPIO_SDIO_INT0_V 0xFFFFFFFF -#define HOST_GPIO_SDIO_INT0_S 0 - -#define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38) -/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT1 0x003FFFFF -#define HOST_GPIO_SDIO_INT1_M ((HOST_GPIO_SDIO_INT1_V)<<(HOST_GPIO_SDIO_INT1_S)) -#define HOST_GPIO_SDIO_INT1_V 0x3FFFFF -#define HOST_GPIO_SDIO_INT1_S 0 - -#define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C) -/* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_IN0 0xFFFFFFFF -#define HOST_GPIO_SDIO_IN0_M ((HOST_GPIO_SDIO_IN0_V)<<(HOST_GPIO_SDIO_IN0_S)) -#define HOST_GPIO_SDIO_IN0_V 0xFFFFFFFF -#define HOST_GPIO_SDIO_IN0_S 0 - -#define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40) -/* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_IN1 0x003FFFFF -#define HOST_GPIO_SDIO_IN1_M ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S)) -#define HOST_GPIO_SDIO_IN1_V 0x3FFFFF -#define HOST_GPIO_SDIO_IN1_S 0 - -#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44) -/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_EOF 0x0000000F -#define HOST_SLC0_RX_PF_EOF_M ((HOST_SLC0_RX_PF_EOF_V)<<(HOST_SLC0_RX_PF_EOF_S)) -#define HOST_SLC0_RX_PF_EOF_V 0xF -#define HOST_SLC0_RX_PF_EOF_S 28 -/* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_TOKEN1 0x00000FFF -#define HOST_HOSTSLC0_TOKEN1_M ((HOST_HOSTSLC0_TOKEN1_V)<<(HOST_HOSTSLC0_TOKEN1_S)) -#define HOST_HOSTSLC0_TOKEN1_V 0xFFF -#define HOST_HOSTSLC0_TOKEN1_S 16 -/* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_VALID (BIT(12)) -#define HOST_SLC0_RX_PF_VALID_M (BIT(12)) -#define HOST_SLC0_RX_PF_VALID_V 0x1 -#define HOST_SLC0_RX_PF_VALID_S 12 -/* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0 0x00000FFF -#define HOST_SLC0_TOKEN0_M ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S)) -#define HOST_SLC0_TOKEN0_V 0xFFF -#define HOST_SLC0_TOKEN0_S 0 - -#define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48) -/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define HOST_SLC0_PF_DATA 0xFFFFFFFF -#define HOST_SLC0_PF_DATA_M ((HOST_SLC0_PF_DATA_V)<<(HOST_SLC0_PF_DATA_S)) -#define HOST_SLC0_PF_DATA_V 0xFFFFFFFF -#define HOST_SLC0_PF_DATA_S 0 - -#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50) -/* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT_RAW (BIT(25)) -#define HOST_GPIO_SDIO_INT_RAW_M (BIT(25)) -#define HOST_GPIO_SDIO_INT_RAW_V 0x1 -#define HOST_GPIO_SDIO_INT_RAW_S 25 -/* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x1 -#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 -/* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x1 -#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 -/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_RAW_M (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_RAW_V 0x1 -#define HOST_SLC0_EXT_BIT3_INT_RAW_S 22 -/* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_RAW_M (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_RAW_V 0x1 -#define HOST_SLC0_EXT_BIT2_INT_RAW_S 21 -/* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_RAW_M (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_RAW_V 0x1 -#define HOST_SLC0_EXT_BIT1_INT_RAW_S 20 -/* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_RAW_M (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_RAW_V 0x1 -#define HOST_SLC0_EXT_BIT0_INT_RAW_S 19 -/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_RAW_M (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_RAW_V 0x1 -#define HOST_SLC0_RX_PF_VALID_INT_RAW_S 18 -/* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TX_OVF_INT_RAW (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_RAW_M (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_RAW_V 0x1 -#define HOST_SLC0_TX_OVF_INT_RAW_S 17 -/* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_UDF_INT_RAW (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_RAW_M (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_RAW_V 0x1 -#define HOST_SLC0_RX_UDF_INT_RAW_S 16 -/* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_RAW_M (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_RAW_V 0x1 -#define HOST_SLC0HOST_TX_START_INT_RAW_S 15 -/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_RAW_M (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_RAW_V 0x1 -#define HOST_SLC0HOST_RX_START_INT_RAW_S 14 -/* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_RAW_M (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_RAW_V 0x1 -#define HOST_SLC0HOST_RX_EOF_INT_RAW_S 13 -/* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_RAW_M (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_RAW_V 0x1 -#define HOST_SLC0HOST_RX_SOF_INT_RAW_S 12 -/* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x1 -#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 -/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x1 -#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 -/* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1 -#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 -/* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1 -#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 -/* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 -/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 -/* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 -/* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 -/* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 -/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 -/* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 -/* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x1 -#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 - -#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58) -/* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT_ST (BIT(25)) -#define HOST_GPIO_SDIO_INT_ST_M (BIT(25)) -#define HOST_GPIO_SDIO_INT_ST_V 0x1 -#define HOST_GPIO_SDIO_INT_ST_S 25 -/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x1 -#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 -/* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x1 -#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 -/* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_ST_M (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_ST_V 0x1 -#define HOST_SLC0_EXT_BIT3_INT_ST_S 22 -/* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_ST_M (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_ST_V 0x1 -#define HOST_SLC0_EXT_BIT2_INT_ST_S 21 -/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_ST_M (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_ST_V 0x1 -#define HOST_SLC0_EXT_BIT1_INT_ST_S 20 -/* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_ST_M (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_ST_V 0x1 -#define HOST_SLC0_EXT_BIT0_INT_ST_S 19 -/* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_ST_M (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_ST_V 0x1 -#define HOST_SLC0_RX_PF_VALID_INT_ST_S 18 -/* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TX_OVF_INT_ST (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_ST_M (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_ST_V 0x1 -#define HOST_SLC0_TX_OVF_INT_ST_S 17 -/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_UDF_INT_ST (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_ST_M (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_ST_V 0x1 -#define HOST_SLC0_RX_UDF_INT_ST_S 16 -/* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TX_START_INT_ST (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_ST_M (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_ST_V 0x1 -#define HOST_SLC0HOST_TX_START_INT_ST_S 15 -/* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_START_INT_ST (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_ST_M (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_ST_V 0x1 -#define HOST_SLC0HOST_RX_START_INT_ST_S 14 -/* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_ST_M (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_ST_V 0x1 -#define HOST_SLC0HOST_RX_EOF_INT_ST_S 13 -/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_ST_M (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_ST_V 0x1 -#define HOST_SLC0HOST_RX_SOF_INT_ST_S 12 -/* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x1 -#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 -/* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x1 -#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 -/* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x1 -#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 -/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x1 -#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 -/* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_ST_M (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT7_INT_ST_S 7 -/* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_ST_M (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT6_INT_ST_S 6 -/* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_ST_M (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT5_INT_ST_S 5 -/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_ST_M (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT4_INT_ST_S 4 -/* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_ST_M (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT3_INT_ST_S 3 -/* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_ST_M (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT2_INT_ST_S 2 -/* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_ST_M (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT1_INT_ST_S 1 -/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_ST_M (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_ST_V 0x1 -#define HOST_SLC0_TOHOST_BIT0_INT_ST_S 0 - -#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60) -/* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN_CHECK 0x00000FFF -#define HOST_HOSTSLC0_LEN_CHECK_M ((HOST_HOSTSLC0_LEN_CHECK_V)<<(HOST_HOSTSLC0_LEN_CHECK_S)) -#define HOST_HOSTSLC0_LEN_CHECK_V 0xFFF -#define HOST_HOSTSLC0_LEN_CHECK_S 20 -/* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN 0x000FFFFF -#define HOST_HOSTSLC0_LEN_M ((HOST_HOSTSLC0_LEN_V)<<(HOST_HOSTSLC0_LEN_S)) -#define HOST_HOSTSLC0_LEN_V 0xFFFFF -#define HOST_HOSTSLC0_LEN_S 0 - -#define HOST_SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64) -/* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE3 0x000000FF -#define HOST_SLCHOST_STATE3_M ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S)) -#define HOST_SLCHOST_STATE3_V 0xFF -#define HOST_SLCHOST_STATE3_S 24 -/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE2 0x000000FF -#define HOST_SLCHOST_STATE2_M ((HOST_SLCHOST_STATE2_V)<<(HOST_SLCHOST_STATE2_S)) -#define HOST_SLCHOST_STATE2_V 0xFF -#define HOST_SLCHOST_STATE2_S 16 -/* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE1 0x000000FF -#define HOST_SLCHOST_STATE1_M ((HOST_SLCHOST_STATE1_V)<<(HOST_SLCHOST_STATE1_S)) -#define HOST_SLCHOST_STATE1_V 0xFF -#define HOST_SLCHOST_STATE1_S 8 -/* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE0 0x000000FF -#define HOST_SLCHOST_STATE0_M ((HOST_SLCHOST_STATE0_V)<<(HOST_SLCHOST_STATE0_S)) -#define HOST_SLCHOST_STATE0_V 0xFF -#define HOST_SLCHOST_STATE0_S 0 - -#define HOST_SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68) -/* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE7 0x000000FF -#define HOST_SLCHOST_STATE7_M ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S)) -#define HOST_SLCHOST_STATE7_V 0xFF -#define HOST_SLCHOST_STATE7_S 24 -/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE6 0x000000FF -#define HOST_SLCHOST_STATE6_M ((HOST_SLCHOST_STATE6_V)<<(HOST_SLCHOST_STATE6_S)) -#define HOST_SLCHOST_STATE6_V 0xFF -#define HOST_SLCHOST_STATE6_S 16 -/* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE5 0x000000FF -#define HOST_SLCHOST_STATE5_M ((HOST_SLCHOST_STATE5_V)<<(HOST_SLCHOST_STATE5_S)) -#define HOST_SLCHOST_STATE5_V 0xFF -#define HOST_SLCHOST_STATE5_S 8 -/* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_STATE4 0x000000FF -#define HOST_SLCHOST_STATE4_M ((HOST_SLCHOST_STATE4_V)<<(HOST_SLCHOST_STATE4_S)) -#define HOST_SLCHOST_STATE4_V 0xFF -#define HOST_SLCHOST_STATE4_S 0 - -#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0)) - -#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C) -/* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF3 0x000000FF -#define HOST_SLCHOST_CONF3_M ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S)) -#define HOST_SLCHOST_CONF3_V 0xFF -#define HOST_SLCHOST_CONF3_S 24 -/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF2 0x000000FF -#define HOST_SLCHOST_CONF2_M ((HOST_SLCHOST_CONF2_V)<<(HOST_SLCHOST_CONF2_S)) -#define HOST_SLCHOST_CONF2_V 0xFF -#define HOST_SLCHOST_CONF2_S 16 -/* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF1 0x000000FF -#define HOST_SLCHOST_CONF1_M ((HOST_SLCHOST_CONF1_V)<<(HOST_SLCHOST_CONF1_S)) -#define HOST_SLCHOST_CONF1_V 0xFF -#define HOST_SLCHOST_CONF1_S 8 -/* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF0 0x000000FF -#define HOST_SLCHOST_CONF0_M ((HOST_SLCHOST_CONF0_V)<<(HOST_SLCHOST_CONF0_S)) -#define HOST_SLCHOST_CONF0_V 0xFF -#define HOST_SLCHOST_CONF0_S 0 - -#define HOST_SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70) -/* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF7 0x000000FF -#define HOST_SLCHOST_CONF7_M ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S)) -#define HOST_SLCHOST_CONF7_V 0xFF -#define HOST_SLCHOST_CONF7_S 24 -/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF6 0x000000FF -#define HOST_SLCHOST_CONF6_M ((HOST_SLCHOST_CONF6_V)<<(HOST_SLCHOST_CONF6_S)) -#define HOST_SLCHOST_CONF6_V 0xFF -#define HOST_SLCHOST_CONF6_S 16 -/* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF5 0x000000FF -#define HOST_SLCHOST_CONF5_M ((HOST_SLCHOST_CONF5_V)<<(HOST_SLCHOST_CONF5_S)) -#define HOST_SLCHOST_CONF5_V 0xFF -#define HOST_SLCHOST_CONF5_S 8 -/* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF4 0x000000FF -#define HOST_SLCHOST_CONF4_M ((HOST_SLCHOST_CONF4_V)<<(HOST_SLCHOST_CONF4_S)) -#define HOST_SLCHOST_CONF4_V 0xFF -#define HOST_SLCHOST_CONF4_S 0 - -#define HOST_SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74) -/* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF11 0x000000FF -#define HOST_SLCHOST_CONF11_M ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S)) -#define HOST_SLCHOST_CONF11_V 0xFF -#define HOST_SLCHOST_CONF11_S 24 -/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF10 0x000000FF -#define HOST_SLCHOST_CONF10_M ((HOST_SLCHOST_CONF10_V)<<(HOST_SLCHOST_CONF10_S)) -#define HOST_SLCHOST_CONF10_V 0xFF -#define HOST_SLCHOST_CONF10_S 16 -/* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF9 0x000000FF -#define HOST_SLCHOST_CONF9_M ((HOST_SLCHOST_CONF9_V)<<(HOST_SLCHOST_CONF9_S)) -#define HOST_SLCHOST_CONF9_V 0xFF -#define HOST_SLCHOST_CONF9_S 8 -/* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF8 0x000000FF -#define HOST_SLCHOST_CONF8_M ((HOST_SLCHOST_CONF8_V)<<(HOST_SLCHOST_CONF8_S)) -#define HOST_SLCHOST_CONF8_V 0xFF -#define HOST_SLCHOST_CONF8_S 0 - -#define HOST_SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78) -/* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF15 0x000000FF -#define HOST_SLCHOST_CONF15_M ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S)) -#define HOST_SLCHOST_CONF15_V 0xFF -#define HOST_SLCHOST_CONF15_S 24 -/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF14 0x000000FF -#define HOST_SLCHOST_CONF14_M ((HOST_SLCHOST_CONF14_V)<<(HOST_SLCHOST_CONF14_S)) -#define HOST_SLCHOST_CONF14_V 0xFF -#define HOST_SLCHOST_CONF14_S 16 -/* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF13 0x000000FF -#define HOST_SLCHOST_CONF13_M ((HOST_SLCHOST_CONF13_V)<<(HOST_SLCHOST_CONF13_S)) -#define HOST_SLCHOST_CONF13_V 0xFF -#define HOST_SLCHOST_CONF13_S 8 -/* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF12 0x000000FF -#define HOST_SLCHOST_CONF12_M ((HOST_SLCHOST_CONF12_V)<<(HOST_SLCHOST_CONF12_S)) -#define HOST_SLCHOST_CONF12_V 0xFF -#define HOST_SLCHOST_CONF12_S 0 - -#define HOST_SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7C) -/* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: Interrupt to target CPU*/ -#define HOST_SLCHOST_CONF19 0x000000FF -#define HOST_SLCHOST_CONF19_M ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S)) -#define HOST_SLCHOST_CONF19_V 0xFF -#define HOST_SLCHOST_CONF19_S 24 -/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF18 0x000000FF -#define HOST_SLCHOST_CONF18_M ((HOST_SLCHOST_CONF18_V)<<(HOST_SLCHOST_CONF18_S)) -#define HOST_SLCHOST_CONF18_V 0xFF -#define HOST_SLCHOST_CONF18_S 16 -/* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: SLC timeout enable*/ -#define HOST_SLCHOST_CONF17 0x000000FF -#define HOST_SLCHOST_CONF17_M ((HOST_SLCHOST_CONF17_V)<<(HOST_SLCHOST_CONF17_S)) -#define HOST_SLCHOST_CONF17_V 0xFF -#define HOST_SLCHOST_CONF17_S 8 -/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */ -/*description: SLC timeout value*/ -#define HOST_SLCHOST_CONF16 0x000000FF -#define HOST_SLCHOST_CONF16_M ((HOST_SLCHOST_CONF16_V)<<(HOST_SLCHOST_CONF16_S)) -#define HOST_SLCHOST_CONF16_V 0xFF -#define HOST_SLCHOST_CONF16_S 0 - -#define HOST_SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80) -/* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF23 0x000000FF -#define HOST_SLCHOST_CONF23_M ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S)) -#define HOST_SLCHOST_CONF23_V 0xFF -#define HOST_SLCHOST_CONF23_S 24 -/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF22 0x000000FF -#define HOST_SLCHOST_CONF22_M ((HOST_SLCHOST_CONF22_V)<<(HOST_SLCHOST_CONF22_S)) -#define HOST_SLCHOST_CONF22_V 0xFF -#define HOST_SLCHOST_CONF22_S 16 -/* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF21 0x000000FF -#define HOST_SLCHOST_CONF21_M ((HOST_SLCHOST_CONF21_V)<<(HOST_SLCHOST_CONF21_S)) -#define HOST_SLCHOST_CONF21_V 0xFF -#define HOST_SLCHOST_CONF21_S 8 -/* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF20 0x000000FF -#define HOST_SLCHOST_CONF20_M ((HOST_SLCHOST_CONF20_V)<<(HOST_SLCHOST_CONF20_S)) -#define HOST_SLCHOST_CONF20_V 0xFF -#define HOST_SLCHOST_CONF20_S 0 - -#define HOST_SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84) -/* HOST_SLCHOST_WIN_CMD : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: */ -#define HOST_SLCHOST_WIN_CMD 0x0000FFFF -#define HOST_SLCHOST_WIN_CMD_M ((HOST_SLCHOST_WIN_CMD_V)<<(HOST_SLCHOST_WIN_CMD_S)) -#define HOST_SLCHOST_WIN_CMD_V 0xFFFF -#define HOST_SLCHOST_WIN_CMD_S 0 - -#define HOST_SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88) -/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF27 0x000000FF -#define HOST_SLCHOST_CONF27_M ((HOST_SLCHOST_CONF27_V)<<(HOST_SLCHOST_CONF27_S)) -#define HOST_SLCHOST_CONF27_V 0xFF -#define HOST_SLCHOST_CONF27_S 24 -/* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF26 0x000000FF -#define HOST_SLCHOST_CONF26_M ((HOST_SLCHOST_CONF26_V)<<(HOST_SLCHOST_CONF26_S)) -#define HOST_SLCHOST_CONF26_V 0xFF -#define HOST_SLCHOST_CONF26_S 16 -/* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF25 0x000000FF -#define HOST_SLCHOST_CONF25_M ((HOST_SLCHOST_CONF25_V)<<(HOST_SLCHOST_CONF25_S)) -#define HOST_SLCHOST_CONF25_V 0xFF -#define HOST_SLCHOST_CONF25_S 8 -/* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF24 0x000000FF -#define HOST_SLCHOST_CONF24_M ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S)) -#define HOST_SLCHOST_CONF24_V 0xFF -#define HOST_SLCHOST_CONF24_S 0 - -#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C) -/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF31 0x000000FF -#define HOST_SLCHOST_CONF31_M ((HOST_SLCHOST_CONF31_V)<<(HOST_SLCHOST_CONF31_S)) -#define HOST_SLCHOST_CONF31_V 0xFF -#define HOST_SLCHOST_CONF31_S 24 -/* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF30 0x000000FF -#define HOST_SLCHOST_CONF30_M ((HOST_SLCHOST_CONF30_V)<<(HOST_SLCHOST_CONF30_S)) -#define HOST_SLCHOST_CONF30_V 0xFF -#define HOST_SLCHOST_CONF30_S 16 -/* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF29 0x000000FF -#define HOST_SLCHOST_CONF29_M ((HOST_SLCHOST_CONF29_V)<<(HOST_SLCHOST_CONF29_S)) -#define HOST_SLCHOST_CONF29_V 0xFF -#define HOST_SLCHOST_CONF29_S 8 -/* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF28 0x000000FF -#define HOST_SLCHOST_CONF28_M ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S)) -#define HOST_SLCHOST_CONF28_V 0xFF -#define HOST_SLCHOST_CONF28_S 0 - -#define HOST_SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90) -/* HOST_HOSTSLC0_LEN0_CHECK : RO ;bitpos:[31:20] ;default: 12'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN0_CHECK 0x00000FFF -#define HOST_HOSTSLC0_LEN0_CHECK_M ((HOST_HOSTSLC0_LEN0_CHECK_V)<<(HOST_HOSTSLC0_LEN0_CHECK_S)) -#define HOST_HOSTSLC0_LEN0_CHECK_V 0xFFF -#define HOST_HOSTSLC0_LEN0_CHECK_S 20 -/* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN0 0x000FFFFF -#define HOST_HOSTSLC0_LEN0_M ((HOST_HOSTSLC0_LEN0_V)<<(HOST_HOSTSLC0_LEN0_S)) -#define HOST_HOSTSLC0_LEN0_V 0xFFFFF -#define HOST_HOSTSLC0_LEN0_S 0 - -#define HOST_SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94) -/* HOST_HOSTSLC0_LEN1_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN1_CHECK 0x00000FFF -#define HOST_HOSTSLC0_LEN1_CHECK_M ((HOST_HOSTSLC0_LEN1_CHECK_V)<<(HOST_HOSTSLC0_LEN1_CHECK_S)) -#define HOST_HOSTSLC0_LEN1_CHECK_V 0xFFF -#define HOST_HOSTSLC0_LEN1_CHECK_S 20 -/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN1 0x000FFFFF -#define HOST_HOSTSLC0_LEN1_M ((HOST_HOSTSLC0_LEN1_V)<<(HOST_HOSTSLC0_LEN1_S)) -#define HOST_HOSTSLC0_LEN1_V 0xFFFFF -#define HOST_HOSTSLC0_LEN1_S 0 - -#define HOST_SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98) -/* HOST_HOSTSLC0_LEN2_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN2_CHECK 0x00000FFF -#define HOST_HOSTSLC0_LEN2_CHECK_M ((HOST_HOSTSLC0_LEN2_CHECK_V)<<(HOST_HOSTSLC0_LEN2_CHECK_S)) -#define HOST_HOSTSLC0_LEN2_CHECK_V 0xFFF -#define HOST_HOSTSLC0_LEN2_CHECK_S 20 -/* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define HOST_HOSTSLC0_LEN2 0x000FFFFF -#define HOST_HOSTSLC0_LEN2_M ((HOST_HOSTSLC0_LEN2_V)<<(HOST_HOSTSLC0_LEN2_S)) -#define HOST_HOSTSLC0_LEN2_V 0xFFFFF -#define HOST_HOSTSLC0_LEN2_S 0 - -#define HOST_SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9C) -/* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF35 0x000000FF -#define HOST_SLCHOST_CONF35_M ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S)) -#define HOST_SLCHOST_CONF35_V 0xFF -#define HOST_SLCHOST_CONF35_S 24 -/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF34 0x000000FF -#define HOST_SLCHOST_CONF34_M ((HOST_SLCHOST_CONF34_V)<<(HOST_SLCHOST_CONF34_S)) -#define HOST_SLCHOST_CONF34_V 0xFF -#define HOST_SLCHOST_CONF34_S 16 -/* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF33 0x000000FF -#define HOST_SLCHOST_CONF33_M ((HOST_SLCHOST_CONF33_V)<<(HOST_SLCHOST_CONF33_S)) -#define HOST_SLCHOST_CONF33_V 0xFF -#define HOST_SLCHOST_CONF33_S 8 -/* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF32 0x000000FF -#define HOST_SLCHOST_CONF32_M ((HOST_SLCHOST_CONF32_V)<<(HOST_SLCHOST_CONF32_S)) -#define HOST_SLCHOST_CONF32_V 0xFF -#define HOST_SLCHOST_CONF32_S 0 - -#define HOST_SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xA0) -/* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF39 0x000000FF -#define HOST_SLCHOST_CONF39_M ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S)) -#define HOST_SLCHOST_CONF39_V 0xFF -#define HOST_SLCHOST_CONF39_S 24 -/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF38 0x000000FF -#define HOST_SLCHOST_CONF38_M ((HOST_SLCHOST_CONF38_V)<<(HOST_SLCHOST_CONF38_S)) -#define HOST_SLCHOST_CONF38_V 0xFF -#define HOST_SLCHOST_CONF38_S 16 -/* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF37 0x000000FF -#define HOST_SLCHOST_CONF37_M ((HOST_SLCHOST_CONF37_V)<<(HOST_SLCHOST_CONF37_S)) -#define HOST_SLCHOST_CONF37_V 0xFF -#define HOST_SLCHOST_CONF37_S 8 -/* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF36 0x000000FF -#define HOST_SLCHOST_CONF36_M ((HOST_SLCHOST_CONF36_V)<<(HOST_SLCHOST_CONF36_S)) -#define HOST_SLCHOST_CONF36_V 0xFF -#define HOST_SLCHOST_CONF36_S 0 - -#define HOST_SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xA4) -/* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF43 0x000000FF -#define HOST_SLCHOST_CONF43_M ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S)) -#define HOST_SLCHOST_CONF43_V 0xFF -#define HOST_SLCHOST_CONF43_S 24 -/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF42 0x000000FF -#define HOST_SLCHOST_CONF42_M ((HOST_SLCHOST_CONF42_V)<<(HOST_SLCHOST_CONF42_S)) -#define HOST_SLCHOST_CONF42_V 0xFF -#define HOST_SLCHOST_CONF42_S 16 -/* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF41 0x000000FF -#define HOST_SLCHOST_CONF41_M ((HOST_SLCHOST_CONF41_V)<<(HOST_SLCHOST_CONF41_S)) -#define HOST_SLCHOST_CONF41_V 0xFF -#define HOST_SLCHOST_CONF41_S 8 -/* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF40 0x000000FF -#define HOST_SLCHOST_CONF40_M ((HOST_SLCHOST_CONF40_V)<<(HOST_SLCHOST_CONF40_S)) -#define HOST_SLCHOST_CONF40_V 0xFF -#define HOST_SLCHOST_CONF40_S 0 - -#define HOST_SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xA8) -/* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF47 0x000000FF -#define HOST_SLCHOST_CONF47_M ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S)) -#define HOST_SLCHOST_CONF47_V 0xFF -#define HOST_SLCHOST_CONF47_S 24 -/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF46 0x000000FF -#define HOST_SLCHOST_CONF46_M ((HOST_SLCHOST_CONF46_V)<<(HOST_SLCHOST_CONF46_S)) -#define HOST_SLCHOST_CONF46_V 0xFF -#define HOST_SLCHOST_CONF46_S 16 -/* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF45 0x000000FF -#define HOST_SLCHOST_CONF45_M ((HOST_SLCHOST_CONF45_V)<<(HOST_SLCHOST_CONF45_S)) -#define HOST_SLCHOST_CONF45_V 0xFF -#define HOST_SLCHOST_CONF45_S 8 -/* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF44 0x000000FF -#define HOST_SLCHOST_CONF44_M ((HOST_SLCHOST_CONF44_V)<<(HOST_SLCHOST_CONF44_S)) -#define HOST_SLCHOST_CONF44_V 0xFF -#define HOST_SLCHOST_CONF44_S 0 - -#define HOST_SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xAC) -/* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF51 0x000000FF -#define HOST_SLCHOST_CONF51_M ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S)) -#define HOST_SLCHOST_CONF51_V 0xFF -#define HOST_SLCHOST_CONF51_S 24 -/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF50 0x000000FF -#define HOST_SLCHOST_CONF50_M ((HOST_SLCHOST_CONF50_V)<<(HOST_SLCHOST_CONF50_S)) -#define HOST_SLCHOST_CONF50_V 0xFF -#define HOST_SLCHOST_CONF50_S 16 -/* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF49 0x000000FF -#define HOST_SLCHOST_CONF49_M ((HOST_SLCHOST_CONF49_V)<<(HOST_SLCHOST_CONF49_S)) -#define HOST_SLCHOST_CONF49_V 0xFF -#define HOST_SLCHOST_CONF49_S 8 -/* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF48 0x000000FF -#define HOST_SLCHOST_CONF48_M ((HOST_SLCHOST_CONF48_V)<<(HOST_SLCHOST_CONF48_S)) -#define HOST_SLCHOST_CONF48_V 0xFF -#define HOST_SLCHOST_CONF48_S 0 - -#define HOST_SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xB0) -/* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF55 0x000000FF -#define HOST_SLCHOST_CONF55_M ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S)) -#define HOST_SLCHOST_CONF55_V 0xFF -#define HOST_SLCHOST_CONF55_S 24 -/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF54 0x000000FF -#define HOST_SLCHOST_CONF54_M ((HOST_SLCHOST_CONF54_V)<<(HOST_SLCHOST_CONF54_S)) -#define HOST_SLCHOST_CONF54_V 0xFF -#define HOST_SLCHOST_CONF54_S 16 -/* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF53 0x000000FF -#define HOST_SLCHOST_CONF53_M ((HOST_SLCHOST_CONF53_V)<<(HOST_SLCHOST_CONF53_S)) -#define HOST_SLCHOST_CONF53_V 0xFF -#define HOST_SLCHOST_CONF53_S 8 -/* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF52 0x000000FF -#define HOST_SLCHOST_CONF52_M ((HOST_SLCHOST_CONF52_V)<<(HOST_SLCHOST_CONF52_S)) -#define HOST_SLCHOST_CONF52_V 0xFF -#define HOST_SLCHOST_CONF52_S 0 - -#define HOST_SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xB4) -/* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF59 0x000000FF -#define HOST_SLCHOST_CONF59_M ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S)) -#define HOST_SLCHOST_CONF59_V 0xFF -#define HOST_SLCHOST_CONF59_S 24 -/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF58 0x000000FF -#define HOST_SLCHOST_CONF58_M ((HOST_SLCHOST_CONF58_V)<<(HOST_SLCHOST_CONF58_S)) -#define HOST_SLCHOST_CONF58_V 0xFF -#define HOST_SLCHOST_CONF58_S 16 -/* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF57 0x000000FF -#define HOST_SLCHOST_CONF57_M ((HOST_SLCHOST_CONF57_V)<<(HOST_SLCHOST_CONF57_S)) -#define HOST_SLCHOST_CONF57_V 0xFF -#define HOST_SLCHOST_CONF57_S 8 -/* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF56 0x000000FF -#define HOST_SLCHOST_CONF56_M ((HOST_SLCHOST_CONF56_V)<<(HOST_SLCHOST_CONF56_S)) -#define HOST_SLCHOST_CONF56_V 0xFF -#define HOST_SLCHOST_CONF56_S 0 - -#define HOST_SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xB8) -/* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF63 0x000000FF -#define HOST_SLCHOST_CONF63_M ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S)) -#define HOST_SLCHOST_CONF63_V 0xFF -#define HOST_SLCHOST_CONF63_S 24 -/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF62 0x000000FF -#define HOST_SLCHOST_CONF62_M ((HOST_SLCHOST_CONF62_V)<<(HOST_SLCHOST_CONF62_S)) -#define HOST_SLCHOST_CONF62_V 0xFF -#define HOST_SLCHOST_CONF62_S 16 -/* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF61 0x000000FF -#define HOST_SLCHOST_CONF61_M ((HOST_SLCHOST_CONF61_V)<<(HOST_SLCHOST_CONF61_S)) -#define HOST_SLCHOST_CONF61_V 0xFF -#define HOST_SLCHOST_CONF61_S 8 -/* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define HOST_SLCHOST_CONF60 0x000000FF -#define HOST_SLCHOST_CONF60_M ((HOST_SLCHOST_CONF60_V)<<(HOST_SLCHOST_CONF60_S)) -#define HOST_SLCHOST_CONF60_V 0xFF -#define HOST_SLCHOST_CONF60_S 0 - -#define HOST_SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xBC) -/* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFF -#define HOST_SLCHOST_CHECK_SUM0_M ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S)) -#define HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFF -#define HOST_SLCHOST_CHECK_SUM0_S 0 - -#define HOST_SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xC0) -/* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_SLCHOST_CHECK_SUM1 0xFFFFFFFF -#define HOST_SLCHOST_CHECK_SUM1_M ((HOST_SLCHOST_CHECK_SUM1_V)<<(HOST_SLCHOST_CHECK_SUM1_S)) -#define HOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFF -#define HOST_SLCHOST_CHECK_SUM1_S 0 - -#define HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xC8) -/* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */ -/*description: */ -#define HOST_SLC0HOST_TOKEN1_WD 0x00000FFF -#define HOST_SLC0HOST_TOKEN1_WD_M ((HOST_SLC0HOST_TOKEN1_WD_V)<<(HOST_SLC0HOST_TOKEN1_WD_S)) -#define HOST_SLC0HOST_TOKEN1_WD_V 0xFFF -#define HOST_SLC0HOST_TOKEN1_WD_S 16 -/* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: */ -#define HOST_SLC0HOST_TOKEN0_WD 0x00000FFF -#define HOST_SLC0HOST_TOKEN0_WD_M ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S)) -#define HOST_SLC0HOST_TOKEN0_WD_V 0xFFF -#define HOST_SLC0HOST_TOKEN0_WD_S 0 - -#define HOST_SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xD0) -/* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_LEN_WR (BIT(8)) -#define HOST_SLC0HOST_LEN_WR_M (BIT(8)) -#define HOST_SLC0HOST_LEN_WR_V 0x1 -#define HOST_SLC0HOST_LEN_WR_S 8 -/* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TOKEN1_WR (BIT(3)) -#define HOST_SLC0HOST_TOKEN1_WR_M (BIT(3)) -#define HOST_SLC0HOST_TOKEN1_WR_V 0x1 -#define HOST_SLC0HOST_TOKEN1_WR_S 3 -/* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TOKEN0_WR (BIT(2)) -#define HOST_SLC0HOST_TOKEN0_WR_M (BIT(2)) -#define HOST_SLC0HOST_TOKEN0_WR_V 0x1 -#define HOST_SLC0HOST_TOKEN0_WR_S 2 -/* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TOKEN1_DEC (BIT(1)) -#define HOST_SLC0HOST_TOKEN1_DEC_M (BIT(1)) -#define HOST_SLC0HOST_TOKEN1_DEC_V 0x1 -#define HOST_SLC0HOST_TOKEN1_DEC_S 1 -/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TOKEN0_DEC (BIT(0)) -#define HOST_SLC0HOST_TOKEN0_DEC_M (BIT(0)) -#define HOST_SLC0HOST_TOKEN0_DEC_V 0x1 -#define HOST_SLC0HOST_TOKEN0_DEC_S 0 - -#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4) -/* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT_CLR (BIT(25)) -#define HOST_GPIO_SDIO_INT_CLR_M (BIT(25)) -#define HOST_GPIO_SDIO_INT_CLR_V 0x1 -#define HOST_GPIO_SDIO_INT_CLR_S 25 -/* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x1 -#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 -/* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x1 -#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 -/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_CLR_M (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_CLR_V 0x1 -#define HOST_SLC0_EXT_BIT3_INT_CLR_S 22 -/* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_CLR_M (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_CLR_V 0x1 -#define HOST_SLC0_EXT_BIT2_INT_CLR_S 21 -/* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_CLR_M (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_CLR_V 0x1 -#define HOST_SLC0_EXT_BIT1_INT_CLR_S 20 -/* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_CLR_M (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_CLR_V 0x1 -#define HOST_SLC0_EXT_BIT0_INT_CLR_S 19 -/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_CLR_M (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_CLR_V 0x1 -#define HOST_SLC0_RX_PF_VALID_INT_CLR_S 18 -/* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TX_OVF_INT_CLR (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_CLR_M (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_CLR_V 0x1 -#define HOST_SLC0_TX_OVF_INT_CLR_S 17 -/* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_UDF_INT_CLR (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_CLR_M (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_CLR_V 0x1 -#define HOST_SLC0_RX_UDF_INT_CLR_S 16 -/* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_CLR_M (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_CLR_V 0x1 -#define HOST_SLC0HOST_TX_START_INT_CLR_S 15 -/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_CLR_M (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_CLR_V 0x1 -#define HOST_SLC0HOST_RX_START_INT_CLR_S 14 -/* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_CLR_M (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_CLR_V 0x1 -#define HOST_SLC0HOST_RX_EOF_INT_CLR_S 13 -/* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_CLR_M (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_CLR_V 0x1 -#define HOST_SLC0HOST_RX_SOF_INT_CLR_S 12 -/* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x1 -#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 -/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x1 -#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 -/* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1 -#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 -/* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1 -#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 -/* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 -/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 -/* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 -/* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 -/* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 -/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 -/* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 -/* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x1 -#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 - -#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC) -/* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) -#define HOST_FN1_GPIO_SDIO_INT_ENA_M (BIT(25)) -#define HOST_FN1_GPIO_SDIO_INT_ENA_V 0x1 -#define HOST_FN1_GPIO_SDIO_INT_ENA_S 25 -/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) -#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 -/* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) -#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 -/* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) -#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) -#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 -/* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) -#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) -#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 -/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) -#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) -#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 -/* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) -#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) -#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 -/* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) -#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) -#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 -/* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) -#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M (BIT(17)) -#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 -/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) -#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M (BIT(16)) -#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 -/* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) -#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) -#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x1 -#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 -/* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) -#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) -#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x1 -#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 -/* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) -#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) -#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x1 -#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 -/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) -#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) -#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x1 -#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 -/* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) -#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 -/* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) -#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 -/* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) -#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 -/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) -#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 -/* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) -#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) -#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 -/* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) -#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) -#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 -/* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) -#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) -#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 -/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) -#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) -#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 -/* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) -#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) -#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 -/* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) -#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) -#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 -/* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) -#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) -#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 -/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) -#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) -#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 -#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 - -#define HOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xEC) -/* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT_ENA (BIT(25)) -#define HOST_GPIO_SDIO_INT_ENA_M (BIT(25)) -#define HOST_GPIO_SDIO_INT_ENA_V 0x1 -#define HOST_GPIO_SDIO_INT_ENA_S 25 -/* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 -/* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 -/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_ENA_V 0x1 -#define HOST_SLC0_EXT_BIT3_INT_ENA_S 22 -/* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_ENA_V 0x1 -#define HOST_SLC0_EXT_BIT2_INT_ENA_S 21 -/* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_ENA_V 0x1 -#define HOST_SLC0_EXT_BIT1_INT_ENA_S 20 -/* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_ENA_V 0x1 -#define HOST_SLC0_EXT_BIT0_INT_ENA_S 19 -/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_ENA_V 0x1 -#define HOST_SLC0_RX_PF_VALID_INT_ENA_S 18 -/* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TX_OVF_INT_ENA (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_ENA_M (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_ENA_V 0x1 -#define HOST_SLC0_TX_OVF_INT_ENA_S 17 -/* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_UDF_INT_ENA (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_ENA_M (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_ENA_V 0x1 -#define HOST_SLC0_RX_UDF_INT_ENA_S 16 -/* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_ENA_V 0x1 -#define HOST_SLC0HOST_TX_START_INT_ENA_S 15 -/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_ENA_V 0x1 -#define HOST_SLC0HOST_RX_START_INT_ENA_S 14 -/* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_ENA_V 0x1 -#define HOST_SLC0HOST_RX_EOF_INT_ENA_S 13 -/* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_ENA_V 0x1 -#define HOST_SLC0HOST_RX_SOF_INT_ENA_S 12 -/* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 -/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 -/* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 -/* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 -/* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 -/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 -/* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 -/* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 -/* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 -/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 -/* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 -/* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 -#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 - -#define HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF4) -/* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_INFOR 0x000FFFFF -#define HOST_SLC0HOST_RX_INFOR_M ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S)) -#define HOST_SLC0HOST_RX_INFOR_V 0xFFFFF -#define HOST_SLC0HOST_RX_INFOR_S 0 - -#define HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xFC) -/* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_LEN_WD 0xFFFFFFFF -#define HOST_SLC0HOST_LEN_WD_M ((HOST_SLC0HOST_LEN_WD_V)<<(HOST_SLC0HOST_LEN_WD_S)) -#define HOST_SLC0HOST_LEN_WD_V 0xFFFFFFFF -#define HOST_SLC0HOST_LEN_WD_S 0 - -#define HOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100) -/* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_SLC_APBWIN_WDATA 0xFFFFFFFF -#define HOST_SLC_APBWIN_WDATA_M ((HOST_SLC_APBWIN_WDATA_V)<<(HOST_SLC_APBWIN_WDATA_S)) -#define HOST_SLC_APBWIN_WDATA_V 0xFFFFFFFF -#define HOST_SLC_APBWIN_WDATA_S 0 - -#define HOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104) -/* HOST_SLC_APBWIN_BUS : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC_APBWIN_BUS (BIT(30)) -#define HOST_SLC_APBWIN_BUS_M (BIT(30)) -#define HOST_SLC_APBWIN_BUS_V 0x1 -#define HOST_SLC_APBWIN_BUS_S 30 -/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC_APBWIN_START (BIT(29)) -#define HOST_SLC_APBWIN_START_M (BIT(29)) -#define HOST_SLC_APBWIN_START_V 0x1 -#define HOST_SLC_APBWIN_START_S 29 -/* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC_APBWIN_WR (BIT(28)) -#define HOST_SLC_APBWIN_WR_M (BIT(28)) -#define HOST_SLC_APBWIN_WR_V 0x1 -#define HOST_SLC_APBWIN_WR_S 28 -/* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ -/*description: */ -#define HOST_SLC_APBWIN_ADDR 0x0FFFFFFF -#define HOST_SLC_APBWIN_ADDR_M ((HOST_SLC_APBWIN_ADDR_V)<<(HOST_SLC_APBWIN_ADDR_S)) -#define HOST_SLC_APBWIN_ADDR_V 0xFFFFFFF -#define HOST_SLC_APBWIN_ADDR_S 0 - -#define HOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108) -/* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define HOST_SLC_APBWIN_RDATA 0xFFFFFFFF -#define HOST_SLC_APBWIN_RDATA_M ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S)) -#define HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFF -#define HOST_SLC_APBWIN_RDATA_S 0 - -#define HOST_SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10C) -/* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */ -/*description: */ -#define HOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FF -#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT6_CLRADDR_S)) -#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x1FF -#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 -/* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */ -/*description: */ -#define HOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FF -#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT7_CLRADDR_S)) -#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x1FF -#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 - -#define HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114) -/* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_GPIO_SDIO_INT_ENA1 (BIT(25)) -#define HOST_GPIO_SDIO_INT_ENA1_M (BIT(25)) -#define HOST_GPIO_SDIO_INT_ENA1_V 0x1 -#define HOST_GPIO_SDIO_INT_ENA1_S 25 -/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (BIT(24)) -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x1 -#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 -/* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (BIT(23)) -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x1 -#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 -/* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_ENA1_M (BIT(22)) -#define HOST_SLC0_EXT_BIT3_INT_ENA1_V 0x1 -#define HOST_SLC0_EXT_BIT3_INT_ENA1_S 22 -/* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_ENA1_M (BIT(21)) -#define HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x1 -#define HOST_SLC0_EXT_BIT2_INT_ENA1_S 21 -/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_ENA1_M (BIT(20)) -#define HOST_SLC0_EXT_BIT1_INT_ENA1_V 0x1 -#define HOST_SLC0_EXT_BIT1_INT_ENA1_S 20 -/* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_ENA1_M (BIT(19)) -#define HOST_SLC0_EXT_BIT0_INT_ENA1_V 0x1 -#define HOST_SLC0_EXT_BIT0_INT_ENA1_S 19 -/* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M (BIT(18)) -#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x1 -#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 -/* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_ENA1_M (BIT(17)) -#define HOST_SLC0_TX_OVF_INT_ENA1_V 0x1 -#define HOST_SLC0_TX_OVF_INT_ENA1_S 17 -/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_ENA1_M (BIT(16)) -#define HOST_SLC0_RX_UDF_INT_ENA1_V 0x1 -#define HOST_SLC0_RX_UDF_INT_ENA1_S 16 -/* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_ENA1_M (BIT(15)) -#define HOST_SLC0HOST_TX_START_INT_ENA1_V 0x1 -#define HOST_SLC0HOST_TX_START_INT_ENA1_S 15 -/* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_ENA1_M (BIT(14)) -#define HOST_SLC0HOST_RX_START_INT_ENA1_V 0x1 -#define HOST_SLC0HOST_RX_START_INT_ENA1_S 14 -/* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M (BIT(13)) -#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x1 -#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 -/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M (BIT(12)) -#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x1 -#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 -/* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (BIT(11)) -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x1 -#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 -/* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (BIT(10)) -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x1 -#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 -/* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(9)) -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1 -#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 -/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(8)) -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1 -#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 -/* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M (BIT(7)) -#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 -/* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M (BIT(6)) -#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 -/* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (BIT(5)) -#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 -/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M (BIT(4)) -#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 -/* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M (BIT(3)) -#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 -/* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M (BIT(2)) -#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 -/* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (BIT(1)) -#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 -/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M (BIT(0)) -#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x1 -#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 - -#define HOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178) -/* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */ -/*description: */ -#define HOST_SLCHOST_DATE 0xFFFFFFFF -#define HOST_SLCHOST_DATE_M ((HOST_SLCHOST_DATE_V)<<(HOST_SLCHOST_DATE_S)) -#define HOST_SLCHOST_DATE_V 0xFFFFFFFF -#define HOST_SLCHOST_DATE_S 0 - -#define HOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17C) -/* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */ -/*description: */ -#define HOST_SLCHOST_ID 0xFFFFFFFF -#define HOST_SLCHOST_ID_M ((HOST_SLCHOST_ID_V)<<(HOST_SLCHOST_ID_S)) -#define HOST_SLCHOST_ID_V 0xFFFFFFFF -#define HOST_SLCHOST_ID_S 0 - -#define HOST_SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1F0) -/* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define HOST_HSPEED_CON_EN (BIT(27)) -#define HOST_HSPEED_CON_EN_M (BIT(27)) -#define HOST_HSPEED_CON_EN_V 0x1 -#define HOST_HSPEED_CON_EN_S 27 -/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SDIO_PAD_PULLUP (BIT(26)) -#define HOST_SDIO_PAD_PULLUP_M (BIT(26)) -#define HOST_SDIO_PAD_PULLUP_V 0x1 -#define HOST_SDIO_PAD_PULLUP_S 26 -/* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define HOST_SDIO20_INT_DELAY (BIT(25)) -#define HOST_SDIO20_INT_DELAY_M (BIT(25)) -#define HOST_SDIO20_INT_DELAY_V 0x1 -#define HOST_SDIO20_INT_DELAY_S 25 -/* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */ -/*description: */ -#define HOST_FRC_QUICK_IN 0x0000001F -#define HOST_FRC_QUICK_IN_M ((HOST_FRC_QUICK_IN_V)<<(HOST_FRC_QUICK_IN_S)) -#define HOST_FRC_QUICK_IN_V 0x1F -#define HOST_FRC_QUICK_IN_S 20 -/* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: */ -#define HOST_FRC_POS_SAMP 0x0000001F -#define HOST_FRC_POS_SAMP_M ((HOST_FRC_POS_SAMP_V)<<(HOST_FRC_POS_SAMP_S)) -#define HOST_FRC_POS_SAMP_V 0x1F -#define HOST_FRC_POS_SAMP_S 15 -/* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: */ -#define HOST_FRC_NEG_SAMP 0x0000001F -#define HOST_FRC_NEG_SAMP_M ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S)) -#define HOST_FRC_NEG_SAMP_V 0x1F -#define HOST_FRC_NEG_SAMP_S 10 -/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: */ -#define HOST_FRC_SDIO20 0x0000001F -#define HOST_FRC_SDIO20_M ((HOST_FRC_SDIO20_V)<<(HOST_FRC_SDIO20_S)) -#define HOST_FRC_SDIO20_V 0x1F -#define HOST_FRC_SDIO20_S 5 -/* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: */ -#define HOST_FRC_SDIO11 0x0000001F -#define HOST_FRC_SDIO11_M ((HOST_FRC_SDIO11_V)<<(HOST_FRC_SDIO11_S)) -#define HOST_FRC_SDIO11_V 0x1F -#define HOST_FRC_SDIO11_S 0 - -#define HOST_SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1F4) -/* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: */ -#define HOST_SDIO_QUICK_IN 0x0000001F -#define HOST_SDIO_QUICK_IN_M ((HOST_SDIO_QUICK_IN_V)<<(HOST_SDIO_QUICK_IN_S)) -#define HOST_SDIO_QUICK_IN_V 0x1F -#define HOST_SDIO_QUICK_IN_S 10 -/* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: */ -#define HOST_SDIO_NEG_SAMP 0x0000001F -#define HOST_SDIO_NEG_SAMP_M ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S)) -#define HOST_SDIO_NEG_SAMP_V 0x1F -#define HOST_SDIO_NEG_SAMP_S 5 -/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: */ -#define HOST_SDIO20_MODE 0x0000001F -#define HOST_SDIO20_MODE_M ((HOST_SDIO20_MODE_V)<<(HOST_SDIO20_MODE_S)) -#define HOST_SDIO20_MODE_V 0x1F -#define HOST_SDIO20_MODE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_HOST_REG_H_ */ - - diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_struct.h deleted file mode 100644 index fd7844c3..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/host_struct.h +++ /dev/null @@ -1,602 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_HOST_STRUCT_H_ -#define _SOC_HOST_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - uint32_t reserved_0; - uint32_t reserved_4; - uint32_t reserved_8; - uint32_t reserved_c; - uint32_t reserved_10; - uint32_t reserved_14; - uint32_t reserved_18; - uint32_t reserved_1c; - union { - struct { - uint32_t func1_mdstat: 1; - uint32_t reserved1: 31; - }; - uint32_t val; - } func2_2; - uint32_t reserved_24; - uint32_t reserved_28; - uint32_t reserved_2c; - uint32_t reserved_30; - uint32_t gpio_status0; /**/ - union { - struct { - uint32_t sdio_int1: 22; - uint32_t reserved22: 10; - }; - uint32_t val; - } gpio_status1; - uint32_t gpio_in0; /**/ - union { - struct { - uint32_t sdio_in1: 22; - uint32_t reserved22: 10; - }; - uint32_t val; - } gpio_in1; - union { - struct { - uint32_t token0: 12; - uint32_t rx_pf_valid: 1; - uint32_t reserved13: 3; - uint32_t reg_token1: 12; - uint32_t rx_pf_eof: 4; - }; - uint32_t val; - } slc0_token_rdata; - uint32_t slc0_pf; /**/ - uint32_t reserved_4c; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_raw; - uint32_t reserved_54; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_st; - uint32_t reserved_5c; - union { - struct { - uint32_t reg_slc0_len: 20; - uint32_t reg_slc0_len_check:12; - }; - uint32_t val; - } pkt_len; - union { - struct { - uint32_t state0: 8; - uint32_t state1: 8; - uint32_t state2: 8; - uint32_t state3: 8; - }; - uint32_t val; - } state_w0; - union { - struct { - uint32_t state4: 8; - uint32_t state5: 8; - uint32_t state6: 8; - uint32_t state7: 8; - }; - uint32_t val; - } state_w1; - union { - struct { - uint32_t conf0: 8; - uint32_t conf1: 8; - uint32_t conf2: 8; - uint32_t conf3: 8; - }; - uint32_t val; - } conf_w0; - union { - struct { - uint32_t conf4: 8; - uint32_t conf5: 8; - uint32_t conf6: 8; - uint32_t conf7: 8; - }; - uint32_t val; - } conf_w1; - union { - struct { - uint32_t conf8: 8; - uint32_t conf9: 8; - uint32_t conf10: 8; - uint32_t conf11: 8; - }; - uint32_t val; - } conf_w2; - union { - struct { - uint32_t conf12: 8; - uint32_t conf13: 8; - uint32_t conf14: 8; - uint32_t conf15: 8; - }; - uint32_t val; - } conf_w3; - union { - struct { - uint32_t conf16: 8; /*SLC timeout value*/ - uint32_t conf17: 8; /*SLC timeout enable*/ - uint32_t conf18: 8; - uint32_t conf19: 8; /*Interrupt to target CPU*/ - }; - uint32_t val; - } conf_w4; - union { - struct { - uint32_t conf20: 8; - uint32_t conf21: 8; - uint32_t conf22: 8; - uint32_t conf23: 8; - }; - uint32_t val; - } conf_w5; - union { - struct { - uint32_t win_cmd: 16; - uint32_t reserved16: 16; - }; - uint32_t val; - } win_cmd; - union { - struct { - uint32_t conf24: 8; - uint32_t conf25: 8; - uint32_t conf26: 8; - uint32_t conf27: 8; - }; - uint32_t val; - } conf_w6; - union { - struct { - uint32_t conf28: 8; - uint32_t conf29: 8; - uint32_t conf30: 8; - uint32_t conf31: 8; - }; - uint32_t val; - } conf_w7; - union { - struct { - uint32_t reg_slc0_len0: 20; - uint32_t reg_slc0_len0_check:12; - }; - uint32_t val; - } pkt_len0; - union { - struct { - uint32_t reg_slc0_len1: 20; - uint32_t reg_slc0_len1_check:12; - }; - uint32_t val; - } pkt_len1; - union { - struct { - uint32_t reg_slc0_len2: 20; - uint32_t reg_slc0_len2_check:12; - }; - uint32_t val; - } pkt_len2; - union { - struct { - uint32_t conf32: 8; - uint32_t conf33: 8; - uint32_t conf34: 8; - uint32_t conf35: 8; - }; - uint32_t val; - } conf_w8; - union { - struct { - uint32_t conf36: 8; - uint32_t conf37: 8; - uint32_t conf38: 8; - uint32_t conf39: 8; - }; - uint32_t val; - } conf_w9; - union { - struct { - uint32_t conf40: 8; - uint32_t conf41: 8; - uint32_t conf42: 8; - uint32_t conf43: 8; - }; - uint32_t val; - } conf_w10; - union { - struct { - uint32_t conf44: 8; - uint32_t conf45: 8; - uint32_t conf46: 8; - uint32_t conf47: 8; - }; - uint32_t val; - } conf_w11; - union { - struct { - uint32_t conf48: 8; - uint32_t conf49: 8; - uint32_t conf50: 8; - uint32_t conf51: 8; - }; - uint32_t val; - } conf_w12; - union { - struct { - uint32_t conf52: 8; - uint32_t conf53: 8; - uint32_t conf54: 8; - uint32_t conf55: 8; - }; - uint32_t val; - } conf_w13; - union { - struct { - uint32_t conf56: 8; - uint32_t conf57: 8; - uint32_t conf58: 8; - uint32_t conf59: 8; - }; - uint32_t val; - } conf_w14; - union { - struct { - uint32_t conf60: 8; - uint32_t conf61: 8; - uint32_t conf62: 8; - uint32_t conf63: 8; - }; - uint32_t val; - } conf_w15; - uint32_t check_sum0; /**/ - uint32_t check_sum1; /**/ - uint32_t reserved_c4; - union { - struct { - uint32_t token0_wd: 12; - uint32_t reserved12: 4; - uint32_t token1_wd: 12; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_token_wdata; - uint32_t reserved_cc; - union { - struct { - uint32_t slc0_token0_dec: 1; - uint32_t slc0_token1_dec: 1; - uint32_t slc0_token0_wr: 1; - uint32_t slc0_token1_wr: 1; - uint32_t reserved4: 4; - uint32_t slc0_len_wr: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } token_con; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_clr; - uint32_t reserved_d8; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_func1_int_ena; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t tohost_bit1: 1; - uint32_t tohost_bit2: 1; - uint32_t tohost_bit3: 1; - uint32_t tohost_bit4: 1; - uint32_t tohost_bit5: 1; - uint32_t tohost_bit6: 1; - uint32_t tohost_bit7: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t token0_0to1: 1; - uint32_t token1_0to1: 1; - uint32_t rx_sof: 1; - uint32_t rx_eof: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t rx_pf_valid: 1; - uint32_t ext_bit0: 1; - uint32_t ext_bit1: 1; - uint32_t ext_bit2: 1; - uint32_t ext_bit3: 1; - uint32_t rx_new_packet: 1; - uint32_t rd_retry: 1; - uint32_t gpio_sdio: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_ena; - uint32_t reserved_f0; - union { - struct { - uint32_t infor: 20; - uint32_t reserved20: 12; - }; - uint32_t val; - } slc0_rx_infor; - uint32_t reserved_f8; - uint32_t slc0_len_wd; /**/ - uint32_t apbwin_wdata; /**/ - union { - struct { - uint32_t addr: 28; - uint32_t wr: 1; - uint32_t start: 1; - uint32_t bus: 1; - uint32_t reserved31: 1; - }; - uint32_t val; - } apbwin_conf; - uint32_t apbwin_rdata; /**/ - union { - struct { - uint32_t bit7_clraddr: 9; - uint32_t bit6_clraddr: 9; - uint32_t reserved18: 14; - }; - uint32_t val; - } slc0_rdclr; - uint32_t reserved_110; - union { - struct { - uint32_t tohost_bit01: 1; - uint32_t tohost_bit11: 1; - uint32_t tohost_bit21: 1; - uint32_t tohost_bit31: 1; - uint32_t tohost_bit41: 1; - uint32_t tohost_bit51: 1; - uint32_t tohost_bit61: 1; - uint32_t tohost_bit71: 1; - uint32_t token0_1to01: 1; - uint32_t token1_1to01: 1; - uint32_t token0_0to11: 1; - uint32_t token1_0to11: 1; - uint32_t rx_sof1: 1; - uint32_t rx_eof1: 1; - uint32_t rx_start1: 1; - uint32_t tx_start1: 1; - uint32_t rx_udf1: 1; - uint32_t tx_ovf1: 1; - uint32_t rx_pf_valid1: 1; - uint32_t ext_bit01: 1; - uint32_t ext_bit11: 1; - uint32_t ext_bit21: 1; - uint32_t ext_bit31: 1; - uint32_t rx_new_packet1: 1; - uint32_t rd_retry1: 1; - uint32_t gpio_sdio1: 1; - uint32_t reserved26: 6; - }; - uint32_t val; - } slc0_int_ena1; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t date; /**/ - uint32_t id; /**/ - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - union { - struct { - uint32_t frc_sdio11: 5; - uint32_t frc_sdio20: 5; - uint32_t frc_neg_samp: 5; - uint32_t frc_pos_samp: 5; - uint32_t frc_quick_in: 5; - uint32_t sdio20_int_delay: 1; - uint32_t sdio_pad_pullup: 1; - uint32_t hspeed_con_en: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t sdio20_mode: 5; - uint32_t sdio_neg_samp: 5; - uint32_t sdio_quick_in: 5; - uint32_t reserved15: 17; - }; - uint32_t val; - } inf_st; -} host_dev_t; -extern host_dev_t HOST; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_HOST_STRUCT_H_ */ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/mcp_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/mcp_reg.h deleted file mode 100644 index 907cf4bf..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/mcp_reg.h +++ /dev/null @@ -1,540 +0,0 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCP_REG_H_ -#define _SOC_MCP_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define MCP_INT_RAW_REG (DR_REG_MCP_BASE + 0x0000) -/* MCP_CRC_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define MCP_CRC_DONE_INT_RAW (BIT(8)) -#define MCP_CRC_DONE_INT_RAW_M (BIT(8)) -#define MCP_CRC_DONE_INT_RAW_V 0x1 -#define MCP_CRC_DONE_INT_RAW_S 8 -/* MCP_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_TOTAL_EOF_INT_RAW (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_RAW_M (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_RAW_V 0x1 -#define MCP_OUT_TOTAL_EOF_INT_RAW_S 7 -/* MCP_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_EMPTY_INT_RAW (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_RAW_M (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_RAW_V 0x1 -#define MCP_IN_DSCR_EMPTY_INT_RAW_S 6 -/* MCP_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DSCR_ERR_INT_RAW (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_RAW_M (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_RAW_V 0x1 -#define MCP_OUT_DSCR_ERR_INT_RAW_S 5 -/* MCP_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_ERR_INT_RAW (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_RAW_M (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_RAW_V 0x1 -#define MCP_IN_DSCR_ERR_INT_RAW_S 4 -/* MCP_OUT_EOF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_EOF_INT_RAW (BIT(3)) -#define MCP_OUT_EOF_INT_RAW_M (BIT(3)) -#define MCP_OUT_EOF_INT_RAW_V 0x1 -#define MCP_OUT_EOF_INT_RAW_S 3 -/* MCP_OUT_DONE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DONE_INT_RAW (BIT(2)) -#define MCP_OUT_DONE_INT_RAW_M (BIT(2)) -#define MCP_OUT_DONE_INT_RAW_V 0x1 -#define MCP_OUT_DONE_INT_RAW_S 2 -/* MCP_IN_SUC_EOF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_SUC_EOF_INT_RAW (BIT(1)) -#define MCP_IN_SUC_EOF_INT_RAW_M (BIT(1)) -#define MCP_IN_SUC_EOF_INT_RAW_V 0x1 -#define MCP_IN_SUC_EOF_INT_RAW_S 1 -/* MCP_IN_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DONE_INT_RAW (BIT(0)) -#define MCP_IN_DONE_INT_RAW_M (BIT(0)) -#define MCP_IN_DONE_INT_RAW_V 0x1 -#define MCP_IN_DONE_INT_RAW_S 0 - -#define MCP_INT_ST_REG (DR_REG_MCP_BASE + 0x0004) -/* MCP_CRC_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define MCP_CRC_DONE_INT_ST (BIT(8)) -#define MCP_CRC_DONE_INT_ST_M (BIT(8)) -#define MCP_CRC_DONE_INT_ST_V 0x1 -#define MCP_CRC_DONE_INT_ST_S 8 -/* MCP_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_TOTAL_EOF_INT_ST (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_ST_M (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_ST_V 0x1 -#define MCP_OUT_TOTAL_EOF_INT_ST_S 7 -/* MCP_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_EMPTY_INT_ST (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_ST_M (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_ST_V 0x1 -#define MCP_IN_DSCR_EMPTY_INT_ST_S 6 -/* MCP_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DSCR_ERR_INT_ST (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_ST_M (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_ST_V 0x1 -#define MCP_OUT_DSCR_ERR_INT_ST_S 5 -/* MCP_IN_DSCR_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_ERR_INT_ST (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_ST_M (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_ST_V 0x1 -#define MCP_IN_DSCR_ERR_INT_ST_S 4 -/* MCP_OUT_EOF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_EOF_INT_ST (BIT(3)) -#define MCP_OUT_EOF_INT_ST_M (BIT(3)) -#define MCP_OUT_EOF_INT_ST_V 0x1 -#define MCP_OUT_EOF_INT_ST_S 3 -/* MCP_OUT_DONE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DONE_INT_ST (BIT(2)) -#define MCP_OUT_DONE_INT_ST_M (BIT(2)) -#define MCP_OUT_DONE_INT_ST_V 0x1 -#define MCP_OUT_DONE_INT_ST_S 2 -/* MCP_IN_SUC_EOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_SUC_EOF_INT_ST (BIT(1)) -#define MCP_IN_SUC_EOF_INT_ST_M (BIT(1)) -#define MCP_IN_SUC_EOF_INT_ST_V 0x1 -#define MCP_IN_SUC_EOF_INT_ST_S 1 -/* MCP_IN_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DONE_INT_ST (BIT(0)) -#define MCP_IN_DONE_INT_ST_M (BIT(0)) -#define MCP_IN_DONE_INT_ST_V 0x1 -#define MCP_IN_DONE_INT_ST_S 0 - -#define MCP_INT_ENA_REG (DR_REG_MCP_BASE + 0x008) -/* MCP_CRC_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define MCP_CRC_DONE_INT_ENA (BIT(8)) -#define MCP_CRC_DONE_INT_ENA_M (BIT(8)) -#define MCP_CRC_DONE_INT_ENA_V 0x1 -#define MCP_CRC_DONE_INT_ENA_S 8 -/* MCP_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_TOTAL_EOF_INT_ENA (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_ENA_M (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_ENA_V 0x1 -#define MCP_OUT_TOTAL_EOF_INT_ENA_S 7 -/* MCP_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_EMPTY_INT_ENA (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_ENA_M (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_ENA_V 0x1 -#define MCP_IN_DSCR_EMPTY_INT_ENA_S 6 -/* MCP_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DSCR_ERR_INT_ENA (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_ENA_M (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_ENA_V 0x1 -#define MCP_OUT_DSCR_ERR_INT_ENA_S 5 -/* MCP_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_ERR_INT_ENA (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_ENA_M (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_ENA_V 0x1 -#define MCP_IN_DSCR_ERR_INT_ENA_S 4 -/* MCP_OUT_EOF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_EOF_INT_ENA (BIT(3)) -#define MCP_OUT_EOF_INT_ENA_M (BIT(3)) -#define MCP_OUT_EOF_INT_ENA_V 0x1 -#define MCP_OUT_EOF_INT_ENA_S 3 -/* MCP_OUT_DONE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DONE_INT_ENA (BIT(2)) -#define MCP_OUT_DONE_INT_ENA_M (BIT(2)) -#define MCP_OUT_DONE_INT_ENA_V 0x1 -#define MCP_OUT_DONE_INT_ENA_S 2 -/* MCP_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_SUC_EOF_INT_ENA (BIT(1)) -#define MCP_IN_SUC_EOF_INT_ENA_M (BIT(1)) -#define MCP_IN_SUC_EOF_INT_ENA_V 0x1 -#define MCP_IN_SUC_EOF_INT_ENA_S 1 -/* MCP_IN_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DONE_INT_ENA (BIT(0)) -#define MCP_IN_DONE_INT_ENA_M (BIT(0)) -#define MCP_IN_DONE_INT_ENA_V 0x1 -#define MCP_IN_DONE_INT_ENA_S 0 - -#define MCP_INT_CLR_REG (DR_REG_MCP_BASE + 0x000c) -/* MCP_CRC_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define MCP_CRC_DONE_INT_CLR (BIT(8)) -#define MCP_CRC_DONE_INT_CLR_M (BIT(8)) -#define MCP_CRC_DONE_INT_CLR_V 0x1 -#define MCP_CRC_DONE_INT_CLR_S 8 -/* MCP_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_TOTAL_EOF_INT_CLR (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_CLR_M (BIT(7)) -#define MCP_OUT_TOTAL_EOF_INT_CLR_V 0x1 -#define MCP_OUT_TOTAL_EOF_INT_CLR_S 7 -/* MCP_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_EMPTY_INT_CLR (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_CLR_M (BIT(6)) -#define MCP_IN_DSCR_EMPTY_INT_CLR_V 0x1 -#define MCP_IN_DSCR_EMPTY_INT_CLR_S 6 -/* MCP_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DSCR_ERR_INT_CLR (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_CLR_M (BIT(5)) -#define MCP_OUT_DSCR_ERR_INT_CLR_V 0x1 -#define MCP_OUT_DSCR_ERR_INT_CLR_S 5 -/* MCP_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_ERR_INT_CLR (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_CLR_M (BIT(4)) -#define MCP_IN_DSCR_ERR_INT_CLR_V 0x1 -#define MCP_IN_DSCR_ERR_INT_CLR_S 4 -/* MCP_OUT_EOF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_EOF_INT_CLR (BIT(3)) -#define MCP_OUT_EOF_INT_CLR_M (BIT(3)) -#define MCP_OUT_EOF_INT_CLR_V 0x1 -#define MCP_OUT_EOF_INT_CLR_S 3 -/* MCP_OUT_DONE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUT_DONE_INT_CLR (BIT(2)) -#define MCP_OUT_DONE_INT_CLR_M (BIT(2)) -#define MCP_OUT_DONE_INT_CLR_V 0x1 -#define MCP_OUT_DONE_INT_CLR_S 2 -/* MCP_IN_SUC_EOF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_SUC_EOF_INT_CLR (BIT(1)) -#define MCP_IN_SUC_EOF_INT_CLR_M (BIT(1)) -#define MCP_IN_SUC_EOF_INT_CLR_V 0x1 -#define MCP_IN_SUC_EOF_INT_CLR_S 1 -/* MCP_IN_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define MCP_IN_DONE_INT_CLR (BIT(0)) -#define MCP_IN_DONE_INT_CLR_M (BIT(0)) -#define MCP_IN_DONE_INT_CLR_V 0x1 -#define MCP_IN_DONE_INT_CLR_S 0 - -#define MCP_OUT_LINK_REG (DR_REG_MCP_BASE + 0x0010) -/* MCP_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define MCP_OUTLINK_PARK (BIT(31)) -#define MCP_OUTLINK_PARK_M (BIT(31)) -#define MCP_OUTLINK_PARK_V 0x1 -#define MCP_OUTLINK_PARK_S 31 -/* MCP_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUTLINK_RESTART (BIT(30)) -#define MCP_OUTLINK_RESTART_M (BIT(30)) -#define MCP_OUTLINK_RESTART_V 0x1 -#define MCP_OUTLINK_RESTART_S 30 -/* MCP_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUTLINK_START (BIT(29)) -#define MCP_OUTLINK_START_M (BIT(29)) -#define MCP_OUTLINK_START_V 0x1 -#define MCP_OUTLINK_START_S 29 -/* MCP_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define MCP_OUTLINK_STOP (BIT(28)) -#define MCP_OUTLINK_STOP_M (BIT(28)) -#define MCP_OUTLINK_STOP_V 0x1 -#define MCP_OUTLINK_STOP_S 28 -/* MCP_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define MCP_OUTLINK_ADDR 0x000FFFFF -#define MCP_OUTLINK_ADDR_M ((MCP_OUTLINK_ADDR_V)<<(MCP_OUTLINK_ADDR_S)) -#define MCP_OUTLINK_ADDR_V 0xFFFFF -#define MCP_OUTLINK_ADDR_S 0 - -#define MCP_IN_LINK_REG (DR_REG_MCP_BASE + 0x0014) -/* MCP_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define MCP_INLINK_PARK (BIT(31)) -#define MCP_INLINK_PARK_M (BIT(31)) -#define MCP_INLINK_PARK_V 0x1 -#define MCP_INLINK_PARK_S 31 -/* MCP_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define MCP_INLINK_RESTART (BIT(30)) -#define MCP_INLINK_RESTART_M (BIT(30)) -#define MCP_INLINK_RESTART_V 0x1 -#define MCP_INLINK_RESTART_S 30 -/* MCP_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define MCP_INLINK_START (BIT(29)) -#define MCP_INLINK_START_M (BIT(29)) -#define MCP_INLINK_START_V 0x1 -#define MCP_INLINK_START_S 29 -/* MCP_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define MCP_INLINK_STOP (BIT(28)) -#define MCP_INLINK_STOP_M (BIT(28)) -#define MCP_INLINK_STOP_V 0x1 -#define MCP_INLINK_STOP_S 28 -/* MCP_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define MCP_INLINK_ADDR 0x000FFFFF -#define MCP_INLINK_ADDR_M ((MCP_INLINK_ADDR_V)<<(MCP_INLINK_ADDR_S)) -#define MCP_INLINK_ADDR_V 0xFFFFF -#define MCP_INLINK_ADDR_S 0 - -#define MCP_OUT_EOF_DES_ADDR_REG (DR_REG_MCP_BASE + 0x0018) -/* MCP_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define MCP_OUT_EOF_DES_ADDR 0xFFFFFFFF -#define MCP_OUT_EOF_DES_ADDR_M ((MCP_OUT_EOF_DES_ADDR_V)<<(MCP_OUT_EOF_DES_ADDR_S)) -#define MCP_OUT_EOF_DES_ADDR_V 0xFFFFFFFF -#define MCP_OUT_EOF_DES_ADDR_S 0 - -#define MCP_IN_EOF_DES_ADDR_REG (DR_REG_MCP_BASE + 0x001c) -/* MCP_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define MCP_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF -#define MCP_IN_SUC_EOF_DES_ADDR_M ((MCP_IN_SUC_EOF_DES_ADDR_V)<<(MCP_IN_SUC_EOF_DES_ADDR_S)) -#define MCP_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF -#define MCP_IN_SUC_EOF_DES_ADDR_S 0 - -#define MCP_OUT_EOF_BFR_DES_ADDR_REG (DR_REG_MCP_BASE + 0x0020) -/* MCP_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define MCP_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF -#define MCP_OUT_EOF_BFR_DES_ADDR_M ((MCP_OUT_EOF_BFR_DES_ADDR_V)<<(MCP_OUT_EOF_BFR_DES_ADDR_S)) -#define MCP_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF -#define MCP_OUT_EOF_BFR_DES_ADDR_S 0 - -#define MCP_INLINK_DSCR_REG (DR_REG_MCP_BASE + 0x0024) -/* MCP_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define MCP_INLINK_DSCR 0xFFFFFFFF -#define MCP_INLINK_DSCR_M ((MCP_INLINK_DSCR_V)<<(MCP_INLINK_DSCR_S)) -#define MCP_INLINK_DSCR_V 0xFFFFFFFF -#define MCP_INLINK_DSCR_S 0 - -#define MCP_INLINK_DSCR_BF0_REG (DR_REG_MCP_BASE + 0x0028) -/* MCP_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define MCP_INLINK_DSCR_BF0 0xFFFFFFFF -#define MCP_INLINK_DSCR_BF0_M ((MCP_INLINK_DSCR_BF0_V)<<(MCP_INLINK_DSCR_BF0_S)) -#define MCP_INLINK_DSCR_BF0_V 0xFFFFFFFF -#define MCP_INLINK_DSCR_BF0_S 0 - -#define MCP_INLINK_DSCR_BF1_REG (DR_REG_MCP_BASE + 0x002c) -/* MCP_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define MCP_INLINK_DSCR_BF1 0xFFFFFFFF -#define MCP_INLINK_DSCR_BF1_M ((MCP_INLINK_DSCR_BF1_V)<<(MCP_INLINK_DSCR_BF1_S)) -#define MCP_INLINK_DSCR_BF1_V 0xFFFFFFFF -#define MCP_INLINK_DSCR_BF1_S 0 - -#define MCP_OUTLINK_DSCR_REG (DR_REG_MCP_BASE + 0x0030) -/* MCP_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define MCP_OUTLINK_DSCR 0xFFFFFFFF -#define MCP_OUTLINK_DSCR_M ((MCP_OUTLINK_DSCR_V)<<(MCP_OUTLINK_DSCR_S)) -#define MCP_OUTLINK_DSCR_V 0xFFFFFFFF -#define MCP_OUTLINK_DSCR_S 0 - -#define MCP_OUTLINK_DSCR_BF0_REG (DR_REG_MCP_BASE + 0x0034) -/* MCP_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define MCP_OUTLINK_DSCR_BF0 0xFFFFFFFF -#define MCP_OUTLINK_DSCR_BF0_M ((MCP_OUTLINK_DSCR_BF0_V)<<(MCP_OUTLINK_DSCR_BF0_S)) -#define MCP_OUTLINK_DSCR_BF0_V 0xFFFFFFFF -#define MCP_OUTLINK_DSCR_BF0_S 0 - -#define MCP_OUTLINK_DSCR_BF1_REG (DR_REG_MCP_BASE + 0x0038) -/* MCP_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define MCP_OUTLINK_DSCR_BF1 0xFFFFFFFF -#define MCP_OUTLINK_DSCR_BF1_M ((MCP_OUTLINK_DSCR_BF1_V)<<(MCP_OUTLINK_DSCR_BF1_S)) -#define MCP_OUTLINK_DSCR_BF1_V 0xFFFFFFFF -#define MCP_OUTLINK_DSCR_BF1_S 0 - -#define MCP_CONF_REG (DR_REG_MCP_BASE + 0x003c) -/* MCP_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define MCP_CLK_EN (BIT(31)) -#define MCP_CLK_EN_M (BIT(31)) -#define MCP_CLK_EN_V 0x1 -#define MCP_CLK_EN_S 31 -/* MCP_CRC_OUT_REVERSE_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define MCP_CRC_OUT_REVERSE_EN (BIT(11)) -#define MCP_CRC_OUT_REVERSE_EN_M (BIT(11)) -#define MCP_CRC_OUT_REVERSE_EN_V 0x1 -#define MCP_CRC_OUT_REVERSE_EN_S 11 -/* MCP_CRC_BIG_ENDIAN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to reorder the bit of data which will be send to excute crc.*/ -#define MCP_CRC_BIG_ENDIAN_EN (BIT(10)) -#define MCP_CRC_BIG_ENDIAN_EN_M (BIT(10)) -#define MCP_CRC_BIG_ENDIAN_EN_V 0x1 -#define MCP_CRC_BIG_ENDIAN_EN_S 10 -/* MCP_CRC_CAL_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit enable crc calculation function.*/ -#define MCP_CRC_CAL_EN (BIT(9)) -#define MCP_CRC_CAL_EN_M (BIT(9)) -#define MCP_CRC_CAL_EN_V 0x1 -#define MCP_CRC_CAL_EN_S 9 -/* MCP_CRC_CAL_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to reset crc calculation.*/ -#define MCP_CRC_CAL_RESET (BIT(8)) -#define MCP_CRC_CAL_RESET_M (BIT(8)) -#define MCP_CRC_CAL_RESET_V 0x1 -#define MCP_CRC_CAL_RESET_S 8 -/* MCP_CHECK_OWNER : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to enable owner bit check in descriptor.*/ -#define MCP_CHECK_OWNER (BIT(7)) -#define MCP_CHECK_OWNER_M (BIT(7)) -#define MCP_CHECK_OWNER_V 0x1 -#define MCP_CHECK_OWNER_S 7 -/* MCP_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: this bit is used to write back out descriptor when hardware has - already used this descriptor.*/ -#define MCP_OUT_AUTO_WRBACK (BIT(6)) -#define MCP_OUT_AUTO_WRBACK_M (BIT(6)) -#define MCP_OUT_AUTO_WRBACK_V 0x1 -#define MCP_OUT_AUTO_WRBACK_S 6 -/* MCP_IN_OWNER : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is used to configure the owner bit in IN descriptor.*/ -#define MCP_IN_OWNER (BIT(5)) -#define MCP_IN_OWNER_M (BIT(5)) -#define MCP_IN_OWNER_V 0x1 -#define MCP_IN_OWNER_S 5 -/* MCP_OUT_OWNER : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is used to configure the owner bit in OUT descriptor. This - is effective only when you set reg_out_auto_wrback.*/ -#define MCP_OUT_OWNER (BIT(4)) -#define MCP_OUT_OWNER_M (BIT(4)) -#define MCP_OUT_OWNER_V 0x1 -#define MCP_OUT_OWNER_S 4 -/* MCP_FIFO_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define MCP_FIFO_RST (BIT(3)) -#define MCP_FIFO_RST_M (BIT(3)) -#define MCP_FIFO_RST_V 0x1 -#define MCP_FIFO_RST_S 3 -/* MCP_CMDFIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: set this bit to reset in_cmdfifo and out_cmdfifo.*/ -#define MCP_CMDFIFO_RST (BIT(2)) -#define MCP_CMDFIFO_RST_M (BIT(2)) -#define MCP_CMDFIFO_RST_V 0x1 -#define MCP_CMDFIFO_RST_S 2 -/* MCP_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: set this bit to reset out_inf state machine.*/ -#define MCP_OUT_RST (BIT(1)) -#define MCP_OUT_RST_M (BIT(1)) -#define MCP_OUT_RST_V 0x1 -#define MCP_OUT_RST_S 1 -/* MCP_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: set this bit to reset in_inf state machine.*/ -#define MCP_IN_RST (BIT(0)) -#define MCP_IN_RST_M (BIT(0)) -#define MCP_IN_RST_V 0x1 -#define MCP_IN_RST_S 0 - -#define MCP_IN_ST_REG (DR_REG_MCP_BASE + 0x0040) -/* MCP_FIFO_EMPTY : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define MCP_FIFO_EMPTY (BIT(23)) -#define MCP_FIFO_EMPTY_M (BIT(23)) -#define MCP_FIFO_EMPTY_V 0x1 -#define MCP_FIFO_EMPTY_S 23 -/* MCP_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: */ -#define MCP_IN_STATE 0x00000007 -#define MCP_IN_STATE_M ((MCP_IN_STATE_V)<<(MCP_IN_STATE_S)) -#define MCP_IN_STATE_V 0x7 -#define MCP_IN_STATE_S 20 -/* MCP_IN_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: */ -#define MCP_IN_DSCR_STATE 0x00000003 -#define MCP_IN_DSCR_STATE_M ((MCP_IN_DSCR_STATE_V)<<(MCP_IN_DSCR_STATE_S)) -#define MCP_IN_DSCR_STATE_V 0x3 -#define MCP_IN_DSCR_STATE_S 18 -/* MCP_INLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: */ -#define MCP_INLINK_DSCR_ADDR 0x0003FFFF -#define MCP_INLINK_DSCR_ADDR_M ((MCP_INLINK_DSCR_ADDR_V)<<(MCP_INLINK_DSCR_ADDR_S)) -#define MCP_INLINK_DSCR_ADDR_V 0x3FFFF -#define MCP_INLINK_DSCR_ADDR_S 0 - -#define MCP_OUT_ST_REG (DR_REG_MCP_BASE + 0x0044) -/* MCP_FIFO_FULL : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define MCP_FIFO_FULL (BIT(23)) -#define MCP_FIFO_FULL_M (BIT(23)) -#define MCP_FIFO_FULL_V 0x1 -#define MCP_FIFO_FULL_S 23 -/* MCP_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: */ -#define MCP_OUT_STATE 0x00000007 -#define MCP_OUT_STATE_M ((MCP_OUT_STATE_V)<<(MCP_OUT_STATE_S)) -#define MCP_OUT_STATE_V 0x7 -#define MCP_OUT_STATE_S 20 -/* MCP_OUT_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */ -/*description: */ -#define MCP_OUT_DSCR_STATE 0x00000003 -#define MCP_OUT_DSCR_STATE_M ((MCP_OUT_DSCR_STATE_V)<<(MCP_OUT_DSCR_STATE_S)) -#define MCP_OUT_DSCR_STATE_V 0x3 -#define MCP_OUT_DSCR_STATE_S 18 -/* MCP_OUTLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */ -/*description: */ -#define MCP_OUTLINK_DSCR_ADDR 0x0003FFFF -#define MCP_OUTLINK_DSCR_ADDR_M ((MCP_OUTLINK_DSCR_ADDR_V)<<(MCP_OUTLINK_DSCR_ADDR_S)) -#define MCP_OUTLINK_DSCR_ADDR_V 0x3FFFF -#define MCP_OUTLINK_DSCR_ADDR_S 0 - -#define MCP_CRC_OUT_REG (DR_REG_MCP_BASE + 0x0048) -/* MCP_CRC_RESULT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define MCP_CRC_RESULT 0xFFFFFFFF -#define MCP_CRC_RESULT_M ((MCP_CRC_RESULT_V)<<(MCP_CRC_RESULT_S)) -#define MCP_CRC_RESULT_V 0xFFFFFFFF -#define MCP_CRC_RESULT_S 0 - -#define MCP_DATE_REG (DR_REG_MCP_BASE + 0x00fc) -/* MCP_DMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h18082000 ; */ -/*description: */ -#define MCP_DMA_DATE 0xFFFFFFFF -#define MCP_DMA_DATE_M ((MCP_DMA_DATE_V)<<(MCP_DMA_DATE_S)) -#define MCP_DMA_DATE_V 0xFFFFFFFF -#define MCP_DMA_DATE_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_MCP_REG_H_ */ - - diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/mcp_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/mcp_struct.h deleted file mode 100644 index 6648a48c..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/mcp_struct.h +++ /dev/null @@ -1,203 +0,0 @@ -// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_MCP_STRUCT_H_ -#define _SOC_MCP_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t in_done: 1; - uint32_t in_suc_eof: 1; - uint32_t out_done: 1; - uint32_t out_eof: 1; - uint32_t in_dscr_err: 1; - uint32_t out_dscr_err: 1; - uint32_t in_dscr_empty: 1; - uint32_t out_total_eof: 1; - uint32_t crc_done: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t in_done: 1; - uint32_t in_suc_eof: 1; - uint32_t out_done: 1; - uint32_t out_eof: 1; - uint32_t in_dscr_err: 1; - uint32_t out_dscr_err: 1; - uint32_t in_dscr_empty: 1; - uint32_t out_total_eof: 1; - uint32_t crc_done: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t in_done: 1; - uint32_t in_suc_eof: 1; - uint32_t out_done: 1; - uint32_t out_eof: 1; - uint32_t in_dscr_err: 1; - uint32_t out_dscr_err: 1; - uint32_t in_dscr_empty: 1; - uint32_t out_total_eof: 1; - uint32_t crc_done: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t in_done: 1; - uint32_t in_suc_eof: 1; - uint32_t out_done: 1; - uint32_t out_eof: 1; - uint32_t in_dscr_err: 1; - uint32_t out_dscr_err: 1; - uint32_t in_dscr_empty: 1; - uint32_t out_total_eof: 1; - uint32_t crc_done: 1; - uint32_t reserved9: 23; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t addr: 20; - uint32_t reserved20: 8; - uint32_t stop: 1; - uint32_t start: 1; - uint32_t restart: 1; - uint32_t park: 1; - }; - uint32_t val; - } out_link; - union { - struct { - uint32_t addr: 20; - uint32_t reserved20: 8; - uint32_t stop: 1; - uint32_t start: 1; - uint32_t restart: 1; - uint32_t park: 1; - }; - uint32_t val; - } in_link; - uint32_t out_eof_des_addr; /**/ - uint32_t in_eof_des_addr; /**/ - uint32_t out_eof_bfr_des_addr; /**/ - uint32_t inlink_dscr; /**/ - uint32_t inlink_dscr_bf0; /**/ - uint32_t inlink_dscr_bf1; /**/ - uint32_t outlink_dscr; /**/ - uint32_t outlink_dscr_bf0; /**/ - uint32_t outlink_dscr_bf1; /**/ - union { - struct { - uint32_t in_rst: 1; /*set this bit to reset in_inf state machine.*/ - uint32_t out_rst: 1; /*set this bit to reset out_inf state machine.*/ - uint32_t cmdfifo_rst: 1; /*set this bit to reset in_cmdfifo and out_cmdfifo.*/ - uint32_t fifo_rst: 1; - uint32_t out_owner: 1; /*This is used to configure the owner bit in OUT descriptor. This is effective only when you set reg_out_auto_wrback.*/ - uint32_t in_owner: 1; /*This is used to configure the owner bit in IN descriptor.*/ - uint32_t out_auto_wrback: 1; /*this bit is used to write back out descriptor when hardware has already used this descriptor.*/ - uint32_t check_owner: 1; /*Set this bit to enable owner bit check in descriptor.*/ - uint32_t crc_cal_reset: 1; /*Set this bit to reset crc calculation.*/ - uint32_t crc_cal_en: 1; /*Set this bit enable crc calculation function.*/ - uint32_t crc_big_endian_en: 1; /*Set this bit to reorder the bit of data which will be send to excute crc.*/ - uint32_t crc_out_reverse_en: 1; - uint32_t reserved12: 19; - uint32_t clk_en: 1; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t dscr_addr: 18; - uint32_t dscr_state: 2; - uint32_t state: 3; - uint32_t fifo_empty: 1; - uint32_t reserved24: 8; - }; - uint32_t val; - } in_st; - union { - struct { - uint32_t dscr_addr: 18; - uint32_t dscr_state: 2; - uint32_t state: 3; - uint32_t fifo_full: 1; - uint32_t reserved24: 8; - }; - uint32_t val; - } out_st; - uint32_t crc_out; /**/ - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t date; /**/ -} mcp_dev_t; -extern mcp_dev_t MCP; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_MCP_STRUCT_H_ */ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/periph_defs.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/periph_defs.h index d890f74f..40a1e559 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/periph_defs.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/periph_defs.h @@ -43,7 +43,7 @@ typedef enum { PERIPH_HSPI_MODULE, //SPI3 PERIPH_SPI2_DMA_MODULE, PERIPH_SPI3_DMA_MODULE, - PERIPH_CAN_MODULE, + PERIPH_TWAI_MODULE, PERIPH_RNG_MODULE, PERIPH_WIFI_MODULE, PERIPH_WIFI_BT_COMMON_MODULE, @@ -107,7 +107,7 @@ typedef enum { ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/ ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ - ETS_CAN_INTR_SOURCE , /**< interrupt of can, level*/ + ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc.h index 2f7ba5c4..d90804e3 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc.h @@ -687,14 +687,6 @@ typedef struct { void rtc_sleep_init(rtc_sleep_config_t cfg); -/** - * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source - * @param t value of RTC counter at which wakeup from sleep will happen; - * only the lower 48 bits are used - */ -void rtc_sleep_set_wakeup_time(uint64_t t); - - #define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup #define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup #define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only) @@ -809,6 +801,7 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config(void); */ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_reg.h index de61f173..8128c482 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_reg.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_reg.h @@ -3114,30 +3114,30 @@ extern "C" { #define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) #define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 #define RTC_CNTL_TOUCH_DEBOUNCE_S 25 -/* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ +/* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ /*description: */ -#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 -#define RTC_CNTL_TOUCH_HYSTERESIS_M ((RTC_CNTL_TOUCH_HYSTERESIS_V)<<(RTC_CNTL_TOUCH_HYSTERESIS_S)) -#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x3 -#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 +#define RTC_CNTL_TOUCH_CONFIG3 0x00000003 +#define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V)<<(RTC_CNTL_TOUCH_CONFIG3_S)) +#define RTC_CNTL_TOUCH_CONFIG3_V 0x3 +#define RTC_CNTL_TOUCH_CONFIG3_S 23 /* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ /*description: */ #define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 #define RTC_CNTL_TOUCH_NOISE_THRES_S 21 -/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ +/* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ /*description: */ -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)) -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x3 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 -/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ -/*description: negative threshold counter limit*/ -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)) -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0xF -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 +#define RTC_CNTL_TOUCH_CONFIG2 0x00000003 +#define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V)<<(RTC_CNTL_TOUCH_CONFIG2_S)) +#define RTC_CNTL_TOUCH_CONFIG2_V 0x3 +#define RTC_CNTL_TOUCH_CONFIG2_S 19 +/* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_CONFIG1 0x0000000F +#define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V)<<(RTC_CNTL_TOUCH_CONFIG1_S)) +#define RTC_CNTL_TOUCH_CONFIG1_V 0xF +#define RTC_CNTL_TOUCH_CONFIG1_S 15 /* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ /*description: touch jitter step*/ #define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_struct.h index e2981358..4a901a32 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_struct.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/rtc_cntl_struct.h @@ -800,10 +800,10 @@ typedef volatile struct { uint32_t reserved0: 9; uint32_t touch_smooth_lvl: 2; uint32_t touch_jitter_step: 4; /*touch jitter step*/ - uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/ - uint32_t touch_neg_noise_thres: 2; + uint32_t config1: 4; + uint32_t config2: 2; uint32_t touch_noise_thres: 2; - uint32_t touch_hysteresis: 2; + uint32_t config3: 2; uint32_t touch_debounce: 3; /*debounce counter*/ uint32_t touch_filter_mode: 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ uint32_t touch_filter_en: 1; /*touch filter enable*/ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_reg.h index b8c465f5..04e29f13 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_reg.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_reg.h @@ -631,7 +631,7 @@ extern "C" { #define SENS_TOUCH_DENOISE_END_V 0x1 #define SENS_TOUCH_DENOISE_END_S 18 /* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ -/*description: 3: smooth data 2: baseline 1 0: raw_data*/ +/*description: 3: smooth data 2: benchmark 1 0: raw_data*/ #define SENS_TOUCH_DATA_SEL 0x00000003 #define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S)) #define SENS_TOUCH_DATA_SEL_V 0x3 diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_struct.h index ae0f6931..5f56714e 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_struct.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/sens_struct.h @@ -225,7 +225,7 @@ typedef volatile struct { struct { uint32_t touch_outen: 15; /*touch controller output enable*/ uint32_t touch_status_clr: 1; /*clear all touch active status*/ - uint32_t touch_data_sel: 2; /*3: smooth data 2: baseline 1 0: raw_data*/ + uint32_t touch_data_sel: 2; /*3: smooth data 2: benchmark 1 0: raw_data*/ uint32_t touch_denoise_end: 1; /*touch_denoise_done*/ uint32_t touch_unit_end: 1; /*touch_unit_done*/ uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/slc_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/slc_reg.h deleted file mode 100644 index a4f59af9..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/slc_reg.h +++ /dev/null @@ -1,1914 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SLC_REG_H_ -#define _SOC_SLC_REG_H_ - - -#ifdef __cplusplus -extern "C" { -#endif -#include "soc.h" -#define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0) -/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_MASK_EN (BIT(18)) -#define SLC_SLC0_WR_RETRY_MASK_EN_M (BIT(18)) -#define SLC_SLC0_WR_RETRY_MASK_EN_V 0x1 -#define SLC_SLC0_WR_RETRY_MASK_EN_S 18 -/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */ -/*description: */ -#define SLC_SLC0_TOKEN_SEL (BIT(15)) -#define SLC_SLC0_TOKEN_SEL_M (BIT(15)) -#define SLC_SLC0_TOKEN_SEL_V 0x1 -#define SLC_SLC0_TOKEN_SEL_S 15 -/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */ -/*description: */ -#define SLC_SLC0_TOKEN_AUTO_CLR (BIT(14)) -#define SLC_SLC0_TOKEN_AUTO_CLR_M (BIT(14)) -#define SLC_SLC0_TOKEN_AUTO_CLR_V 0x1 -#define SLC_SLC0_TOKEN_AUTO_CLR_S 14 -/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_TXDATA_BURST_EN (BIT(13)) -#define SLC_SLC0_TXDATA_BURST_EN_M (BIT(13)) -#define SLC_SLC0_TXDATA_BURST_EN_V 0x1 -#define SLC_SLC0_TXDATA_BURST_EN_S 13 -/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_TXDSCR_BURST_EN (BIT(12)) -#define SLC_SLC0_TXDSCR_BURST_EN_M (BIT(12)) -#define SLC_SLC0_TXDSCR_BURST_EN_V 0x1 -#define SLC_SLC0_TXDSCR_BURST_EN_S 12 -/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_AUTO_RET (BIT(11)) -#define SLC_SLC0_TXLINK_AUTO_RET_M (BIT(11)) -#define SLC_SLC0_TXLINK_AUTO_RET_V 0x1 -#define SLC_SLC0_TXLINK_AUTO_RET_S 11 -/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_AUTO_RET (BIT(10)) -#define SLC_SLC0_RXLINK_AUTO_RET_M (BIT(10)) -#define SLC_SLC0_RXLINK_AUTO_RET_V 0x1 -#define SLC_SLC0_RXLINK_AUTO_RET_S 10 -/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RXDATA_BURST_EN (BIT(9)) -#define SLC_SLC0_RXDATA_BURST_EN_M (BIT(9)) -#define SLC_SLC0_RXDATA_BURST_EN_V 0x1 -#define SLC_SLC0_RXDATA_BURST_EN_S 9 -/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RXDSCR_BURST_EN (BIT(8)) -#define SLC_SLC0_RXDSCR_BURST_EN_M (BIT(8)) -#define SLC_SLC0_RXDSCR_BURST_EN_V 0x1 -#define SLC_SLC0_RXDSCR_BURST_EN_S 8 -/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_NO_RESTART_CLR (BIT(7)) -#define SLC_SLC0_RX_NO_RESTART_CLR_M (BIT(7)) -#define SLC_SLC0_RX_NO_RESTART_CLR_V 0x1 -#define SLC_SLC0_RX_NO_RESTART_CLR_S 7 -/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_AUTO_WRBACK (BIT(6)) -#define SLC_SLC0_RX_AUTO_WRBACK_M (BIT(6)) -#define SLC_SLC0_RX_AUTO_WRBACK_V 0x1 -#define SLC_SLC0_RX_AUTO_WRBACK_S 6 -/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RX_LOOP_TEST (BIT(5)) -#define SLC_SLC0_RX_LOOP_TEST_M (BIT(5)) -#define SLC_SLC0_RX_LOOP_TEST_V 0x1 -#define SLC_SLC0_RX_LOOP_TEST_S 5 -/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_TX_LOOP_TEST (BIT(4)) -#define SLC_SLC0_TX_LOOP_TEST_M (BIT(4)) -#define SLC_SLC0_TX_LOOP_TEST_V 0x1 -#define SLC_SLC0_TX_LOOP_TEST_S 4 -/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_AHBM_RST (BIT(3)) -#define SLC_AHBM_RST_M (BIT(3)) -#define SLC_AHBM_RST_V 0x1 -#define SLC_AHBM_RST_S 3 -/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_AHBM_FIFO_RST (BIT(2)) -#define SLC_AHBM_FIFO_RST_M (BIT(2)) -#define SLC_AHBM_FIFO_RST_V 0x1 -#define SLC_AHBM_FIFO_RST_S 2 -/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_RST (BIT(1)) -#define SLC_SLC0_RX_RST_M (BIT(1)) -#define SLC_SLC0_RX_RST_V 0x1 -#define SLC_SLC0_RX_RST_S 1 -/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_RST (BIT(0)) -#define SLC_SLC0_TX_RST_M (BIT(0)) -#define SLC_SLC0_TX_RST_V 0x1 -#define SLC_SLC0_TX_RST_S 0 - -#define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) -/* SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x1 -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 -/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V 0x1 -#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S 26 -/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CMD_DTC_INT_RAW (BIT(25)) -#define SLC_CMD_DTC_INT_RAW_M (BIT(25)) -#define SLC_CMD_DTC_INT_RAW_V 0x1 -#define SLC_CMD_DTC_INT_RAW_S 25 -/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V 0x1 -#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S 24 -/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V 0x1 -#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S 23 -/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V 0x1 -#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S 22 -/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x1 -#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 -/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V 0x1 -#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S 20 -/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V 0x1 -#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S 19 -/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INT_RAW (BIT(18)) -#define SLC_SLC0_TOHOST_INT_RAW_M (BIT(18)) -#define SLC_SLC0_TOHOST_INT_RAW_V 0x1 -#define SLC_SLC0_TOHOST_INT_RAW_S 18 -/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_INT_RAW (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_RAW_M (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_RAW_V 0x1 -#define SLC_SLC0_RX_EOF_INT_RAW_S 17 -/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_INT_RAW (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_RAW_M (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_RAW_V 0x1 -#define SLC_SLC0_RX_DONE_INT_RAW_S 16 -/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V 0x1 -#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S 15 -/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DONE_INT_RAW (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_RAW_M (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_RAW_V 0x1 -#define SLC_SLC0_TX_DONE_INT_RAW_S 14 -/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1 -#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S 13 -/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1 -#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S 12 -/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_OVF_INT_RAW (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_RAW_M (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_RAW_V 0x1 -#define SLC_SLC0_TX_OVF_INT_RAW_S 11 -/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_UDF_INT_RAW (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_RAW_M (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_RAW_V 0x1 -#define SLC_SLC0_RX_UDF_INT_RAW_S 10 -/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_START_INT_RAW (BIT(9)) -#define SLC_SLC0_TX_START_INT_RAW_M (BIT(9)) -#define SLC_SLC0_TX_START_INT_RAW_V 0x1 -#define SLC_SLC0_TX_START_INT_RAW_S 9 -/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_START_INT_RAW (BIT(8)) -#define SLC_SLC0_RX_START_INT_RAW_M (BIT(8)) -#define SLC_SLC0_RX_START_INT_RAW_V 0x1 -#define SLC_SLC0_RX_START_INT_RAW_S 8 -/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT7_INT_RAW (BIT(7)) -#define SLC_FRHOST_BIT7_INT_RAW_M (BIT(7)) -#define SLC_FRHOST_BIT7_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT7_INT_RAW_S 7 -/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT6_INT_RAW (BIT(6)) -#define SLC_FRHOST_BIT6_INT_RAW_M (BIT(6)) -#define SLC_FRHOST_BIT6_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT6_INT_RAW_S 6 -/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT5_INT_RAW (BIT(5)) -#define SLC_FRHOST_BIT5_INT_RAW_M (BIT(5)) -#define SLC_FRHOST_BIT5_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT5_INT_RAW_S 5 -/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT4_INT_RAW (BIT(4)) -#define SLC_FRHOST_BIT4_INT_RAW_M (BIT(4)) -#define SLC_FRHOST_BIT4_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT4_INT_RAW_S 4 -/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT3_INT_RAW (BIT(3)) -#define SLC_FRHOST_BIT3_INT_RAW_M (BIT(3)) -#define SLC_FRHOST_BIT3_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT3_INT_RAW_S 3 -/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT2_INT_RAW (BIT(2)) -#define SLC_FRHOST_BIT2_INT_RAW_M (BIT(2)) -#define SLC_FRHOST_BIT2_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT2_INT_RAW_S 2 -/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT1_INT_RAW (BIT(1)) -#define SLC_FRHOST_BIT1_INT_RAW_M (BIT(1)) -#define SLC_FRHOST_BIT1_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT1_INT_RAW_S 1 -/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT0_INT_RAW (BIT(0)) -#define SLC_FRHOST_BIT0_INT_RAW_M (BIT(0)) -#define SLC_FRHOST_BIT0_INT_RAW_V 0x1 -#define SLC_FRHOST_BIT0_INT_RAW_S 0 - -#define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8) -/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_M (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x1 -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 -/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V 0x1 -#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S 26 -/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CMD_DTC_INT_ST (BIT(25)) -#define SLC_CMD_DTC_INT_ST_M (BIT(25)) -#define SLC_CMD_DTC_INT_ST_V 0x1 -#define SLC_CMD_DTC_INT_ST_S 25 -/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ST_M (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ST_V 0x1 -#define SLC_SLC0_TX_ERR_EOF_INT_ST_S 24 -/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V 0x1 -#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S 23 -/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ST_M (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ST_V 0x1 -#define SLC_SLC0_HOST_RD_ACK_INT_ST_S 22 -/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x1 -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 -/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V 0x1 -#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S 20 -/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V 0x1 -#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S 19 -/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INT_ST (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ST_M (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ST_V 0x1 -#define SLC_SLC0_TOHOST_INT_ST_S 18 -/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_INT_ST (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ST_M (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ST_V 0x1 -#define SLC_SLC0_RX_EOF_INT_ST_S 17 -/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_INT_ST (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ST_M (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ST_V 0x1 -#define SLC_SLC0_RX_DONE_INT_ST_S 16 -/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ST_M (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ST_V 0x1 -#define SLC_SLC0_TX_SUC_EOF_INT_ST_S 15 -/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DONE_INT_ST (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ST_M (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ST_V 0x1 -#define SLC_SLC0_TX_DONE_INT_ST_S 14 -/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V 0x1 -#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S 13 -/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V 0x1 -#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S 12 -/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_OVF_INT_ST (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ST_M (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ST_V 0x1 -#define SLC_SLC0_TX_OVF_INT_ST_S 11 -/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_UDF_INT_ST (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ST_M (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ST_V 0x1 -#define SLC_SLC0_RX_UDF_INT_ST_S 10 -/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_START_INT_ST (BIT(9)) -#define SLC_SLC0_TX_START_INT_ST_M (BIT(9)) -#define SLC_SLC0_TX_START_INT_ST_V 0x1 -#define SLC_SLC0_TX_START_INT_ST_S 9 -/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_START_INT_ST (BIT(8)) -#define SLC_SLC0_RX_START_INT_ST_M (BIT(8)) -#define SLC_SLC0_RX_START_INT_ST_V 0x1 -#define SLC_SLC0_RX_START_INT_ST_S 8 -/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT7_INT_ST (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ST_M (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ST_V 0x1 -#define SLC_FRHOST_BIT7_INT_ST_S 7 -/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT6_INT_ST (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ST_M (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ST_V 0x1 -#define SLC_FRHOST_BIT6_INT_ST_S 6 -/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT5_INT_ST (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ST_M (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ST_V 0x1 -#define SLC_FRHOST_BIT5_INT_ST_S 5 -/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT4_INT_ST (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ST_M (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ST_V 0x1 -#define SLC_FRHOST_BIT4_INT_ST_S 4 -/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT3_INT_ST (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ST_M (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ST_V 0x1 -#define SLC_FRHOST_BIT3_INT_ST_S 3 -/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT2_INT_ST (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ST_M (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ST_V 0x1 -#define SLC_FRHOST_BIT2_INT_ST_S 2 -/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT1_INT_ST (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ST_M (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ST_V 0x1 -#define SLC_FRHOST_BIT1_INT_ST_S 1 -/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT0_INT_ST (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ST_M (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ST_V 0x1 -#define SLC_FRHOST_BIT0_INT_ST_S 0 - -#define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC) -/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x1 -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 -/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V 0x1 -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S 26 -/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CMD_DTC_INT_ENA (BIT(25)) -#define SLC_CMD_DTC_INT_ENA_M (BIT(25)) -#define SLC_CMD_DTC_INT_ENA_V 0x1 -#define SLC_CMD_DTC_INT_ENA_S 25 -/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V 0x1 -#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S 24 -/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V 0x1 -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S 23 -/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V 0x1 -#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S 22 -/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x1 -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 -/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V 0x1 -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S 20 -/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V 0x1 -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S 19 -/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INT_ENA (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ENA_M (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ENA_V 0x1 -#define SLC_SLC0_TOHOST_INT_ENA_S 18 -/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_INT_ENA (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ENA_M (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ENA_V 0x1 -#define SLC_SLC0_RX_EOF_INT_ENA_S 17 -/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_INT_ENA (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ENA_M (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ENA_V 0x1 -#define SLC_SLC0_RX_DONE_INT_ENA_S 16 -/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V 0x1 -#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S 15 -/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DONE_INT_ENA (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ENA_M (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ENA_V 0x1 -#define SLC_SLC0_TX_DONE_INT_ENA_S 14 -/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S 13 -/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S 12 -/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_OVF_INT_ENA (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ENA_M (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ENA_V 0x1 -#define SLC_SLC0_TX_OVF_INT_ENA_S 11 -/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_UDF_INT_ENA (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ENA_M (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ENA_V 0x1 -#define SLC_SLC0_RX_UDF_INT_ENA_S 10 -/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_START_INT_ENA (BIT(9)) -#define SLC_SLC0_TX_START_INT_ENA_M (BIT(9)) -#define SLC_SLC0_TX_START_INT_ENA_V 0x1 -#define SLC_SLC0_TX_START_INT_ENA_S 9 -/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_START_INT_ENA (BIT(8)) -#define SLC_SLC0_RX_START_INT_ENA_M (BIT(8)) -#define SLC_SLC0_RX_START_INT_ENA_V 0x1 -#define SLC_SLC0_RX_START_INT_ENA_S 8 -/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT7_INT_ENA (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ENA_M (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT7_INT_ENA_S 7 -/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT6_INT_ENA (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ENA_M (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT6_INT_ENA_S 6 -/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT5_INT_ENA (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ENA_M (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT5_INT_ENA_S 5 -/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT4_INT_ENA (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ENA_M (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT4_INT_ENA_S 4 -/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT3_INT_ENA (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ENA_M (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT3_INT_ENA_S 3 -/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT2_INT_ENA (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ENA_M (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT2_INT_ENA_S 2 -/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT1_INT_ENA (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ENA_M (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT1_INT_ENA_S 1 -/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT0_INT_ENA (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ENA_M (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ENA_V 0x1 -#define SLC_FRHOST_BIT0_INT_ENA_S 0 - -#define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) -/* SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x1 -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 -/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V 0x1 -#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S 26 -/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CMD_DTC_INT_CLR (BIT(25)) -#define SLC_CMD_DTC_INT_CLR_M (BIT(25)) -#define SLC_CMD_DTC_INT_CLR_V 0x1 -#define SLC_CMD_DTC_INT_CLR_S 25 -/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V 0x1 -#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S 24 -/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V 0x1 -#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S 23 -/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V 0x1 -#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S 22 -/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x1 -#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 -/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V 0x1 -#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S 20 -/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V 0x1 -#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S 19 -/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INT_CLR (BIT(18)) -#define SLC_SLC0_TOHOST_INT_CLR_M (BIT(18)) -#define SLC_SLC0_TOHOST_INT_CLR_V 0x1 -#define SLC_SLC0_TOHOST_INT_CLR_S 18 -/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_INT_CLR (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_CLR_M (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_CLR_V 0x1 -#define SLC_SLC0_RX_EOF_INT_CLR_S 17 -/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_INT_CLR (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_CLR_M (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_CLR_V 0x1 -#define SLC_SLC0_RX_DONE_INT_CLR_S 16 -/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V 0x1 -#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S 15 -/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DONE_INT_CLR (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_CLR_M (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_CLR_V 0x1 -#define SLC_SLC0_TX_DONE_INT_CLR_S 14 -/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1 -#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S 13 -/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1 -#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S 12 -/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_OVF_INT_CLR (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_CLR_M (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_CLR_V 0x1 -#define SLC_SLC0_TX_OVF_INT_CLR_S 11 -/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_UDF_INT_CLR (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_CLR_M (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_CLR_V 0x1 -#define SLC_SLC0_RX_UDF_INT_CLR_S 10 -/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_START_INT_CLR (BIT(9)) -#define SLC_SLC0_TX_START_INT_CLR_M (BIT(9)) -#define SLC_SLC0_TX_START_INT_CLR_V 0x1 -#define SLC_SLC0_TX_START_INT_CLR_S 9 -/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_START_INT_CLR (BIT(8)) -#define SLC_SLC0_RX_START_INT_CLR_M (BIT(8)) -#define SLC_SLC0_RX_START_INT_CLR_V 0x1 -#define SLC_SLC0_RX_START_INT_CLR_S 8 -/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT7_INT_CLR (BIT(7)) -#define SLC_FRHOST_BIT7_INT_CLR_M (BIT(7)) -#define SLC_FRHOST_BIT7_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT7_INT_CLR_S 7 -/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT6_INT_CLR (BIT(6)) -#define SLC_FRHOST_BIT6_INT_CLR_M (BIT(6)) -#define SLC_FRHOST_BIT6_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT6_INT_CLR_S 6 -/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT5_INT_CLR (BIT(5)) -#define SLC_FRHOST_BIT5_INT_CLR_M (BIT(5)) -#define SLC_FRHOST_BIT5_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT5_INT_CLR_S 5 -/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT4_INT_CLR (BIT(4)) -#define SLC_FRHOST_BIT4_INT_CLR_M (BIT(4)) -#define SLC_FRHOST_BIT4_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT4_INT_CLR_S 4 -/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT3_INT_CLR (BIT(3)) -#define SLC_FRHOST_BIT3_INT_CLR_M (BIT(3)) -#define SLC_FRHOST_BIT3_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT3_INT_CLR_S 3 -/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT2_INT_CLR (BIT(2)) -#define SLC_FRHOST_BIT2_INT_CLR_M (BIT(2)) -#define SLC_FRHOST_BIT2_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT2_INT_CLR_S 2 -/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT1_INT_CLR (BIT(1)) -#define SLC_FRHOST_BIT1_INT_CLR_M (BIT(1)) -#define SLC_FRHOST_BIT1_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT1_INT_CLR_S 1 -/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT0_INT_CLR (BIT(0)) -#define SLC_FRHOST_BIT0_INT_CLR_M (BIT(0)) -#define SLC_FRHOST_BIT0_INT_CLR_V 0x1 -#define SLC_FRHOST_BIT0_INT_CLR_S 0 - -#define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24) -/* SLC_SLC0_RX_BUF_LEN : RO ;bitpos:[13:2] ;default: 12'h0 ; */ -/*description: */ -#define SLC_SLC0_RX_BUF_LEN 0x00000FFF -#define SLC_SLC0_RX_BUF_LEN_M ((SLC_SLC0_RX_BUF_LEN_V)<<(SLC_SLC0_RX_BUF_LEN_S)) -#define SLC_SLC0_RX_BUF_LEN_V 0xFFF -#define SLC_SLC0_RX_BUF_LEN_S 2 -/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RX_EMPTY (BIT(1)) -#define SLC_SLC0_RX_EMPTY_M (BIT(1)) -#define SLC_SLC0_RX_EMPTY_V 0x1 -#define SLC_SLC0_RX_EMPTY_S 1 -/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_FULL (BIT(0)) -#define SLC_SLC0_RX_FULL_M (BIT(0)) -#define SLC_SLC0_RX_FULL_V 0x1 -#define SLC_SLC0_RX_FULL_S 0 - -#define SLC_0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) -/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: */ -#define SLC_SLC0_RXFIFO_PUSH (BIT(16)) -#define SLC_SLC0_RXFIFO_PUSH_M (BIT(16)) -#define SLC_SLC0_RXFIFO_PUSH_V 0x1 -#define SLC_SLC0_RXFIFO_PUSH_S 16 -/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ -/*description: */ -#define SLC_SLC0_RXFIFO_WDATA 0x000001FF -#define SLC_SLC0_RXFIFO_WDATA_M ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S)) -#define SLC_SLC0_RXFIFO_WDATA_V 0x1FF -#define SLC_SLC0_RXFIFO_WDATA_S 0 - -#define SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30) -/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_TX_EMPTY (BIT(1)) -#define SLC_SLC0_TX_EMPTY_M (BIT(1)) -#define SLC_SLC0_TX_EMPTY_V 0x1 -#define SLC_SLC0_TX_EMPTY_S 1 -/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_FULL (BIT(0)) -#define SLC_SLC0_TX_FULL_M (BIT(0)) -#define SLC_SLC0_TX_FULL_V 0x1 -#define SLC_SLC0_TX_FULL_S 0 - -#define SLC_0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) -/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ -/*description: */ -#define SLC_SLC0_TXFIFO_POP (BIT(16)) -#define SLC_SLC0_TXFIFO_POP_M (BIT(16)) -#define SLC_SLC0_TXFIFO_POP_V 0x1 -#define SLC_SLC0_TXFIFO_POP_S 16 -/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */ -/*description: */ -#define SLC_SLC0_TXFIFO_RDATA 0x000007FF -#define SLC_SLC0_TXFIFO_RDATA_M ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S)) -#define SLC_SLC0_TXFIFO_RDATA_V 0x7FF -#define SLC_SLC0_TXFIFO_RDATA_S 0 - -#define SLC_0RX_LINK_REG (DR_REG_SLC_BASE + 0x3C) -/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_PARK (BIT(31)) -#define SLC_SLC0_RXLINK_PARK_M (BIT(31)) -#define SLC_SLC0_RXLINK_PARK_V 0x1 -#define SLC_SLC0_RXLINK_PARK_S 31 -/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_RESTART (BIT(30)) -#define SLC_SLC0_RXLINK_RESTART_M (BIT(30)) -#define SLC_SLC0_RXLINK_RESTART_V 0x1 -#define SLC_SLC0_RXLINK_RESTART_S 30 -/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_START (BIT(29)) -#define SLC_SLC0_RXLINK_START_M (BIT(29)) -#define SLC_SLC0_RXLINK_START_V 0x1 -#define SLC_SLC0_RXLINK_START_S 29 -/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_STOP (BIT(28)) -#define SLC_SLC0_RXLINK_STOP_M (BIT(28)) -#define SLC_SLC0_RXLINK_STOP_V 0x1 -#define SLC_SLC0_RXLINK_STOP_S 28 -/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_ADDR 0x000FFFFF -#define SLC_SLC0_RXLINK_ADDR_M ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S)) -#define SLC_SLC0_RXLINK_ADDR_V 0xFFFFF -#define SLC_SLC0_RXLINK_ADDR_S 0 - -#define SLC_0TX_LINK_REG (DR_REG_SLC_BASE + 0x40) -/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_PARK (BIT(31)) -#define SLC_SLC0_TXLINK_PARK_M (BIT(31)) -#define SLC_SLC0_TXLINK_PARK_V 0x1 -#define SLC_SLC0_TXLINK_PARK_S 31 -/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_RESTART (BIT(30)) -#define SLC_SLC0_TXLINK_RESTART_M (BIT(30)) -#define SLC_SLC0_TXLINK_RESTART_V 0x1 -#define SLC_SLC0_TXLINK_RESTART_S 30 -/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_START (BIT(29)) -#define SLC_SLC0_TXLINK_START_M (BIT(29)) -#define SLC_SLC0_TXLINK_START_V 0x1 -#define SLC_SLC0_TXLINK_START_S 29 -/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_STOP (BIT(28)) -#define SLC_SLC0_TXLINK_STOP_M (BIT(28)) -#define SLC_SLC0_TXLINK_STOP_V 0x1 -#define SLC_SLC0_TXLINK_STOP_S 28 -/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_ADDR 0x000FFFFF -#define SLC_SLC0_TXLINK_ADDR_M ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S)) -#define SLC_SLC0_TXLINK_ADDR_V 0xFFFFF -#define SLC_SLC0_TXLINK_ADDR_S 0 - -#define SLC_INTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x4C) -/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INTVEC 0x000000FF -#define SLC_SLC0_TOHOST_INTVEC_M ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S)) -#define SLC_SLC0_TOHOST_INTVEC_V 0xFF -#define SLC_SLC0_TOHOST_INTVEC_S 0 - -#define SLC_0TOKEN0_REG (DR_REG_SLC_BASE + 0x50) -/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0 0x00000FFF -#define SLC_SLC0_TOKEN0_M ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S)) -#define SLC_SLC0_TOKEN0_V 0xFFF -#define SLC_SLC0_TOKEN0_S 16 -/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_INC_MORE (BIT(14)) -#define SLC_SLC0_TOKEN0_INC_MORE_M (BIT(14)) -#define SLC_SLC0_TOKEN0_INC_MORE_V 0x1 -#define SLC_SLC0_TOKEN0_INC_MORE_S 14 -/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_INC (BIT(13)) -#define SLC_SLC0_TOKEN0_INC_M (BIT(13)) -#define SLC_SLC0_TOKEN0_INC_V 0x1 -#define SLC_SLC0_TOKEN0_INC_S 13 -/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_WR (BIT(12)) -#define SLC_SLC0_TOKEN0_WR_M (BIT(12)) -#define SLC_SLC0_TOKEN0_WR_V 0x1 -#define SLC_SLC0_TOKEN0_WR_S 12 -/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_WDATA 0x00000FFF -#define SLC_SLC0_TOKEN0_WDATA_M ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S)) -#define SLC_SLC0_TOKEN0_WDATA_V 0xFFF -#define SLC_SLC0_TOKEN0_WDATA_S 0 - -#define SLC_0TOKEN1_REG (DR_REG_SLC_BASE + 0x54) -/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1 0x00000FFF -#define SLC_SLC0_TOKEN1_M ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S)) -#define SLC_SLC0_TOKEN1_V 0xFFF -#define SLC_SLC0_TOKEN1_S 16 -/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_INC_MORE (BIT(14)) -#define SLC_SLC0_TOKEN1_INC_MORE_M (BIT(14)) -#define SLC_SLC0_TOKEN1_INC_MORE_V 0x1 -#define SLC_SLC0_TOKEN1_INC_MORE_S 14 -/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_INC (BIT(13)) -#define SLC_SLC0_TOKEN1_INC_M (BIT(13)) -#define SLC_SLC0_TOKEN1_INC_V 0x1 -#define SLC_SLC0_TOKEN1_INC_S 13 -/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_WR (BIT(12)) -#define SLC_SLC0_TOKEN1_WR_M (BIT(12)) -#define SLC_SLC0_TOKEN1_WR_V 0x1 -#define SLC_SLC0_TOKEN1_WR_S 12 -/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_WDATA 0x00000FFF -#define SLC_SLC0_TOKEN1_WDATA_M ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S)) -#define SLC_SLC0_TOKEN1_WDATA_V 0xFFF -#define SLC_SLC0_TOKEN1_WDATA_S 0 - -#define SLC_CONF1_REG (DR_REG_SLC_BASE + 0x60) -/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CLK_EN (BIT(22)) -#define SLC_CLK_EN_M (BIT(22)) -#define SLC_CLK_EN_V 0x1 -#define SLC_CLK_EN_S 22 -/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_HOST_INT_LEVEL_SEL (BIT(19)) -#define SLC_HOST_INT_LEVEL_SEL_M (BIT(19)) -#define SLC_HOST_INT_LEVEL_SEL_V 0x1 -#define SLC_HOST_INT_LEVEL_SEL_S 19 -/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RX_STITCH_EN (BIT(6)) -#define SLC_SLC0_RX_STITCH_EN_M (BIT(6)) -#define SLC_SLC0_RX_STITCH_EN_V 0x1 -#define SLC_SLC0_RX_STITCH_EN_S 6 -/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_TX_STITCH_EN (BIT(5)) -#define SLC_SLC0_TX_STITCH_EN_M (BIT(5)) -#define SLC_SLC0_TX_STITCH_EN_V 0x1 -#define SLC_SLC0_TX_STITCH_EN_S 5 -/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_LEN_AUTO_CLR (BIT(4)) -#define SLC_SLC0_LEN_AUTO_CLR_M (BIT(4)) -#define SLC_SLC0_LEN_AUTO_CLR_V 0x1 -#define SLC_SLC0_LEN_AUTO_CLR_S 4 -/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SLC_CMD_HOLD_EN (BIT(3)) -#define SLC_CMD_HOLD_EN_M (BIT(3)) -#define SLC_CMD_HOLD_EN_V 0x1 -#define SLC_CMD_HOLD_EN_S 3 -/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_CHECK_SUM_EN (BIT(2)) -#define SLC_SLC0_RX_CHECK_SUM_EN_M (BIT(2)) -#define SLC_SLC0_RX_CHECK_SUM_EN_V 0x1 -#define SLC_SLC0_RX_CHECK_SUM_EN_S 2 -/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_CHECK_SUM_EN (BIT(1)) -#define SLC_SLC0_TX_CHECK_SUM_EN_M (BIT(1)) -#define SLC_SLC0_TX_CHECK_SUM_EN_V 0x1 -#define SLC_SLC0_TX_CHECK_SUM_EN_S 1 -/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_CHECK_OWNER (BIT(0)) -#define SLC_SLC0_CHECK_OWNER_M (BIT(0)) -#define SLC_SLC0_CHECK_OWNER_V 0x1 -#define SLC_SLC0_CHECK_OWNER_S 0 - -#define SLC_0_STATE0_REG (DR_REG_SLC_BASE + 0x64) -/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_STATE0 0xFFFFFFFF -#define SLC_SLC0_STATE0_M ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S)) -#define SLC_SLC0_STATE0_V 0xFFFFFFFF -#define SLC_SLC0_STATE0_S 0 - -#define SLC_0_STATE1_REG (DR_REG_SLC_BASE + 0x68) -/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_STATE1 0xFFFFFFFF -#define SLC_SLC0_STATE1_M ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S)) -#define SLC_SLC0_STATE1_V 0xFFFFFFFF -#define SLC_SLC0_STATE1_S 0 - -#define SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x74) -/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */ -/*description: */ -#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF -#define SLC_TX_PUSH_IDLE_NUM_M ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S)) -#define SLC_TX_PUSH_IDLE_NUM_V 0xFFFF -#define SLC_TX_PUSH_IDLE_NUM_S 16 -/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */ -/*description: */ -#define SLC_HDA_MAP_128K (BIT(13)) -#define SLC_HDA_MAP_128K_M (BIT(13)) -#define SLC_HDA_MAP_128K_V 0x1 -#define SLC_HDA_MAP_128K_S 13 -/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: */ -#define SLC_SLC0_TX_DUMMY_MODE (BIT(12)) -#define SLC_SLC0_TX_DUMMY_MODE_M (BIT(12)) -#define SLC_SLC0_TX_DUMMY_MODE_V 0x1 -#define SLC_SLC0_TX_DUMMY_MODE_S 12 -/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */ -/*description: */ -#define SLC_FIFO_MAP_ENA 0x0000000F -#define SLC_FIFO_MAP_ENA_M ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S)) -#define SLC_FIFO_MAP_ENA_V 0xF -#define SLC_FIFO_MAP_ENA_S 8 -/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ -/*description: */ -#define SLC_TXEOF_ENA 0x0000003F -#define SLC_TXEOF_ENA_M ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S)) -#define SLC_TXEOF_ENA_V 0x3F -#define SLC_TXEOF_ENA_S 0 - -#define SLC_0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x78) -/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFF -#define SLC_SLC0_TO_EOF_DES_ADDR_M ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S)) -#define SLC_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TO_EOF_DES_ADDR_S 0 - -#define SLC_0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x7C) -/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF -#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S)) -#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S 0 - -#define SLC_0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x80) -/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF -#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S)) -#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S 0 - -#define SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0x90) -/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ -/*description: */ -#define SLC_AHB_TESTADDR 0x00000003 -#define SLC_AHB_TESTADDR_M ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S)) -#define SLC_AHB_TESTADDR_V 0x3 -#define SLC_AHB_TESTADDR_S 4 -/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define SLC_AHB_TESTMODE 0x00000007 -#define SLC_AHB_TESTMODE_M ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S)) -#define SLC_AHB_TESTMODE_V 0x7 -#define SLC_AHB_TESTMODE_S 0 - -#define SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0x94) -/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */ -/*description: */ -#define SLC_FUNC1_ACC_STATE 0x0000001F -#define SLC_FUNC1_ACC_STATE_M ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S)) -#define SLC_FUNC1_ACC_STATE_V 0x1F -#define SLC_FUNC1_ACC_STATE_S 16 -/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */ -/*description: */ -#define SLC_BUS_ST 0x00000007 -#define SLC_BUS_ST_M ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S)) -#define SLC_BUS_ST_V 0x7 -#define SLC_BUS_ST_S 12 -/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SDIO_WAKEUP (BIT(8)) -#define SLC_SDIO_WAKEUP_M (BIT(8)) -#define SLC_SDIO_WAKEUP_V 0x1 -#define SLC_SDIO_WAKEUP_S 8 -/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: */ -#define SLC_FUNC_ST 0x0000000F -#define SLC_FUNC_ST_M ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S)) -#define SLC_FUNC_ST_V 0xF -#define SLC_FUNC_ST_S 4 -#define SLC_FUNC_ST_IDLE 2 -/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: */ -#define SLC_CMD_ST 0x00000007 -#define SLC_CMD_ST_M ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S)) -#define SLC_CMD_ST_V 0x7 -#define SLC_CMD_ST_S 0 -#define SLC_CMD_ST_IDLE 1 - -#define SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0x98) -/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */ -/*description: */ -#define SLC_SLC0_RD_RETRY_THRESHOLD 0x000007FF -#define SLC_SLC0_RD_RETRY_THRESHOLD_M ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S)) -#define SLC_SLC0_RD_RETRY_THRESHOLD_V 0x7FF -#define SLC_SLC0_RD_RETRY_THRESHOLD_S 5 -/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RX_FILL_EN (BIT(4)) -#define SLC_SLC0_RX_FILL_EN_M (BIT(4)) -#define SLC_SLC0_RX_FILL_EN_V 0x1 -#define SLC_SLC0_RX_FILL_EN_S 4 -/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_MODE (BIT(3)) -#define SLC_SLC0_RX_EOF_MODE_M (BIT(3)) -#define SLC_SLC0_RX_EOF_MODE_V 0x1 -#define SLC_SLC0_RX_EOF_MODE_S 3 -/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_FILL_MODE (BIT(2)) -#define SLC_SLC0_RX_FILL_MODE_M (BIT(2)) -#define SLC_SLC0_RX_FILL_MODE_V 0x1 -#define SLC_SLC0_RX_FILL_MODE_S 2 -/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: */ -#define SLC_SLC0_INFOR_NO_REPLACE (BIT(1)) -#define SLC_SLC0_INFOR_NO_REPLACE_M (BIT(1)) -#define SLC_SLC0_INFOR_NO_REPLACE_V 0x1 -#define SLC_SLC0_INFOR_NO_REPLACE_S 1 -/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN_NO_REPLACE (BIT(0)) -#define SLC_SLC0_TOKEN_NO_REPLACE_M (BIT(0)) -#define SLC_SLC0_TOKEN_NO_REPLACE_V 0x1 -#define SLC_SLC0_TOKEN_NO_REPLACE_S 0 - -#define SLC_0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0x9C) -/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_DSCR 0xFFFFFFFF -#define SLC_SLC0_TXLINK_DSCR_M ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S)) -#define SLC_SLC0_TXLINK_DSCR_V 0xFFFFFFFF -#define SLC_SLC0_TXLINK_DSCR_S 0 - -#define SLC_0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xA0) -/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFF -#define SLC_SLC0_TXLINK_DSCR_BF0_M ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S)) -#define SLC_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFF -#define SLC_SLC0_TXLINK_DSCR_BF0_S 0 - -#define SLC_0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xA4) -/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFF -#define SLC_SLC0_TXLINK_DSCR_BF1_M ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S)) -#define SLC_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFF -#define SLC_SLC0_TXLINK_DSCR_BF1_S 0 - -#define SLC_0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xA8) -/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_DSCR 0xFFFFFFFF -#define SLC_SLC0_RXLINK_DSCR_M ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S)) -#define SLC_SLC0_RXLINK_DSCR_V 0xFFFFFFFF -#define SLC_SLC0_RXLINK_DSCR_S 0 - -#define SLC_0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xAC) -/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFF -#define SLC_SLC0_RXLINK_DSCR_BF0_M ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S)) -#define SLC_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFF -#define SLC_SLC0_RXLINK_DSCR_BF0_S 0 - -#define SLC_0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xB0) -/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFF -#define SLC_SLC0_RXLINK_DSCR_BF1_M ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S)) -#define SLC_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFF -#define SLC_SLC0_RXLINK_DSCR_BF1_S 0 - -#define SLC_0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xCC) -/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF -#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S)) -#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S 0 - -#define SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xD4) -/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN 0x00000FFF -#define SLC_SLC0_TOKEN_M ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S)) -#define SLC_SLC0_TOKEN_V 0xFFF -#define SLC_SLC0_TOKEN_S 0 - -#define SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xD8) -/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */ -/*description: */ -#define SLC_WR_RETRY_THRESHOLD 0x000007FF -#define SLC_WR_RETRY_THRESHOLD_M ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S)) -#define SLC_WR_RETRY_THRESHOLD_V 0x7FF -#define SLC_WR_RETRY_THRESHOLD_S 0 - -#define SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xDC) -/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_CMD_CONTENT0 0xFFFFFFFF -#define SLC_CMD_CONTENT0_M ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S)) -#define SLC_CMD_CONTENT0_V 0xFFFFFFFF -#define SLC_CMD_CONTENT0_S 0 - -#define SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xE0) -/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_CMD_CONTENT1 0xFFFFFFFF -#define SLC_CMD_CONTENT1_M ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S)) -#define SLC_CMD_CONTENT1_V 0xFFFFFFFF -#define SLC_CMD_CONTENT1_S 0 - -#define SLC_0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xE4) -/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_NEW_PKT_IND (BIT(28)) -#define SLC_SLC0_TX_NEW_PKT_IND_M (BIT(28)) -#define SLC_SLC0_TX_NEW_PKT_IND_V 0x1 -#define SLC_SLC0_TX_NEW_PKT_IND_S 28 -/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_NEW_PKT_IND (BIT(27)) -#define SLC_SLC0_RX_NEW_PKT_IND_M (BIT(27)) -#define SLC_SLC0_RX_NEW_PKT_IND_V 0x1 -#define SLC_SLC0_RX_NEW_PKT_IND_S 27 -/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_GET_USED_DSCR (BIT(26)) -#define SLC_SLC0_TX_GET_USED_DSCR_M (BIT(26)) -#define SLC_SLC0_TX_GET_USED_DSCR_V 0x1 -#define SLC_SLC0_TX_GET_USED_DSCR_S 26 -/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_GET_USED_DSCR (BIT(25)) -#define SLC_SLC0_RX_GET_USED_DSCR_M (BIT(25)) -#define SLC_SLC0_RX_GET_USED_DSCR_V 0x1 -#define SLC_SLC0_RX_GET_USED_DSCR_S 25 -/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_PACKET_LOAD_EN (BIT(24)) -#define SLC_SLC0_TX_PACKET_LOAD_EN_M (BIT(24)) -#define SLC_SLC0_TX_PACKET_LOAD_EN_V 0x1 -#define SLC_SLC0_TX_PACKET_LOAD_EN_S 24 -/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_PACKET_LOAD_EN (BIT(23)) -#define SLC_SLC0_RX_PACKET_LOAD_EN_M (BIT(23)) -#define SLC_SLC0_RX_PACKET_LOAD_EN_V 0x1 -#define SLC_SLC0_RX_PACKET_LOAD_EN_S 23 -/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_LEN_INC_MORE (BIT(22)) -#define SLC_SLC0_LEN_INC_MORE_M (BIT(22)) -#define SLC_SLC0_LEN_INC_MORE_V 0x1 -#define SLC_SLC0_LEN_INC_MORE_S 22 -/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_LEN_INC (BIT(21)) -#define SLC_SLC0_LEN_INC_M (BIT(21)) -#define SLC_SLC0_LEN_INC_V 0x1 -#define SLC_SLC0_LEN_INC_S 21 -/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_LEN_WR (BIT(20)) -#define SLC_SLC0_LEN_WR_M (BIT(20)) -#define SLC_SLC0_LEN_WR_V 0x1 -#define SLC_SLC0_LEN_WR_S 20 -/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define SLC_SLC0_LEN_WDATA 0x000FFFFF -#define SLC_SLC0_LEN_WDATA_M ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S)) -#define SLC_SLC0_LEN_WDATA_V 0xFFFFF -#define SLC_SLC0_LEN_WDATA_S 0 - -#define SLC_0_LENGTH_REG (DR_REG_SLC_BASE + 0xE8) -/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: */ -#define SLC_SLC0_LEN 0x000FFFFF -#define SLC_SLC0_LEN_M ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S)) -#define SLC_SLC0_LEN_V 0xFFFFF -#define SLC_SLC0_LEN_S 0 - -#define SLC_0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xEC) -/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S)) -#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S 0 - -#define SLC_0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF0) -/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S)) -#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S 0 - -#define SLC_0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xF4) -/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S)) -#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S 0 - -#define SLC_0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF8) -/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S)) -#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S 0 - -#define SLC_0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0xFC) -/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S)) -#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S 0 - -#define SLC_0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) -/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S)) -#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S 0 - -#define SLC_0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) -/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S)) -#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S 0 - -#define SLC_0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) -/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: */ -#define SLC_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S)) -#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S 0 - -#define SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x114) -/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */ -/*description: */ -#define SLC_SLC0_SEQ_POSITION 0x000000FF -#define SLC_SLC0_SEQ_POSITION_M ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S)) -#define SLC_SLC0_SEQ_POSITION_V 0xFF -#define SLC_SLC0_SEQ_POSITION_S 0 - -#define SLC_0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x118) -/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_REC_LIM 0x000003FF -#define SLC_SLC0_RX_DSCR_REC_LIM_M ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S)) -#define SLC_SLC0_RX_DSCR_REC_LIM_V 0x3FF -#define SLC_SLC0_RX_DSCR_REC_LIM_S 0 - -#define SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x11C) -/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */ -/*description: */ -#define SLC_DAT3_CRC_ERR_CNT 0x000000FF -#define SLC_DAT3_CRC_ERR_CNT_M ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S)) -#define SLC_DAT3_CRC_ERR_CNT_V 0xFF -#define SLC_DAT3_CRC_ERR_CNT_S 24 -/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */ -/*description: */ -#define SLC_DAT2_CRC_ERR_CNT 0x000000FF -#define SLC_DAT2_CRC_ERR_CNT_M ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S)) -#define SLC_DAT2_CRC_ERR_CNT_V 0xFF -#define SLC_DAT2_CRC_ERR_CNT_S 16 -/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: */ -#define SLC_DAT1_CRC_ERR_CNT 0x000000FF -#define SLC_DAT1_CRC_ERR_CNT_M ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S)) -#define SLC_DAT1_CRC_ERR_CNT_V 0xFF -#define SLC_DAT1_CRC_ERR_CNT_S 8 -/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SLC_DAT0_CRC_ERR_CNT 0x000000FF -#define SLC_DAT0_CRC_ERR_CNT_M ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S)) -#define SLC_DAT0_CRC_ERR_CNT_V 0xFF -#define SLC_DAT0_CRC_ERR_CNT_S 0 - -#define SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x120) -/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: */ -#define SLC_ERR_CNT_CLR (BIT(31)) -#define SLC_ERR_CNT_CLR_M (BIT(31)) -#define SLC_ERR_CNT_CLR_V 0x1 -#define SLC_ERR_CNT_CLR_S 31 -/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: */ -#define SLC_CMD_CRC_ERR_CNT 0x000000FF -#define SLC_CMD_CRC_ERR_CNT_M ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S)) -#define SLC_CMD_CRC_ERR_CNT_V 0xFF -#define SLC_CMD_CRC_ERR_CNT_S 0 - -#define SLC_0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x124) -/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_EOF_START_DES_ADDR 0xFFFFFFFF -#define SLC_SLC0_EOF_START_DES_ADDR_M ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S)) -#define SLC_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_EOF_START_DES_ADDR_S 0 - -#define SLC_0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x128) -/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S)) -#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S 0 - -#define SLC_0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x12C) -/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_RX_DONE_DSCR_ADDR_M ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S)) -#define SLC_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_RX_DONE_DSCR_ADDR_S 0 - -#define SLC_0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x130) -/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: */ -#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFF -#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S)) -#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFF -#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 - -#define SLC_0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x134) -/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_GET_EOF_OCC (BIT(16)) -#define SLC_SLC0_RX_GET_EOF_OCC_M (BIT(16)) -#define SLC_SLC0_RX_GET_EOF_OCC_V 0x1 -#define SLC_SLC0_RX_GET_EOF_OCC_S 16 -/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_CNT_LAT 0x000003FF -#define SLC_SLC0_RX_DSCR_CNT_LAT_M ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S)) -#define SLC_SLC0_RX_DSCR_CNT_LAT_V 0x3FF -#define SLC_SLC0_RX_DSCR_CNT_LAT_S 0 - -#define SLC_0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x138) -/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */ -/*description: */ -#define SLC_SLC0_LEN_LIM 0x000FFFFF -#define SLC_SLC0_LEN_LIM_M ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S)) -#define SLC_SLC0_LEN_LIM_V 0xFFFFF -#define SLC_SLC0_LEN_LIM_S 0 - -#define SLC_0INT_ST1_REG (DR_REG_SLC_BASE + 0x13C) -/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x1 -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 -/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V 0x1 -#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S 26 -/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CMD_DTC_INT_ST1 (BIT(25)) -#define SLC_CMD_DTC_INT_ST1_M (BIT(25)) -#define SLC_CMD_DTC_INT_ST1_V 0x1 -#define SLC_CMD_DTC_INT_ST1_S 25 -/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V 0x1 -#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S 24 -/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V 0x1 -#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S 23 -/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V 0x1 -#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S 22 -/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x1 -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 -/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V 0x1 -#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S 20 -/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V 0x1 -#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S 19 -/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INT_ST1 (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ST1_M (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ST1_V 0x1 -#define SLC_SLC0_TOHOST_INT_ST1_S 18 -/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_INT_ST1 (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ST1_M (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ST1_V 0x1 -#define SLC_SLC0_RX_EOF_INT_ST1_S 17 -/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_INT_ST1 (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ST1_M (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ST1_V 0x1 -#define SLC_SLC0_RX_DONE_INT_ST1_S 16 -/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V 0x1 -#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S 15 -/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DONE_INT_ST1 (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ST1_M (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ST1_V 0x1 -#define SLC_SLC0_TX_DONE_INT_ST1_S 14 -/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V 0x1 -#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S 13 -/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V 0x1 -#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S 12 -/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_OVF_INT_ST1 (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ST1_M (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ST1_V 0x1 -#define SLC_SLC0_TX_OVF_INT_ST1_S 11 -/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_UDF_INT_ST1 (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ST1_M (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ST1_V 0x1 -#define SLC_SLC0_RX_UDF_INT_ST1_S 10 -/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_START_INT_ST1 (BIT(9)) -#define SLC_SLC0_TX_START_INT_ST1_M (BIT(9)) -#define SLC_SLC0_TX_START_INT_ST1_V 0x1 -#define SLC_SLC0_TX_START_INT_ST1_S 9 -/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_START_INT_ST1 (BIT(8)) -#define SLC_SLC0_RX_START_INT_ST1_M (BIT(8)) -#define SLC_SLC0_RX_START_INT_ST1_V 0x1 -#define SLC_SLC0_RX_START_INT_ST1_S 8 -/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ST1_M (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT7_INT_ST1_S 7 -/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ST1_M (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT6_INT_ST1_S 6 -/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ST1_M (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT5_INT_ST1_S 5 -/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ST1_M (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT4_INT_ST1_S 4 -/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ST1_M (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT3_INT_ST1_S 3 -/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ST1_M (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT2_INT_ST1_S 2 -/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ST1_M (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT1_INT_ST1_S 1 -/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ST1_M (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ST1_V 0x1 -#define SLC_FRHOST_BIT0_INT_ST1_S 0 - -#define SLC_0INT_ENA1_REG (DR_REG_SLC_BASE + 0x140) -/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (BIT(27)) -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x1 -#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 -/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M (BIT(26)) -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x1 -#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 -/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: */ -#define SLC_CMD_DTC_INT_ENA1 (BIT(25)) -#define SLC_CMD_DTC_INT_ENA1_M (BIT(25)) -#define SLC_CMD_DTC_INT_ENA1_V 0x1 -#define SLC_CMD_DTC_INT_ENA1_S 25 -/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M (BIT(24)) -#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S 24 -/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M (BIT(23)) -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x1 -#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 -/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M (BIT(22)) -#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V 0x1 -#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S 22 -/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21)) -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 -/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M (BIT(20)) -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x1 -#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 -/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M (BIT(19)) -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 -/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOHOST_INT_ENA1 (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ENA1_M (BIT(18)) -#define SLC_SLC0_TOHOST_INT_ENA1_V 0x1 -#define SLC_SLC0_TOHOST_INT_ENA1_S 18 -/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_EOF_INT_ENA1 (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ENA1_M (BIT(17)) -#define SLC_SLC0_RX_EOF_INT_ENA1_V 0x1 -#define SLC_SLC0_RX_EOF_INT_ENA1_S 17 -/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_DONE_INT_ENA1 (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ENA1_M (BIT(16)) -#define SLC_SLC0_RX_DONE_INT_ENA1_V 0x1 -#define SLC_SLC0_RX_DONE_INT_ENA1_S 16 -/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M (BIT(15)) -#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S 15 -/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_DONE_INT_ENA1 (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ENA1_M (BIT(14)) -#define SLC_SLC0_TX_DONE_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_DONE_INT_ENA1_S 14 -/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(13)) -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1 -#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 -/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(12)) -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1 -#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 -/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_OVF_INT_ENA1 (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ENA1_M (BIT(11)) -#define SLC_SLC0_TX_OVF_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_OVF_INT_ENA1_S 11 -/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_UDF_INT_ENA1 (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ENA1_M (BIT(10)) -#define SLC_SLC0_RX_UDF_INT_ENA1_V 0x1 -#define SLC_SLC0_RX_UDF_INT_ENA1_S 10 -/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_TX_START_INT_ENA1 (BIT(9)) -#define SLC_SLC0_TX_START_INT_ENA1_M (BIT(9)) -#define SLC_SLC0_TX_START_INT_ENA1_V 0x1 -#define SLC_SLC0_TX_START_INT_ENA1_S 9 -/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: */ -#define SLC_SLC0_RX_START_INT_ENA1 (BIT(8)) -#define SLC_SLC0_RX_START_INT_ENA1_M (BIT(8)) -#define SLC_SLC0_RX_START_INT_ENA1_V 0x1 -#define SLC_SLC0_RX_START_INT_ENA1_S 8 -/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ENA1_M (BIT(7)) -#define SLC_FRHOST_BIT7_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT7_INT_ENA1_S 7 -/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ENA1_M (BIT(6)) -#define SLC_FRHOST_BIT6_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT6_INT_ENA1_S 6 -/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ENA1_M (BIT(5)) -#define SLC_FRHOST_BIT5_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT5_INT_ENA1_S 5 -/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ENA1_M (BIT(4)) -#define SLC_FRHOST_BIT4_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT4_INT_ENA1_S 4 -/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ENA1_M (BIT(3)) -#define SLC_FRHOST_BIT3_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT3_INT_ENA1_S 3 -/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ENA1_M (BIT(2)) -#define SLC_FRHOST_BIT2_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT2_INT_ENA1_S 2 -/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ENA1_M (BIT(1)) -#define SLC_FRHOST_BIT1_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT1_INT_ENA1_S 1 -/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: */ -#define SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ENA1_M (BIT(0)) -#define SLC_FRHOST_BIT0_INT_ENA1_V 0x1 -#define SLC_FRHOST_BIT0_INT_ENA1_S 0 - -#define SLC_DATE_REG (DR_REG_SLC_BASE + 0x1F8) -/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */ -/*description: */ -#define SLC_DATE 0xFFFFFFFF -#define SLC_DATE_M ((SLC_DATE_V)<<(SLC_DATE_S)) -#define SLC_DATE_V 0xFFFFFFFF -#define SLC_DATE_S 0 - -#define SLC_ID_REG (DR_REG_SLC_BASE + 0x1FC) -/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */ -/*description: */ -#define SLC_ID 0xFFFFFFFF -#define SLC_ID_M ((SLC_ID_V)<<(SLC_ID_S)) -#define SLC_ID_V 0xFFFFFFFF -#define SLC_ID_S 0 - -#ifdef __cplusplus -} -#endif - - - -#endif /*_SOC_SLC_REG_H_ */ - - diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/slc_struct.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/slc_struct.h deleted file mode 100644 index 74cb22c3..00000000 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/slc_struct.h +++ /dev/null @@ -1,588 +0,0 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_SLC_STRUCT_H_ -#define _SOC_SLC_STRUCT_H_ -#ifdef __cplusplus -extern "C" { -#endif - -typedef volatile struct { - union { - struct { - uint32_t slc0_tx_rst: 1; - uint32_t slc0_rx_rst: 1; - uint32_t ahbm_fifo_rst: 1; - uint32_t ahbm_rst: 1; - uint32_t slc0_tx_loop_test: 1; - uint32_t slc0_rx_loop_test: 1; - uint32_t slc0_rx_auto_wrback: 1; - uint32_t slc0_rx_no_restart_clr: 1; - uint32_t slc0_rxdscr_burst_en: 1; - uint32_t slc0_rxdata_burst_en: 1; - uint32_t slc0_rxlink_auto_ret: 1; - uint32_t slc0_txlink_auto_ret: 1; - uint32_t slc0_txdscr_burst_en: 1; - uint32_t slc0_txdata_burst_en: 1; - uint32_t slc0_token_auto_clr: 1; - uint32_t slc0_token_sel: 1; - uint32_t reserved16: 2; - uint32_t slc0_wr_retry_mask_en: 1; - uint32_t reserved19: 13; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t host_rd_ack: 1; - uint32_t wr_retry_done: 1; - uint32_t tx_err_eof: 1; - uint32_t cmd_dtc: 1; - uint32_t rx_quick_eof: 1; - uint32_t host_pop_eof_err: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_int_raw; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t host_rd_ack: 1; - uint32_t wr_retry_done: 1; - uint32_t tx_err_eof: 1; - uint32_t cmd_dtc: 1; - uint32_t rx_quick_eof: 1; - uint32_t host_pop_eof_err: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_int_st; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t host_rd_ack: 1; - uint32_t wr_retry_done: 1; - uint32_t tx_err_eof: 1; - uint32_t cmd_dtc: 1; - uint32_t rx_quick_eof: 1; - uint32_t host_pop_eof_err: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_int_ena; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t host_rd_ack: 1; - uint32_t wr_retry_done: 1; - uint32_t tx_err_eof: 1; - uint32_t cmd_dtc: 1; - uint32_t rx_quick_eof: 1; - uint32_t host_pop_eof_err: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_int_clr; - uint32_t reserved_14; - uint32_t reserved_18; - uint32_t reserved_1c; - uint32_t reserved_20; - union { - struct { - uint32_t slc0_rx_full: 1; - uint32_t slc0_rx_empty: 1; - uint32_t slc0_rx_buf_len:12; - uint32_t reserved14: 18; - }; - uint32_t val; - } rx_status; - union { - struct { - uint32_t rxfifo_wdata: 9; - uint32_t reserved9: 7; - uint32_t rxfifo_push: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } slc0_rxfifo_push; - uint32_t reserved_2c; - union { - struct { - uint32_t slc0_tx_full: 1; - uint32_t slc0_tx_empty: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } tx_status; - union { - struct { - uint32_t txfifo_rdata: 11; - uint32_t reserved11: 5; - uint32_t txfifo_pop: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } slc0_txfifo_pop; - uint32_t reserved_38; - union { - struct { - uint32_t addr: 20; - uint32_t reserved20: 8; - uint32_t stop: 1; - uint32_t start: 1; - uint32_t restart: 1; - uint32_t park: 1; - }; - uint32_t val; - } slc0_rx_link; - union { - struct { - uint32_t addr: 20; - uint32_t reserved20: 8; - uint32_t stop: 1; - uint32_t start: 1; - uint32_t restart: 1; - uint32_t park: 1; - }; - uint32_t val; - } slc0_tx_link; - uint32_t reserved_44; - uint32_t reserved_48; - union { - struct { - uint32_t slc0_intvec: 8; - uint32_t reserved8: 24; - }; - uint32_t val; - } intvec_tohost; - union { - struct { - uint32_t wdata: 12; - uint32_t wr: 1; - uint32_t inc: 1; - uint32_t inc_more: 1; - uint32_t reserved15: 1; - uint32_t token0: 12; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_token0; - union { - struct { - uint32_t wdata: 12; - uint32_t wr: 1; - uint32_t inc: 1; - uint32_t inc_more: 1; - uint32_t reserved15: 1; - uint32_t token1: 12; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_token1; - uint32_t reserved_58; - uint32_t reserved_5c; - union { - struct { - uint32_t slc0_check_owner: 1; - uint32_t slc0_tx_check_sum_en: 1; - uint32_t slc0_rx_check_sum_en: 1; - uint32_t cmd_hold_en: 1; - uint32_t slc0_len_auto_clr: 1; - uint32_t slc0_tx_stitch_en: 1; - uint32_t slc0_rx_stitch_en: 1; - uint32_t reserved7: 12; - uint32_t host_int_level_sel: 1; - uint32_t reserved20: 2; - uint32_t clk_en: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } conf1; - uint32_t slc0_state0; /**/ - uint32_t slc0_state1; /**/ - uint32_t reserved_6c; - uint32_t reserved_70; - union { - struct { - uint32_t txeof_ena: 6; - uint32_t reserved6: 2; - uint32_t fifo_map_ena: 4; - uint32_t slc0_tx_dummy_mode: 1; - uint32_t hda_map_128k: 1; - uint32_t reserved14: 2; - uint32_t tx_push_idle_num: 16; - }; - uint32_t val; - } bridge_conf; - uint32_t slc0_to_eof_des_addr; /**/ - uint32_t slc0_tx_eof_des_addr; /**/ - uint32_t slc0_to_eof_bfr_des_addr; /**/ - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - union { - struct { - uint32_t mode: 3; - uint32_t reserved3: 1; - uint32_t addr: 2; - uint32_t reserved6: 26; - }; - uint32_t val; - } ahb_test; - union { - struct { - uint32_t cmd_st: 3; - uint32_t reserved3: 1; - uint32_t func_st: 4; - uint32_t sdio_wakeup: 1; - uint32_t reserved9: 3; - uint32_t bus_st: 3; - uint32_t reserved15: 1; - uint32_t func1_acc_state: 5; - uint32_t reserved21: 11; - }; - uint32_t val; - } sdio_st; - union { - struct { - uint32_t slc0_token_no_replace: 1; - uint32_t slc0_infor_no_replace: 1; - uint32_t slc0_rx_fill_mode: 1; - uint32_t slc0_rx_eof_mode: 1; - uint32_t slc0_rx_fill_en: 1; - uint32_t slc0_rd_retry_threshold:11; - uint32_t reserved16: 16; - }; - uint32_t val; - } rx_dscr_conf; - uint32_t slc0_txlink_dscr; /**/ - uint32_t slc0_txlink_dscr_bf0; /**/ - uint32_t slc0_txlink_dscr_bf1; /**/ - uint32_t slc0_rxlink_dscr; /**/ - uint32_t slc0_rxlink_dscr_bf0; /**/ - uint32_t slc0_rxlink_dscr_bf1; /**/ - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t slc0_tx_erreof_des_addr; /**/ - uint32_t reserved_d0; - union { - struct { - uint32_t slc0_token:12; - uint32_t reserved12:20; - }; - uint32_t val; - } token_lat; - union { - struct { - uint32_t wr_retry_threshold:11; - uint32_t reserved11: 21; - }; - uint32_t val; - } tx_dscr_conf; - uint32_t cmd_infor0; /**/ - uint32_t cmd_infor1; /**/ - union { - struct { - uint32_t len_wdata: 20; - uint32_t len_wr: 1; - uint32_t len_inc: 1; - uint32_t len_inc_more: 1; - uint32_t rx_packet_load_en: 1; - uint32_t tx_packet_load_en: 1; - uint32_t rx_get_used_dscr: 1; - uint32_t tx_get_used_dscr: 1; - uint32_t rx_new_pkt_ind: 1; - uint32_t tx_new_pkt_ind: 1; - uint32_t reserved29: 3; - }; - uint32_t val; - } slc0_len_conf; - union { - struct { - uint32_t len: 20; - uint32_t reserved20:12; - }; - uint32_t val; - } slc0_length; - uint32_t slc0_txpkt_h_dscr; /**/ - uint32_t slc0_txpkt_e_dscr; /**/ - uint32_t slc0_rxpkt_h_dscr; /**/ - uint32_t slc0_rxpkt_e_dscr; /**/ - uint32_t slc0_txpktu_h_dscr; /**/ - uint32_t slc0_txpktu_e_dscr; /**/ - uint32_t slc0_rxpktu_h_dscr; /**/ - uint32_t slc0_rxpktu_e_dscr; /**/ - uint32_t reserved_10c; - uint32_t reserved_110; - union { - struct { - uint32_t slc0_position: 8; - uint32_t reserved8: 24; - }; - uint32_t val; - } seq_position; - union { - struct { - uint32_t rx_dscr_rec_lim: 10; - uint32_t reserved10: 22; - }; - uint32_t val; - } slc0_dscr_rec_conf; - union { - struct { - uint32_t dat0_crc_err_cnt: 8; - uint32_t dat1_crc_err_cnt: 8; - uint32_t dat2_crc_err_cnt: 8; - uint32_t dat3_crc_err_cnt: 8; - }; - uint32_t val; - } sdio_crc_st0; - union { - struct { - uint32_t cmd_crc_err_cnt: 8; - uint32_t reserved8: 23; - uint32_t err_cnt_clr: 1; - }; - uint32_t val; - } sdio_crc_st1; - uint32_t slc0_eof_start_des; /**/ - uint32_t slc0_push_dscr_addr; /**/ - uint32_t slc0_done_dscr_addr; /**/ - uint32_t slc0_sub_start_des; /**/ - union { - struct { - uint32_t rx_dscr_cnt_lat: 10; - uint32_t reserved10: 6; - uint32_t rx_get_eof_occ: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } slc0_dscr_cnt; - union { - struct { - uint32_t len_lim: 20; - uint32_t reserved20: 12; - }; - uint32_t val; - } slc0_len_lim_conf; - union { - struct { - uint32_t frhost_bit01: 1; - uint32_t frhost_bit11: 1; - uint32_t frhost_bit21: 1; - uint32_t frhost_bit31: 1; - uint32_t frhost_bit41: 1; - uint32_t frhost_bit51: 1; - uint32_t frhost_bit61: 1; - uint32_t frhost_bit71: 1; - uint32_t rx_start1: 1; - uint32_t tx_start1: 1; - uint32_t rx_udf1: 1; - uint32_t tx_ovf1: 1; - uint32_t token0_1to01: 1; - uint32_t token1_1to01: 1; - uint32_t tx_done1: 1; - uint32_t tx_suc_eof1: 1; - uint32_t rx_done1: 1; - uint32_t rx_eof1: 1; - uint32_t tohost1: 1; - uint32_t tx_dscr_err1: 1; - uint32_t rx_dscr_err1: 1; - uint32_t tx_dscr_empty1: 1; - uint32_t host_rd_ack1: 1; - uint32_t wr_retry_done1: 1; - uint32_t tx_err_eof1: 1; - uint32_t cmd_dtc1: 1; - uint32_t rx_quick_eof1: 1; - uint32_t host_pop_eof_err1: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_int_st1; - union { - struct { - uint32_t frhost_bit01: 1; - uint32_t frhost_bit11: 1; - uint32_t frhost_bit21: 1; - uint32_t frhost_bit31: 1; - uint32_t frhost_bit41: 1; - uint32_t frhost_bit51: 1; - uint32_t frhost_bit61: 1; - uint32_t frhost_bit71: 1; - uint32_t rx_start1: 1; - uint32_t tx_start1: 1; - uint32_t rx_udf1: 1; - uint32_t tx_ovf1: 1; - uint32_t token0_1to01: 1; - uint32_t token1_1to01: 1; - uint32_t tx_done1: 1; - uint32_t tx_suc_eof1: 1; - uint32_t rx_done1: 1; - uint32_t rx_eof1: 1; - uint32_t tohost1: 1; - uint32_t tx_dscr_err1: 1; - uint32_t rx_dscr_err1: 1; - uint32_t tx_dscr_empty1: 1; - uint32_t host_rd_ack1: 1; - uint32_t wr_retry_done1: 1; - uint32_t tx_err_eof1: 1; - uint32_t cmd_dtc1: 1; - uint32_t rx_quick_eof1: 1; - uint32_t host_pop_eof_err1: 1; - uint32_t reserved28: 4; - }; - uint32_t val; - } slc0_int_ena1; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t date; /**/ - uint32_t id; /**/ -} slc_dev_t; -extern slc_dev_t SLC; -#ifdef __cplusplus -} -#endif - -#endif /* _SOC_SLC_STRUCT_H_ */ diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h index 0181a992..1db40881 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc.h @@ -93,6 +93,10 @@ #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +//Convenient way to replace the register ops when ulp riscv projects +//consume this file +#ifndef ULP_RISCV_REGISTER_OPS + //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) @@ -229,6 +233,7 @@ #endif /* !__ASSEMBLER__ */ //}} +#endif /* !ULP_RISCV_REGISTER_OPS */ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h index 3aa4973c..6efffea1 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h @@ -5,6 +5,7 @@ #pragma once +#define SOC_TWAI_SUPPORTED 1 #define SOC_CPU_CORES_NUM 1 - #define SOC_SUPPORTS_SECURE_DL_MODE 1 +#define SOC_RISCV_COPROC_SUPPORTED 1 diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/spi_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/spi_caps.h index a34e55fd..b527fafd 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/spi_caps.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/spi_caps.h @@ -16,7 +16,7 @@ #define SOC_SPI_PERIPH_NUM 3 #define SOC_SPI_DMA_CHAN_NUM 3 -#define SOC_SPI_PERIPH_CS_NUM(i) 3 +#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) #define SPI_FUNC_NUM 0 #define SPI_IOMUX_PIN_NUM_HD 27 @@ -45,7 +45,8 @@ #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 #define SOC_SPI_SUPPORT_CD_SIG 1 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 - +/// The SPI Slave half duplex mode has been updated greatly in ESP32-S2 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 // Peripheral supports DIO, DOUT, QIO, or QOUT // VSPI (SPI3) only support 1-bit mode @@ -55,3 +56,4 @@ // Only SPI1 supports this feature #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(host_id) ((host_id) == 0) +#define SOC_MEMSPI_IS_INDEPENDENT 1 diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/system_reg.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/system_reg.h index 0bb4a7f9..cc7183c8 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/system_reg.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/system_reg.h @@ -262,12 +262,12 @@ extern "C" { #define DPORT_PWM1_CLK_EN_M (BIT(20)) #define DPORT_PWM1_CLK_EN_V 0x1 #define DPORT_PWM1_CLK_EN_S 20 -/* DPORT_CAN_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/* DPORT_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ /*description: */ -#define DPORT_CAN_CLK_EN (BIT(19)) -#define DPORT_CAN_CLK_EN_M (BIT(19)) -#define DPORT_CAN_CLK_EN_V 0x1 -#define DPORT_CAN_CLK_EN_S 19 +#define DPORT_TWAI_CLK_EN (BIT(19)) +#define DPORT_TWAI_CLK_EN_M (BIT(19)) +#define DPORT_TWAI_CLK_EN_V 0x1 +#define DPORT_TWAI_CLK_EN_S 19 /* DPORT_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ /*description: */ #define DPORT_I2C_EXT1_CLK_EN (BIT(18)) @@ -496,12 +496,12 @@ extern "C" { #define DPORT_PWM1_RST_M (BIT(20)) #define DPORT_PWM1_RST_V 0x1 #define DPORT_PWM1_RST_S 20 -/* DPORT_CAN_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/* DPORT_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ /*description: */ -#define DPORT_CAN_RST (BIT(19)) -#define DPORT_CAN_RST_M (BIT(19)) -#define DPORT_CAN_RST_V 0x1 -#define DPORT_CAN_RST_S 19 +#define DPORT_TWAI_RST (BIT(19)) +#define DPORT_TWAI_RST_M (BIT(19)) +#define DPORT_TWAI_RST_V 0x1 +#define DPORT_TWAI_RST_S 19 /* DPORT_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ /*description: */ #define DPORT_I2C_EXT1_RST (BIT(18)) diff --git a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/touch_sensor_caps.h b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/touch_sensor_caps.h index 61fdb6e1..d9dfb1e9 100644 --- a/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/touch_sensor_caps.h +++ b/tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/touch_sensor_caps.h @@ -24,9 +24,7 @@ extern "C" { #define SOC_TOUCH_PAD_MEASURE_WAIT (0xFF) /*! + +/* ---------------------------- Register Layout ------------------------------ */ + +/* The TWAI peripheral's registers are 8bits, however the ESP32 can only access + * peripheral registers every 32bits. Therefore each TWAI register is mapped to + * the least significant byte of every 32bits. + */ + +typedef volatile struct twai_dev_s { + //Configuration and Control Registers + union { + struct { + uint32_t rm: 1; /* MOD.0 Reset Mode */ + uint32_t lom: 1; /* MOD.1 Listen Only Mode */ + uint32_t stm: 1; /* MOD.2 Self Test Mode */ + uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */ + uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ + }; + uint32_t val; + } mode_reg; /* Address 0 */ + union { + struct { + uint32_t tr: 1; /* CMR.0 Transmission Request */ + uint32_t at: 1; /* CMR.1 Abort Transmission */ + uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */ + uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */ + uint32_t srr: 1; /* CMR.4 Self Reception Request */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; + } command_reg; /* Address 1 */ + union { + struct { + uint32_t rbs: 1; /* SR.0 Receive Buffer Status */ + uint32_t dos: 1; /* SR.1 Data Overrun Status */ + uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */ + uint32_t tcs: 1; /* SR.3 Transmission Complete Status */ + uint32_t rs: 1; /* SR.4 Receive Status */ + uint32_t ts: 1; /* SR.5 Transmit Status */ + uint32_t es: 1; /* SR.6 Error Status */ + uint32_t bs: 1; /* SR.7 Bus Status */ + uint32_t ms: 1; /* SR.8 Miss Status */ + uint32_t reserved23: 23; /* Internal Reserved */ + }; + uint32_t val; + } status_reg; /* Address 2 */ + union { + struct { + uint32_t ri: 1; /* IR.0 Receive Interrupt */ + uint32_t ti: 1; /* IR.1 Transmit Interrupt */ + uint32_t ei: 1; /* IR.2 Error Interrupt */ + uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ + uint32_t epi: 1; /* IR.5 Error Passive Interrupt */ + uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */ + uint32_t bei: 1; /* IR.7 Bus Error Interrupt */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } interrupt_reg; /* Address 3 */ + union { + struct { + uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */ + uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */ + uint32_t eie: 1; /* IER.2 Error Interrupt Enable */ + uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */ + uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */ + uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */ + uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } interrupt_enable_reg; /* Address 4 */ + uint32_t reserved_05; /* Address 5 */ + union { + struct { + uint32_t brp: 14; /* BTR0[13:0] Baud Rate Prescaler */ + uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/ + uint32_t reserved16: 16; /* Internal Reserved */ + }; + uint32_t val; + } bus_timing_0_reg; /* Address 6 */ + union { + struct { + uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */ + uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */ + uint32_t sam: 1; /* BTR1.7 Sampling*/ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } bus_timing_1_reg; /* Address 7 */ + uint32_t reserved_08; /* Address 8 (Output control not supported) */ + uint32_t reserved_09; /* Address 9 (Test Register not supported) */ + uint32_t reserved_10; /* Address 10 */ + + //Capture and Counter Registers + union { + struct { + uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */ + uint32_t reserved27: 27; /* Internal Reserved */ + }; + uint32_t val; + } arbitration_lost_captue_reg; /* Address 11 */ + union { + struct { + uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ + uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */ + uint32_t errc: 2; /* ECC[7:6] Error Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } error_code_capture_reg; /* Address 12 */ + union { + struct { + uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */ + union { + struct { + uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } rx_error_counter_reg; /* Address 12 */ + union { + struct { + uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } tx_error_counter_reg; /* Address 15 */ + + //Shared Registers (TX Buff/RX Buff/Acc Filter) + union { + struct { + union { + struct { + uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } acr[4]; + union { + struct { + uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ + uint32_t reserved24: 24; /* Internal Reserved */ + }; + uint32_t val; + } amr[4]; + uint32_t reserved32[5]; + } acceptance_filter; + union { + struct { + uint32_t byte: 8; + uint32_t reserved24: 24; + }; + uint32_t val; + } tx_rx_buffer[13]; + }; /* Address 16-28 TX/RX Buffer and Acc Filter*/; + + //Misc Registers + union { + struct { + uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */ + uint32_t reserved25: 25; /* Internal Reserved */ + }; + uint32_t val; + } rx_message_counter_reg; /* Address 29 */ + uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */ + union { + struct { + uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */ + uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */ + uint32_t reserved24: 23; /* Internal Reserved */ + }; + uint32_t val; + } clock_divider_reg; /* Address 31 */ +} twai_dev_t; + +_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes"); + +extern twai_dev_t TWAI; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/soc/include/soc/spi_periph.h b/tools/sdk/esp32s2/include/soc/soc/include/soc/spi_periph.h index 32b873fe..79b637ce 100644 --- a/tools/sdk/esp32s2/include/soc/soc/include/soc/spi_periph.h +++ b/tools/sdk/esp32s2/include/soc/soc/include/soc/spi_periph.h @@ -14,6 +14,7 @@ #pragma once #include +#include "sdkconfig.h" #include "soc/soc.h" #include "soc/periph_defs.h" @@ -22,8 +23,7 @@ #include "soc/spi_reg.h" #include "soc/spi_struct.h" #include "soc/gpio_sig_map.h" -#include "sdkconfig.h" -#if CONFIG_IDF_TARGET_ESP32S2 +#if SOC_MEMSPI_IS_INDEPENDENT #include "soc/spi_mem_struct.h" #include "soc/spi_mem_reg.h" #endif diff --git a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/tbconsole.h b/tools/sdk/esp32s2/include/soc/soc/include/soc/twai_periph.h similarity index 78% rename from tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/tbconsole.h rename to tools/sdk/esp32s2/include/soc/soc/include/soc/twai_periph.h index d6ca069c..b59a4bae 100644 --- a/tools/sdk/esp32s2/include/esp_rom/include/esp32s2/rom/tbconsole.h +++ b/tools/sdk/esp32s2/include/soc/soc/include/soc/twai_periph.h @@ -1,9 +1,9 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at - +// // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software @@ -11,17 +11,18 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. -#ifndef _ROM_TBCONSOLE_H_ -#define _ROM_TBCONSOLE_H_ + +#pragma once + +#include "sdkconfig.h" #ifdef __cplusplus extern "C" { #endif -void start_tb_console(void); +#include "soc/twai_struct.h" +#include "soc/twai_caps.h" #ifdef __cplusplus } #endif - -#endif /* _ROM_TBCONSOLE_H_ */ diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_ll.h index 3eaadfb8..13949394 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_ll.h @@ -110,6 +110,19 @@ typedef enum { #define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2 #define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2 #define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0 + +#define ADC_LL_SARADC_DTEST_RTC_ADDR 0x7 +#define ADC_LL_SARADC_DTEST_RTC_ADDR_MSB 1 +#define ADC_LL_SARADC_DTEST_RTC_ADDR_LSB 0 + +#define ADC_LL_SARADC_ENT_TSENS_ADDR 0x7 +#define ADC_LL_SARADC_ENT_TSENS_ADDR_MSB 2 +#define ADC_LL_SARADC_ENT_TSENS_ADDR_LSB 2 + +#define ADC_LL_SARADC_ENT_RTC_ADDR 0x7 +#define ADC_LL_SARADC_ENT_RTC_ADDR_MSB 3 +#define ADC_LL_SARADC_ENT_RTC_ADDR_LSB 3 + /* ADC calibration defines end. */ /*--------------------------------------------------------------- @@ -1248,6 +1261,59 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par } /* Temp code end. */ +/** + * Output ADCn inter reference voltage to ADC2 channels. + * + * This function routes the internal reference voltage of ADCn to one of + * ADC2's channels. This reference voltage can then be manually measured + * for calibration purposes. + * + * @param[in] adc ADC unit select + * @param[in] channel ADC2 channel number + * @param[in] en Enable/disable the reference voltage output + */ +static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en) +{ + /* Should be called before writing I2C registers. */ + void phy_get_romfunc_addr(void); + phy_get_romfunc_addr(); + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18)); + SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16)); + + if (en) { + if (adc == ADC_NUM_1) { + /* Config test mux to route v_ref to ADC1 Channels */ + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 1); + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0); + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 1); + } else { + /* Config test mux to route v_ref to ADC2 Channels */ + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 0); + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1); + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0); + } + //in sleep force to use rtc to control ADC + SENS.sar_meas2_mux.sar2_rtc_force = 1; + //set sar2_en_test + SENS.sar_meas2_ctrl1.sar2_en_test = 1; + //set sar2 en force + SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW + //set en_pad for ADC2 channels (bits 0x380) + SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel; + } else { + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0); + I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0); + SENS.sar_meas2_mux.sar2_rtc_force = 0; + //set sar2_en_test + SENS.sar_meas2_ctrl1.sar2_en_test = 0; + //set sar2 en force + SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; //Pad bitmap controlled by SW + //set en_pad for ADC2 channels (bits 0x380) + SENS.sar_meas2_ctrl2.sar2_en_pad = 0; + } +} + #ifdef __cplusplus } #endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/clk_gate_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/clk_gate_ll.h index 261398f9..868be82b 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/clk_gate_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/clk_gate_ll.h @@ -74,8 +74,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return DPORT_SPI2_DMA_CLK_EN; case PERIPH_SPI3_DMA_MODULE: return DPORT_SPI3_DMA_CLK_EN; - case PERIPH_CAN_MODULE: - return DPORT_CAN_CLK_EN; + case PERIPH_TWAI_MODULE: + return DPORT_TWAI_CLK_EN; case PERIPH_RNG_MODULE: return DPORT_WIFI_CLK_RNG_EN; case PERIPH_WIFI_MODULE: @@ -152,8 +152,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en return DPORT_SPI2_DMA_RST; case PERIPH_SPI3_DMA_MODULE: return DPORT_SPI3_DMA_RST; - case PERIPH_CAN_MODULE: - return DPORT_CAN_RST; + case PERIPH_TWAI_MODULE: + return DPORT_TWAI_RST; case PERIPH_SYSTIMER_MODULE: return DPORT_SYSTIMER_RST; case PERIPH_AES_MODULE: @@ -254,12 +254,30 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph) DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } +static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void) +{ + DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); +} + +static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void) +{ + DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_BT_COMMON_M); + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0); +} + static inline void periph_ll_reset(periph_module_t periph) { DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)); } +static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph) +{ + return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) != 0 && + DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0; +} + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_hal.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_hal.h new file mode 100644 index 00000000..bec3dcfc --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_hal.h @@ -0,0 +1,155 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +// CP DMA HAL usages: +// 1. Initialize HAL layer by cp_dma_hal_init, pass in the allocated descriptors for TX and RX +// 2. Enable DMA and interrupt by cp_dma_hal_start +// 3. Prepare descriptors used for TX and RX +// 4. Restart the DMA engine in case it's not in working + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "esp_attr.h" +#include "soc/cp_dma_struct.h" + +typedef struct cp_dma_descriptor { + struct { + uint32_t size : 12; /*!< buffer size */ + uint32_t length : 12; /*!< specify number of valid bytes in the buffer */ + uint32_t reversed24_27 : 4; /*!< reserved */ + uint32_t err : 1; /*!< specify whether a received buffer contains error */ + uint32_t reserved29 : 1; /*!< reserved */ + uint32_t eof : 1; /*!< if this dma link is the last one, you shoule set this bit 1 */ + uint32_t owner : 1; /*!< specify the owner of buffer that this descriptor points to, 1=DMA, 0=CPU. DMA will clear it after use. */ + } dw0; /*!< descriptor word 0 */ + void *buffer; /*!< pointer to the buffer */ + struct cp_dma_descriptor *next; /*!< pointer to the next descriptor or NULL if this descriptor is the last one */ +} cp_dma_descriptor_t; + +_Static_assert(sizeof(cp_dma_descriptor_t) == 12, "cp_dma_descriptor_t should occupy 12 bytes in memory"); + +/** + * @brief HAL context + * + * @note `tx_desc` and `rx_desc` are internal state of the HAL, will be modified during the operations. + * Upper layer of HAL should keep the buffer address themselves and make sure the buffers are freed when the HAL is no longer used. + * + */ +typedef struct { + cp_dma_dev_t *dev; + cp_dma_descriptor_t *tx_desc; + cp_dma_descriptor_t *rx_desc; + cp_dma_descriptor_t *next_rx_desc_to_check; +} cp_dma_hal_context_t; + +/** + * @brief Initialize HAL layer context + * + * @param hal HAL layer context, memroy should be allocated at driver layer + * @param tx_descriptors out link descriptor pool + * @param tx_desc_num number of out link descriptors + * @param rx_descriptors in line descriptor pool + * @param rx_desc_num number of in link descriptors + */ +void cp_dma_hal_init(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *tx_descriptors[], uint32_t tx_desc_num, cp_dma_descriptor_t *rx_descriptors[], uint32_t rx_desc_num); + +/** + * @brief Deinitialize HAL layer context + */ +void cp_dma_hal_deinit(cp_dma_hal_context_t *hal); + +/** + * @brief Start mem2mem DMA state machine + */ +void cp_dma_hal_start(cp_dma_hal_context_t *hal); + +/** + * @brief Stop mem2mem DMA state machine + */ +void cp_dma_hal_stop(cp_dma_hal_context_t *hal); + +/** + * @brief Get interrupt status word + * + * @return uint32_t Interrupt status + */ +uint32_t cp_dma_hal_get_intr_status(cp_dma_hal_context_t *hal) IRAM_ATTR; + +/** + * @brief Clear interrupt mask + * + * @param mask interrupt mask + */ +void cp_dma_hal_clear_intr_status(cp_dma_hal_context_t *hal, uint32_t mask) IRAM_ATTR; + +/** + * @brief Get next RX descriptor that needs recycling + * + * @param eof_desc EOF descriptor for this iteration + * @param[out] next_desc Next descriptor needs to check + * @return Whether to continue + */ +bool cp_dma_hal_get_next_rx_descriptor(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *eof_desc, cp_dma_descriptor_t **next_desc); + +/** + * @brief Prepare buffer to be transmitted + * + * @param hal HAL layer context + * @param buffer buffer address + * @param len buffer size + * @param[out] start_desc The first descriptor that carry the TX transaction + * @param[out] end_desc The last descriptor that carry the TX transaction + * @return Number of bytes has been parepared to transmit + */ +int cp_dma_hal_prepare_transmit(cp_dma_hal_context_t *hal, void *buffer, size_t len, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc); + +/** + * @brief Prepare buffer to receive + * + * @param hal HAL layer context + * @param buffer buffer address + * @param size buffer size + * @param[out] start_desc The first descriptor that carries the RX transaction + * @param[out] end_desc The last descriptor that carries the RX transaction + * @return Number of bytes has been parepared to receive + */ +int cp_dma_hal_prepare_receive(cp_dma_hal_context_t *hal, void *buffer, size_t size, cp_dma_descriptor_t **start_desc, cp_dma_descriptor_t **end_desc); + +/**@{*/ +/** + * @brief Give the owner of descriptors between [start_desc, end_desc] to DMA, and restart DMA HW engine + * + * @param hal HAL layer context + * @param start_desc The first descriptor that carries one transaction + * @param end_desc The last descriptor that carries one transaction + */ +void cp_dma_hal_restart_tx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc); +void cp_dma_hal_restart_rx(cp_dma_hal_context_t *hal, cp_dma_descriptor_t *start_desc, cp_dma_descriptor_t *end_desc); +/**@}*/ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_ll.h new file mode 100644 index 00000000..1c04315e --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_ll.h @@ -0,0 +1,159 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "soc/cp_dma_struct.h" + +#define CP_DMA_LL_EVENT_RX_DONE (1 << 0) +#define CP_DMA_LL_EVENT_RX_EOF (1 << 1) +#define CP_DMA_LL_EVENT_TX_DONE (1 << 2) +#define CP_DMA_LL_EVENT_TX_EOF (1 << 3) +#define CP_DMA_LL_EVENT_RX_DESC_ERR (1 << 4) +#define CP_DMA_LL_EVENT_TX_DESC_ERR (1 << 5) +#define CP_DMA_LL_EVENT_RX_DESC_EMPTY (1 << 6) +#define CP_DMA_LL_EVENT_TX_TOTAL_EOF (1 << 7) +#define CP_DMA_LL_EVENT_ALL (0xFF) + +/** + * Copy DMA firstly reads data to be transferred from internal RAM, + * stores the data into DMA FIFO via an outlink, + * and then writes the data to the destination internal RAM via an inlink. + */ + +static inline void cp_dma_ll_reset_in_link(cp_dma_dev_t *dev) +{ + dev->dma_conf.dma_in_rst = 1; + dev->dma_conf.dma_in_rst = 0; +} + +static inline void cp_dma_ll_reset_out_link(cp_dma_dev_t *dev) +{ + dev->dma_conf.dma_out_rst = 1; + dev->dma_conf.dma_out_rst = 0; +} + +static inline void cp_dma_ll_reset_fifo(cp_dma_dev_t *dev) +{ + dev->dma_conf.dma_fifo_rst = 1; + dev->dma_conf.dma_fifo_rst = 0; +} + +static inline void cp_dma_ll_reset_cmd_fifo(cp_dma_dev_t *dev) +{ + dev->dma_conf.dma_cmdfifo_rst = 1; + dev->dma_conf.dma_cmdfifo_rst = 0; +} + +static inline void cp_dma_ll_enable_owner_check(cp_dma_dev_t *dev, bool enable) +{ + dev->dma_conf.dma_check_owner = enable; + dev->dma_conf.dma_out_auto_wrback = 1; + dev->dma_conf.dma_out_owner = 0; + dev->dma_conf.dma_in_owner = 0; +} + +static inline void cp_dma_ll_enable_clock(cp_dma_dev_t *dev, bool enable) +{ + dev->dma_conf.dma_clk_en = enable; +} + +static inline void cp_dma_ll_enable_intr(cp_dma_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->dma_int_ena.val |= mask; + } else { + dev->dma_int_ena.val &= ~mask; + } +} + +static inline __attribute__((always_inline)) uint32_t cp_dma_ll_get_intr_status(cp_dma_dev_t *dev) +{ + return dev->dma_int_st.val; +} + +static inline __attribute__((always_inline)) void cp_dma_ll_clear_intr_status(cp_dma_dev_t *dev, uint32_t mask) +{ + dev->dma_int_clr.val = mask; +} + +static inline void cp_dma_ll_tx_set_descriptor_base_addr(cp_dma_dev_t *dev, uint32_t address) +{ + dev->dma_out_link.dma_outlink_addr = address; +} + +static inline void cp_dma_ll_rx_set_descriptor_base_addr(cp_dma_dev_t *dev, uint32_t address) +{ + dev->dma_in_link.dma_inlink_addr = address; +} + +static inline void cp_dma_ll_start_tx(cp_dma_dev_t *dev, bool enable) +{ + if (enable) { + dev->dma_out_link.dma_outlink_start = 1; // cleared automatically by HW + } else { + dev->dma_out_link.dma_outlink_stop = 1; // cleared automatically by HW + } +} + +static inline void cp_dma_ll_start_rx(cp_dma_dev_t *dev, bool enable) +{ + if (enable) { + dev->dma_in_link.dma_inlink_start = 1; // cleared automatically by HW + } else { + dev->dma_in_link.dma_inlink_stop = 1; // cleared automatically by HW + } +} + +static inline void cp_dma_ll_restart_tx(cp_dma_dev_t *dev) +{ + dev->dma_out_link.dma_outlink_restart = 1; // cleared automatically by HW +} + +static inline void cp_dma_ll_restart_rx(cp_dma_dev_t *dev) +{ + dev->dma_in_link.dma_inlink_restart = 1; // cleared automatically by HW +} + +// get the address of last rx descriptor +static inline uint32_t cp_dma_ll_get_rx_eof_descriptor_address(cp_dma_dev_t *dev) +{ + return dev->dma_in_eof_des_addr.dma_in_suc_eof_des_addr; +} + +// get the address of last tx descriptor +static inline uint32_t cp_dma_ll_get_tx_eof_descriptor_address(cp_dma_dev_t *dev) +{ + return dev->dma_out_eof_des_addr.dma_out_eof_des_addr; +} + +static inline uint32_t cp_dma_ll_get_tx_status(cp_dma_dev_t *dev) +{ + return dev->dma_out_st.val; +} + +static inline uint32_t cp_dma_ll_get_rx_status(cp_dma_dev_t *dev) +{ + return dev->dma_in_st.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpio_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpio_ll.h index 7d671874..3f83f77b 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpio_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpio_ll.h @@ -18,7 +18,7 @@ * See readme.md in soc/include/hal/readme.md ******************************************************************************/ -// The LL layer for ESP32 GPIO register operations +// The LL layer for ESP32-S2 GPIO register operations #pragma once diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpspi_flash_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpspi_flash_ll.h index b53b8eab..2db7e6fc 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpspi_flash_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpspi_flash_ll.h @@ -185,8 +185,12 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev) */ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin) { - dev->misc.cs0_dis = (pin == 0) ? 0 : 1; - dev->misc.cs1_dis = (pin == 1) ? 0 : 1; + dev->misc.cs0_dis = (pin != 0); + dev->misc.cs1_dis = (pin != 1); + dev->misc.cs2_dis = (pin != 2); + dev->misc.cs3_dis = (pin != 3); + dev->misc.cs4_dis = (pin != 4); + dev->misc.cs5_dis = (pin != 5); } /** @@ -203,10 +207,10 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M); user.val &= ~(SPI_FWRITE_QUAD_M | SPI_FWRITE_DUAL_M); - // ctrl.val |= SPI_FAST_RD_MODE_M; switch (read_mode) { case SPI_FLASH_FASTRD: //the default option + case SPI_FLASH_SLOWRD: break; case SPI_FLASH_QIO: ctrl.fread_quad = 1; @@ -226,9 +230,6 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod ctrl.fread_dual = 1; user.fwrite_dual = 1; break; - // case SPI_FLASH_SLOWRD: - // ctrl.fast_rd_mode = 0; - // break; default: abort(); } diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_cntl_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_cntl_ll.h new file mode 100644 index 00000000..47bb2195 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_cntl_ll.h @@ -0,0 +1,58 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/rtc_cntl_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +{ + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); + WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); + + SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_MAIN_TIMER_INT_CLR_M); + SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); +} + +static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +{ + return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); +} + +static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +{ + REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, + mode, RTC_CNTL_EXT_WAKEUP1_LV_S); +} + +static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +{ + REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); +} + +static inline void rtc_cntl_ll_ulp_wakeup_enable(void) +{ + SET_PERI_REG_BITS(RTC_CNTL_STATE0_REG, RTC_CNTL_WAKEUP_ENA_V, 0x800, RTC_CNTL_WAKEUP_ENA_S); +} + +#ifdef __cplusplus +} +#endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_io_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_io_ll.h index bce10549..c687915e 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_io_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_io_ll.h @@ -354,6 +354,14 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num) CLEAR_PERI_REG_MASK(rtc_io_desc[gpio_num].reg, rtc_io_desc[gpio_num].slpsel); } +static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level) +{ + REG_SET_FIELD(RTC_IO_EXT_WAKEUP0_REG, RTC_IO_EXT_WAKEUP0_SEL, rtcio_num); + // Set level which will trigger wakeup + SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, + level , RTC_CNTL_EXT_WAKEUP0_LV_S); +} + #ifdef __cplusplus } #endif \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/soc_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/soc_ll.h index e6165158..e195c935 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/soc_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/soc_ll.h @@ -16,6 +16,7 @@ #include "soc/soc.h" #include "soc/rtc_cntl_reg.h" #include "soc/soc_caps.h" +#include "soc/rtc.h" #ifdef __cplusplus extern "C" { diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spi_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spi_ll.h index f719202a..cc3a3ded 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spi_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spi_ll.h @@ -28,6 +28,7 @@ #include "esp_types.h" #include "soc/spi_periph.h" #include "esp32s2/rom/lldesc.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -64,6 +65,34 @@ typedef enum { SPI_LL_INT_TYPE_SEG = 1, ///< Wait for DMA signals } spi_ll_slave_intr_type; +/// Type definition of all supported interrupts +typedef enum { + SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done + SPI_LL_INTR_IN_SUC_EOF = BIT(1), ///< DMA in_suc_eof triggered + SPI_LL_INTR_OUT_EOF = BIT(2), ///< DMA out_eof triggered + SPI_LL_INTR_OUT_TOTAL_EOF = BIT(3), ///< DMA out_total_eof triggered + SPI_LL_INTR_IN_FULL = BIT(4), ///< DMA in_full error happened + SPI_LL_INTR_OUT_EMPTY = BIT(5), ///< DMA out_empty error happened + SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD. + SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD. + SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD. + SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD. + SPI_LL_INTR_WR_DONE = BIT(10), ///< Has received WR_DONE command. Only available in slave HD. + SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD. + SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD. + SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD. + SPI_LL_INTR_SEG_DONE = BIT(14), +} spi_ll_intr_t; +FLAG_ATTR(spi_ll_intr_t) + +///< Flags for conditions under which the transaction length should be recorded +typedef enum { + SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded + SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded + SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded + SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded +} spi_ll_trans_len_cond_t; +FLAG_ATTR(spi_ll_trans_len_cond_t) /*------------------------------------------------------------------------------ * Control @@ -125,6 +154,76 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) hw->dma_int_ena.val = 0; } +static inline void spi_ll_slave_hd_init(spi_dev_t* hw) +{ + hw->clock.val = 0; + hw->user.val = 0; + hw->ctrl.val = 0; + hw->user.sio = 0; + //hw->user.tx_start_bit = 7; + + hw->slave.soft_reset = 1; + hw->slave.soft_reset = 0; + + //Reset DMA + hw->dma_conf.val |= SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST; + hw->dma_out_link.start = 0; + hw->dma_in_link.start = 0; + hw->dma_conf.val &= ~(SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST); + + if (hw == &GPSPI2) { + hw->dma_conf.out_data_burst_en = 1; + } else { + hw->dma_conf.out_data_burst_en = 0; + } + hw->dma_conf.outdscr_burst_en = 1; + hw->dma_conf.indscr_burst_en = 1; + + hw->dma_conf.rx_eof_en = 0; + hw->dma_conf.out_eof_mode = 1; + hw->dma_conf.out_auto_wrback = 1; + + hw->user.doutdin = 0; //we only support full duplex + hw->slave.slave_mode = 1; +} + +/** + * Check whether user-defined transaction is done. + * + * @param hw Beginning address of the peripheral registers. + * + * @return true if transaction is done, otherwise false. + */ +static inline bool spi_ll_usr_is_done(spi_dev_t *hw) +{ + return hw->slave.trans_done; +} + +/** + * Trigger start of user-defined transaction. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_user_start(spi_dev_t *hw) +{ + hw->cmd.usr = 1; +} + +/** + * Get current running command bit-mask. (Preview) + * + * @param hw Beginning address of the peripheral registers. + * + * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. + */ +static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) +{ + return hw->cmd.val; +} + +/*------------------------------------------------------------------------------ + * DMA + *----------------------------------------------------------------------------*/ /** * Reset TX and RX DMAs. * @@ -168,6 +267,62 @@ static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr) hw->dma_out_link.start = 1; } +static inline void spi_ll_rxdma_reset(spi_dev_t* hw) +{ + hw->dma_conf.in_rst = 1; + hw->dma_conf.in_rst = 0; + hw->dma_conf.infifo_full_clr = 1; + hw->dma_conf.infifo_full_clr = 0; +} + +static inline void spi_ll_txdma_reset(spi_dev_t* hw) +{ + hw->dma_conf.out_rst = 1; + hw->dma_conf.out_rst = 0; + hw->dma_conf.outfifo_empty_clr = 1; + hw->dma_conf.outfifo_empty_clr = 0; +} + +static inline void spi_ll_rxdma_restart(spi_dev_t* hw) +{ + hw->dma_in_link.restart = 1; +} + +static inline void spi_ll_txdma_restart(spi_dev_t* hw) +{ + hw->dma_out_link.restart = 1; +} + +static inline void spi_ll_rxdma_disable(spi_dev_t* hw) +{ + hw->dma_in_link.dma_rx_ena = 0; +} + +static inline void spi_ll_txdma_disable(spi_dev_t* hw) +{ + hw->dma_out_link.dma_tx_ena = 0; + hw->dma_out_link.stop = 1; +} + +static inline void spi_ll_rxdma_clr_err(spi_dev_t* hw) +{ + hw->dma_conf.infifo_full_clr = 1; + hw->dma_conf.infifo_full_clr = 0; +} + +static inline void spi_ll_txdma_clr_err(spi_dev_t* hw) +{ + hw->dma_int_clr.outfifo_empty_err= 1; +} + +static inline bool spi_ll_txdma_get_empty_err(spi_dev_t* hw) +{ + return hw->dma_int_raw.outfifo_empty_err; +} + +/*------------------------------------------------------------------------------ + * Buffer + *----------------------------------------------------------------------------*/ /** * Write to SPI buffer. * @@ -205,99 +360,43 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz } } -/** - * Check whether user-defined transaction is done. - * - * @param hw Beginning address of the peripheral registers. - * - * @return true if transaction is done, otherwise false. - */ -static inline bool spi_ll_usr_is_done(spi_dev_t *hw) +static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t *out_data, int len) { - return hw->slave.trans_done; + while (len>0) { + uint32_t word = hw->data_buf[byte_addr/4]; + int offset = byte_addr % 4; + + int copy_len = 4 - offset; + if (copy_len > len) copy_len = len; + + memcpy(out_data, ((uint8_t*)&word)+offset, copy_len); + byte_addr += copy_len; + out_data += copy_len; + len -= copy_len; + } } -/** - * Trigger start of user-defined transaction. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_user_start(spi_dev_t *hw) +static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t *data, int len) { - hw->cmd.usr = 1; -} + assert( byte_addr + len <= 72); + assert(len > 0); + assert(byte_addr >= 0); -/** - * Get current running command bit-mask. (Preview) - * - * @param hw Beginning address of the peripheral registers. - * - * @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command. - */ -static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw) -{ - return hw->cmd.val; -} + while (len > 0) { + uint32_t word; + int offset = byte_addr % 4; -/** - * Disable the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_disable_int(spi_dev_t *hw) -{ - hw->slave.int_trans_done_en = 0; -} + int copy_len = 4 - offset; + if (copy_len > len) copy_len = len; -/** - * Clear the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_clear_int_stat(spi_dev_t *hw) -{ - hw->slave.trans_done = 0; - hw->dma_int_clr.val = UINT32_MAX; -} + //read-modify-write + if (copy_len != 4) word = hw->data_buf[byte_addr / 4]; -/** - * Set the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_set_int_stat(spi_dev_t *hw) -{ - hw->slave.trans_done = 1; -} - -/** - * Enable the trans_done interrupt. - * - * @param hw Beginning address of the peripheral registers. - */ -static inline void spi_ll_enable_int(spi_dev_t *hw) -{ - hw->slave.int_trans_done_en = 1; -} - -/** - * Set different interrupt types for the slave. - * - * @param hw Beginning address of the peripheral registers. - * @param int_type Interrupt type - */ -static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type) -{ - switch (int_type) { - case SPI_LL_INT_TYPE_SEG: - hw->dma_int_ena.in_suc_eof = 1; - hw->dma_int_ena.out_total_eof = 1; - hw->slave.int_trans_done_en = 0; - break; - default: - hw->dma_int_ena.in_suc_eof = 0; - hw->dma_int_ena.out_total_eof = 0; - hw->slave.int_trans_done_en = 1; + memcpy(((uint8_t *)&word) + offset, data, copy_len); + hw->data_buf[byte_addr / 4] = word; + data += copy_len; + byte_addr += copy_len; + len -= copy_len; } } @@ -460,6 +559,12 @@ static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_ } } +static inline void spi_ll_slave_set_seg_mode(spi_dev_t* hw, bool seg_trans) +{ + hw->dma_conf.dma_seg_trans_en = seg_trans; + hw->dma_conf.rx_eof_en = seg_trans; +} + /** * Select one of the CS to use in current transaction. * @@ -471,6 +576,9 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id) hw->misc.cs0_dis = (cs_id == 0) ? 0 : 1; hw->misc.cs1_dis = (cs_id == 1) ? 0 : 1; hw->misc.cs2_dis = (cs_id == 2) ? 0 : 1; + hw->misc.cs3_dis = (cs_id == 3) ? 0 : 1; + hw->misc.cs4_dis = (cs_id == 4) ? 0 : 1; + hw->misc.cs5_dis = (cs_id == 5) ? 0 : 1; } /*------------------------------------------------------------------------------ @@ -859,7 +967,150 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) return hw->slv_rd_byte.data_bytelen * 8; } +/*------------------------------------------------------------------------------ + * Interrupts + *----------------------------------------------------------------------------*/ +//helper macros to generate code for each interrupts +#define FOR_EACH_ITEM(op, list) do { list(op) } while(0) +#define INTR_LIST(item) \ + item(SPI_LL_INTR_TRANS_DONE, slave.int_trans_done_en, slave.trans_done, slave.trans_done=0) \ + item(SPI_LL_INTR_RDBUF, slave.int_rd_buf_done_en, slv_rdbuf_dlen.rd_buf_done, slv_rdbuf_dlen.rd_buf_done=0) \ + item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.wr_buf_done, slv_wrbuf_dlen.wr_buf_done=0) \ + item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.rd_dma_done, slv_rd_byte.rd_dma_done=0) \ + item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.wr_dma_done, slave1.wr_dma_done=0) \ + item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof, dma_int_raw.in_suc_eof, dma_int_clr.in_suc_eof=1) \ + item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof, dma_int_raw.out_eof, dma_int_clr.out_eof=1) \ + item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof, dma_int_raw.out_total_eof, dma_int_clr.out_total_eof=1) \ + item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \ + item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \ + item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err=1) \ + item(SPI_LL_INTR_WR_DONE, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1) + +static inline void spi_ll_enable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1; + FOR_EACH_ITEM(ENA_INTR, INTR_LIST); +#undef ENA_INTR +} + +static inline void spi_ll_disable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0; + FOR_EACH_ITEM(DIS_INTR, INTR_LIST); +#undef DIS_INTR +} + +static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define SET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit)) hw->st_reg = 1; + FOR_EACH_ITEM(SET_INTR, INTR_LIST); +#undef SET_INTR +} + +static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define CLR_INTR(intr_bit, _, __, clr_op) if (intr_mask & (intr_bit)) hw->clr_op; + FOR_EACH_ITEM(CLR_INTR, INTR_LIST); +#undef CLR_INTR +} + +static inline bool spi_ll_get_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask) +{ +#define GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true; + FOR_EACH_ITEM(GET_INTR, INTR_LIST); + return false; +#undef GET_INTR +} + +#undef FOR_EACH_ITEM +#undef INTR_LIST + +/** + * Disable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_disable_int(spi_dev_t *hw) +{ + hw->slave.int_trans_done_en = 0; +} + +/** + * Clear the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_clear_int_stat(spi_dev_t *hw) +{ + hw->slave.trans_done = 0; + hw->dma_int_clr.val = UINT32_MAX; +} + +/** + * Set the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_set_int_stat(spi_dev_t *hw) +{ + hw->slave.trans_done = 1; +} + +/** + * Enable the trans_done interrupt. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline void spi_ll_enable_int(spi_dev_t *hw) +{ + hw->slave.int_trans_done_en = 1; +} + +/** + * Set different interrupt types for the slave. + * + * @param hw Beginning address of the peripheral registers. + * @param int_type Interrupt type + */ +static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type) +{ + switch (int_type) { + case SPI_LL_INT_TYPE_SEG: + hw->dma_int_ena.in_suc_eof = 1; + hw->dma_int_ena.out_total_eof = 1; + hw->slave.int_trans_done_en = 0; + break; + default: + hw->dma_int_ena.in_suc_eof = 0; + hw->dma_int_ena.out_total_eof = 0; + hw->slave.int_trans_done_en = 1; + } +} + +/*------------------------------------------------------------------------------ + * Slave HD + *----------------------------------------------------------------------------*/ +static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t* hw, spi_ll_trans_len_cond_t cond_mask) +{ + hw->slv_rd_byte.rdbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slv_rd_byte.wrbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slv_rd_byte.rddma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slv_rd_byte.wrdma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; +} + +static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t* hw) +{ + return hw->slv_rd_byte.data_bytelen; +} + +static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw) +{ + return hw->slave1.last_addr; +} #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spimem_flash_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spimem_flash_ll.h index cb257d7f..d5a0e26a 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spimem_flash_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spimem_flash_ll.h @@ -227,12 +227,12 @@ static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev) * Select which pin to use for the flash * * @param dev Beginning address of the peripheral registers. - * @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins. + * @param pin Pin ID to use, 0-1. Set to other values to disable all the CS pins. */ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin) { - dev->misc.cs0_dis = (pin == 0) ? 0 : 1; - dev->misc.cs1_dis = (pin == 1) ? 0 : 1; + dev->misc.cs0_dis = (pin != 0); + dev->misc.cs1_dis = (pin != 1); } /** diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_hal.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_hal.h index d0aaff52..4c984a35 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_hal.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_hal.h @@ -182,32 +182,33 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info); #define touch_hal_filter_read_smooth(touch_num, smooth_data) touch_ll_filter_read_smooth(touch_num, smooth_data) /** - * Get baseline value of touch sensor. + * Get benchmark value of touch sensor. * - * @note After initialization, the baseline value is the maximum during the first measurement period. + * @note After initialization, the benchmark value is the maximum during the first measurement period. * @param touch_num touch pad index * @param touch_value pointer to accept touch sensor value */ -#define touch_hal_filter_read_baseline(touch_num, basedata) touch_ll_filter_read_baseline(touch_num, basedata) +#define touch_hal_read_benchmark(touch_num, benchmark) touch_ll_read_benchmark(touch_num, benchmark) /** - * Force reset baseline to raw data of touch sensor. + * Force reset benchmark to raw data of touch sensor. * * @param touch_num touch pad index * - TOUCH_PAD_MAX Reset basaline of all channels. */ -#define touch_hal_filter_reset_baseline(touch_num) touch_ll_filter_reset_baseline(touch_num) +#define touch_hal_reset_benchmark(touch_num) touch_ll_reset_benchmark(touch_num) /** - * Set filter mode. The input to the filter is raw data and the output is the baseline value. - * Larger filter coefficients increase the stability of the baseline. + * Set filter mode. The input of the filter is the raw value of touch reading, + * and the output of the filter is involved in the judgment of the touch state. * * @param mode Filter mode type. Refer to ``touch_filter_mode_t``. */ #define touch_hal_filter_set_filter_mode(mode) touch_ll_filter_set_filter_mode(mode) /** - * Get filter mode. The input to the filter is raw data and the output is the baseline value. + * Get filter mode. The input of the filter is the raw value of touch reading, + * and the output of the filter is involved in the judgment of the touch state. * * @param mode Filter mode type. Refer to ``touch_filter_mode_t``. */ @@ -229,89 +230,47 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info); #define touch_hal_filter_get_debounce(dbc_cnt) touch_ll_filter_get_debounce(dbc_cnt) /** - * Set hysteresis threshold coefficient. hysteresis = hysteresis_thr * touch_threshold. - * If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched. - * If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released. - * Range: 0 ~ 3. The coefficient is 0: 1/8; 1: 3/32; 2: 1/16; 3: 1/32 - * - * @param hys_thr hysteresis coefficient. - */ -#define touch_hal_filter_set_hysteresis(hys_thr) touch_ll_filter_set_hysteresis(hys_thr) - -/** - * Get hysteresis threshold coefficient. hysteresis = hysteresis_thr * touch_threshold. - * If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched. - * If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released. - * Range: 0 ~ 3. The coefficient is 0: 1/8; 1: 3/32; 2: 1/16; 3: 1/32 - * - * @param hys_thr hysteresis coefficient. - */ -#define touch_hal_filter_get_hysteresis(hys_thr) touch_ll_filter_get_hysteresis(hys_thr) - -/** - * Set noise threshold coefficient. noise = noise_thr * touch threshold. - * If (raw data - baseline) > (noise), the baseline stop updating. - * If (raw data - baseline) < (noise), the baseline start updating. - * Range: 0 ~ 3. The coefficient is 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; + * Set noise threshold coefficient. Higher = More noise resistance. + * The actual noise should be less than (noise coefficient * touch threshold). + * Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; * * @param hys_thr Noise threshold coefficient. */ #define touch_hal_filter_set_noise_thres(noise_thr) touch_ll_filter_set_noise_thres(noise_thr) /** - * Get noise threshold coefficient. noise = noise_thr * touch threshold. - * If (raw data - baseline) > (noise), the baseline stop updating. - * If (raw data - baseline) < (noise), the baseline start updating. - * Range: 0 ~ 3. The coefficient is 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; + * Get noise threshold coefficient. Higher = More noise resistance. + * The actual noise should be less than (noise coefficient * touch threshold). + * Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; * * @param noise_thr Noise threshold coefficient. */ #define touch_hal_filter_get_noise_thres(noise_thr) touch_ll_filter_get_noise_thres(noise_thr) /** - * Set negative noise threshold coefficient. negative noise = noise_neg_thr * touch threshold. - * If (baseline - raw data) > (negative noise), the baseline restart reset process(refer to `baseline_reset`). - * If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`). - * Range: 0 ~ 3. The coefficient is 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; - * - * @param noise_thr Negative threshold coefficient. - */ -#define touch_hal_filter_set_neg_noise_thres(noise_thr) touch_ll_filter_set_neg_noise_thres(noise_thr) - -/** - * Get negative noise threshold coefficient. negative noise = noise_neg_thr * touch threshold. - * If (baseline - raw data) > (negative noise), the baseline restart reset process(refer to `baseline_reset`). - * If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`). - * Range: 0 ~ 3. The coefficient is 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; - * - * @param noise_thr Negative noise threshold coefficient. - */ -#define touch_hal_filter_get_neg_noise_thres(noise_thr) touch_ll_filter_get_neg_noise_thres(noise_thr) - -/** - * Set the cumulative number of baseline reset processes. such as `n`. If the measured values continue to exceed - * the negative noise threshold for `n` times, the baseline reset to raw data. + * Set the cumulative number of benchmark reset processes. such as `n`. If the measured values continue to exceed + * the negative noise threshold for `n` times, the benchmark reset to raw data. * Range: 0 ~ 15 * - * @param reset_cnt The cumulative number of baseline reset processes. + * @param reset_cnt The cumulative number of benchmark reset processes. */ -#define touch_hal_filter_set_baseline_reset(reset_cnt) touch_ll_filter_set_baseline_reset(reset_cnt) +#define touch_hal_filter_set_benchmark_reset(reset_cnt) touch_ll_filter_set_benchmark_reset(reset_cnt) /** - * Get the cumulative number of baseline reset processes. such as `n`. If the measured values continue to exceed - * the negative noise threshold for `n` times, the baseline reset to raw data. + * Get the cumulative number of benchmark reset processes. such as `n`. If the measured values continue to exceed + * the negative noise threshold for `n` times, the benchmark reset to raw data. * Range: 0 ~ 15 * - * @param reset_cnt The cumulative number of baseline reset processes. + * @param reset_cnt The cumulative number of benchmark reset processes. */ -#define touch_hal_filter_get_baseline_reset(reset_cnt) touch_ll_filter_get_baseline_reset(reset_cnt) +#define touch_hal_filter_get_benchmark_reset(reset_cnt) touch_ll_filter_get_benchmark_reset(reset_cnt) /** * Set jitter filter step size. * If filter mode is jitter, should set filter step for jitter. * Range: 0 ~ 15 * - * @param step The step size of the data change when the baseline is updated. + * @param step The step size of the data change. */ #define touch_hal_filter_set_jitter_step(step) touch_ll_filter_set_jitter_step(step) @@ -320,7 +279,7 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info); * If filter mode is jitter, should set filter step for jitter. * Range: 0 ~ 15 * - * @param step The step size of the data change when the baseline is updated. + * @param step The step size of the data change. */ #define touch_hal_filter_get_jitter_step(step) touch_ll_filter_get_jitter_step(step) @@ -453,11 +412,11 @@ void touch_hal_denoise_enable(void); /** * Set parameter of waterproof function. - * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. - * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. + * + * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. + * Guard pad is used to detect the large area of water covering the touch panel. + * Shield pad is used to shield the influence of water droplets covering the touch panel. + * It is generally designed as a grid and is placed around the touch buttons. * * @param waterproof parameter of waterproof */ @@ -472,21 +431,12 @@ void touch_hal_waterproof_get_config(touch_pad_waterproof_t *waterproof); /** * Enable parameter of waterproof function. - * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. - * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. + * Should be called after function ``touch_hal_waterproof_set_config``. */ void touch_hal_waterproof_enable(void); /** * Disable parameter of waterproof function. - * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. - * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. */ #define touch_hal_waterproof_disable() touch_ll_waterproof_disable() @@ -591,7 +541,7 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable); /** * Set the trigger threshold of touch sensor in deep sleep. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * * @note The threshold at sleep is the same as the threshold before sleep. */ @@ -600,7 +550,7 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable); /** * Get the trigger threshold of touch sensor in deep sleep. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * * @note The threshold at sleep is the same as the threshold before sleep. */ @@ -617,11 +567,11 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable); #define touch_hal_sleep_disable_approach() touch_ll_sleep_disable_approach() /** - * Read baseline of touch sensor for sleep pad. + * Read benchmark of touch sensor for sleep pad. * - * @param baseline Pointer to accept touch sensor baseline value. + * @param benchmark Pointer to accept touch sensor benchmark value. */ -#define touch_hal_sleep_read_baseline(baseline) touch_ll_sleep_read_baseline(baseline) +#define touch_hal_sleep_read_benchmark(benchmark) touch_ll_sleep_read_benchmark(benchmark) /** * Read smooth data of touch sensor for sleep pad. @@ -634,9 +584,9 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable); #define touch_hal_sleep_read_data(raw_data) touch_ll_sleep_read_data(raw_data) /** - * Reset baseline of touch sensor for sleep pad. + * Reset benchmark of touch sensor for sleep pad. */ -#define touch_hal_sleep_reset_baseline() touch_ll_sleep_reset_baseline() +#define touch_hal_sleep_reset_benchmark() touch_ll_sleep_reset_benchmark() /** * Read debounce of touch sensor for sleep pad. diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_ll.h index 2d59dfe0..76a64dcf 100644 --- a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_ll.h +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_ll.h @@ -32,7 +32,7 @@ extern "C" { #endif #define TOUCH_LL_READ_RAW 0x0 -#define TOUCH_LL_READ_BASELINE 0x2 +#define TOUCH_LL_READ_BENCHMARK 0x2 #define TOUCH_LL_READ_SMOOTH 0x3 #define TOUCH_LL_TIMER_FORCE_DONE 0x3 #define TOUCH_LL_TIMER_DONE 0x0 @@ -307,7 +307,7 @@ static inline void touch_ll_start_sw_meas(void) /** * Set the trigger threshold of touch sensor. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * * @note If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be trigered. * @param touch_num touch pad index @@ -321,7 +321,7 @@ static inline void touch_ll_set_threshold(touch_pad_t touch_num, uint32_t thresh /** * Get the trigger threshold of touch sensor. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * * @param touch_num touch pad index. * @param threshold pointer to accept threshold. @@ -635,28 +635,28 @@ static inline void IRAM_ATTR touch_ll_filter_read_smooth(touch_pad_t touch_num, } /** - * Get baseline value of touch sensor. + * Get benchmark value of touch sensor. * - * @note After initialization, the baseline value is the maximum during the first measurement period. + * @note After initialization, the benchmark value is the maximum during the first measurement period. * @param touch_num touch pad index * @param touch_value pointer to accept touch sensor value */ -static inline void IRAM_ATTR touch_ll_filter_read_baseline(touch_pad_t touch_num, uint32_t *basedata) +static inline void IRAM_ATTR touch_ll_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark) { - SENS.sar_touch_conf.touch_data_sel = TOUCH_LL_READ_BASELINE; - *basedata = SENS.sar_touch_status[touch_num - 1].touch_pad_data; + SENS.sar_touch_conf.touch_data_sel = TOUCH_LL_READ_BENCHMARK; + *benchmark = SENS.sar_touch_status[touch_num - 1].touch_pad_data; } /** - * Force reset baseline to raw data of touch sensor. + * Force reset benchmark to raw data of touch sensor. * * @note If call this API, make sure enable clock gate(`touch_ll_clkgate`) first. * @param touch_num touch pad index * - TOUCH_PAD_MAX Reset basaline of all channels. */ -static inline void touch_ll_filter_reset_baseline(touch_pad_t touch_num) +static inline void touch_ll_reset_benchmark(touch_pad_t touch_num) { - /* Clear touch channels to initialize the channel value (baseline, raw_data). + /* Clear touch channels to initialize the channel value (benchmark, raw_data). */ if (touch_num == TOUCH_PAD_MAX) { SENS.sar_touch_chn_st.touch_channel_clr = SOC_TOUCH_SENSOR_BIT_MASK_MAX; @@ -666,8 +666,8 @@ static inline void touch_ll_filter_reset_baseline(touch_pad_t touch_num) } /** - * Set filter mode. The input to the filter is raw data and the output is the baseline value. - * Larger filter coefficients increase the stability of the baseline. + * Set filter mode. The input of the filter is the raw value of touch reading, + * and the output of the filter is involved in the judgment of the touch state. * * @param mode Filter mode type. Refer to ``touch_filter_mode_t``. */ @@ -677,7 +677,8 @@ static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode) } /** - * Get filter mode. The input to the filter is raw data and the output is the baseline value. + * Get filter mode. The input of the filter is the raw value of touch reading, + * and the output of the filter is involved in the judgment of the touch state. * * @param mode Filter mode type. Refer to ``touch_filter_mode_t``. */ @@ -729,35 +730,8 @@ static inline void touch_ll_filter_get_debounce(uint32_t *dbc_cnt) } /** - * Set hysteresis threshold coefficient. hysteresis = hysteresis_thr * touch_threshold. - * If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched. - * If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released. - * Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 2/32; 3: OFF. - * - * @param hys_thr hysteresis coefficient. - */ -static inline void touch_ll_filter_set_hysteresis(uint32_t hys_thr) -{ - RTCCNTL.touch_filter_ctrl.touch_hysteresis = hys_thr; -} - -/** - * Get hysteresis threshold coefficient. hysteresis = hysteresis_thr * touch_threshold. - * If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched. - * If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released. - * Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 2/32; 3: OFF. - * - * @param hys_thr hysteresis coefficient. - */ -static inline void touch_ll_filter_get_hysteresis(uint32_t *hys_thr) -{ - *hys_thr = RTCCNTL.touch_filter_ctrl.touch_hysteresis; -} - -/** - * Set noise threshold coefficient. noise = noise_thr * touch threshold. - * If (raw data - baseline) > (noise), the baseline stop updating. - * If (raw data - baseline) < (noise), the baseline start updating. + * Set noise threshold coefficient. Higher = More noise resistance. + * The actual noise should be less than (noise coefficient * touch threshold). * Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; * * @param hys_thr Noise threshold coefficient. @@ -765,12 +739,14 @@ static inline void touch_ll_filter_get_hysteresis(uint32_t *hys_thr) static inline void touch_ll_filter_set_noise_thres(uint32_t noise_thr) { RTCCNTL.touch_filter_ctrl.touch_noise_thres = noise_thr; + RTCCNTL.touch_filter_ctrl.config2 = noise_thr; + RTCCNTL.touch_filter_ctrl.config1 = 0xF; + RTCCNTL.touch_filter_ctrl.config3 = 2; } /** - * Get noise threshold coefficient. noise = noise_thr * touch threshold. - * If (raw data - baseline) > (noise), the baseline stop updating. - * If (raw data - baseline) < (noise), the baseline start updating. + * Get noise threshold coefficient. Higher = More noise resistance. + * The actual noise should be less than (noise coefficient * touch threshold). * Range: 0 ~ 3. The coefficient is 0: 4/8; 1: 3/8; 2: 2/8; 3: 1; * * @param noise_thr Noise threshold coefficient. @@ -780,62 +756,12 @@ static inline void touch_ll_filter_get_noise_thres(uint32_t *noise_thr) *noise_thr = RTCCNTL.touch_filter_ctrl.touch_noise_thres; } -/** - * Set negative noise threshold coefficient. negative noise = noise_neg_thr * touch threshold. - * If (baseline - raw data) > (negative noise), the baseline restart reset process(refer to `baseline_reset`). - * If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`). - * Range: 0 ~ 3. The coefficient is 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; - * - * @param noise_thr Negative threshold coefficient. - */ -static inline void touch_ll_filter_set_neg_noise_thres(uint32_t noise_thr) -{ - RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres = noise_thr; -} - -/** - * Get negative noise threshold coefficient. negative noise = noise_neg_thr * touch threshold. - * If (baseline - raw data) > (negative noise), the baseline restart reset process(refer to `baseline_reset`). - * If (baseline - raw data) < (negative noise), the baseline stop reset process(refer to `baseline_reset`). - * Range: 0 ~ 3. The coefficient is 0: 1/2; 1: 3/8; 2: 1/4; 3: 1/8; - * - * @param noise_thr Negative noise threshold coefficient. - */ -static inline void touch_ll_filter_get_neg_noise_thres(uint32_t *noise_thr) -{ - *noise_thr = RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres; -} - -/** - * Set the cumulative number of baseline reset processes. such as `n`. If the measured values continue to exceed - * the negative noise threshold for `n+1` times, the baseline reset to raw data. - * Range: 0 ~ 15 - * - * @param reset_cnt The cumulative number of baseline reset processes. - */ -static inline void touch_ll_filter_set_baseline_reset(uint32_t reset_cnt) -{ - RTCCNTL.touch_filter_ctrl.touch_neg_noise_limit = reset_cnt; -} - -/** - * Get the cumulative number of baseline reset processes. such as `n`. If the measured values continue to exceed - * the negative noise threshold for `n+1` times, the baseline reset to raw data. - * Range: 0 ~ 15 - * - * @param reset_cnt The cumulative number of baseline reset processes. - */ -static inline void touch_ll_filter_get_baseline_reset(uint32_t *reset_cnt) -{ - *reset_cnt = RTCCNTL.touch_filter_ctrl.touch_neg_noise_limit; -} - /** * Set jitter filter step size. * If filter mode is jitter, should set filter step for jitter. * Range: 0 ~ 15 * - * @param step The step size of the data change when the baseline is updated. + * @param step The step size of the data change. */ static inline void touch_ll_filter_set_jitter_step(uint32_t step) { @@ -847,7 +773,7 @@ static inline void touch_ll_filter_set_jitter_step(uint32_t step) * If filter mode is jitter, should set filter step for jitter. * Range: 0 ~ 15 * - * @param step The step size of the data change when the baseline is updated. + * @param step The step size of the data change. */ static inline void touch_ll_filter_get_jitter_step(uint32_t *step) { @@ -1004,11 +930,11 @@ static inline void touch_ll_waterproof_get_sheild_driver(touch_pad_shield_driver /** * Enable parameter of waterproof function. + * * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. + * Guard pad is used to detect the large area of water covering the touch panel. + * Shield pad is used to shield the influence of water droplets covering the touch panel. * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. */ static inline void touch_ll_waterproof_enable(void) { @@ -1017,11 +943,6 @@ static inline void touch_ll_waterproof_enable(void) /** * Disable parameter of waterproof function. - * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel. - * The shielded channel outputs the same signal as the channel being measured. - * It is generally designed as a grid and is placed around the touch buttons. - * The shielded channel does not follow the measurement signal of the protection channel. - * So that the guard channel can detect a large area of water. */ static inline void touch_ll_waterproof_disable(void) { @@ -1135,7 +1056,7 @@ static inline void touch_ll_sleep_get_channel_num(touch_pad_t *touch_num) /** * Set the trigger threshold of touch sensor in deep sleep. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep. */ @@ -1147,7 +1068,7 @@ static inline void touch_ll_sleep_set_threshold(uint32_t touch_thres) /** * Get the trigger threshold of touch sensor in deep sleep. * The threshold determines the sensitivity of the touch sensor. - * The threshold is the original value of the trigger state minus the baseline value. + * The threshold is the original value of the trigger state minus the benchmark value. * * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep. */ @@ -1181,14 +1102,14 @@ static inline bool touch_ll_sleep_get_approach_status(void) } /** - * Read baseline of touch sensor for sleep pad. + * Read benchmark of touch sensor for sleep pad. * - * @param baseline Pointer to accept touch sensor baseline value. + * @param benchmark Pointer to accept touch sensor benchmark value. */ -static inline void touch_ll_sleep_read_baseline(uint32_t *baseline) +static inline void touch_ll_sleep_read_benchmark(uint32_t *benchmark) { - SENS.sar_touch_conf.touch_data_sel = TOUCH_LL_READ_BASELINE; - *baseline = SENS.sar_touch_slp_status.touch_slp_data; + SENS.sar_touch_conf.touch_data_sel = TOUCH_LL_READ_BENCHMARK; + *benchmark = SENS.sar_touch_slp_status.touch_slp_data; } static inline void touch_ll_sleep_read_smooth(uint32_t *smooth_data) @@ -1205,7 +1126,7 @@ static inline void touch_ll_sleep_read_data(uint32_t *raw_data) *raw_data = SENS.sar_touch_status[touch_num - 1].touch_pad_data; } -static inline void touch_ll_sleep_reset_baseline(void) +static inline void touch_ll_sleep_reset_benchmark(void) { RTCCNTL.touch_approach.touch_slp_channel_clr = 1; } diff --git a/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/twai_ll.h b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/twai_ll.h new file mode 100644 index 00000000..2c05b4f5 --- /dev/null +++ b/tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/twai_ll.h @@ -0,0 +1,675 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The ll is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The Lowlevel layer for TWAI + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "hal/twai_types.h" +#include "soc/twai_periph.h" + +/* ------------------------- Defines and Typedefs --------------------------- */ + +#define TWAI_LL_STATUS_RBS (0x1 << 0) +#define TWAI_LL_STATUS_DOS (0x1 << 1) +#define TWAI_LL_STATUS_TBS (0x1 << 2) +#define TWAI_LL_STATUS_TCS (0x1 << 3) +#define TWAI_LL_STATUS_RS (0x1 << 4) +#define TWAI_LL_STATUS_TS (0x1 << 5) +#define TWAI_LL_STATUS_ES (0x1 << 6) +#define TWAI_LL_STATUS_BS (0x1 << 7) +//Todo: Add Miss status support + +#define TWAI_LL_INTR_RI (0x1 << 0) +#define TWAI_LL_INTR_TI (0x1 << 1) +#define TWAI_LL_INTR_EI (0x1 << 2) +//Data overrun interrupt not supported in SW due to HW peculiarities +#define TWAI_LL_INTR_EPI (0x1 << 5) +#define TWAI_LL_INTR_ALI (0x1 << 6) +#define TWAI_LL_INTR_BEI (0x1 << 7) + +/* + * The following frame structure has an NEARLY identical bit field layout to + * each byte of the TX buffer. This allows for formatting and parsing frames to + * be done outside of time critical regions (i.e., ISRs). All the ISR needs to + * do is to copy byte by byte to/from the TX/RX buffer. The two reserved bits in + * TX buffer are used in the frame structure to store the self_reception and + * single_shot flags which in turn indicate the type of transmission to execute. + */ +typedef union { + struct { + struct { + uint8_t dlc: 4; //Data length code (0 to 8) of the frame + uint8_t self_reception: 1; //This frame should be transmitted using self reception command + uint8_t single_shot: 1; //This frame should be transmitted using single shot command + uint8_t rtr: 1; //This frame is a remote transmission request + uint8_t frame_format: 1; //Format of the frame (1 = extended, 0 = standard) + }; + union { + struct { + uint8_t id[2]; //11 bit standard frame identifier + uint8_t data[8]; //Data bytes (0 to 8) + uint8_t reserved8[2]; + } standard; + struct { + uint8_t id[4]; //29 bit extended frame identifier + uint8_t data[8]; //Data bytes (0 to 8) + } extended; + }; + }; + uint8_t bytes[13]; +} __attribute__((packed)) twai_ll_frame_buffer_t; + +_Static_assert(sizeof(twai_ll_frame_buffer_t) == 13, "TX/RX buffer type should be 13 bytes"); + +/* ---------------------------- Mode Register ------------------------------- */ + +/** + * @brief Enter reset mode + * + * When in reset mode, the TWAI controller is effectively disconnected from the + * TWAI bus and will not participate in any bus activates. Reset mode is required + * in order to write the majority of configuration registers. + * + * @param hw Start address of the TWAI registers + * @return true if reset mode was entered successfully + * + * @note Reset mode is automatically entered on BUS OFF condition + */ +static inline bool twai_ll_enter_reset_mode(twai_dev_t *hw) +{ + hw->mode_reg.rm = 1; + return hw->mode_reg.rm; +} + +/** + * @brief Exit reset mode + * + * When not in reset mode, the TWAI controller will take part in bus activities + * (e.g., send/receive/acknowledge messages and error frames) depending on the + * operating mode. + * + * @param hw Start address of the TWAI registers + * @return true if reset mode was exit successfully + * + * @note Reset mode must be exit to initiate BUS OFF recovery + */ +static inline bool twai_ll_exit_reset_mode(twai_dev_t *hw) +{ + hw->mode_reg.rm = 0; + return !(hw->mode_reg.rm); +} + +/** + * @brief Check if in reset mode + * @param hw Start address of the TWAI registers + * @return true if in reset mode + */ +static inline bool twai_ll_is_in_reset_mode(twai_dev_t *hw) +{ + return hw->mode_reg.rm; +} + +/** + * @brief Set operating mode of TWAI controller + * + * @param hw Start address of the TWAI registers + * @param mode Operating mode + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_mode(twai_dev_t *hw, twai_mode_t mode) +{ + if (mode == TWAI_MODE_NORMAL) { //Normal Operating mode + hw->mode_reg.lom = 0; + hw->mode_reg.stm = 0; + } else if (mode == TWAI_MODE_NO_ACK) { //Self Test Mode (No Ack) + hw->mode_reg.lom = 0; + hw->mode_reg.stm = 1; + } else if (mode == TWAI_MODE_LISTEN_ONLY) { //Listen Only Mode + hw->mode_reg.lom = 1; + hw->mode_reg.stm = 0; + } +} + +/* --------------------------- Command Register ----------------------------- */ + +/** + * @brief Set TX command + * + * Setting the TX command will cause the TWAI controller to attempt to transmit + * the frame stored in the TX buffer. The TX buffer will be occupied (i.e., + * locked) until TX completes. + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_tx(twai_dev_t *hw) +{ + hw->command_reg.tr = 1; +} + +/** + * @brief Set single shot TX command + * + * Similar to setting TX command, but the TWAI controller will not automatically + * retry transmission upon an error (e.g., due to an acknowledgement error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_tx_single_shot(twai_dev_t *hw) +{ + hw->command_reg.val = 0x03; //Set command_reg.tr and command_reg.at simultaneously for single shot transmittion request +} + +/** + * @brief Aborts TX + * + * Frames awaiting TX will be aborted. Frames already being TX are not aborted. + * Transmission Complete Status bit is automatically set to 1. + * Similar to setting TX command, but the TWAI controller will not automatically + * retry transmission upon an error (e.g., due to acknowledge error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_abort_tx(twai_dev_t *hw) +{ + hw->command_reg.at = 1; +} + +/** + * @brief Release RX buffer + * + * Rotates RX buffer to the next frame in the RX FIFO. + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_set_cmd_release_rx_buffer(twai_dev_t *hw) +{ + hw->command_reg.rrb = 1; +} + +/** + * @brief Clear data overrun + * + * Clears the data overrun status bit + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_set_cmd_clear_data_overrun(twai_dev_t *hw) +{ + hw->command_reg.cdo = 1; +} + +/** + * @brief Set self reception single shot command + * + * Similar to setting TX command, but the TWAI controller also simultaneously + * receive the transmitted frame and is generally used for self testing + * purposes. The TWAI controller will not ACK the received message, so consider + * using the NO_ACK operating mode. + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_self_rx_request(twai_dev_t *hw) +{ + hw->command_reg.srr = 1; +} + +/** + * @brief Set self reception request command + * + * Similar to setting the self reception request, but the TWAI controller will + * not automatically retry transmission upon an error (e.g., due to and + * acknowledgement error). + * + * @param hw Start address of the TWAI registers + * + * @note Transmit commands should be called last (i.e., after handling buffer + * release and clear data overrun) in order to prevent the other commands + * overwriting this latched TX bit with 0. + */ +static inline void twai_ll_set_cmd_self_rx_single_shot(twai_dev_t *hw) +{ + hw->command_reg.val = 0x12; //Set command_reg.srr and command_reg.at simultaneously for single shot self reception request +} + +/* --------------------------- Status Register ------------------------------ */ + +/** + * @brief Get all status bits + * + * @param hw Start address of the TWAI registers + * @return Status bits + */ +static inline uint32_t twai_ll_get_status(twai_dev_t *hw) +{ + return hw->status_reg.val; +} + +/** + * @brief Check if RX FIFO overrun status bit is set + * + * @param hw Start address of the TWAI registers + * @return Overrun status bit + */ +static inline bool twai_ll_is_fifo_overrun(twai_dev_t *hw) +{ + return hw->status_reg.dos; +} + +/** + * @brief Check if previously TX was successful + * + * @param hw Start address of the TWAI registers + * @return Whether previous TX was successful + */ +static inline bool twai_ll_is_last_tx_successful(twai_dev_t *hw) +{ + return hw->status_reg.tcs; +} + +//Todo: Add stand alone status bit check functions when necessary + +/* -------------------------- Interrupt Register ---------------------------- */ + +/** + * @brief Get currently set interrupts + * + * Reading the interrupt registers will automatically clear all interrupts + * except for the Receive Interrupt. + * + * @param hw Start address of the TWAI registers + * @return Bit mask of set interrupts + */ +static inline uint32_t twai_ll_get_and_clear_intrs(twai_dev_t *hw) +{ + return hw->interrupt_reg.val; +} + +/* ----------------------- Interrupt Enable Register ------------------------ */ + +/** + * @brief Set which interrupts are enabled + * + * @param hw Start address of the TWAI registers + * @param Bit mask of interrupts to enable + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask) +{ + hw->interrupt_enable_reg.val = intr_mask; +} + +/* ------------------------ Bus Timing Registers --------------------------- */ + +/** + * @brief Set bus timing + * + * @param hw Start address of the TWAI registers + * @param brp Baud Rate Prescaler + * @param sjw Synchronization Jump Width + * @param tseg1 Timing Segment 1 + * @param tseg2 Timing Segment 2 + * @param triple_sampling Triple Sampling enable/disable + * + * @note Must be called in reset mode + * @note ESP32S2 brp can be any even number between 2 to 32768 + */ +static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling) +{ + hw->bus_timing_0_reg.brp = (brp / 2) - 1; + hw->bus_timing_0_reg.sjw = sjw - 1; + hw->bus_timing_1_reg.tseg1 = tseg1 - 1; + hw->bus_timing_1_reg.tseg2 = tseg2 - 1; + hw->bus_timing_1_reg.sam = triple_sampling; +} + +/* ----------------------------- ALC Register ------------------------------- */ + +/** + * @brief Clear Arbitration Lost Capture Register + * + * Reading the ALC register rearms the Arbitration Lost Interrupt + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_clear_arb_lost_cap(twai_dev_t *hw) +{ + (void)hw->arbitration_lost_captue_reg.val; + //Todo: Decode ALC register +} + +/* ----------------------------- ECC Register ------------------------------- */ + +/** + * @brief Clear Error Code Capture register + * + * Reading the ECC register rearms the Bus Error Interrupt + * + * @param hw Start address of the TWAI registers + */ +static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw) +{ + (void)hw->error_code_capture_reg.val; + //Todo: Decode error code capture +} + +/* ----------------------------- EWL Register ------------------------------- */ + +/** + * @brief Set Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @param ewl Error Warning Limit + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_err_warn_lim(twai_dev_t *hw, uint32_t ewl) +{ + hw->error_warning_limit_reg.ewl = ewl; +} + +/** + * @brief Get Error Warning Limit + * + * @param hw Start address of the TWAI registers + * @return Error Warning Limit + */ +static inline uint32_t twai_ll_get_err_warn_lim(twai_dev_t *hw) +{ + return hw->error_warning_limit_reg.val; +} + +/* ------------------------ RX Error Count Register ------------------------- */ + +/** + * @brief Get RX Error Counter + * + * @param hw Start address of the TWAI registers + * @return REC value + * + * @note REC is not frozen in reset mode. Listen only mode will freeze it. A BUS + * OFF condition automatically sets the REC to 0. + */ +static inline uint32_t twai_ll_get_rec(twai_dev_t *hw) +{ + return hw->rx_error_counter_reg.val; +} + +/** + * @brief Set RX Error Counter + * + * @param hw Start address of the TWAI registers + * @param rec REC value + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_rec(twai_dev_t *hw, uint32_t rec) +{ + hw->rx_error_counter_reg.rxerr = rec; +} + +/* ------------------------ TX Error Count Register ------------------------- */ + +/** + * @brief Get TX Error Counter + * + * @param hw Start address of the TWAI registers + * @return TEC value + * + * @note A BUS OFF condition will automatically set this to 128 + */ +static inline uint32_t twai_ll_get_tec(twai_dev_t *hw) +{ + return hw->tx_error_counter_reg.val; +} + +/** + * @brief Set TX Error Counter + * + * @param hw Start address of the TWAI registers + * @param tec TEC value + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec) +{ + hw->tx_error_counter_reg.txerr = tec; +} + +/* ---------------------- Acceptance Filter Registers ----------------------- */ + +/** + * @brief Set Acceptance Filter + * @param hw Start address of the TWAI registers + * @param code Acceptance Code + * @param mask Acceptance Mask + * @param single_filter Whether to enable single filter mode + * + * @note Must be called in reset mode + */ +static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter) +{ + uint32_t code_swapped = __builtin_bswap32(code); + uint32_t mask_swapped = __builtin_bswap32(mask); + for (int i = 0; i < 4; i++) { + hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF); + hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF); + } + hw->mode_reg.afm = single_filter; +} + +/* ------------------------- TX/RX Buffer Registers ------------------------- */ + +/** + * @brief Copy a formatted TWAI frame into TX buffer for transmission + * + * @param hw Start address of the TWAI registers + * @param tx_frame Pointer to formatted frame + * + * @note Call twai_ll_format_frame_buffer() to format a frame + */ +static inline void twai_ll_set_tx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t *tx_frame) +{ + //Copy formatted frame into TX buffer + for (int i = 0; i < 13; i++) { + hw->tx_rx_buffer[i].val = tx_frame->bytes[i]; + } +} + +/** + * @brief Copy a received frame from the RX buffer for parsing + * + * @param hw Start address of the TWAI registers + * @param rx_frame Pointer to store formatted frame + * + * @note Call twai_ll_prase_frame_buffer() to parse the formatted frame + */ +static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t *rx_frame) +{ + //Copy RX buffer registers into frame + for (int i = 0; i < 13; i++) { + rx_frame->bytes[i] = hw->tx_rx_buffer[i].byte; + } +} + +/** + * @brief Format contents of a TWAI frame into layout of TX Buffer + * + * This function encodes a message into a frame structure. The frame structure + * has an identical layout to the TX buffer, allowing the frame structure to be + * directly copied into TX buffer. + * + * @param[in] 11bit or 29bit ID + * @param[in] dlc Data length code + * @param[in] data Pointer to an 8 byte array containing data. NULL if no data + * @param[in] format Type of TWAI frame + * @param[in] single_shot Frame will not be retransmitted on failure + * @param[in] self_rx Frame will also be simultaneously received + * @param[out] tx_frame Pointer to store formatted frame + */ +static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const uint8_t *data, + uint32_t flags, twai_ll_frame_buffer_t *tx_frame) +{ + bool is_extd = flags & TWAI_MSG_FLAG_EXTD; + bool is_rtr = flags & TWAI_MSG_FLAG_RTR; + + //Set frame information + tx_frame->dlc = dlc; + tx_frame->frame_format = is_extd; + tx_frame->rtr = is_rtr; + tx_frame->self_reception = (flags & TWAI_MSG_FLAG_SELF) ? 1 : 0; + tx_frame->single_shot = (flags & TWAI_MSG_FLAG_SS) ? 1 : 0; + + //Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required + if (is_extd) { + uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i)) + for (int i = 0; i < 4; i++) { + tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF; + } + } else { + uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i)) + for (int i = 0; i < 2; i++) { + tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF; + } + } + + uint8_t *data_buffer = (is_extd) ? tx_frame->extended.data : tx_frame->standard.data; + if (!is_rtr) { //Only copy data if the frame is a data frame (i.e not a remote frame) + for (int i = 0; (i < dlc) && (i < TWAI_FRAME_MAX_DLC); i++) { + data_buffer[i] = data[i]; + } + } +} + +/** + * @brief Parse formatted TWAI frame (RX Buffer Layout) into its constituent contents + * + * @param[in] rx_frame Pointer to formatted frame + * @param[out] id 11 or 29bit ID + * @param[out] dlc Data length code + * @param[out] data Data. Left over bytes set to 0. + * @param[out] format Type of TWAI frame + */ +static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame, uint32_t *id, uint8_t *dlc, + uint8_t *data, uint32_t *flags) +{ + //Copy frame information + *dlc = rx_frame->dlc; + uint32_t flags_temp = 0; + flags_temp |= (rx_frame->frame_format) ? TWAI_MSG_FLAG_EXTD : 0; + flags_temp |= (rx_frame->rtr) ? TWAI_MSG_FLAG_RTR : 0; + flags_temp |= (rx_frame->dlc > TWAI_FRAME_MAX_DLC) ? TWAI_MSG_FLAG_DLC_NON_COMP : 0; + *flags = flags_temp; + + //Copy ID. The ID registers are big endian and left aligned, therefore a bswap will be required + if (rx_frame->frame_format) { + uint32_t id_temp = 0; + for (int i = 0; i < 4; i++) { + id_temp |= rx_frame->extended.id[i] << (8 * i); + } + id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3) + *id = id_temp & TWAI_EXTD_ID_MASK; + } else { + uint32_t id_temp = 0; + for (int i = 0; i < 2; i++) { + id_temp |= rx_frame->standard.id[i] << (8 * i); + } + id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5) + *id = id_temp & TWAI_STD_ID_MASK; + } + + uint8_t *data_buffer = (rx_frame->frame_format) ? rx_frame->extended.data : rx_frame->standard.data; + //Only copy data if the frame is a data frame (i.e. not a remote frame) + int data_length = (rx_frame->rtr) ? 0 : ((rx_frame->dlc > TWAI_FRAME_MAX_DLC) ? TWAI_FRAME_MAX_DLC : rx_frame->dlc); + for (int i = 0; i < data_length; i++) { + data[i] = data_buffer[i]; + } + //Set remaining bytes of data to 0 + for (int i = data_length; i < TWAI_FRAME_MAX_DLC; i++) { + data[i] = 0; + } +} + +/* ----------------------- RX Message Count Register ------------------------ */ + +/** + * @brief Get RX Message Counter + * + * @param hw Start address of the TWAI registers + * @return RX Message Counter + */ +static inline uint32_t twai_ll_get_rx_msg_count(twai_dev_t *hw) +{ + return hw->rx_message_counter_reg.val; +} + +/* ------------------------- Clock Divider Register ------------------------- */ + +/** + * @brief Set CLKOUT Divider and enable/disable + * + * Configure CLKOUT. CLKOUT is a pre-scaled version of APB CLK. Divider can be + * 1, or any even number from 2 to 490. Set the divider to 0 to disable CLKOUT. + * + * @param hw Start address of the TWAI registers + * @param divider Divider for CLKOUT (any even number from 2 to 490). Set to 0 to disable CLKOUT + */ +static inline void twai_ll_set_clkout(twai_dev_t *hw, uint32_t divider) +{ + if (divider >= 2 && divider <= 490) { + hw->clock_divider_reg.co = 0; + hw->clock_divider_reg.cd = (divider / 2) - 1; + } else if (divider == 1) { + //Setting the divider reg to max value (255) means a divider of 1 + hw->clock_divider_reg.co = 0; + hw->clock_divider_reg.cd = 255; + } else { + hw->clock_divider_reg.co = 1; + hw->clock_divider_reg.cd = 0; + } +} + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/spi_flash/include/esp_flash.h b/tools/sdk/esp32s2/include/spi_flash/include/esp_flash.h index a60bfe43..d100c57f 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/esp_flash.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/esp_flash.h @@ -34,7 +34,15 @@ typedef struct { uint32_t size; ///< Size of the region } esp_flash_region_t; -/** OS-level integration hooks for accessing flash chips inside a running OS */ +/** @brief OS-level integration hooks for accessing flash chips inside a running OS + * + * It's in the public header because some instances should be allocated statically in the startup + * code. May be updated according to hardware version and new flash chip feature requirements, + * shouldn't be treated as public API. + * + * For advanced developers, you may replace some of them with your implementations at your own + * risk. +*/ typedef struct { /** * Called before commencing any flash operation. Does not need to be @@ -50,14 +58,29 @@ typedef struct { /** Delay for at least 'us' microseconds. Called in between 'start' and 'end'. */ esp_err_t (*delay_us)(void *arg, unsigned us); + + /** Called for get temp buffer when buffer from application cannot be directly read into/write from. */ + void *(*get_temp_buffer)(void* arg, size_t reqest_size, size_t* out_size); + + /** Called for release temp buffer. */ + void (*release_temp_buffer)(void* arg, void *temp_buf); + + /** Yield to other tasks. Called during erase operations. */ + esp_err_t (*yield)(void *arg); } esp_flash_os_functions_t; /** @brief Structure to describe a SPI flash chip connected to the system. - Structure must be initialized before use (passed to esp_flash_init()). + Structure must be initialized before use (passed to esp_flash_init()). It's in the public + header because some instances should be allocated statically in the startup code. May be + updated according to hardware version and new flash chip feature requirements, shouldn't be + treated as public API. + + For advanced developers, you may replace some of them with your implementations at your own + risk. */ struct esp_flash_t { - spi_flash_host_driver_t *host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used. + spi_flash_host_inst_t* host; ///< Pointer to hardware-specific "host_driver" structure. Must be initialized before used. const spi_flash_chip_t *chip_drv; ///< Pointer to chip-model-specific "adapter" structure. If NULL, will be detected during initialisation. const esp_flash_os_functions_t *os_func; ///< Pointer to os-specific hook structure. Call ``esp_flash_init_os_functions()`` to setup this field, after the host is properly initialized. diff --git a/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash.h b/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash.h index 9e8b19e8..59d3679d 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/esp_spi_flash.h @@ -341,6 +341,10 @@ typedef void (*spi_flash_op_unlock_func_t)(void); * @brief Function to protect SPI flash critical regions corruption. */ typedef bool (*spi_flash_is_safe_write_address_t)(size_t addr, size_t size); +/** + * @brief Function to yield to the OS during erase operation. + */ +typedef void (*spi_flash_os_yield_t)(void); /** * Structure holding SPI flash access critical sections management functions. @@ -381,6 +385,7 @@ typedef struct { #if !CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED spi_flash_is_safe_write_address_t is_safe_write_address; /**< checks flash write addresses.*/ #endif + spi_flash_os_yield_t yield; /**< yield to the OS during flash erase */ } spi_flash_guard_funcs_t; /** diff --git a/tools/sdk/esp32s2/include/spi_flash/include/memspi_host_driver.h b/tools/sdk/esp32s2/include/spi_flash/include/memspi_host_driver.h index 8832adfc..a94260b2 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/memspi_host_driver.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/memspi_host_driver.h @@ -28,9 +28,9 @@ .supports_direct_write = spi_flash_hal_supports_direct_write, \ .supports_direct_read = spi_flash_hal_supports_direct_read, \ .program_page = spi_flash_hal_program_page, \ - .max_write_bytes = SPI_FLASH_HAL_MAX_WRITE_BYTES, \ + .write_data_slicer = memspi_host_write_data_slicer, \ .read = spi_flash_hal_read, \ - .max_read_bytes = SPI_FLASH_HAL_MAX_READ_BYTES, \ + .read_data_slicer = memspi_host_read_data_slicer, \ .host_idle = spi_flash_hal_host_idle, \ .configure_host_io_mode = spi_flash_hal_configure_host_io_mode, \ .poll_cmd_done = spi_flash_hal_poll_cmd_done, \ @@ -38,20 +38,19 @@ } /// configuration for the memspi host -typedef spi_flash_memspi_config_t memspi_host_config_t; +typedef spi_flash_hal_config_t memspi_host_config_t; /// context for the memspi host -typedef spi_flash_memspi_data_t memspi_host_data_t; +typedef spi_flash_hal_context_t memspi_host_inst_t; /** * Initialize the memory SPI host. * * @param host Pointer to the host structure. - * @param data Pointer to allocated space to hold the context of host driver. * @param cfg Pointer to configuration structure * * @return always return ESP_OK */ -esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_data_t *data, const memspi_host_config_t *cfg); +esp_err_t memspi_host_init_pointers(memspi_host_inst_t *host, const memspi_host_config_t *cfg); /******************************************************************************* * NOTICE @@ -66,7 +65,7 @@ esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_d * High speed implementation of RDID through memspi interface relying on the * ``common_command``. * - * @param driver The driver context. + * @param host The driver context. * @param id Output of the read ID from the slave. * * @return @@ -74,69 +73,106 @@ esp_err_t memspi_host_init_pointers(spi_flash_host_driver_t *host, memspi_host_d * - ESP_ERR_FLASH_NO_RESPONSE: if no response from chip * - or other cases from ``spi_hal_common_command`` */ -esp_err_t memspi_host_read_id_hs(spi_flash_host_driver_t *driver, uint32_t *id); +esp_err_t memspi_host_read_id_hs(spi_flash_host_inst_t *host, uint32_t *id); /** * High speed implementation of RDSR through memspi interface relying on the * ``common_command``. * - * @param driver The driver context. + * @param host The driver context. * @param id Output of the read ID from the slave. * * @return * - ESP_OK: if success * - or other cases from ``spi_hal_common_command`` */ -esp_err_t memspi_host_read_status_hs(spi_flash_host_driver_t *driver, uint8_t *out_sr); +esp_err_t memspi_host_read_status_hs(spi_flash_host_inst_t *host, uint8_t *out_sr); /** * Flush the cache (if needed) after the contents are modified. * - * @param driver The driver context. + * @param host The driver context. * @param addr Start address of the modified region * @param size Size of the region modified. * * @return always ESP_OK. */ -esp_err_t memspi_host_flush_cache(spi_flash_host_driver_t* driver, uint32_t addr, uint32_t size); +esp_err_t memspi_host_flush_cache(spi_flash_host_inst_t *host, uint32_t addr, uint32_t size); /** * Erase contents of entire chip. * - * @param driver The driver context. + * @param host The driver context. */ -void memspi_host_erase_chip(spi_flash_host_driver_t *driver); +void memspi_host_erase_chip(spi_flash_host_inst_t *host); /** * Erase a sector starting from a given address. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Starting address of the sector. */ -void memspi_host_erase_sector(spi_flash_host_driver_t *driver, uint32_t start_address); +void memspi_host_erase_sector(spi_flash_host_inst_t *host, uint32_t start_address); /** * Erase a block starting from a given address. * - * @param driver The driver context. + * @param host The driver context. * @param start_address Starting address of the block. */ -void memspi_host_erase_block(spi_flash_host_driver_t *driver, uint32_t start_address); +void memspi_host_erase_block(spi_flash_host_inst_t *host, uint32_t start_address); /** * Program a page with contents of a buffer. * - * @param driver The driver context. + * @param host The driver context. * @param buffer Buffer which contains the data to be flashed. * @param address Starting address of where to flash the data. * @param length The number of bytes to flash. */ -void memspi_host_program_page(spi_flash_host_driver_t *driver, const void *buffer, uint32_t address, uint32_t length); +void memspi_host_program_page(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length); /** * Set ability to write to chip. * - * @param driver The driver context. + * @param host The driver context. * @param wp Enable or disable write protect (true - enable, false - disable). */ -esp_err_t memspi_host_set_write_protect(spi_flash_host_driver_t *driver, bool wp); +esp_err_t memspi_host_set_write_protect(spi_flash_host_inst_t *host, bool wp); + +/** + * Read data to buffer. + * + * @param host The driver context. + * @param buffer Buffer which contains the data to be read. + * @param address Starting address of where to read the data. + * @param length The number of bytes to read. + */ +esp_err_t memspi_host_read(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len); + +/** + * @brief Slicer for read data used in non-encrypted regions. This slicer does nothing but + * limit the length to the maximum size the host supports. + * + * @param address Flash address to read + * @param len Length to read + * @param align_address Output of the address to read, should be equal to the input `address` + * @param page_size Physical SPI flash page size + * + * @return Length that can actually be read in one `read` call in `spi_flash_host_driver_t`. + */ +int memspi_host_read_data_slicer(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_address, uint32_t page_size); + +/** + * @brief Slicer for write data used in non-encrypted regions. This slicer limit the length to the + * maximum size the host supports, and truncate if the write data lie accross the page boundary + * (256 bytes) + * + * @param address Flash address to write + * @param len Length to write + * @param align_address Output of the address to write, should be equal to the input `address` + * @param page_size Physical SPI flash page size + * + * @return Length that can actually be written in one `program_page` call in `spi_flash_host_driver_t`. + */ +int memspi_host_write_data_slicer(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_address, uint32_t page_size); \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_driver.h b/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_driver.h index 46667350..c0b19bad 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_driver.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_driver.h @@ -19,6 +19,16 @@ struct esp_flash_t; typedef struct esp_flash_t esp_flash_t; typedef struct spi_flash_chip_t spi_flash_chip_t; + +/** Timeout configurations for flash operations, all in us */ +typedef struct { + uint32_t chip_erase_timeout; ///< Timeout for chip erase operation + uint32_t block_erase_timeout; ///< Timeout for block erase operation + uint32_t sector_erase_timeout; ///< Timeout for sector erase operation + uint32_t idle_timeout; ///< Default timeout for other commands to be sent by host and get done by flash + uint32_t page_program_timeout; ///< Timeout for page program operation +} flash_chip_op_timeout_t; + /** @brief SPI flash chip driver definition structure. * * The chip driver structure contains chip-specific pointers to functions to perform SPI flash operations, and some @@ -38,6 +48,7 @@ typedef struct spi_flash_chip_t spi_flash_chip_t; */ struct spi_flash_chip_t { const char *name; ///< Name of the chip driver + const flash_chip_op_timeout_t *timeout; ///< Timeout configuration for this chip /* Probe to detect if a supported SPI flash chip is found. * * Attempts to configure 'chip' with these operations and probes for a matching SPI flash chip. diff --git a/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h b/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h index 15ff8f7b..814502d2 100644 --- a/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h +++ b/tools/sdk/esp32s2/include/spi_flash/include/spi_flash_chip_generic.h @@ -368,3 +368,6 @@ esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t * - or other error passed from the ``configure_host_mode`` function of host driver */ esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip); + +/// Default timeout configuration used by most chips +const flash_chip_op_timeout_t spi_flash_chip_generic_timeout; \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/tinyusb.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/tinyusb.h similarity index 75% rename from tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/tinyusb.h rename to tools/sdk/esp32s2/include/tinyusb/additions/include/tinyusb.h index b8592bb0..efd3472a 100644 --- a/tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/tinyusb.h +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/tinyusb.h @@ -15,10 +15,11 @@ #pragma once #include -#include "descriptors_control.h" -#include "board.h" #include "tusb.h" +#include "tusb_option.h" #include "tusb_config.h" +#include "tinyusb_types.h" + #ifdef __cplusplus extern "C" { @@ -41,9 +42,9 @@ extern "C" { # endif # if CFG_TUD_CDC -# if (CFG_TUD_CDC_EPSIZE < 4) -# define CFG_TUD_CDC_EPSIZE 4 -# warning "CFG_TUD_CDC_EPSIZE was too low and was set to 4" +# if (CFG_TUD_CDC_EP_BUFSIZE < 4) +# define CFG_TUD_CDC_EP_BUFSIZE 4 +# warning "CFG_TUD_CDC_EP_BUFSIZE was too low and was set to 4" # endif # endif @@ -55,16 +56,9 @@ extern "C" { # endif # if CFG_TUD_MIDI -# if (CFG_TUD_MIDI_EPSIZE < 4) -# define CFG_TUD_MIDI_EPSIZE 4 -# warning "CFG_TUD_MIDI_EPSIZE was too low and was set to 4" -# endif -# endif - -# if CFG_TUD_VENDOR -# if (CFG_TUD_VENDOR_EPSIZE < 4) -# define CFG_TUD_VENDOR_EPSIZE 4 -# warning "CFG_TUD_VENDOR_EPSIZE was too low and was set to 4" +# if (CFG_TUD_MIDI_EP_BUFSIZE < 4) +# define CFG_TUD_MIDI_EP_BUFSIZE 4 +# warning "CFG_TUD_MIDI_EP_BUFSIZE was too low and was set to 4" # endif # endif @@ -73,17 +67,21 @@ extern "C" { # endif #endif +/** + * @brief Configuration structure of the tinyUSB core + */ typedef struct { -#if CONFIG_USB_USE_BUILTIN_DESCRIPTORS +#ifndef CONFIG_USB_CUSTOM tusb_desc_device_t *descriptor; char **string_descriptor; -#endif /* CONFIG_USB_USE_BUILTIN_DESCRIPTORS */ +#endif bool external_phy; } tinyusb_config_t; esp_err_t tinyusb_driver_install(const tinyusb_config_t *config); // TODO esp_err_t tinyusb_driver_uninstall(void); (IDF-1474) + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/tinyusb/additions/include/tinyusb_types.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/tinyusb_types.h new file mode 100644 index 00000000..e741fdca --- /dev/null +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/tinyusb_types.h @@ -0,0 +1,32 @@ +// Copyright 2020 Espressif Systems (Shanghai) Co. Ltd. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define USB_ESPRESSIF_VID 0x303A +#define USB_STRING_DESCRIPTOR_ARRAY_SIZE 10 + +typedef enum{ + TINYUSB_USBDEV_0, +} tinyusb_usbdev_t; + +typedef char *tusb_desc_strarray_device_t[USB_STRING_DESCRIPTOR_ARRAY_SIZE]; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_cdc_acm.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_cdc_acm.h new file mode 100644 index 00000000..f17f375d --- /dev/null +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_cdc_acm.h @@ -0,0 +1,197 @@ +// Copyright 2020 Espressif Systems (Shanghai) Co. Ltd. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "freertos/FreeRTOS.h" +#include "freertos/ringbuf.h" +#include "freertos/semphr.h" +#include "freertos/timers.h" +#include "tusb.h" +#include "tinyusb.h" + +/** + * @brief CDC ports available to setup + */ +typedef enum{ + TINYUSB_CDC_ACM_0 = 0x0 +}tinyusb_cdcacm_itf_t; + +/* Callbacks and events + ********************************************************************* */ + +/** + * @brief Data provided to the input of the `callback_rx_wanted_char` callback + */ +typedef struct { + char wanted_char; +} cdcacm_event_rx_wanted_char_data_t; + +/** + * @brief Data provided to the input of the `callback_line_state_changed` callback + */ +typedef struct { + bool dtr; + bool rts; +} cdcacm_event_line_state_changed_data_t; + +/** + * @brief Data provided to the input of the `line_coding_changed` callback + */ +typedef struct { + cdc_line_coding_t const *p_line_coding; +} cdcacm_event_line_coding_changed_data_t; + +/** + * @brief Types of CDC ACM events + */ +typedef enum { + CDC_EVENT_RX, + CDC_EVENT_RX_WANTED_CHAR, + CDC_EVENT_LINE_STATE_CHANGED, + CDC_EVENT_LINE_CODING_CHANGED +} cdcacm_event_type_t; + +/** + * @brief Describes an event passing to the input of a callbacks + */ +typedef struct { + cdcacm_event_type_t type; + union { + cdcacm_event_rx_wanted_char_data_t rx_wanted_char_data; + cdcacm_event_line_state_changed_data_t line_state_changed_data; + cdcacm_event_line_coding_changed_data_t line_coding_changed_data; + }; +} cdcacm_event_t; + +/** + * @brief CDC-ACM callback type + */ +typedef void(*tusb_cdcacm_callback_t)(int itf, cdcacm_event_t *event); + +/*********************************************************************** Callbacks and events*/ +/* Other structs + ********************************************************************* */ + +/** + * @brief Configuration structure for CDC-ACM + */ +typedef struct { + tinyusb_usbdev_t usb_dev; /*!< Usb device to set up */ + tinyusb_cdcacm_itf_t cdc_port; /*!< CDC port */ + size_t rx_unread_buf_sz; /*!< Amount of data that can be passed to the AMC at once */ + tusb_cdcacm_callback_t callback_rx; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ + tusb_cdcacm_callback_t callback_rx_wanted_char; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ + tusb_cdcacm_callback_t callback_line_state_changed; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ + tusb_cdcacm_callback_t callback_line_coding_changed; /*!< Pointer to the function with the `tusb_cdcacm_callback_t` type that will be handled as a callback */ +} tinyusb_config_cdcacm_t; + +/*********************************************************************** Other structs*/ +/* Public functions + ********************************************************************* */ +/** + * @brief Initialize CDC ACM. Initialization will be finished with + * the `tud_cdc_line_state_cb` callback + * + * @param cfg - init configuration structure + * @return esp_err_t + */ +esp_err_t tusb_cdc_acm_init(const tinyusb_config_cdcacm_t *cfg); + + +/** + * @brief Register a callback invoking on CDC event. If the callback had been + * already registered, it will be overwritten + * + * @param itf - number of a CDC object + * @param event_type - type of registered event for a callback + * @param callback - callback function + * @return esp_err_t - ESP_OK or ESP_ERR_INVALID_ARG + */ +esp_err_t tinyusb_cdcacm_register_callback(tinyusb_cdcacm_itf_t itf, + cdcacm_event_type_t event_type, + tusb_cdcacm_callback_t callback); + + +/** + * @brief Unregister a callback invoking on CDC event. + * + * @param itf - number of a CDC object + * @param event_type - type of registered event for a callback + * @return esp_err_t - ESP_OK or ESP_ERR_INVALID_ARG + */ +esp_err_t tinyusb_cdcacm_unregister_callback(tinyusb_cdcacm_itf_t itf, cdcacm_event_type_t event_type); + + +/** + * @brief Sent one character to a write buffer + * + * @param itf - number of a CDC object + * @param ch - character to send + * @return size_t - amount of queued bytes + */ +size_t tinyusb_cdcacm_write_queue_char(tinyusb_cdcacm_itf_t itf, char ch); + + +/** + * @brief Write data to write buffer from a byte array + * + * @param itf - number of a CDC object + * @param in_buf - a source array + * @param in_size - size to write from arr_src + * @return size_t - amount of queued bytes + */ +size_t tinyusb_cdcacm_write_queue(tinyusb_cdcacm_itf_t itf, uint8_t *in_buf, size_t in_size); + +/** + * @brief Send all data from a write buffer. Use `tinyusb_cdcacm_write_queue` to add data to the buffer + * + * @param itf - number of a CDC object + * @param timeout_ticks - waiting until flush will be considered as failed + * @return esp_err_t - ESP_OK if (timeout_ticks > 0) and and flush was successful, + * ESP_ERR_TIMEOUT if timeout occurred3 or flush was successful with (timeout_ticks == 0) + * ESP_FAIL if flush was unsuccessful + */ +esp_err_t tinyusb_cdcacm_write_flush(tinyusb_cdcacm_itf_t itf, uint32_t timeout_ticks); + +/** + * @brief Read a content to the array, and defines it's size to the sz_store + * + * @param itf - number of a CDC object + * @param out_buf - to this array will be stored the object from a CDC buffer + * @param out_buf_sz - size of buffer for results + * @param rx_data_size - to this address will be stored the object's size + * @return esp_err_t ESP_OK, ESP_FAIL or ESP_ERR_INVALID_STATE + */ +esp_err_t tinyusb_cdcacm_read(tinyusb_cdcacm_itf_t itf, uint8_t *out_buf, size_t out_buf_sz, size_t *rx_data_size); + + +/** + * @brief Check if the ACM initialized + * + * @param itf - number of a CDC object + * @return true or false + */ +bool tusb_cdc_acm_initialized(tinyusb_cdcacm_itf_t itf); + +/*********************************************************************** Public functions*/ + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/tusb_config.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_config.h similarity index 64% rename from tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/tusb_config.h rename to tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_config.h index 741681af..20a18ef2 100644 --- a/tools/sdk/esp32s2/include/tinyusb/port/esp32s2/include/tusb_config.h +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_config.h @@ -25,49 +25,17 @@ */ #pragma once +#include "tusb_option.h" #include "sdkconfig.h" #ifdef __cplusplus extern "C" { #endif +/* */ +/* KCONFIG */ +/* */ - -//-------------------------------------------------------------------- -// COMMON CONFIGURATION -//-------------------------------------------------------------------- -#define OPT_MCU_ESP32_S2 900 // TODO remove after rebase to the last TUSB (IDF-1473) -#define CFG_TUSB_MCU OPT_MCU_ESP32_S2 - -#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE -#define CFG_TUSB_OS OPT_OS_FREERTOS - -// CFG_TUSB_DEBUG is defined by compiler in DEBUG build -#define CFG_TUSB_DEBUG CONFIG_USB_DEBUG - -/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. - * Tinyusb use follows macros to declare transferring memory so that they can be put - * into those specific section. - * e.g - * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) - * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) - */ -#ifndef CFG_TUSB_MEM_SECTION -# define CFG_TUSB_MEM_SECTION -#endif - -#ifndef CFG_TUSB_MEM_ALIGN -# define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) -#endif - - -//-------------------------------------------------------------------- -// DEVICE CONFIGURATION -//-------------------------------------------------------------------- - -#define CFG_TUD_ENDOINT0_SIZE 64 - -//------kconfig adaptor part -------// #ifndef CONFIG_USB_CDC_ENABLED # define CONFIG_USB_CDC_ENABLED 0 #endif @@ -96,35 +64,63 @@ extern "C" { # define CONFIG_USB_VENDOR_ENABLED 0 #endif -//------------- CLASS -------------// -#define CFG_TUD_CDC CONFIG_USB_CDC_ENABLED -#define CFG_TUD_MSC CONFIG_USB_MSC_ENABLED -#define CFG_TUD_HID CONFIG_USB_HID_ENABLED -#define CFG_TUD_DFU_RT CONFIG_USB_DFU_RT_ENABLED +/* */ +/* COMMON CONFIGURATION */ +/* */ -#define CFG_TUD_MIDI CONFIG_USB_MIDI_ENABLED -#define CFG_TUD_CUSTOM_CLASS CONFIG_USB_CUSTOM_CLASS_ENABLED +#define CFG_TUSB_MCU OPT_MCU_ESP32S2 +#define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE +#define CFG_TUSB_OS OPT_OS_FREERTOS +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +# define CFG_TUSB_MEM_SECTION +#endif -#define CFG_TUD_VENDOR CONFIG_USB_VENDOR_ENABLED +#ifndef CFG_TUSB_MEM_ALIGN +# define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) +#endif + +/* */ +/* DRIVER CONFIGURATION */ +/* */ + +#define CFG_TUD_MAINTASK_SIZE 4096 +#define CFG_TUD_ENDOINT0_SIZE 64 + +// Enabled Drivers +#define CFG_TUD_CDC CONFIG_USB_CDC_ENABLED +#define CFG_TUD_MSC CONFIG_USB_MSC_ENABLED +#define CFG_TUD_HID CONFIG_USB_HID_ENABLED +#define CFG_TUD_MIDI CONFIG_USB_MIDI_ENABLED +#define CFG_TUD_CUSTOM_CLASS CONFIG_USB_CUSTOM_CLASS_ENABLED +#define CFG_TUD_DFU_RT CONFIG_USB_DFU_RT_ENABLED +#define CFG_TUD_VENDOR CONFIG_USB_VENDOR_ENABLED // CDC FIFO size of TX and RX -#define CFG_TUD_CDC_RX_BUFSIZE CONFIG_USB_CDC_RX_BUFSIZE -#define CFG_TUD_CDC_TX_BUFSIZE CONFIG_USB_CDC_TX_BUFSIZE +#define CFG_TUD_CDC_RX_BUFSIZE CONFIG_USB_CDC_RX_BUFSIZE +#define CFG_TUD_CDC_TX_BUFSIZE CONFIG_USB_CDC_TX_BUFSIZE // MSC Buffer size of Device Mass storage: -#define CFG_TUD_MSC_BUFSIZE CONFIG_USB_MSC_BUFSIZE +#define CFG_TUD_MSC_BUFSIZE CONFIG_USB_MSC_BUFSIZE // HID buffer size Should be sufficient to hold ID (if any) + Data -#define CFG_TUD_HID_BUFSIZE CONFIG_USB_HID_BUFSIZE - -// VENDOR FIFO size of TX and RX -#define CFG_TUD_VENDOR_RX_BUFSIZE 64 -#define CFG_TUD_VENDOR_TX_BUFSIZE 64 +#define CFG_TUD_HID_BUFSIZE CONFIG_USB_HID_BUFSIZE // MIDI FIFO size of TX and RX -#define CFG_TUD_MIDI_RX_BUFSIZE CONFIG_USB_MIDI_RX_BUFSIZE -#define CFG_TUD_MIDI_TX_BUFSIZE CONFIG_USB_MIDI_TX_BUFSIZE +#define CFG_TUD_MIDI_RX_BUFSIZE CONFIG_USB_MIDI_RX_BUFSIZE +#define CFG_TUD_MIDI_TX_BUFSIZE CONFIG_USB_MIDI_TX_BUFSIZE + +// VENDOR FIFO size of TX and RX +#define CFG_TUD_VENDOR_RX_BUFSIZE CONFIG_USB_VENDOR_RX_BUFSIZE +#define CFG_TUD_VENDOR_TX_BUFSIZE CONFIG_USB_VENDOR_TX_BUFSIZE + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_console.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_console.h new file mode 100644 index 00000000..f7304eea --- /dev/null +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_console.h @@ -0,0 +1,33 @@ +// Copyright 2020 Espressif Systems (Shanghai) Co. Ltd. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_err.h" + +/** + * @brief Redirect output to the USB serial + * @param cdc_intf - interface number of TinyUSB's CDC + * + * @return esp_err_t - ESP_OK, ESP_FAIL or an error code + */ +esp_err_t esp_tusb_init_console(int cdc_intf); + +/** + * @brief Switch log to the default output + * @param cdc_intf - interface number of TinyUSB's CDC + * + * @return esp_err_t + */ +esp_err_t esp_tusb_deinit_console(int cdc_intf); diff --git a/tools/sdk/esp32s2/include/tinyusb/port/common/include/usb_descriptors.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_tasks.h similarity index 53% rename from tools/sdk/esp32s2/include/tinyusb/port/common/include/usb_descriptors.h rename to tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_tasks.h index f1a4cee2..f1a47991 100644 --- a/tools/sdk/esp32s2/include/tinyusb/port/common/include/usb_descriptors.h +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/tusb_tasks.h @@ -11,29 +11,33 @@ // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. + #pragma once +#include "esp_err.h" + + #ifdef __cplusplus extern "C" { #endif -#include "tusb.h" +/** + * @brief This API starts a task with a wrapper function of tud_task and default task parameters. + * + * The wrapper function basically wraps tud_task and some log. Default parameters: stack size and priority as configured, argument = NULL, + * not pinned to any core. + * If you have more requirements for this task, you can create your own task which calls tud_task as the last step. + * + * @return ESP_OK or ESP_FAIL + */ +esp_err_t tusb_run_task(void); -#define USB_ESPRESSIF_VID 0x303A - -#if CONFIG_USB_USE_BUILTIN_DESCRIPTORS - -#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) - -#define USB_STRING_DESCRIPTOR_ARRAY_SIZE 10 -typedef char *tusb_desc_strarray_device_t[USB_STRING_DESCRIPTOR_ARRAY_SIZE]; - -extern tusb_desc_device_t descriptor_tinyusb; -extern tusb_desc_strarray_device_t descriptor_str_tinyusb; - -extern tusb_desc_device_t descriptor_kconfig; -extern tusb_desc_strarray_device_t descriptor_str_kconfig; -#endif /* CONFIG_USB_USE_BUILTIN_DESCRIPTORS */ +/** + * @brief Stops a FreeRTOS task with @ref tusb_device_task + * + * @return ESP_OK or ESP_FAIL + */ +esp_err_t tusb_stop_task(void); #ifdef __cplusplus } diff --git a/tools/sdk/esp32s2/include/tinyusb/additions/include/vfs_tinyusb.h b/tools/sdk/esp32s2/include/tinyusb/additions/include/vfs_tinyusb.h new file mode 100644 index 00000000..233b7f14 --- /dev/null +++ b/tools/sdk/esp32s2/include/tinyusb/additions/include/vfs_tinyusb.h @@ -0,0 +1,42 @@ +// Copyright 2020 Espressif Systems (Shanghai) Co. Ltd. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Register TinyUSB CDC at VFS with path + * @param cdc_intf - interface number of TinyUSB's CDC + * @param path - path where the CDC will be registered, `/dev/tusb_cdc` will be used if left NULL. + * + * @return esp_err_t ESP_OK or ESP_FAIL + */ +esp_err_t esp_vfs_tusb_cdc_register(int cdc_intf, char const *path); + +/** + * @brief Unregister TinyUSB CDC from VFS + * @param path - path where the CDC will be unregistered if NULL will be used `/dev/tusb_cdc` + * + * @return esp_err_t ESP_OK or ESP_FAIL + */ +esp_err_t esp_vfs_tusb_cdc_unregister(char const *path); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/port/common/include/descriptors_control.h b/tools/sdk/esp32s2/include/tinyusb/port/common/include/descriptors_control.h deleted file mode 100644 index f979acbc..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/port/common/include/descriptors_control.h +++ /dev/null @@ -1,89 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#include -#include "usb_descriptors.h" - -#if CONFIG_USB_USE_BUILTIN_DESCRIPTORS -/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. - * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. - * - * Auto ProductID layout's Bitmap: - * [MSB] HID | MSC | CDC [LSB] - */ -#define EPNUM_MSC 0x02 -#define EPNUM_HID 0x03 -#define EPNUM_MIDI 0x06 -#define EPNUM_VENDOR 0x01 - -#ifdef __cplusplus -extern "C" { -#endif -//------------- HID Report Descriptor -------------// -#if CFG_TUD_HID -enum { - REPORT_ID_KEYBOARD = 1, - REPORT_ID_MOUSE -}; -#endif - -//------------- Configuration Descriptor -------------// -enum { -# if CFG_TUD_CDC - ITF_NUM_CDC = 0, - ITF_NUM_CDC_DATA, -# endif - -# if CFG_TUD_DFU_RT - ITF_NUM_DFU_RT, -# endif - -# if CFG_TUD_MSC - ITF_NUM_MSC, -# endif - -# if CFG_TUD_HID - ITF_NUM_HID, -# endif - -# if CFG_TUD_MIDI - ITF_NUM_MIDI, - ITF_NUM_MIDI_STREAMING, -# endif - -# if CFG_TUD_VENDOR - ITF_NUM_VENDOR, -# endif - - ITF_NUM_TOTAL -}; - -enum { - CONFIG_TOTAL_LEN = TUD_CONFIG_DESC_LEN + CFG_TUD_CDC * TUD_CDC_DESC_LEN + CFG_TUD_DFU_RT * TUD_DFU_RT_DESC_LEN + CFG_TUD_MSC * TUD_MSC_DESC_LEN + - CFG_TUD_HID * TUD_HID_DESC_LEN + CFG_TUD_VENDOR * TUD_VENDOR_DESC_LEN + CFG_TUD_MIDI * TUD_MIDI_DESC_LEN -}; - -bool tusb_desc_set; -void tusb_set_descriptor(tusb_desc_device_t *desc, char **str_desc); -tusb_desc_device_t *tusb_get_active_desc(void); -char **tusb_get_active_str_desc(void); -void tusb_clear_descriptor(void); - -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_USB_USE_BUILTIN_DESCRIPTORS */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/ansi_escape.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/ansi_escape.h deleted file mode 100644 index 35342cfe..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/ansi_escape.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/** \ingroup group_board - * \defgroup group_ansi_esc ANSI Esacpe Code - * @{ */ - -#ifndef _TUSB_ANSI_ESC_CODE_H_ -#define _TUSB_ANSI_ESC_CODE_H_ - - -#ifdef __cplusplus - extern "C" { -#endif - -#define CSI_CODE(seq) "\33[" seq -#define CSI_SGR(x) CSI_CODE(#x) "m" - -//------------- Cursor movement -------------// -/** \defgroup group_ansi_cursor Cursor Movement - * @{ */ -#define ANSI_CURSOR_UP(n) CSI_CODE(#n "A") ///< Move cursor up -#define ANSI_CURSOR_DOWN(n) CSI_CODE(#n "B") ///< Move cursor down -#define ANSI_CURSOR_FORWARD(n) CSI_CODE(#n "C") ///< Move cursor forward -#define ANSI_CURSOR_BACKWARD(n) CSI_CODE(#n "D") ///< Move cursor backward -#define ANSI_CURSOR_LINE_DOWN(n) CSI_CODE(#n "E") ///< Move cursor to the beginning of the line (n) down -#define ANSI_CURSOR_LINE_UP(n) CSI_CODE(#n "F") ///< Move cursor to the beginning of the line (n) up -#define ANSI_CURSOR_POSITION(n, m) CSI_CODE(#n ";" #m "H") ///< Move cursor to position (n, m) -/** @} */ - -//------------- Screen -------------// -/** \defgroup group_ansi_screen Screen Control - * @{ */ -#define ANSI_ERASE_SCREEN(n) CSI_CODE(#n "J") ///< Erase the screen -#define ANSI_ERASE_LINE(n) CSI_CODE(#n "K") ///< Erase the line (n) -#define ANSI_SCROLL_UP(n) CSI_CODE(#n "S") ///< Scroll the whole page up (n) lines -#define ANSI_SCROLL_DOWN(n) CSI_CODE(#n "T") ///< Scroll the whole page down (n) lines -/** @} */ - -//------------- Text Color -------------// -/** \defgroup group_ansi_text Text Color - * @{ */ -#define ANSI_TEXT_BLACK CSI_SGR(30) -#define ANSI_TEXT_RED CSI_SGR(31) -#define ANSI_TEXT_GREEN CSI_SGR(32) -#define ANSI_TEXT_YELLOW CSI_SGR(33) -#define ANSI_TEXT_BLUE CSI_SGR(34) -#define ANSI_TEXT_MAGENTA CSI_SGR(35) -#define ANSI_TEXT_CYAN CSI_SGR(36) -#define ANSI_TEXT_WHITE CSI_SGR(37) -#define ANSI_TEXT_DEFAULT CSI_SGR(39) -/** @} */ - -//------------- Background Color -------------// -/** \defgroup group_ansi_background Background Color - * @{ */ -#define ANSI_BG_BLACK CSI_SGR(40) -#define ANSI_BG_RED CSI_SGR(41) -#define ANSI_BG_GREEN CSI_SGR(42) -#define ANSI_BG_YELLOW CSI_SGR(43) -#define ANSI_BG_BLUE CSI_SGR(44) -#define ANSI_BG_MAGENTA CSI_SGR(45) -#define ANSI_BG_CYAN CSI_SGR(46) -#define ANSI_BG_WHITE CSI_SGR(47) -#define ANSI_BG_DEFAULT CSI_SGR(49) -/** @} */ - -#ifdef __cplusplus - } -#endif - -#endif /* _TUSB_ANSI_ESC_CODE_H_ */ - -/** @} */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/board.h deleted file mode 100644 index a8f973a7..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/board.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/** \ingroup group_demo - * \defgroup group_board Boards Abstraction Layer - * @{ */ - -#ifndef _BSP_BOARD_H_ -#define _BSP_BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#include -#include - -#include "ansi_escape.h" -#include "tusb.h" - -#define CFG_BOARD_UART_BAUDRATE 115200 - -//--------------------------------------------------------------------+ -// Board Porting API -// For simplicity, only one LED and one Button are used -//--------------------------------------------------------------------+ - -// Initialize on-board peripherals : led, button, uart and USB -void board_init(void); - -// Turn LED on or off -void board_led_write(bool state); - -// Get the current state of button -// a '1' means active (pressed), a '0' means inactive. -uint32_t board_button_read(void); - -// Get characters from UART -int board_uart_read(uint8_t* buf, int len); - -// Send characters to UART -int board_uart_write(void const * buf, int len); - -#if CFG_TUSB_OS == OPT_OS_NONE - // Get current milliseconds, must be implemented when no RTOS is used - uint32_t board_millis(void); - -#elif CFG_TUSB_OS == OPT_OS_FREERTOS - static inline uint32_t board_millis(void) - { - return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ ); - } - -#elif CFG_TUSB_OS == OPT_OS_MYNEWT - static inline uint32_t board_millis(void) - { - return os_time_ticks_to_ms32( os_time_get() ); - } - -#else - #error "board_millis() is not implemented for this OS" -#endif - -//--------------------------------------------------------------------+ -// Helper functions -//--------------------------------------------------------------------+ -static inline void board_led_on(void) -{ - board_led_write(true); -} - -static inline void board_led_off(void) -{ - board_led_write(false); -} - -// TODO remove -static inline void board_delay(uint32_t ms) -{ - uint32_t start_ms = board_millis(); - while (board_millis() - start_ms < ms) - { - #if TUSB_OPT_DEVICE_ENABLED - // take chance to run usb background - tud_task(); - #endif - } -} - -static inline int board_uart_getchar(void) -{ - uint8_t c; - return board_uart_read(&c, 1) ? (int) c : (-1); -} - -static inline int board_uart_putchar(uint8_t c) -{ - return board_uart_write(&c, 1); -} - -#ifdef __cplusplus - } -#endif - -#endif /* _BSP_BOARD_H_ */ - -/** @} */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/board_mcu.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/board_mcu.h deleted file mode 100644 index 15b31edf..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/board_mcu.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_MCU_H_ -#define BOARD_MCU_H_ - -#include "tusb_option.h" - -//--------------------------------------------------------------------+ -// Low Level MCU header include. TinyUSB stack and example should be -// platform independent and mostly doens't need to include this file. -// However there are still certain situation where this file is needed: -// - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex -// - SWO logging for Cortex M with ITM_SendChar() / ITM_ReceiveChar() -//--------------------------------------------------------------------+ - -// Include order follows OPT_MCU_ number -#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC15XX || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \ - CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX || \ - CFG_TUSB_MCU == OPT_MCU_LPC40XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX - #include "chip.h" - -#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \ - CFG_TUSB_MCU == OPT_MCU_LPC55XX - #include "fsl_device_registers.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NRF5X - #include "nrf.h" - -#elif CFG_TUSB_MCU == OPT_MCU_SAMD21 || CFG_TUSB_MCU == OPT_MCU_SAMD51 - #include "sam.h" - -#elif CFG_TUSB_MCU == OPT_MCU_SAMG - #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined - #include "sam.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F0 - #include "stm32f0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 - #include "stm32f1xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F2 - #include "stm32f2xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F3 - #include "stm32f3xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F4 - #include "stm32f4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 - #include "stm32f7xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H7 - #include "stm32h7xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L0 - #include "stm32l0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L1 - #include "stm32l1xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 - #include "stm32l4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_CXD56 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx - #include "msp430.h" - -#elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX - #include "fsl_device_registers.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC120 - #include "NUC100Series.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC121 || CFG_TUSB_MCU == OPT_MCU_NUC126 - #include "NuMicro.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC505 - #include "NUC505Series.h" - -#elif CFG_TUSB_MCU == OPT_MCU_ESP32S2 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_DA1469X - #include "DA1469xAB.h" - -#else - #error "Missing MCU header" -#endif - - -#endif /* BOARD_MCU_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/da14695_dk_usb/syscfg/syscfg.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/da14695_dk_usb/syscfg/syscfg.h deleted file mode 100644 index 6cbb4319..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/da14695_dk_usb/syscfg/syscfg.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * This file was generated by Apache newt version: 1.9.0-dev - */ - -#ifndef H_MYNEWT_SYSCFG_ -#define H_MYNEWT_SYSCFG_ - -/** - * This macro exists to ensure code includes this header when needed. If code - * checks the existence of a setting directly via ifdef without including this - * header, the setting macro will silently evaluate to 0. In contrast, an - * attempt to use these macros without including this header will result in a - * compiler error. - */ -#define MYNEWT_VAL(_name) MYNEWT_VAL_ ## _name -#define MYNEWT_VAL_CHOICE(_name, _val) MYNEWT_VAL_ ## _name ## __ ## _val - -#ifndef MYNEWT_VAL_RAM_RESIDENT -#define MYNEWT_VAL_RAM_RESIDENT (0) -#endif - -#ifndef MYNEWT_VAL_MCU_GPIO_MAX_IRQ -#define MYNEWT_VAL_MCU_GPIO_MAX_IRQ (4) -#endif - -#ifndef MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM -#define MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM (-1) -#endif - -#ifndef MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US -#define MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US (2000) -#endif - -#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h deleted file mode 100644 index 6cbb4319..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/da1469x_dk_pro/syscfg/syscfg.h +++ /dev/null @@ -1,34 +0,0 @@ -/** - * This file was generated by Apache newt version: 1.9.0-dev - */ - -#ifndef H_MYNEWT_SYSCFG_ -#define H_MYNEWT_SYSCFG_ - -/** - * This macro exists to ensure code includes this header when needed. If code - * checks the existence of a setting directly via ifdef without including this - * header, the setting macro will silently evaluate to 0. In contrast, an - * attempt to use these macros without including this header will result in a - * compiler error. - */ -#define MYNEWT_VAL(_name) MYNEWT_VAL_ ## _name -#define MYNEWT_VAL_CHOICE(_name, _val) MYNEWT_VAL_ ## _name ## __ ## _val - -#ifndef MYNEWT_VAL_RAM_RESIDENT -#define MYNEWT_VAL_RAM_RESIDENT (0) -#endif - -#ifndef MYNEWT_VAL_MCU_GPIO_MAX_IRQ -#define MYNEWT_VAL_MCU_GPIO_MAX_IRQ (4) -#endif - -#ifndef MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM -#define MYNEWT_VAL_MCU_GPIO_RETAINABLE_NUM (-1) -#endif - -#ifndef MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US -#define MYNEWT_VAL_MCU_CLOCK_XTAL32M_SETTLE_TIME_US (2000) -#endif - -#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/ea4357/pca9532.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/ea4357/pca9532.h deleted file mode 100644 index 7a7c6e14..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/ea4357/pca9532.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************** - * - * Copyright(C) 2011, Embedded Artists AB - * All rights reserved. - * - ****************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * Embedded Artists AB assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. Embedded Artists AB - * reserves the right to make changes in the software without - * notification. Embedded Artists AB also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - *****************************************************************************/ -#ifndef __PCA9532C_H -#define __PCA9532C_H - - -#define PCA9532_I2C_ADDR (0xC0>>1) - -#define PCA9532_INPUT0 0x00 -#define PCA9532_INPUT1 0x01 -#define PCA9532_PSC0 0x02 -#define PCA9532_PWM0 0x03 -#define PCA9532_PSC1 0x04 -#define PCA9532_PWM1 0x05 -#define PCA9532_LS0 0x06 -#define PCA9532_LS1 0x07 -#define PCA9532_LS2 0x08 -#define PCA9532_LS3 0x09 - -#define PCA9532_AUTO_INC 0x10 - - -/* - * The Keys on the base board are mapped to LED0 -> LED3 on - * the PCA9532. - */ - -#define KEY1 0x0001 -#define KEY2 0x0002 -#define KEY3 0x0004 -#define KEY4 0x0008 - -#define KEY_MASK 0x000F - -/* - * MMC Card Detect and MMC Write Protect are mapped to LED4 - * and LED5 on the PCA9532. Please note that WP is active low. - */ - -#define MMC_CD 0x0010 -#define MMC_WP 0x0020 - -#define MMC_MASK 0x30 - -/* NOTE: LED6 and LED7 on PCA9532 are not connected to anything */ -#define PCA9532_NOT_USED 0xC0 - -/* - * Below are the LED constants to use when enabling/disabling a LED. - * The LED names are the names printed on the base board and not - * the names from the PCA9532 device. base_LED1 -> LED8 on PCA9532, - * base_LED2 -> LED9, and so on. - */ - -#define LED1 0x0100 -#define LED2 0x0200 -#define LED3 0x0400 -#define LED4 0x0800 -#define LED5 0x1000 -#define LED6 0x2000 -#define LED7 0x4000 -#define LED8 0x8000 - -#define LED_MASK 0xFF00 - -void pca9532_init (void); -uint16_t pca9532_getLedState (uint32_t shadow); -void pca9532_setLeds (uint16_t ledOnMask, uint16_t ledOffMask); -void pca9532_setBlink0Period(uint8_t period); -void pca9532_setBlink0Duty(uint8_t duty); -void pca9532_setBlink0Leds(uint16_t ledMask); -void pca9532_setBlink1Period(uint8_t period); -void pca9532_setBlink1Duty(uint8_t duty); -void pca9532_setBlink1Leds(uint16_t ledMask); - -#endif /* end __PCA9532C_H */ -/**************************************************************************** -** End Of File -*****************************************************************************/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/esp32s2_kaluga_1/led_strip/include/led_strip.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/esp32s2_kaluga_1/led_strip/include/led_strip.h deleted file mode 100644 index a9dffc32..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/esp32s2_kaluga_1/led_strip/include/led_strip.h +++ /dev/null @@ -1,126 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include "esp_err.h" - -/** -* @brief LED Strip Type -* -*/ -typedef struct led_strip_s led_strip_t; - -/** -* @brief LED Strip Device Type -* -*/ -typedef void *led_strip_dev_t; - -/** -* @brief Declare of LED Strip Type -* -*/ -struct led_strip_s { - /** - * @brief Set RGB for a specific pixel - * - * @param strip: LED strip - * @param index: index of pixel to set - * @param red: red part of color - * @param green: green part of color - * @param blue: blue part of color - * - * @return - * - ESP_OK: Set RGB for a specific pixel successfully - * - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters - * - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred - */ - esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue); - - /** - * @brief Refresh memory colors to LEDs - * - * @param strip: LED strip - * @param timeout_ms: timeout value for refreshing task - * - * @return - * - ESP_OK: Refresh successfully - * - ESP_ERR_TIMEOUT: Refresh failed because of timeout - * - ESP_FAIL: Refresh failed because some other error occurred - * - * @note: - * After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip. - */ - esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms); - - /** - * @brief Clear LED strip (turn off all LEDs) - * - * @param strip: LED strip - * @param timeout_ms: timeout value for clearing task - * - * @return - * - ESP_OK: Clear LEDs successfully - * - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout - * - ESP_FAIL: Clear LEDs failed because some other error occurred - */ - esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms); - - /** - * @brief Free LED strip resources - * - * @param strip: LED strip - * - * @return - * - ESP_OK: Free resources successfully - * - ESP_FAIL: Free resources failed because error occurred - */ - esp_err_t (*del)(led_strip_t *strip); -}; - -/** -* @brief LED Strip Configuration Type -* -*/ -typedef struct { - uint32_t max_leds; /*!< Maximum LEDs in a single strip */ - led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */ -} led_strip_config_t; - -/** - * @brief Default configuration for LED strip - * - */ -#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \ - { \ - .max_leds = number, \ - .dev = dev_hdl, \ - } - -/** -* @brief Install a new ws2812 driver (based on RMT peripheral) -* -* @param config: LED strip configuration -* @return -* LED strip instance or NULL -*/ -led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h deleted file mode 100644 index a9dffc32..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/esp32s2_saola_1/led_strip/include/led_strip.h +++ /dev/null @@ -1,126 +0,0 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#include "esp_err.h" - -/** -* @brief LED Strip Type -* -*/ -typedef struct led_strip_s led_strip_t; - -/** -* @brief LED Strip Device Type -* -*/ -typedef void *led_strip_dev_t; - -/** -* @brief Declare of LED Strip Type -* -*/ -struct led_strip_s { - /** - * @brief Set RGB for a specific pixel - * - * @param strip: LED strip - * @param index: index of pixel to set - * @param red: red part of color - * @param green: green part of color - * @param blue: blue part of color - * - * @return - * - ESP_OK: Set RGB for a specific pixel successfully - * - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters - * - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred - */ - esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue); - - /** - * @brief Refresh memory colors to LEDs - * - * @param strip: LED strip - * @param timeout_ms: timeout value for refreshing task - * - * @return - * - ESP_OK: Refresh successfully - * - ESP_ERR_TIMEOUT: Refresh failed because of timeout - * - ESP_FAIL: Refresh failed because some other error occurred - * - * @note: - * After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip. - */ - esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms); - - /** - * @brief Clear LED strip (turn off all LEDs) - * - * @param strip: LED strip - * @param timeout_ms: timeout value for clearing task - * - * @return - * - ESP_OK: Clear LEDs successfully - * - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout - * - ESP_FAIL: Clear LEDs failed because some other error occurred - */ - esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms); - - /** - * @brief Free LED strip resources - * - * @param strip: LED strip - * - * @return - * - ESP_OK: Free resources successfully - * - ESP_FAIL: Free resources failed because error occurred - */ - esp_err_t (*del)(led_strip_t *strip); -}; - -/** -* @brief LED Strip Configuration Type -* -*/ -typedef struct { - uint32_t max_leds; /*!< Maximum LEDs in a single strip */ - led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */ -} led_strip_config_t; - -/** - * @brief Default configuration for LED strip - * - */ -#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \ - { \ - .max_leds = number, \ - .dev = dev_hdl, \ - } - -/** -* @brief Install a new ws2812 driver (based on RMT peripheral) -* -* @param config: LED strip configuration -* @return -* LED strip instance or NULL -*/ -led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config); - -#ifdef __cplusplus -} -#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/feather_stm32f405/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/feather_stm32f405/stm32f4xx_hal_conf.h deleted file mode 100644 index b892df3b..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/feather_stm32f405/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,491 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* Copied over manually- STM32Cube didn't generate these for some reason. */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/csr.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/csr.h deleted file mode 100644 index a2f60ecf..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/csr.h +++ /dev/null @@ -1,750 +0,0 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (f4fcd10) & LiteX (1425a68d) on 2019-11-12 19:41:49 -//-------------------------------------------------------------------------------- -#ifndef __GENERATED_CSR_H -#define __GENERATED_CSR_H -#include -#ifdef CSR_ACCESSORS_DEFINED -extern void csr_writeb(uint8_t value, unsigned long addr); -extern uint8_t csr_readb(unsigned long addr); -extern void csr_writew(uint16_t value, unsigned long addr); -extern uint16_t csr_readw(unsigned long addr); -extern void csr_writel(uint32_t value, unsigned long addr); -extern uint32_t csr_readl(unsigned long addr); -#else /* ! CSR_ACCESSORS_DEFINED */ -#include -#endif /* ! CSR_ACCESSORS_DEFINED */ - -/* ctrl */ -#define CSR_CTRL_BASE 0xe0000000L -#define CSR_CTRL_RESET_ADDR 0xe0000000L -#define CSR_CTRL_RESET_SIZE 1 -static inline unsigned char ctrl_reset_read(void) { - unsigned char r = csr_readl(0xe0000000L); - return r; -} -static inline void ctrl_reset_write(unsigned char value) { - csr_writel(value, 0xe0000000L); -} -#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L -#define CSR_CTRL_SCRATCH_SIZE 4 -static inline unsigned int ctrl_scratch_read(void) { - unsigned int r = csr_readl(0xe0000004L); - r <<= 8; - r |= csr_readl(0xe0000008L); - r <<= 8; - r |= csr_readl(0xe000000cL); - r <<= 8; - r |= csr_readl(0xe0000010L); - return r; -} -static inline void ctrl_scratch_write(unsigned int value) { - csr_writel(value >> 24, 0xe0000004L); - csr_writel(value >> 16, 0xe0000008L); - csr_writel(value >> 8, 0xe000000cL); - csr_writel(value, 0xe0000010L); -} -#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L -#define CSR_CTRL_BUS_ERRORS_SIZE 4 -static inline unsigned int ctrl_bus_errors_read(void) { - unsigned int r = csr_readl(0xe0000014L); - r <<= 8; - r |= csr_readl(0xe0000018L); - r <<= 8; - r |= csr_readl(0xe000001cL); - r <<= 8; - r |= csr_readl(0xe0000020L); - return r; -} - -/* messible */ -#define CSR_MESSIBLE_BASE 0xe0008000L -#define CSR_MESSIBLE_IN_ADDR 0xe0008000L -#define CSR_MESSIBLE_IN_SIZE 1 -static inline unsigned char messible_in_read(void) { - unsigned char r = csr_readl(0xe0008000L); - return r; -} -static inline void messible_in_write(unsigned char value) { - csr_writel(value, 0xe0008000L); -} -#define CSR_MESSIBLE_OUT_ADDR 0xe0008004L -#define CSR_MESSIBLE_OUT_SIZE 1 -static inline unsigned char messible_out_read(void) { - unsigned char r = csr_readl(0xe0008004L); - return r; -} -#define CSR_MESSIBLE_STATUS_ADDR 0xe0008008L -#define CSR_MESSIBLE_STATUS_SIZE 1 -static inline unsigned char messible_status_read(void) { - unsigned char r = csr_readl(0xe0008008L); - return r; -} -#define CSR_MESSIBLE_STATUS_FULL_OFFSET 0 -#define CSR_MESSIBLE_STATUS_FULL_SIZE 1 -#define CSR_MESSIBLE_STATUS_HAVE_OFFSET 1 -#define CSR_MESSIBLE_STATUS_HAVE_SIZE 1 - -/* picorvspi */ -#define CSR_PICORVSPI_BASE 0xe0005000L -#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L -#define CSR_PICORVSPI_CFG1_SIZE 1 -static inline unsigned char picorvspi_cfg1_read(void) { - unsigned char r = csr_readl(0xe0005000L); - return r; -} -static inline void picorvspi_cfg1_write(unsigned char value) { - csr_writel(value, 0xe0005000L); -} -#define CSR_PICORVSPI_CFG1_BB_OUT_OFFSET 0 -#define CSR_PICORVSPI_CFG1_BB_OUT_SIZE 4 -#define CSR_PICORVSPI_CFG1_BB_CLK_OFFSET 4 -#define CSR_PICORVSPI_CFG1_BB_CLK_SIZE 1 -#define CSR_PICORVSPI_CFG1_BB_CS_OFFSET 5 -#define CSR_PICORVSPI_CFG1_BB_CS_SIZE 1 -#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L -#define CSR_PICORVSPI_CFG2_SIZE 1 -static inline unsigned char picorvspi_cfg2_read(void) { - unsigned char r = csr_readl(0xe0005004L); - return r; -} -static inline void picorvspi_cfg2_write(unsigned char value) { - csr_writel(value, 0xe0005004L); -} -#define CSR_PICORVSPI_CFG2_BB_OE_OFFSET 0 -#define CSR_PICORVSPI_CFG2_BB_OE_SIZE 4 -#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L -#define CSR_PICORVSPI_CFG3_SIZE 1 -static inline unsigned char picorvspi_cfg3_read(void) { - unsigned char r = csr_readl(0xe0005008L); - return r; -} -static inline void picorvspi_cfg3_write(unsigned char value) { - csr_writel(value, 0xe0005008L); -} -#define CSR_PICORVSPI_CFG3_RLAT_OFFSET 0 -#define CSR_PICORVSPI_CFG3_RLAT_SIZE 4 -#define CSR_PICORVSPI_CFG3_CRM_OFFSET 4 -#define CSR_PICORVSPI_CFG3_CRM_SIZE 1 -#define CSR_PICORVSPI_CFG3_QSPI_OFFSET 5 -#define CSR_PICORVSPI_CFG3_QSPI_SIZE 1 -#define CSR_PICORVSPI_CFG3_DDR_OFFSET 6 -#define CSR_PICORVSPI_CFG3_DDR_SIZE 1 -#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL -#define CSR_PICORVSPI_CFG4_SIZE 1 -static inline unsigned char picorvspi_cfg4_read(void) { - unsigned char r = csr_readl(0xe000500cL); - return r; -} -static inline void picorvspi_cfg4_write(unsigned char value) { - csr_writel(value, 0xe000500cL); -} -#define CSR_PICORVSPI_CFG4_MEMIO_OFFSET 7 -#define CSR_PICORVSPI_CFG4_MEMIO_SIZE 1 -#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L -#define CSR_PICORVSPI_STAT1_SIZE 1 -static inline unsigned char picorvspi_stat1_read(void) { - unsigned char r = csr_readl(0xe0005010L); - return r; -} -#define CSR_PICORVSPI_STAT1_BB_IN_OFFSET 0 -#define CSR_PICORVSPI_STAT1_BB_IN_SIZE 4 -#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L -#define CSR_PICORVSPI_STAT2_SIZE 1 -static inline unsigned char picorvspi_stat2_read(void) { - unsigned char r = csr_readl(0xe0005014L); - return r; -} -#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L -#define CSR_PICORVSPI_STAT3_SIZE 1 -static inline unsigned char picorvspi_stat3_read(void) { - unsigned char r = csr_readl(0xe0005018L); - return r; -} -#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL -#define CSR_PICORVSPI_STAT4_SIZE 1 -static inline unsigned char picorvspi_stat4_read(void) { - unsigned char r = csr_readl(0xe000501cL); - return r; -} - -/* reboot */ -#define CSR_REBOOT_BASE 0xe0006000L -#define CSR_REBOOT_CTRL_ADDR 0xe0006000L -#define CSR_REBOOT_CTRL_SIZE 1 -static inline unsigned char reboot_ctrl_read(void) { - unsigned char r = csr_readl(0xe0006000L); - return r; -} -static inline void reboot_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0006000L); -} -#define CSR_REBOOT_CTRL_IMAGE_OFFSET 0 -#define CSR_REBOOT_CTRL_IMAGE_SIZE 2 -#define CSR_REBOOT_CTRL_KEY_OFFSET 2 -#define CSR_REBOOT_CTRL_KEY_SIZE 6 -#define CSR_REBOOT_ADDR_ADDR 0xe0006004L -#define CSR_REBOOT_ADDR_SIZE 4 -static inline unsigned int reboot_addr_read(void) { - unsigned int r = csr_readl(0xe0006004L); - r <<= 8; - r |= csr_readl(0xe0006008L); - r <<= 8; - r |= csr_readl(0xe000600cL); - r <<= 8; - r |= csr_readl(0xe0006010L); - return r; -} -static inline void reboot_addr_write(unsigned int value) { - csr_writel(value >> 24, 0xe0006004L); - csr_writel(value >> 16, 0xe0006008L); - csr_writel(value >> 8, 0xe000600cL); - csr_writel(value, 0xe0006010L); -} - -/* rgb */ -#define CSR_RGB_BASE 0xe0006800L -#define CSR_RGB_DAT_ADDR 0xe0006800L -#define CSR_RGB_DAT_SIZE 1 -static inline unsigned char rgb_dat_read(void) { - unsigned char r = csr_readl(0xe0006800L); - return r; -} -static inline void rgb_dat_write(unsigned char value) { - csr_writel(value, 0xe0006800L); -} -#define CSR_RGB_ADDR_ADDR 0xe0006804L -#define CSR_RGB_ADDR_SIZE 1 -static inline unsigned char rgb_addr_read(void) { - unsigned char r = csr_readl(0xe0006804L); - return r; -} -static inline void rgb_addr_write(unsigned char value) { - csr_writel(value, 0xe0006804L); -} -#define CSR_RGB_CTRL_ADDR 0xe0006808L -#define CSR_RGB_CTRL_SIZE 1 -static inline unsigned char rgb_ctrl_read(void) { - unsigned char r = csr_readl(0xe0006808L); - return r; -} -static inline void rgb_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0006808L); -} -#define CSR_RGB_CTRL_EXE_OFFSET 0 -#define CSR_RGB_CTRL_EXE_SIZE 1 -#define CSR_RGB_CTRL_CURREN_OFFSET 1 -#define CSR_RGB_CTRL_CURREN_SIZE 1 -#define CSR_RGB_CTRL_RGBLEDEN_OFFSET 2 -#define CSR_RGB_CTRL_RGBLEDEN_SIZE 1 -#define CSR_RGB_CTRL_RRAW_OFFSET 3 -#define CSR_RGB_CTRL_RRAW_SIZE 1 -#define CSR_RGB_CTRL_GRAW_OFFSET 4 -#define CSR_RGB_CTRL_GRAW_SIZE 1 -#define CSR_RGB_CTRL_BRAW_OFFSET 5 -#define CSR_RGB_CTRL_BRAW_SIZE 1 -#define CSR_RGB_RAW_ADDR 0xe000680cL -#define CSR_RGB_RAW_SIZE 1 -static inline unsigned char rgb_raw_read(void) { - unsigned char r = csr_readl(0xe000680cL); - return r; -} -static inline void rgb_raw_write(unsigned char value) { - csr_writel(value, 0xe000680cL); -} -#define CSR_RGB_RAW_R_OFFSET 0 -#define CSR_RGB_RAW_R_SIZE 1 -#define CSR_RGB_RAW_G_OFFSET 1 -#define CSR_RGB_RAW_G_SIZE 1 -#define CSR_RGB_RAW_B_OFFSET 2 -#define CSR_RGB_RAW_B_SIZE 1 - -/* timer0 */ -#define CSR_TIMER0_BASE 0xe0002800L -#define CSR_TIMER0_LOAD_ADDR 0xe0002800L -#define CSR_TIMER0_LOAD_SIZE 4 -static inline unsigned int timer0_load_read(void) { - unsigned int r = csr_readl(0xe0002800L); - r <<= 8; - r |= csr_readl(0xe0002804L); - r <<= 8; - r |= csr_readl(0xe0002808L); - r <<= 8; - r |= csr_readl(0xe000280cL); - return r; -} -static inline void timer0_load_write(unsigned int value) { - csr_writel(value >> 24, 0xe0002800L); - csr_writel(value >> 16, 0xe0002804L); - csr_writel(value >> 8, 0xe0002808L); - csr_writel(value, 0xe000280cL); -} -#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L -#define CSR_TIMER0_RELOAD_SIZE 4 -static inline unsigned int timer0_reload_read(void) { - unsigned int r = csr_readl(0xe0002810L); - r <<= 8; - r |= csr_readl(0xe0002814L); - r <<= 8; - r |= csr_readl(0xe0002818L); - r <<= 8; - r |= csr_readl(0xe000281cL); - return r; -} -static inline void timer0_reload_write(unsigned int value) { - csr_writel(value >> 24, 0xe0002810L); - csr_writel(value >> 16, 0xe0002814L); - csr_writel(value >> 8, 0xe0002818L); - csr_writel(value, 0xe000281cL); -} -#define CSR_TIMER0_EN_ADDR 0xe0002820L -#define CSR_TIMER0_EN_SIZE 1 -static inline unsigned char timer0_en_read(void) { - unsigned char r = csr_readl(0xe0002820L); - return r; -} -static inline void timer0_en_write(unsigned char value) { - csr_writel(value, 0xe0002820L); -} -#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L -#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 -static inline unsigned char timer0_update_value_read(void) { - unsigned char r = csr_readl(0xe0002824L); - return r; -} -static inline void timer0_update_value_write(unsigned char value) { - csr_writel(value, 0xe0002824L); -} -#define CSR_TIMER0_VALUE_ADDR 0xe0002828L -#define CSR_TIMER0_VALUE_SIZE 4 -static inline unsigned int timer0_value_read(void) { - unsigned int r = csr_readl(0xe0002828L); - r <<= 8; - r |= csr_readl(0xe000282cL); - r <<= 8; - r |= csr_readl(0xe0002830L); - r <<= 8; - r |= csr_readl(0xe0002834L); - return r; -} -#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L -#define CSR_TIMER0_EV_STATUS_SIZE 1 -static inline unsigned char timer0_ev_status_read(void) { - unsigned char r = csr_readl(0xe0002838L); - return r; -} -static inline void timer0_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0002838L); -} -#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL -#define CSR_TIMER0_EV_PENDING_SIZE 1 -static inline unsigned char timer0_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000283cL); - return r; -} -static inline void timer0_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000283cL); -} -#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L -#define CSR_TIMER0_EV_ENABLE_SIZE 1 -static inline unsigned char timer0_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0002840L); - return r; -} -static inline void timer0_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0002840L); -} - -/* touch */ -#define CSR_TOUCH_BASE 0xe0005800L -#define CSR_TOUCH_O_ADDR 0xe0005800L -#define CSR_TOUCH_O_SIZE 1 -static inline unsigned char touch_o_read(void) { - unsigned char r = csr_readl(0xe0005800L); - return r; -} -static inline void touch_o_write(unsigned char value) { - csr_writel(value, 0xe0005800L); -} -#define CSR_TOUCH_O_O_OFFSET 0 -#define CSR_TOUCH_O_O_SIZE 4 -#define CSR_TOUCH_OE_ADDR 0xe0005804L -#define CSR_TOUCH_OE_SIZE 1 -static inline unsigned char touch_oe_read(void) { - unsigned char r = csr_readl(0xe0005804L); - return r; -} -static inline void touch_oe_write(unsigned char value) { - csr_writel(value, 0xe0005804L); -} -#define CSR_TOUCH_OE_OE_OFFSET 0 -#define CSR_TOUCH_OE_OE_SIZE 4 -#define CSR_TOUCH_I_ADDR 0xe0005808L -#define CSR_TOUCH_I_SIZE 1 -static inline unsigned char touch_i_read(void) { - unsigned char r = csr_readl(0xe0005808L); - return r; -} -#define CSR_TOUCH_I_I_OFFSET 0 -#define CSR_TOUCH_I_I_SIZE 4 - -/* usb */ -#define CSR_USB_BASE 0xe0004800L -#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L -#define CSR_USB_PULLUP_OUT_SIZE 1 -static inline unsigned char usb_pullup_out_read(void) { - unsigned char r = csr_readl(0xe0004800L); - return r; -} -static inline void usb_pullup_out_write(unsigned char value) { - csr_writel(value, 0xe0004800L); -} -#define CSR_USB_ADDRESS_ADDR 0xe0004804L -#define CSR_USB_ADDRESS_SIZE 1 -static inline unsigned char usb_address_read(void) { - unsigned char r = csr_readl(0xe0004804L); - return r; -} -static inline void usb_address_write(unsigned char value) { - csr_writel(value, 0xe0004804L); -} -#define CSR_USB_ADDRESS_ADDR_OFFSET 0 -#define CSR_USB_ADDRESS_ADDR_SIZE 7 -#define CSR_USB_NEXT_EV_ADDR 0xe0004808L -#define CSR_USB_NEXT_EV_SIZE 1 -static inline unsigned char usb_next_ev_read(void) { - unsigned char r = csr_readl(0xe0004808L); - return r; -} -#define CSR_USB_NEXT_EV_IN_OFFSET 0 -#define CSR_USB_NEXT_EV_IN_SIZE 1 -#define CSR_USB_NEXT_EV_OUT_OFFSET 1 -#define CSR_USB_NEXT_EV_OUT_SIZE 1 -#define CSR_USB_NEXT_EV_SETUP_OFFSET 2 -#define CSR_USB_NEXT_EV_SETUP_SIZE 1 -#define CSR_USB_NEXT_EV_RESET_OFFSET 3 -#define CSR_USB_NEXT_EV_RESET_SIZE 1 -#define CSR_USB_SETUP_DATA_ADDR 0xe000480cL -#define CSR_USB_SETUP_DATA_SIZE 1 -static inline unsigned char usb_setup_data_read(void) { - unsigned char r = csr_readl(0xe000480cL); - return r; -} -#define CSR_USB_SETUP_DATA_DATA_OFFSET 0 -#define CSR_USB_SETUP_DATA_DATA_SIZE 8 -#define CSR_USB_SETUP_CTRL_ADDR 0xe0004810L -#define CSR_USB_SETUP_CTRL_SIZE 1 -static inline unsigned char usb_setup_ctrl_read(void) { - unsigned char r = csr_readl(0xe0004810L); - return r; -} -static inline void usb_setup_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0004810L); -} -#define CSR_USB_SETUP_CTRL_RESET_OFFSET 5 -#define CSR_USB_SETUP_CTRL_RESET_SIZE 1 -#define CSR_USB_SETUP_STATUS_ADDR 0xe0004814L -#define CSR_USB_SETUP_STATUS_SIZE 1 -static inline unsigned char usb_setup_status_read(void) { - unsigned char r = csr_readl(0xe0004814L); - return r; -} -#define CSR_USB_SETUP_STATUS_EPNO_OFFSET 0 -#define CSR_USB_SETUP_STATUS_EPNO_SIZE 4 -#define CSR_USB_SETUP_STATUS_HAVE_OFFSET 4 -#define CSR_USB_SETUP_STATUS_HAVE_SIZE 1 -#define CSR_USB_SETUP_STATUS_PEND_OFFSET 5 -#define CSR_USB_SETUP_STATUS_PEND_SIZE 1 -#define CSR_USB_SETUP_STATUS_IS_IN_OFFSET 6 -#define CSR_USB_SETUP_STATUS_IS_IN_SIZE 1 -#define CSR_USB_SETUP_STATUS_DATA_OFFSET 7 -#define CSR_USB_SETUP_STATUS_DATA_SIZE 1 -#define CSR_USB_SETUP_EV_STATUS_ADDR 0xe0004818L -#define CSR_USB_SETUP_EV_STATUS_SIZE 1 -static inline unsigned char usb_setup_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004818L); - return r; -} -static inline void usb_setup_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004818L); -} -#define CSR_USB_SETUP_EV_PENDING_ADDR 0xe000481cL -#define CSR_USB_SETUP_EV_PENDING_SIZE 1 -static inline unsigned char usb_setup_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000481cL); - return r; -} -static inline void usb_setup_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000481cL); -} -#define CSR_USB_SETUP_EV_ENABLE_ADDR 0xe0004820L -#define CSR_USB_SETUP_EV_ENABLE_SIZE 1 -static inline unsigned char usb_setup_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0004820L); - return r; -} -static inline void usb_setup_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0004820L); -} -#define CSR_USB_IN_DATA_ADDR 0xe0004824L -#define CSR_USB_IN_DATA_SIZE 1 -static inline unsigned char usb_in_data_read(void) { - unsigned char r = csr_readl(0xe0004824L); - return r; -} -static inline void usb_in_data_write(unsigned char value) { - csr_writel(value, 0xe0004824L); -} -#define CSR_USB_IN_DATA_DATA_OFFSET 0 -#define CSR_USB_IN_DATA_DATA_SIZE 8 -#define CSR_USB_IN_CTRL_ADDR 0xe0004828L -#define CSR_USB_IN_CTRL_SIZE 1 -static inline unsigned char usb_in_ctrl_read(void) { - unsigned char r = csr_readl(0xe0004828L); - return r; -} -static inline void usb_in_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0004828L); -} -#define CSR_USB_IN_CTRL_EPNO_OFFSET 0 -#define CSR_USB_IN_CTRL_EPNO_SIZE 4 -#define CSR_USB_IN_CTRL_RESET_OFFSET 5 -#define CSR_USB_IN_CTRL_RESET_SIZE 1 -#define CSR_USB_IN_CTRL_STALL_OFFSET 6 -#define CSR_USB_IN_CTRL_STALL_SIZE 1 -#define CSR_USB_IN_STATUS_ADDR 0xe000482cL -#define CSR_USB_IN_STATUS_SIZE 1 -static inline unsigned char usb_in_status_read(void) { - unsigned char r = csr_readl(0xe000482cL); - return r; -} -#define CSR_USB_IN_STATUS_IDLE_OFFSET 0 -#define CSR_USB_IN_STATUS_IDLE_SIZE 1 -#define CSR_USB_IN_STATUS_HAVE_OFFSET 4 -#define CSR_USB_IN_STATUS_HAVE_SIZE 1 -#define CSR_USB_IN_STATUS_PEND_OFFSET 5 -#define CSR_USB_IN_STATUS_PEND_SIZE 1 -#define CSR_USB_IN_EV_STATUS_ADDR 0xe0004830L -#define CSR_USB_IN_EV_STATUS_SIZE 1 -static inline unsigned char usb_in_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004830L); - return r; -} -static inline void usb_in_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004830L); -} -#define CSR_USB_IN_EV_PENDING_ADDR 0xe0004834L -#define CSR_USB_IN_EV_PENDING_SIZE 1 -static inline unsigned char usb_in_ev_pending_read(void) { - unsigned char r = csr_readl(0xe0004834L); - return r; -} -static inline void usb_in_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe0004834L); -} -#define CSR_USB_IN_EV_ENABLE_ADDR 0xe0004838L -#define CSR_USB_IN_EV_ENABLE_SIZE 1 -static inline unsigned char usb_in_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0004838L); - return r; -} -static inline void usb_in_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0004838L); -} -#define CSR_USB_OUT_DATA_ADDR 0xe000483cL -#define CSR_USB_OUT_DATA_SIZE 1 -static inline unsigned char usb_out_data_read(void) { - unsigned char r = csr_readl(0xe000483cL); - return r; -} -#define CSR_USB_OUT_DATA_DATA_OFFSET 0 -#define CSR_USB_OUT_DATA_DATA_SIZE 8 -#define CSR_USB_OUT_CTRL_ADDR 0xe0004840L -#define CSR_USB_OUT_CTRL_SIZE 1 -static inline unsigned char usb_out_ctrl_read(void) { - unsigned char r = csr_readl(0xe0004840L); - return r; -} -static inline void usb_out_ctrl_write(unsigned char value) { - csr_writel(value, 0xe0004840L); -} -#define CSR_USB_OUT_CTRL_EPNO_OFFSET 0 -#define CSR_USB_OUT_CTRL_EPNO_SIZE 4 -#define CSR_USB_OUT_CTRL_ENABLE_OFFSET 4 -#define CSR_USB_OUT_CTRL_ENABLE_SIZE 1 -#define CSR_USB_OUT_CTRL_RESET_OFFSET 5 -#define CSR_USB_OUT_CTRL_RESET_SIZE 1 -#define CSR_USB_OUT_CTRL_STALL_OFFSET 6 -#define CSR_USB_OUT_CTRL_STALL_SIZE 1 -#define CSR_USB_OUT_STATUS_ADDR 0xe0004844L -#define CSR_USB_OUT_STATUS_SIZE 1 -static inline unsigned char usb_out_status_read(void) { - unsigned char r = csr_readl(0xe0004844L); - return r; -} -#define CSR_USB_OUT_STATUS_EPNO_OFFSET 0 -#define CSR_USB_OUT_STATUS_EPNO_SIZE 4 -#define CSR_USB_OUT_STATUS_HAVE_OFFSET 4 -#define CSR_USB_OUT_STATUS_HAVE_SIZE 1 -#define CSR_USB_OUT_STATUS_PEND_OFFSET 5 -#define CSR_USB_OUT_STATUS_PEND_SIZE 1 -#define CSR_USB_OUT_EV_STATUS_ADDR 0xe0004848L -#define CSR_USB_OUT_EV_STATUS_SIZE 1 -static inline unsigned char usb_out_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004848L); - return r; -} -static inline void usb_out_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004848L); -} -#define CSR_USB_OUT_EV_PENDING_ADDR 0xe000484cL -#define CSR_USB_OUT_EV_PENDING_SIZE 1 -static inline unsigned char usb_out_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000484cL); - return r; -} -static inline void usb_out_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000484cL); -} -#define CSR_USB_OUT_EV_ENABLE_ADDR 0xe0004850L -#define CSR_USB_OUT_EV_ENABLE_SIZE 1 -static inline unsigned char usb_out_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0004850L); - return r; -} -static inline void usb_out_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0004850L); -} -#define CSR_USB_OUT_ENABLE_STATUS_ADDR 0xe0004854L -#define CSR_USB_OUT_ENABLE_STATUS_SIZE 1 -static inline unsigned char usb_out_enable_status_read(void) { - unsigned char r = csr_readl(0xe0004854L); - return r; -} -#define CSR_USB_OUT_STALL_STATUS_ADDR 0xe0004858L -#define CSR_USB_OUT_STALL_STATUS_SIZE 1 -static inline unsigned char usb_out_stall_status_read(void) { - unsigned char r = csr_readl(0xe0004858L); - return r; -} - -/* version */ -#define CSR_VERSION_BASE 0xe0007000L -#define CSR_VERSION_MAJOR_ADDR 0xe0007000L -#define CSR_VERSION_MAJOR_SIZE 1 -static inline unsigned char version_major_read(void) { - unsigned char r = csr_readl(0xe0007000L); - return r; -} -#define CSR_VERSION_MINOR_ADDR 0xe0007004L -#define CSR_VERSION_MINOR_SIZE 1 -static inline unsigned char version_minor_read(void) { - unsigned char r = csr_readl(0xe0007004L); - return r; -} -#define CSR_VERSION_REVISION_ADDR 0xe0007008L -#define CSR_VERSION_REVISION_SIZE 1 -static inline unsigned char version_revision_read(void) { - unsigned char r = csr_readl(0xe0007008L); - return r; -} -#define CSR_VERSION_GITREV_ADDR 0xe000700cL -#define CSR_VERSION_GITREV_SIZE 4 -static inline unsigned int version_gitrev_read(void) { - unsigned int r = csr_readl(0xe000700cL); - r <<= 8; - r |= csr_readl(0xe0007010L); - r <<= 8; - r |= csr_readl(0xe0007014L); - r <<= 8; - r |= csr_readl(0xe0007018L); - return r; -} -#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL -#define CSR_VERSION_GITEXTRA_SIZE 2 -static inline unsigned short int version_gitextra_read(void) { - unsigned short int r = csr_readl(0xe000701cL); - r <<= 8; - r |= csr_readl(0xe0007020L); - return r; -} -#define CSR_VERSION_DIRTY_ADDR 0xe0007024L -#define CSR_VERSION_DIRTY_SIZE 1 -static inline unsigned char version_dirty_read(void) { - unsigned char r = csr_readl(0xe0007024L); - return r; -} -#define CSR_VERSION_DIRTY_DIRTY_OFFSET 0 -#define CSR_VERSION_DIRTY_DIRTY_SIZE 1 -#define CSR_VERSION_MODEL_ADDR 0xe0007028L -#define CSR_VERSION_MODEL_SIZE 1 -static inline unsigned char version_model_read(void) { - unsigned char r = csr_readl(0xe0007028L); - return r; -} -#define CSR_VERSION_MODEL_MODEL_OFFSET 0 -#define CSR_VERSION_MODEL_MODEL_SIZE 8 -#define CSR_VERSION_SEED_ADDR 0xe000702cL -#define CSR_VERSION_SEED_SIZE 4 -static inline unsigned int version_seed_read(void) { - unsigned int r = csr_readl(0xe000702cL); - r <<= 8; - r |= csr_readl(0xe0007030L); - r <<= 8; - r |= csr_readl(0xe0007034L); - r <<= 8; - r |= csr_readl(0xe0007038L); - return r; -} - -/* constants */ -#define TIMER0_INTERRUPT 2 -static inline int timer0_interrupt_read(void) { - return 2; -} -#define USB_INTERRUPT 3 -static inline int usb_interrupt_read(void) { - return 3; -} -#define CONFIG_BITSTREAM_SYNC_HEADER1 2123999870 -static inline int config_bitstream_sync_header1_read(void) { - return 2123999870; -} -#define CONFIG_BITSTREAM_SYNC_HEADER2 2125109630 -static inline int config_bitstream_sync_header2_read(void) { - return 2125109630; -} -#define CONFIG_CLOCK_FREQUENCY 12000000 -static inline int config_clock_frequency_read(void) { - return 12000000; -} -#define CONFIG_CPU_RESET_ADDR 0 -static inline int config_cpu_reset_addr_read(void) { - return 0; -} -#define CONFIG_CPU_TYPE "VEXRISCV" -static inline const char * config_cpu_type_read(void) { - return "VEXRISCV"; -} -#define CONFIG_CPU_TYPE_VEXRISCV 1 -static inline int config_cpu_type_vexriscv_read(void) { - return 1; -} -#define CONFIG_CPU_VARIANT "MIN" -static inline const char * config_cpu_variant_read(void) { - return "MIN"; -} -#define CONFIG_CPU_VARIANT_MIN 1 -static inline int config_cpu_variant_min_read(void) { - return 1; -} -#define CONFIG_CSR_ALIGNMENT 32 -static inline int config_csr_alignment_read(void) { - return 32; -} -#define CONFIG_CSR_DATA_WIDTH 8 -static inline int config_csr_data_width_read(void) { - return 8; -} - -#endif diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/hw/common.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/hw/common.h deleted file mode 100644 index 6a97ca2e..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/hw/common.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _HW_COMMON_H_ -#define _HW_COMMON_H_ -#include -static inline void csr_writeb(uint8_t value, uint32_t addr) -{ - *((volatile uint8_t *)addr) = value; -} - -static inline uint8_t csr_readb(uint32_t addr) -{ - return *(volatile uint8_t *)addr; -} - -static inline void csr_writew(uint16_t value, uint32_t addr) -{ - *((volatile uint16_t *)addr) = value; -} - -static inline uint16_t csr_readw(uint32_t addr) -{ - return *(volatile uint16_t *)addr; -} - -static inline void csr_writel(uint32_t value, uint32_t addr) -{ - *((volatile uint32_t *)addr) = value; -} - -static inline uint32_t csr_readl(uint32_t addr) -{ - return *(volatile uint32_t *)addr; -} -#endif /* _HW_COMMON_H_ */ \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/irq.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/irq.h deleted file mode 100644 index a8221890..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/fomu/include/irq.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef __IRQ_H -#define __IRQ_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#define CSR_MSTATUS_MIE 0x8 - -#define CSR_IRQ_MASK 0xBC0 -#define CSR_IRQ_PENDING 0xFC0 - -#define CSR_DCACHE_INFO 0xCC0 - -#define csrr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define csrw(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define csrs(reg, bit) ({ \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \ - else \ - asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); }) - -#define csrc(reg, bit) ({ \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \ - else \ - asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); }) - -static inline unsigned int irq_getie(void) -{ - return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; -} - -static inline void irq_setie(unsigned int ie) -{ - if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); -} - -static inline unsigned int irq_getmask(void) -{ - unsigned int mask; - asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); - return mask; -} - -static inline void irq_setmask(unsigned int mask) -{ - asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); -} - -static inline unsigned int irq_pending(void) -{ - unsigned int pending; - asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); - return pending; -} - -#ifdef __cplusplus -} -#endif - -#endif /* __IRQ_H */ \ No newline at end of file diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1010_evk/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1010_evk/board.h deleted file mode 100644 index 7e4b5729..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1010_evk/board.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -#include "fsl_device_registers.h" - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (0x1000000U) - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h deleted file mode 100644 index 4be2760b..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_120MHz = 7, - kFlexSpiSerialClk_133MHz = 8, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1015_evk/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1015_evk/board.h deleted file mode 100644 index 5f3e3158..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1015_evk/board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (0x1000000U) - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h deleted file mode 100644 index 94af5a11..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1020_evk/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1020_evk/board.h deleted file mode 100644 index f1bd0636..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1020_evk/board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (0x800000U) - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h deleted file mode 100644 index f5e1aca5..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1050_evkb/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1050_evkb/board.h deleted file mode 100644 index 3f660ac7..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1050_evkb/board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (0x4000000U) - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h deleted file mode 100644 index fe40e7ed..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ -#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1060_evk/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1060_evk/board.h deleted file mode 100644 index f1bd0636..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1060_evk/board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (0x800000U) - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h deleted file mode 100644 index 28d7db57..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_120MHz = 7, - kFlexSpiSerialClk_133MHz = 8, - kFlexSpiSerialClk_166MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1064_evk/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1064_evk/board.h deleted file mode 100644 index 3157e7d5..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1064_evk/board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (0x400000U) - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h deleted file mode 100644 index efdfe583..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ -#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_120MHz = 7, - kFlexSpiSerialClk_133MHz = 8, - kFlexSpiSerialClk_166MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/pyboardv11/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/pyboardv11/stm32f4xx_hal_conf.h deleted file mode 100644 index dbef20e0..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/pyboardv11/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,489 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)12000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* Copied over manually- STM32Cube didn't generate these for some reason. */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848_PHY_ADDRESS Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) - -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/samg55xplained/hpl_usart_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/samg55xplained/hpl_usart_config.h deleted file mode 100644 index 4f2837d2..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/samg55xplained/hpl_usart_config.h +++ /dev/null @@ -1,215 +0,0 @@ -/* Auto-generated config file hpl_usart_config.h */ -#ifndef HPL_USART_CONFIG_H -#define HPL_USART_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -#ifndef CONF_USART_7_ENABLE -#define CONF_USART_7_ENABLE 1 -#endif - -// Basic Configuration - -// Frame parity -// <0x0=>Even parity -// <0x1=>Odd parity -// <0x2=>Parity forced to 0 -// <0x3=>Parity forced to 1 -// <0x4=>No parity -// Parity bit mode for USART frame -// usart_parity -#ifndef CONF_USART_7_PARITY -#define CONF_USART_7_PARITY 0x4 -#endif - -// Character Size -// <0x0=>5 bits -// <0x1=>6 bits -// <0x2=>7 bits -// <0x3=>8 bits -// Data character size in USART frame -// usart_character_size -#ifndef CONF_USART_7_CHSIZE -#define CONF_USART_7_CHSIZE 0x3 -#endif - -// Stop Bit -// <0=>1 stop bit -// <1=>1.5 stop bits -// <2=>2 stop bits -// Number of stop bits in USART frame -// usart_stop_bit -#ifndef CONF_USART_7_SBMODE -#define CONF_USART_7_SBMODE 0 -#endif - -// Clock Output Select -// <0=>The USART does not drive the SCK pin -// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK -// Clock Output Select in USART sck, if in usrt master mode, please drive SCK. -// usart_clock_output_select -#ifndef CONF_USART_7_CLKO -#define CONF_USART_7_CLKO 0 -#endif - -// Baud rate <1-3000000> -// USART baud rate setting -// usart_baud_rate -#ifndef CONF_USART_7_BAUD -#define CONF_USART_7_BAUD 9600 -#endif - -// - -// Advanced configuration -// usart_advanced -#ifndef CONF_USART_7_ADVANCED_CONFIG -#define CONF_USART_7_ADVANCED_CONFIG 0 -#endif - -// Channel Mode -// <0=>Normal Mode -// <1=>Automatic Echo -// <2=>Local Loopback -// <3=>Remote Loopback -// Channel mode in USART frame -// usart_channel_mode -#ifndef CONF_USART_7_CHMODE -#define CONF_USART_7_CHMODE 0 -#endif - -// 9 bits character enable -// Enable 9 bits character, this has high priority than 5/6/7/8 bits. -// usart_9bits_enable -#ifndef CONF_USART_7_MODE9 -#define CONF_USART_7_MODE9 0 -#endif - -// Variable Sync -// <0=>User defined configuration -// <1=>sync field is updated when a character is written into US_THR -// Variable Synchronization of Command/Data Sync Start Frarm Delimiter -// variable_sync -#ifndef CONF_USART_7_VAR_SYNC -#define CONF_USART_7_VAR_SYNC 0 -#endif - -// Oversampling Mode -// <0=>16 Oversampling -// <1=>8 Oversampling -// Oversampling Mode in UART mode -// usart__oversampling_mode -#ifndef CONF_USART_7_OVER -#define CONF_USART_7_OVER 0 -#endif - -// Inhibit Non Ack -// <0=>The NACK is generated -// <1=>The NACK is not generated -// Inhibit Non Acknowledge -// usart__inack -#ifndef CONF_USART_7_INACK -#define CONF_USART_7_INACK 1 -#endif - -// Disable Successive NACK -// <0=>NACK is sent on the ISO line as soon as a parity error occurs -// <1=>Many parity errors generate a NACK on the ISO line -// Disable Successive NACK -// usart_dsnack -#ifndef CONF_USART_7_DSNACK -#define CONF_USART_7_DSNACK 0 -#endif - -// Inverted Data -// <0=>Data isn't inverted, nomal mode -// <1=>Data is inverted -// Inverted Data -// usart_invdata -#ifndef CONF_USART_7_INVDATA -#define CONF_USART_7_INVDATA 0 -#endif - -// Maximum Number of Automatic Iteration <0-7> -// Defines the maximum number of iterations in mode ISO7816, protocol T = 0. -// usart_max_iteration -#ifndef CONF_USART_7_MAX_ITERATION -#define CONF_USART_7_MAX_ITERATION 0 -#endif - -// Receive Line Filter enable -// whether the USART filters the receive line using a three-sample filter -// usart_receive_filter_enable -#ifndef CONF_USART_7_FILTER -#define CONF_USART_7_FILTER 0 -#endif - -// Manchester Encoder/Decoder Enable -// whether the USART Manchester Encoder/Decoder -// usart_manchester_filter_enable -#ifndef CONF_USART_7_MAN -#define CONF_USART_7_MAN 0 -#endif - -// Manchester Synchronization Mode -// <0=>The Manchester start bit is a 0 to 1 transition -// <1=>The Manchester start bit is a 1 to 0 transition -// Manchester Synchronization Mode -// usart_manchester_synchronization_mode -#ifndef CONF_USART_7_MODSYNC -#define CONF_USART_7_MODSYNC 0 -#endif - -// Start Frame Delimiter Selector -// <0=>Start frame delimiter is COMMAND or DATA SYNC -// <1=>Start frame delimiter is one bit -// Start Frame Delimiter Selector -// usart_start_frame_delimiter -#ifndef CONF_USART_7_ONEBIT -#define CONF_USART_7_ONEBIT 0 -#endif - -// Fractional Part <0-7> -// Fractional part of the baud rate if baud rate generator is in fractional mode -// usart_arch_fractional -#ifndef CONF_USART_7_FRACTIONAL -#define CONF_USART_7_FRACTIONAL 0x0 -#endif - -// Data Order -// <0=>LSB is transmitted first -// <1=>MSB is transmitted first -// Data order of the data bits in the frame -// usart_arch_msbf -#ifndef CONF_USART_7_MSBF -#define CONF_USART_7_MSBF 0 -#endif - -// - -#define CONF_USART_7_MODE 0x0 - -// Calculate BAUD register value in UART mode -#if CONF_FLEXCOM7_CK_SRC < 3 -#ifndef CONF_USART_7_BAUD_CD -#define CONF_USART_7_BAUD_CD ((CONF_FLEXCOM7_FREQUENCY) / CONF_USART_7_BAUD / 8 / (2 - CONF_USART_7_OVER)) -#endif -#ifndef CONF_USART_7_BAUD_FP -#define CONF_USART_7_BAUD_FP \ - ((CONF_FLEXCOM7_FREQUENCY) / CONF_USART_7_BAUD / (2 - CONF_USART_7_OVER) - 8 * CONF_USART_7_BAUD_CD) -#endif -#elif CONF_FLEXCOM7_CK_SRC == 3 -// No division is active. The value written in US_BRGR has no effect. -#ifndef CONF_USART_7_BAUD_CD -#define CONF_USART_7_BAUD_CD 1 -#endif -#ifndef CONF_USART_7_BAUD_FP -#define CONF_USART_7_BAUD_FP 1 -#endif -#endif - -// <<< end of configuration section >>> - -#endif // HPL_USART_CONFIG_H diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/samg55xplained/peripheral_clk_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/samg55xplained/peripheral_clk_config.h deleted file mode 100644 index 6d390f38..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/samg55xplained/peripheral_clk_config.h +++ /dev/null @@ -1,85 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -/** - * \def CONF_HCLK_FREQUENCY - * \brief HCLK's Clock frequency - */ -#ifndef CONF_HCLK_FREQUENCY -#define CONF_HCLK_FREQUENCY 8000000 -#endif - -/** - * \def CONF_FCLK_FREQUENCY - * \brief FCLK's Clock frequency - */ -#ifndef CONF_FCLK_FREQUENCY -#define CONF_FCLK_FREQUENCY 8000000 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 8000000 -#endif - -/** - * \def CONF_SLCK_FREQUENCY - * \brief Slow Clock frequency - */ -#define CONF_SLCK_FREQUENCY 32768 - -/** - * \def CONF_MCK_FREQUENCY - * \brief Master Clock frequency - */ -#define CONF_MCK_FREQUENCY 8000000 - -// USB Clock Source -// <0=> USB Clock Controller (USB_48M) -// usb_clock_source -// Select the clock source for USB. -#ifndef CONF_UDP_SRC -#define CONF_UDP_SRC 0 -#endif - -/** - * \def CONF_UDP_FREQUENCY - * \brief UDP's Clock frequency - */ -#ifndef CONF_UDP_FREQUENCY -#define CONF_UDP_FREQUENCY 48005120 -#endif - -// FLEXCOM Clock Settings -// FLEXCOM Clock source -// <0=> Master Clock (MCK) -// <1=> MCK / 8 -// <2=> Programmable Clock Controller 6 (PMC_PCK6) -// <2=> Programmable Clock Controller 7 (PMC_PCK7) -// <3=> External Clock -// This defines the clock source for the FLEXCOM, PCK6 is used for FLEXCOM0/1/2/3 and PCK7 is used for FLEXCOM4/5/6/7 -// flexcom_clock_source -#ifndef CONF_FLEXCOM7_CK_SRC -#define CONF_FLEXCOM7_CK_SRC 0 -#endif - -// FLEXCOM External Clock Input on SCK <1-4294967295> -// Inputs the external clock frequency on SCK -// flexcom_clock_freq -#ifndef CONF_FLEXCOM7_SCK_FREQ -#define CONF_FLEXCOM7_SCK_FREQ 10000000 -#endif - -#ifndef CONF_FLEXCOM7_FREQUENCY -#define CONF_FLEXCOM7_FREQUENCY 8000000 -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f070rbnucleo/stm32f0xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f070rbnucleo/stm32f0xx_hal_conf.h deleted file mode 100644 index cfa66b36..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f070rbnucleo/stm32f0xx_hal_conf.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_CONF_H -#define __STM32F0xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -/*#define HAL_EXTI_MODULE_ENABLED */ -/*#define HAL_I2C_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ - -/* ######################### Oscillator Values adaptation ################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator for ADC (HSI14) value. - */ -#if !defined (HSI14_VALUE) - #define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -/** - * @brief Internal High Speed oscillator for USB (HSI48) value. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief Time out for LSE start up value in ms. - */ -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ - /* Warning: Must be set to higher priority for HAL_Delay() */ - /* and HAL_GetTick() usage under interrupt context */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 0U -#define DATA_CACHE_ENABLE 0U -#define USE_SPI_CRC 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ - #define USE_FULL_ASSERT 1 - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f0xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f0xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f0xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f0xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f0xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f0xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f0xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f0xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32f0xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f0xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f0xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f0xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f0xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f0xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f0xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f0xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f0xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f0xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f0xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f0xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f0xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f0xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f0xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32f0xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f0xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f0xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f0xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f072disco/stm32f0xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f072disco/stm32f0xx_hal_conf.h deleted file mode 100644 index cfa66b36..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f072disco/stm32f0xx_hal_conf.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f0xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F0xx_HAL_CONF_H -#define __STM32F0xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_CEC_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -/*#define HAL_EXTI_MODULE_ENABLED */ -/*#define HAL_I2C_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ - -/* ######################### Oscillator Values adaptation ################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator for ADC (HSI14) value. - */ -#if !defined (HSI14_VALUE) - #define HSI14_VALUE 14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI14_VALUE */ - -/** - * @brief Internal High Speed oscillator for USB (HSI48) value. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief Time out for LSE start up value in ms. - */ -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ - /* Warning: Must be set to higher priority for HAL_Delay() */ - /* and HAL_GetTick() usage under interrupt context */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 0U -#define DATA_CACHE_ENABLE 0U -#define USE_SPI_CRC 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ - #define USE_FULL_ASSERT 1 - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f0xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f0xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f0xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f0xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f0xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f0xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f0xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f0xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32f0xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f0xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f0xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f0xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f0xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f0xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f0xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f0xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f0xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f0xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f0xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f0xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f0xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f0xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f0xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32f0xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f0xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f0xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f0xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F0xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f103bluepill/stm32f1xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f103bluepill/stm32f1xx_hal_conf.h deleted file mode 100644 index a4a3f308..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f103bluepill/stm32f1xx_hal_conf.h +++ /dev/null @@ -1,379 +0,0 @@ -/** - ****************************************************************************** - * @file USB_Device/HID_Standalone/Inc/stm32f1xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32f1xx_hal_conf.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F1xx_HAL_CONF_H -#define __STM32F1xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -#define HAL_EXTI_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) -#if defined(USE_STM3210C_EVAL) - #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ -#else - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0x00U /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f1xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f1xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f1xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f1xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f1xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "Legacy/stm32f1xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f1xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f1xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f1xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f1xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f1xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f1xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f1xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f1xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f1xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f1xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f1xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f1xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f1xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f1xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f1xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f1xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f1xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f1xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f1xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f1xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f1xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f1xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F1xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h deleted file mode 100644 index 2ab46b26..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h +++ /dev/null @@ -1,407 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_HAL_CONF_H -#define __STM32F2xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DMA_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_EXTI_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_PCD_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ - - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* LAN8742A PHY Address*/ -#define LAN8742A_PHY_ADDRESS 0x00U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< PHY Duplex mask */ - - -#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f2xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f2xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f2xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f2xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f2xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f2xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f2xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f2xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f2xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f2xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f2xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f2xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f2xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f2xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f2xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f2xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f2xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f2xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f2xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f2xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f2xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f2xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f2xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f2xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f2xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f2xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f2xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f2xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f2xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f2xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f2xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f2xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f2xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f2xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h deleted file mode 100644 index 0abcbb01..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h +++ /dev/null @@ -1,357 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f3xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F3xx_HAL_CONF_H -#define __STM32F3xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_HRTIM_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_OPAMP_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_PWR_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SDADC_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - * Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - * Timeout value - */ -#if !defined (HSI_STARTUP_TIMEOUT) - #define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */ -#endif /* HSI_STARTUP_TIMEOUT */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (40000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -/** - * @brief Time out for LSE start up value in ms. - */ -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - * - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal) - * - External clock not generated on EVAL 373 - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 0U -#define DATA_CACHE_ENABLE 0U -#define USE_SPI_CRC 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SDADC_REGISTER_CALLBACKS 0U /* SDADC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/*#define USE_FULL_ASSERT 1U*/ - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f3xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f3xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f3xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f3xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f3xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f3xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f3xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f3xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f3xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32f3xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f3xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f3xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f3xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f3xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f3xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f3xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f3xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_HRTIM_MODULE_ENABLED - #include "stm32f3xx_hal_hrtim.h" -#endif /* HAL_HRTIM_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f3xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f3xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f3xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f3xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32f3xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f3xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f3xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f3xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SDADC_MODULE_ENABLED - #include "stm32f3xx_hal_sdadc.h" -#endif /* HAL_SDADC_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f3xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f3xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f3xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f3xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32f3xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f3xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f3xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f3xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F3xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f401blackpill/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f401blackpill/stm32f4xx_hal_conf.h deleted file mode 100644 index a6c88f24..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f401blackpill/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f407disco/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f407disco/stm32f4xx_hal_conf.h deleted file mode 100644 index 7864f8d5..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f407disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f411blackpill/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f411blackpill/stm32f4xx_hal_conf.h deleted file mode 100644 index a6c88f24..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f411blackpill/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (25000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f411disco/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f411disco/stm32f4xx_hal_conf.h deleted file mode 100644 index 7864f8d5..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f411disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f412disco/stm32f4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f412disco/stm32f4xx_hal_conf.h deleted file mode 100644 index 7864f8d5..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f412disco/stm32f4xx_hal_conf.h +++ /dev/null @@ -1,493 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration file - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CONF_H -#define __STM32F4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_PCCARD_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -// #define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_FMPI2C_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (32000U) -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE (12288000U) /*!< Value of the External oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE (3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f4xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f4xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_PCCARD_MODULE_ENABLED - #include "stm32f4xx_hal_pccard.h" -#endif /* HAL_PCCARD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f4xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f4xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f4xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_FMPI2C_MODULE_ENABLED - #include "stm32f4xx_hal_fmpi2c.h" -#endif /* HAL_FMPI2C_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f4xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f4xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f746nucleo/stm32f7xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f746nucleo/stm32f7xx_hal_conf.h deleted file mode 100644 index 234191b0..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f746nucleo/stm32f7xx_hal_conf.h +++ /dev/null @@ -1,472 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CONF_H -#define __STM32F7xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_JPEG_MODULE_ENABLED */ -/* #define HAL_MDIOS_MODULE_ENABLED */ - - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ -/* LAN8742A PHY Address*/ -#define LAN8742A_PHY_ADDRESS 0x00 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x00000FFF) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) - -#define PHY_READ_TO ((uint32_t)0x0000FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< PHY Duplex mask */ - - -#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f7xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f7xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f7xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f7xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f7xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f7xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f7xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f7xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f7xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f7xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f7xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f7xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f7xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f7xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f7xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f7xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f7xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f7xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f7xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f7xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f7xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f7xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f7xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f7xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f7xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f7xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f7xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f7xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f7xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f7xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f7xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f7xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f7xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f7xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f7xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f7xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f7xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f7xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f7xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f7xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED - #include "stm32f7xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_MDIOS_MODULE_ENABLED - #include "stm32f7xx_hal_mdios.h" -#endif /* HAL_MDIOS_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f767nucleo/stm32f7xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f767nucleo/stm32f7xx_hal_conf.h deleted file mode 100644 index 234191b0..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32f767nucleo/stm32f7xx_hal_conf.h +++ /dev/null @@ -1,472 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CONF_H -#define __STM32F7xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_HASH_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -/* #define HAL_DSI_MODULE_ENABLED */ -/* #define HAL_JPEG_MODULE_ENABLED */ -/* #define HAL_MDIOS_MODULE_ENABLED */ - - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ -/* LAN8742A PHY Address*/ -#define LAN8742A_PHY_ADDRESS 0x00 -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x00000FFF) -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) - -#define PHY_READ_TO ((uint32_t)0x0000FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x1F) /*!< PHY special control/ status register Offset */ - -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< PHY Duplex mask */ - - -#define PHY_ISFR ((uint16_t)0x1D) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010) /*!< PHY Link down inturrupt */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f7xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f7xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f7xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f7xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f7xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f7xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f7xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f7xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f7xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f7xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f7xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f7xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f7xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f7xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f7xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f7xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f7xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f7xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f7xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f7xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f7xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f7xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f7xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f7xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f7xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f7xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f7xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f7xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f7xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f7xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f7xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f7xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f7xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f7xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f7xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f7xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f7xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f7xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f7xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f7xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED - #include "stm32f7xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_MDIOS_MODULE_ENABLED - #include "stm32f7xx_hal_mdios.h" -#endif /* HAL_MDIOS_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32h743nucleo/stm32h7xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32h743nucleo/stm32h7xx_hal_conf.h deleted file mode 100644 index c58fdf75..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32h743nucleo/stm32h7xx_hal_conf.h +++ /dev/null @@ -1,480 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h7xx_hal_conf_template.h - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32h7xx_hal_conf.h. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32H7xx_HAL_CONF_H -#define __STM32H7xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -/* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DCMI_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_DMA2D_MODULE_ENABLED */ -/* #define HAL_ETH_MODULE_ENABLED */ -/* #define HAL_EXTI_MODULE_ENABLED */ -/* #define HAL_FDCAN_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_HASH_MODULE_ENABLED */ -/* #define HAL_HCD_MODULE_ENABLED */ -/* #define HAL_HRTIM_MODULE_ENABLED */ -/* #define HAL_HSEM_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_JPEG_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_LTDC_MODULE_ENABLED */ -/* #define HAL_MDIOS_MODULE_ENABLED */ -/* #define HAL_MDMA_MODULE_ENABLED */ -/* #define HAL_MMC_MODULE_ENABLED */ -/* #define HAL_NAND_MODULE_ENABLED */ -/* #define HAL_NOR_MODULE_ENABLED */ -/* #define HAL_OPAMP_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -/* #define HAL_RAMECC_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -/* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ -/* #define HAL_SDRAM_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_SPDIFRX_MODULE_ENABLED */ -#define HAL_SPI_MODULE_ENABLED -/* #define HAL_SRAM_MODULE_ENABLED */ -/* #define HAL_SWPMI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal oscillator (CSI) default value. - * This value is the default CSI value after Reset. - */ -#if !defined (CSI_VALUE) - #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* CSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ -#define USE_RTOS 0 -#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */ -#define USE_SPI_CRC 1U /*!< use CRC in SPI */ - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################### Ethernet Configuration ######################### */ -#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */ -#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */ - -#define ETH_MAC_ADDR0 ((uint8_t)0x02) -#define ETH_MAC_ADDR1 ((uint8_t)0x00) -#define ETH_MAC_ADDR2 ((uint8_t)0x00) -#define ETH_MAC_ADDR3 ((uint8_t)0x00) -#define ETH_MAC_ADDR4 ((uint8_t)0x00) -#define ETH_MAC_ADDR5 ((uint8_t)0x00) - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32h7xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32h7xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32h7xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_MDMA_MODULE_ENABLED - #include "stm32h7xx_hal_mdma.h" -#endif /* HAL_MDMA_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32h7xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32h7xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32h7xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32h7xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32h7xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32h7xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32h7xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32h7xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32h7xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_FDCAN_MODULE_ENABLED - #include "stm32h7xx_hal_fdcan.h" -#endif /* HAL_FDCAN_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32h7xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32h7xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32h7xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32h7xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32h7xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32h7xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_HRTIM_MODULE_ENABLED - #include "stm32h7xx_hal_hrtim.h" -#endif /* HAL_HRTIM_MODULE_ENABLED */ - -#ifdef HAL_HSEM_MODULE_ENABLED - #include "stm32h7xx_hal_hsem.h" -#endif /* HAL_HSEM_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32h7xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32h7xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32h7xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32h7xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32h7xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32h7xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED - #include "stm32h7xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_MDIOS_MODULE_ENABLED - #include "stm32h7xx_hal_mdios.h" -#endif /* HAL_MDIOS_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32h7xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32h7xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED -#include "stm32h7xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32h7xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32h7xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32h7xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RAMECC_MODULE_ENABLED - #include "stm32h7xx_hal_ramecc.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32h7xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32h7xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32h7xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32h7xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32h7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32h7xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32h7xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32h7xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32h7xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32h7xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32h7xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32h7xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32h7xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32h7xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32h7xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32h7xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32h7xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t *file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32H7xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h deleted file mode 100644 index 773b74e2..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h +++ /dev/null @@ -1,331 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l0xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * - * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L0xx_HAL_CONF_H -#define __STM32L0xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -// #define HAL_ADC_MODULE_ENABLED -/* #define HAL_COMP_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_FIREWALL_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -/* #define HAL_I2C_MODULE_ENABLED */ -/* #define HAL_I2S_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -/* #define HAL_LCD_MODULE_ENABLED */ -/* #define HAL_LPTIM_MODULE_ENABLED */ -#define HAL_PWR_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -//#define HAL_RNG_MODULE_ENABLED -/* #define HAL_RTC_MODULE_ENABLED */ -//#define HAL_SPI_MODULE_ENABLED -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_TSC_MODULE_ENABLED */ -/* #define HAL_UART_MODULE_ENABLED */ -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ -//#define HAL_PCD_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_PCD_MODULE_ENABLED */ - - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator for USB (HSI48) value. - */ -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -/** - * @brief Time out for LSE start up value in ms. - */ -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define PREREAD_ENABLE 1U -#define BUFFER_CACHE_DISABLE 0U - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l0xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l0xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l0xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l0xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l0xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l0xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l0xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l0xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l0xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l0xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l0xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l0xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32l0xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l0xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l0xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l0xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l0xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l0xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l0xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l0xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l0xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l0xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l0xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l0xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l0xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l0xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l0xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l0xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l0xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t *file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L0xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h deleted file mode 100644 index dce4008d..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h +++ /dev/null @@ -1,380 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32l4xx_hal_conf.h. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -/* #define HAL_ADC_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_COMP_MODULE_ENABLED */ -#define HAL_CORTEX_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ -/* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ -/* #define HAL_DFSDM_MODULE_ENABLED */ -#define HAL_DMA_MODULE_ENABLED -/* #define HAL_FIREWALL_MODULE_ENABLED */ -#define HAL_FLASH_MODULE_ENABLED -/* #define HAL_NAND_MODULE_ENABLED */ -#define HAL_NOR_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -/* #define HAL_HCD_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -//#define HAL_I2C_MODULE_ENABLED -/* #define HAL_IRDA_MODULE_ENABLED */ -/* #define HAL_IWDG_MODULE_ENABLED */ -//#define HAL_LCD_MODULE_ENABLED -/* #define HAL_LPTIM_MODULE_ENABLED */ -/* #define HAL_OPAMP_MODULE_ENABLED */ -//#define HAL_PCD_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -/* #define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RCC_MODULE_ENABLED -/* #define HAL_RNG_MODULE_ENABLED */ -/* #define HAL_RTC_MODULE_ENABLED */ -//#define HAL_SAI_MODULE_ENABLED -//#define HAL_SD_MODULE_ENABLED -/* #define HAL_SMARTCARD_MODULE_ENABLED */ -/* #define HAL_SMBUS_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ -/* #define HAL_SWPMI_MODULE_ENABLED */ -/* #define HAL_TIM_MODULE_ENABLED */ -/* #define HAL_TSC_MODULE_ENABLED */ -//#define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ -/* #define HAL_WWDG_MODULE_ENABLED */ - - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/** - * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "Legacy/stm32l4xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32l4xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t *file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CONF_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/teensy_40/board.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/teensy_40/board.h deleted file mode 100644 index c5338e27..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/teensy_40/board.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_H_ -#define BOARD_H_ - - -// required since iMX RT10xx SDK include this file for board size -#define BOARD_FLASH_SIZE (2 * 1024 * 1024) - - -#endif /* BOARD_H_ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.h deleted file mode 100644 index 56068ec6..00000000 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__ -#define __TEENSY40_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_120MHz = 7, - kFlexSpiSerialClk_133MHz = 8, - kFlexSpiSerialClk_166MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/cdc/cdc_device.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/cdc/cdc_device.h index a2523d8d..f9692e20 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/cdc/cdc_device.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/cdc/cdc_device.h @@ -34,8 +34,13 @@ //--------------------------------------------------------------------+ // Class Driver Configuration //--------------------------------------------------------------------+ -#ifndef CFG_TUD_CDC_EPSIZE -#define CFG_TUD_CDC_EPSIZE 64 +#if !defined(CFG_TUD_CDC_EP_BUFSIZE) && defined(CFG_TUD_CDC_EPSIZE) + #warning CFG_TUD_CDC_EPSIZE is renamed to CFG_TUD_CDC_EP_BUFSIZE, please update to use the new name + #define CFG_TUD_CDC_EP_BUFSIZE CFG_TUD_CDC_EPSIZE +#endif + +#ifndef CFG_TUD_CDC_EP_BUFSIZE + #define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #endif #ifdef __cplusplus @@ -95,7 +100,7 @@ uint32_t tud_cdc_n_write_str (uint8_t itf, char const* str); // Force sending data if possible, return number of forced bytes uint32_t tud_cdc_n_write_flush (uint8_t itf); -// Return number of characters available for writing +// Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation. uint32_t tud_cdc_n_write_available (uint8_t itf); //--------------------------------------------------------------------+ @@ -128,6 +133,9 @@ TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf); // Invoked when received `wanted_char` TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char); +// Invoked when space becomes available in TX buffer +TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf); + // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts); diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/hid/hid_device.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/hid/hid_device.h index ad8c9ece..f7ad38ba 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/hid/hid_device.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/hid/hid_device.h @@ -39,8 +39,14 @@ // Class Driver Default Configure & Validation //--------------------------------------------------------------------+ -#ifndef CFG_TUD_HID_BUFSIZE -#define CFG_TUD_HID_BUFSIZE 16 +#if !defined(CFG_TUD_HID_EP_BUFSIZE) & defined(CFG_TUD_HID_BUFSIZE) + // TODO warn user to use new name later on + // #warning CFG_TUD_HID_BUFSIZE is renamed to CFG_TUD_HID_EP_BUFSIZE, please update to use the new name + #define CFG_TUD_HID_EP_BUFSIZE CFG_TUD_HID_BUFSIZE +#endif + +#ifndef CFG_TUD_HID_EP_BUFSIZE + #define CFG_TUD_HID_EP_BUFSIZE 16 #endif //--------------------------------------------------------------------+ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/midi/midi_device.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/midi/midi_device.h index bec0984f..1828a21a 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/midi/midi_device.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/midi/midi_device.h @@ -36,8 +36,14 @@ //--------------------------------------------------------------------+ // Class Driver Configuration //--------------------------------------------------------------------+ -#ifndef CFG_TUD_MIDI_EPSIZE -#define CFG_TUD_MIDI_EPSIZE 64 + +#if !defined(CFG_TUD_MIDI_EP_BUFSIZE) && defined(CFG_TUD_MIDI_EPSIZE) + #warning CFG_TUD_MIDI_EPSIZE is renamed to CFG_TUD_MIDI_EP_BUFSIZE, please update to use the new name + #define CFG_TUD_MIDI_EP_BUFSIZE CFG_TUD_MIDI_EPSIZE +#endif + +#ifndef CFG_TUD_MIDI_EP_BUFSIZE + #define CFG_TUD_MIDI_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #endif #ifdef __cplusplus diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/msc/msc_device.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/msc/msc_device.h index 30ffd02e..3aa93ffd 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/msc/msc_device.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/msc/msc_device.h @@ -38,12 +38,19 @@ //--------------------------------------------------------------------+ // Class Driver Configuration //--------------------------------------------------------------------+ -TU_VERIFY_STATIC(CFG_TUD_MSC_BUFSIZE < UINT16_MAX, "Size is not correct"); -#ifndef CFG_TUD_MSC_BUFSIZE - #error CFG_TUD_MSC_BUFSIZE must be defined, value of a block size should work well, the more the better +#if !defined(CFG_TUD_MSC_EP_BUFSIZE) & defined(CFG_TUD_MSC_BUFSIZE) + // TODO warn user to use new name later on + // #warning CFG_TUD_MSC_BUFSIZE is renamed to CFG_TUD_MSC_EP_BUFSIZE, please update to use the new name + #define CFG_TUD_MSC_EP_BUFSIZE CFG_TUD_MSC_BUFSIZE #endif +#ifndef CFG_TUD_MSC_EP_BUFSIZE + #error CFG_TUD_MSC_EP_BUFSIZE must be defined, value of a block size should work well, the more the better +#endif + +TU_VERIFY_STATIC(CFG_TUD_MSC_EP_BUFSIZE < UINT16_MAX, "Size is not correct"); + /** \addtogroup ClassDriver_MSC * @{ * \defgroup MSC_Device Device diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/net/net_device.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/net/net_device.h index fb72146b..0175ea56 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/net/net_device.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/class/net/net_device.h @@ -37,7 +37,7 @@ #include "netif/ethernet.h" /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */ -#define CFG_TUD_NET_ENDPOINT_SIZE ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 512 : 64) +#define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) /* Maximum Tranmission Unit (in bytes) of the network, including Ethernet header */ #define CFG_TUD_NET_MTU (1500 + SIZEOF_ETH_HDR) diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/common/tusb_common.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/common/tusb_common.h index 4b4183ae..d95c0ffc 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/common/tusb_common.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/common/tusb_common.h @@ -228,7 +228,6 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize) for(uint32_t i=0; icount; i++) { @@ -279,6 +278,7 @@ static inline char const* lookup_find(lookup_table_t const* p_table, uint32_t ke #define TU_LOG1_VAR(...) #define TU_LOG1_INT(...) #define TU_LOG1_HEX(...) + #define TU_LOG1_LOCATION() #define TU_LOG1_FAILED() #endif @@ -288,6 +288,7 @@ static inline char const* lookup_find(lookup_table_t const* p_table, uint32_t ke #define TU_LOG2_VAR(...) #define TU_LOG2_INT(...) #define TU_LOG2_HEX(...) + #define TU_LOG2_LOCATION() #endif #ifdef __cplusplus diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/dcd.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/dcd.h index 68798c25..a4635346 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/dcd.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/dcd.h @@ -60,11 +60,17 @@ typedef struct TU_ATTR_ALIGNED(4) uint8_t rhport; uint8_t event_id; - union { - // USBD_EVT_SETUP_RECEIVED + union + { + // BUS RESET + struct { + tusb_speed_t speed; + } bus_reset; + + // SETUP_RECEIVED tusb_control_request_t setup_received; - // USBD_EVT_XFER_COMPLETE + // XFER_COMPLETE struct { uint8_t ep_addr; uint8_t result; @@ -143,6 +149,9 @@ extern void dcd_event_handler(dcd_event_t const * event, bool in_isr); // helper to send bus signal event extern void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr); +// helper to send bus reset event +extern void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr); + // helper to send setup received extern void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr); diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd.h index e9b82747..5338be15 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd.h @@ -35,13 +35,14 @@ #endif #include "common/tusb_common.h" -#include "dcd.h" //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Init device stack +// Note: when using with RTOS, this should be called after scheduler/kernel is started. +// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. bool tud_init (void); // Task function should be called in main/rtos loop @@ -51,8 +52,12 @@ void tud_task (void); bool tud_task_event_ready(void); // Interrupt handler, name alias to DCD +extern void dcd_int_handler(uint8_t rhport); #define tud_int_handler dcd_int_handler +// Get current bus speed +tusb_speed_t tud_speed_get(void); + // Check if device is connected and configured bool tud_mounted(void); @@ -70,21 +75,11 @@ bool tud_remote_wakeup(void); // Enable pull-up resistor on D+ D- // Return false on unsupported MCUs -static inline bool tud_disconnect(void) -{ - TU_VERIFY(dcd_disconnect); - dcd_disconnect(TUD_OPT_RHPORT); - return true; -} +bool tud_disconnect(void); // Disable pull-up resistor on D+ D- // Return false on unsupported MCUs -static inline bool tud_connect(void) -{ - TU_VERIFY(dcd_connect); - dcd_connect(TUD_OPT_RHPORT); - return true; -} +bool tud_connect(void); // Carry out Data and Status stage of control transfer // - If len = 0, it is equivalent to sending status only diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd_pvt.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd_pvt.h index 48188ec9..a5d22332 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd_pvt.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/device/usbd_pvt.h @@ -33,6 +33,30 @@ extern "C" { #endif +//--------------------------------------------------------------------+ +// Class Drivers +//--------------------------------------------------------------------+ + +typedef struct +{ + #if CFG_TUSB_DEBUG >= 2 + char const* name; + #endif + + void (* init ) (void); + void (* reset ) (uint8_t rhport); + uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len); + bool (* control_request ) (uint8_t rhport, tusb_control_request_t const * request); + bool (* control_complete ) (uint8_t rhport, tusb_control_request_t const * request); + bool (* xfer_cb ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); + void (* sof ) (uint8_t rhport); /* optional */ +} usbd_class_driver_t; + +// Invoked when initializing device stack to get additional class drivers. +// Can optionally implemented by application to extend/overwrite class driver support. +// Note: The drivers array must be accessible at all time when stack is active +usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK; + //--------------------------------------------------------------------+ // USBD Endpoint API //--------------------------------------------------------------------+ diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/host/usbh.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/host/usbh.h index 42a2bd09..fe39a19f 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/host/usbh.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/host/usbh.h @@ -91,6 +91,9 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr); //--------------------------------------------------------------------+ // CLASS-USBH & INTERNAL API //--------------------------------------------------------------------+ + +// Note: when using with RTOS, this should be called after scheduler/kernel is started. +// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. bool usbh_init(void); bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data); diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/osal/osal_freertos.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/osal/osal_freertos.h index 416065ee..004bd1b6 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/osal/osal_freertos.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/osal/osal_freertos.h @@ -32,7 +32,6 @@ #include "semphr.h" #include "queue.h" #include "task.h" -#include "tusb_option.h" #ifdef __cplusplus extern "C" { @@ -59,19 +58,23 @@ static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semde static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { - if(!in_isr){ + if ( !in_isr ) + { return xSemaphoreGive(sem_hdl) != 0; } - BaseType_t xHigherPriorityTaskWoken; - BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); + else + { + BaseType_t xHigherPriorityTaskWoken; + BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); + #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 - if (xHigherPriorityTaskWoken) { - portYIELD_FROM_ISR(); - } + if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); #else - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); #endif - return res != 0; + + return res != 0; + } } static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) @@ -138,19 +141,23 @@ static inline bool osal_queue_receive(osal_queue_t qhdl, void* data) static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) { - if(!in_isr){ + if ( !in_isr ) + { return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0; } - BaseType_t xHigherPriorityTaskWoken; - BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); + else + { + BaseType_t xHigherPriorityTaskWoken; + BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); + #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 - if (xHigherPriorityTaskWoken) { - portYIELD_FROM_ISR(); - } + if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); #else - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); #endif - return res != 0; + + return res != 0; + } } static inline bool osal_queue_empty(osal_queue_t qhdl) diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb.h index defbc54f..c252a578 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb.h @@ -109,6 +109,8 @@ * @{ */ // Initialize device/host stack +// Note: when using with RTOS, this should be called after scheduler/kernel is started. +// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. bool tusb_init(void); // Check if stack is initialized diff --git a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb_option.h b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb_option.h index d54685e1..abf6450c 100644 --- a/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb_option.h +++ b/tools/sdk/esp32s2/include/tinyusb/tinyusb/src/tusb_option.h @@ -118,31 +118,35 @@ /** \addtogroup group_configuration * @{ */ + //-------------------------------------------------------------------- -// CONTROLLER -// Only 1 roothub port can be configured to be device and/or host. -// tinyusb does not support dual devices or dual host configuration +// RootHub Mode Configuration +// CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port //-------------------------------------------------------------------- -/** \defgroup group_mode Controller Mode Selection - * \brief CFG_TUSB_CONTROLLER_N_MODE must be defined with these - * @{ */ + +// Lower 4-bit is operational mode #define OPT_MODE_NONE 0x00 ///< Disabled #define OPT_MODE_DEVICE 0x01 ///< Device Mode #define OPT_MODE_HOST 0x02 ///< Host Mode -#define OPT_MODE_HIGH_SPEED 0x10 ///< High speed -/** @} */ + +// Higher 4-bit is max operational speed (corresponding to tusb_speed_t) +#define OPT_MODE_FULL_SPEED 0x00 ///< Max Full Speed +#define OPT_MODE_LOW_SPEED 0x10 ///< Max Low Speed +#define OPT_MODE_HIGH_SPEED 0x20 ///< Max High Speed + #ifndef CFG_TUSB_RHPORT0_MODE #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE #endif + #ifndef CFG_TUSB_RHPORT1_MODE #define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE #endif -#if ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)) || \ +#if ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST ) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST )) || \ ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)) - #error "tinyusb does not support same modes on more than 1 roothub port" + #error "TinyUSB currently does not support same modes on more than 1 roothub port" #endif // Which roothub port is configured as host @@ -160,7 +164,6 @@ #define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 ) - //--------------------------------------------------------------------+ // COMMON OPTIONS //--------------------------------------------------------------------+ @@ -172,15 +175,15 @@ // place data in accessible RAM for usb controller #ifndef CFG_TUSB_MEM_SECTION -#define CFG_TUSB_MEM_SECTION + #define CFG_TUSB_MEM_SECTION #endif #ifndef CFG_TUSB_MEM_ALIGN -#define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) + #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) #endif #ifndef CFG_TUSB_OS -#define CFG_TUSB_OS OPT_OS_NONE + #define CFG_TUSB_OS OPT_OS_NONE #endif //-------------------------------------------------------------------- @@ -188,7 +191,7 @@ //-------------------------------------------------------------------- #ifndef CFG_TUD_ENDPOINT0_SIZE - #define CFG_TUD_ENDPOINT0_SIZE 64 + #define CFG_TUD_ENDPOINT0_SIZE 64 #endif #ifndef CFG_TUD_CDC diff --git a/tools/sdk/esp32s2/include/ulp/include/esp32s2/ulp_riscv.h b/tools/sdk/esp32s2/include/ulp/include/esp32s2/ulp_riscv.h new file mode 100644 index 00000000..6b1682d3 --- /dev/null +++ b/tools/sdk/esp32s2/include/ulp/include/esp32s2/ulp_riscv.h @@ -0,0 +1,44 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include +#include +#include "esp_err.h" +#include "soc/soc.h" +#include "ulp_common.h" + +/** + * @brief Run the program loaded into RTC memory + * @return ESP_OK on success + */ +esp_err_t ulp_riscv_run(void); + +/** + * @brief Load ULP-RISC-V program binary into RTC memory + * + * Different than ULP FSM, the binary program has no special format, it is the ELF + * file generated by RISC-V toolchain converted to binary format using objcopy. + * + * Linker script in components/ulp/ld/esp32s2.ulp.riscv.ld produces ELF files which + * correspond to this format. This linker script produces binaries with load_addr == 0. + * + * @param program_binary pointer to program binary + * @param program_size_bytes size of the program binary + * @return + * - ESP_OK on success + * - ESP_ERR_INVALID_SIZE if program_size_bytes is more than 8KiB + */ +esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes); diff --git a/tools/sdk/esp32s2/include/vfs/include/esp_vfs.h b/tools/sdk/esp32s2/include/vfs/include/esp_vfs.h index 2fbdbba0..98180e57 100644 --- a/tools/sdk/esp32s2/include/vfs/include/esp_vfs.h +++ b/tools/sdk/esp32s2/include/vfs/include/esp_vfs.h @@ -259,12 +259,16 @@ typedef struct * Register a virtual filesystem for given path prefix. * * @param base_path file path prefix associated with the filesystem. - * Must be a zero-terminated C string, up to ESP_VFS_PATH_MAX + * Must be a zero-terminated C string, may be empty. + * If not empty, must be up to ESP_VFS_PATH_MAX * characters long, and at least 2 characters long. * Name must start with a "/" and must not end with "/". * For example, "/data" or "/dev/spi" are valid. * These VFSes would then be called to handle file paths such as * "/data/myfile.txt" or "/dev/spi/0". + * In the special case of an empty base_path, a "fallback" + * VFS is registered. Such VFS will handle paths which are not + * matched by any other registered VFS. * @param vfs Pointer to esp_vfs_t, a structure which maps syscalls to * the filesystem driver functions. VFS component doesn't * assume ownership of this pointer. diff --git a/tools/sdk/esp32s2/include/vfs/include/esp_vfs_cdcacm.h b/tools/sdk/esp32s2/include/vfs/include/esp_vfs_cdcacm.h new file mode 100644 index 00000000..b8dd03d9 --- /dev/null +++ b/tools/sdk/esp32s2/include/vfs/include/esp_vfs_cdcacm.h @@ -0,0 +1,66 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "esp_err.h" +#include "esp_vfs.h" +#include "esp_vfs_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief add /dev/cdcacm virtual filesystem driver + * + * This function is called from startup code to enable console output + */ +esp_err_t esp_vfs_dev_cdcacm_register(void); + +/** + * @brief Set the line endings expected to be received + * + * This specifies the conversion between line endings received and + * newlines ('\n', LF) passed into stdin: + * + * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF + * - ESP_LINE_ENDINGS_CR: convert CR to LF + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. reading + * + * @param mode line endings expected + */ +void esp_vfs_dev_cdcacm_set_rx_line_endings(esp_line_endings_t mode); + +/** + * @brief Set the line endings to sent + * + * This specifies the conversion between newlines ('\n', LF) on stdout and line + * endings sent: + * + * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF + * - ESP_LINE_ENDINGS_CR: convert LF to CR + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. writing + * + * @param mode line endings to send + */ +void esp_vfs_dev_cdcacm_set_tx_line_endings(esp_line_endings_t mode); + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/vfs/include/esp_vfs_common.h b/tools/sdk/esp32s2/include/vfs/include/esp_vfs_common.h new file mode 100644 index 00000000..2d7986a6 --- /dev/null +++ b/tools/sdk/esp32s2/include/vfs/include/esp_vfs_common.h @@ -0,0 +1,32 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Line ending settings + */ +typedef enum { + ESP_LINE_ENDINGS_CRLF,//!< CR + LF + ESP_LINE_ENDINGS_CR, //!< CR + ESP_LINE_ENDINGS_LF, //!< LF +} esp_line_endings_t; + +#ifdef __cplusplus +} +#endif diff --git a/tools/sdk/esp32s2/include/vfs/include/esp_vfs_dev.h b/tools/sdk/esp32s2/include/vfs/include/esp_vfs_dev.h index 95daaa61..30201784 100644 --- a/tools/sdk/esp32s2/include/vfs/include/esp_vfs_dev.h +++ b/tools/sdk/esp32s2/include/vfs/include/esp_vfs_dev.h @@ -15,20 +15,12 @@ #pragma once #include "esp_vfs.h" +#include "esp_vfs_common.h" #ifdef __cplusplus extern "C" { #endif -/** - * @brief Line ending settings - */ -typedef enum { - ESP_LINE_ENDINGS_CRLF,//!< CR + LF - ESP_LINE_ENDINGS_CR, //!< CR - ESP_LINE_ENDINGS_LF, //!< LF -} esp_line_endings_t; - /** * @brief add /dev/uart virtual filesystem driver * @@ -50,7 +42,7 @@ void esp_vfs_dev_uart_register(void); * * @param mode line endings expected on UART */ -void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode); +void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode) __attribute__((deprecated)); /** * @brief Set the line endings to sent to UART @@ -66,7 +58,45 @@ void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode); * * @param mode line endings to send to UART */ -void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode); +void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode) __attribute__((deprecated)); + +/** + * @brief Set the line endings expected to be received on specified UART + * + * This specifies the conversion between line endings received on UART and + * newlines ('\n', LF) passed into stdin: + * + * - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF + * - ESP_LINE_ENDINGS_CR: convert CR to LF + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. reading from UART + * + * @param uart_num the UART number + * @param mode line endings to send to UART + * @return 0 if successed, or -1 + * when an error (specified by errno) have occurred. + */ +int esp_vfs_dev_uart_port_set_rx_line_endings(int uart_num, esp_line_endings_t mode); + +/** + * @brief Set the line endings to sent to specified UART + * + * This specifies the conversion between newlines ('\n', LF) on stdout and line + * endings sent over UART: + * + * - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF + * - ESP_LINE_ENDINGS_CR: convert LF to CR + * - ESP_LINE_ENDINGS_LF: no modification + * + * @note this function is not thread safe w.r.t. writing to UART + * + * @param uart_num the UART number + * @param mode line endings to send to UART + * @return 0 if successed, or -1 + * when an error (specified by errno) have occurred. + */ +int esp_vfs_dev_uart_port_set_tx_line_endings(int uart_num, esp_line_endings_t mode); /** * @brief set VFS to use simple functions for reading and writing UART diff --git a/tools/sdk/esp32s2/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h b/tools/sdk/esp32s2/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h index 53156065..c6c2930a 100644 --- a/tools/sdk/esp32s2/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h +++ b/tools/sdk/esp32s2/include/wpa_supplicant/include/esp_supplicant/esp_wpa2.h @@ -19,6 +19,14 @@ #include "esp_err.h" +typedef enum { + ESP_EAP_TTLS_PHASE2_EAP, + ESP_EAP_TTLS_PHASE2_MSCHAPV2, + ESP_EAP_TTLS_PHASE2_MSCHAP, + ESP_EAP_TTLS_PHASE2_PAP, + ESP_EAP_TTLS_PHASE2_CHAP +} esp_eap_ttls_phase2_types ; + #ifdef __cplusplus extern "C" { #endif @@ -191,6 +199,16 @@ esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable); */ esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable); +/** + * @brief Set wpa2 enterprise ttls phase2 method + * + * @param type: the type of phase 2 method to be used + * + * @return + * - ESP_OK: succeed + */ +esp_err_t esp_wifi_sta_wpa2_ent_set_ttls_phase2_method(esp_eap_ttls_phase2_types type); + #ifdef __cplusplus } #endif diff --git a/tools/sdk/esp32s2/include/wpa_supplicant/port/include/os.h b/tools/sdk/esp32s2/include/wpa_supplicant/port/include/os.h index bff8b146..f39fc599 100644 --- a/tools/sdk/esp32s2/include/wpa_supplicant/port/include/os.h +++ b/tools/sdk/esp32s2/include/wpa_supplicant/port/include/os.h @@ -19,7 +19,6 @@ #include #include #include "esp_err.h" -// #include "esp32/rom/ets_sys.h" typedef time_t os_time_t; @@ -278,6 +277,9 @@ char * ets_strdup(const char *s); #ifndef os_strstr #define os_strstr(h, n) strstr((h), (n)) #endif +#ifndef os_strlcpy +#define os_strlcpy(d, s, n) strlcpy((d), (s), (n)) +#endif #ifndef os_snprintf #ifdef _MSC_VER @@ -291,16 +293,4 @@ static inline int os_snprintf_error(size_t size, int res) { return res < 0 || (unsigned int) res >= size; } - -/** - * os_strlcpy - Copy a string with size bound and NUL-termination - * @dest: Destination - * @src: Source - * @siz: Size of the target buffer - * Returns: Total length of the target string (length of src) (not including - * NUL-termination) - * - * This function matches in behavior with the strlcpy(3) function in OpenBSD. - */ -size_t os_strlcpy(char *dest, const char *src, size_t siz); #endif /* OS_H */ diff --git a/tools/sdk/esp32s2/include/wpa_supplicant/port/include/supplicant_opt.h b/tools/sdk/esp32s2/include/wpa_supplicant/port/include/supplicant_opt.h index f58692a1..a3d4c666 100644 --- a/tools/sdk/esp32s2/include/wpa_supplicant/port/include/supplicant_opt.h +++ b/tools/sdk/esp32s2/include/wpa_supplicant/port/include/supplicant_opt.h @@ -19,14 +19,13 @@ #if CONFIG_WPA_MBEDTLS_CRYPTO #define USE_MBEDTLS_CRYPTO 1 +#else +#define CONFIG_TLS_INTERNAL_CLIENT +#define CONFIG_TLSV12 #endif #if CONFIG_WPA_DEBUG_PRINT #define DEBUG_PRINT #endif -#if CONFIG_WPA_TLS_V12 -#define CONFIG_TLSV12 -#endif - #endif /* _SUPPLICANT_OPT_H */ diff --git a/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h b/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h index d267346b..2b59f16e 100644 --- a/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h +++ b/tools/sdk/esp32s2/include/xtensa/include/esp_attr.h @@ -32,9 +32,13 @@ // Forces data into IRAM instead of DRAM #define IRAM_DATA_ATTR __attribute__((section(".iram.data"))) +// Forces data into IRAM instead of DRAM and map it to coredump +#define COREDUMP_IRAM_DATA_ATTR _SECTION_ATTR_IMPL(".iram.data.coredump", __COUNTER__) + // Forces bss into IRAM instead of DRAM #define IRAM_BSS_ATTR __attribute__((section(".iram.bss"))) #else +#define COREDUMP_IRAM_DATA_ATTR #define IRAM_DATA_ATTR #define IRAM_BSS_ATTR @@ -50,7 +54,7 @@ #define FORCE_INLINE_ATTR static inline __attribute__((always_inline)) // Forces a string into DRAM instead of flash -// Use as ets_printf(DRAM_STR("Hello world!\n")); +// Use as esp_rom_printf(DRAM_STR("Hello world!\n")); #define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;})) // Forces code into RTC fast memory. See "docs/deep-sleep-stub.rst" @@ -85,6 +89,15 @@ // after restart or during a deep sleep / wake cycle. #define RTC_NOINIT_ATTR _SECTION_ATTR_IMPL(".rtc_noinit", __COUNTER__) +// Forces code into DRAM instead of flash and map it to coredump +#define COREDUMP_DRAM_ATTR _SECTION_ATTR_IMPL(".dram1.coredump", __COUNTER__) + +// Forces data into RTC memory and map it to coredump +#define COREDUMP_RTC_DATA_ATTR _SECTION_ATTR_IMPL(".rtc.coredump", __COUNTER__) + +// Allows to place data into RTC_FAST memory and map it to coredump +#define COREDUMP_RTC_FAST_ATTR _SECTION_ATTR_IMPL(".rtc.fast.coredump", __COUNTER__) + // Forces to not inline function #define NOINLINE_ATTR __attribute__((noinline)) diff --git a/tools/sdk/esp32s2/ld/esp32s2.ld b/tools/sdk/esp32s2/ld/esp32s2.ld index 87f4c9ba..2ae61149 100644 --- a/tools/sdk/esp32s2/ld/esp32s2.ld +++ b/tools/sdk/esp32s2/ld/esp32s2.ld @@ -34,7 +34,7 @@ #define RAM_IRAM_START 0x40020000 #define RAM_DRAM_START 0x3FFB0000 -#define DATA_RAM_END 0x3FFE4000 /* 2nd stage bootloader iram_loader_seg starts at block 15 */ +#define DATA_RAM_END 0x3FFE0000 /* 2nd stage bootloader iram_loader_seg starts at SRAM block 14 (reclaimed after app boots) */ #define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \ + CONFIG_ESP32S2_DATA_CACHE_SIZE) @@ -44,6 +44,17 @@ #define I_D_RAM_SIZE DATA_RAM_END - DRAM_ORG +#if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE) + +ASSERT((CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE <= I_D_RAM_SIZE), + "Fixed static ram data does not fit.") + +#define STATIC_RAM_SIZE CONFIG_ESP32S2_FIXED_STATIC_RAM_SIZE + +#else +#define STATIC_RAM_SIZE 0 +#endif + MEMORY { /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length @@ -69,7 +80,7 @@ MEMORY /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */ - dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE + dram0_0_seg (RW) : org = DRAM_ORG, len = I_D_RAM_SIZE - STATIC_RAM_SIZE #ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped constant data */ @@ -93,7 +104,12 @@ MEMORY rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC } +#if defined(CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE) +/* static data ends at defined address */ +_static_data_end = DRAM_ORG + STATIC_RAM_SIZE; +#else _static_data_end = _bss_end; +#endif _heap_end = 0x40000000; diff --git a/tools/sdk/esp32s2/ld/esp32s2.peripherals.ld b/tools/sdk/esp32s2/ld/esp32s2.peripherals.ld index 0c364f92..a35558a9 100644 --- a/tools/sdk/esp32s2/ld/esp32s2.peripherals.ld +++ b/tools/sdk/esp32s2/ld/esp32s2.peripherals.ld @@ -17,14 +17,14 @@ PROVIDE ( RMTMEM = 0x3f416400 ); PROVIDE ( PCNT = 0x3f417000 ); PROVIDE ( SLC = 0x3f418000 ); PROVIDE ( LEDC = 0x3f419000 ); -PROVIDE ( MCP = 0x3f4c3000 ); +PROVIDE ( CP_DMA = 0x3f4c3000 ); PROVIDE ( TIMERG0 = 0x3f41F000 ); PROVIDE ( TIMERG1 = 0x3f420000 ); PROVIDE ( GPSPI2 = 0x3f424000 ); PROVIDE ( GPSPI3 = 0x3f425000 ); PROVIDE ( SYSCON = 0x3f426000 ); PROVIDE ( I2C1 = 0x3f427000 ); -PROVIDE ( CAN = 0x3f42B000 ); +PROVIDE ( TWAI = 0x3f42B000 ); PROVIDE ( APB_SARADC = 0x3f440000 ); PROVIDE ( USB0 = 0x60080000 ); PROVIDE ( USB_WRAP = 0x3f439000 ); diff --git a/tools/sdk/esp32s2/ld/esp32s2.project.ld b/tools/sdk/esp32s2/ld/esp32s2.project.ld index e82604fb..5155ed50 100644 --- a/tools/sdk/esp32s2/ld/esp32s2.project.ld +++ b/tools/sdk/esp32s2/ld/esp32s2.project.ld @@ -43,6 +43,14 @@ SECTIONS { . = ALIGN(4); _rtc_force_fast_start = ABSOLUTE(.); + + _coredump_rtc_fast_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.fast.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.fast.coredump.*) + *libfreertos.a:queue.*( .rtc.fast.coredump.*) + *libfreertos.a:queue.*(.rtc.fast.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .rtc.fast.coredump .rtc.fast.coredump.*) + _coredump_rtc_fast_end = ABSOLUTE(.); + *(.rtc.force_fast .rtc.force_fast.*) . = ALIGN(4) ; _rtc_force_fast_end = ABSOLUTE(.); @@ -59,6 +67,15 @@ SECTIONS { _rtc_data_start = ABSOLUTE(.); + /* coredump mapping */ + _coredump_rtc_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.coredump.*) + *libfreertos.a:queue.*( .rtc.coredump.*) + *libfreertos.a:queue.*(.rtc.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .rtc.coredump .rtc.coredump.*) + _coredump_rtc_end = ABSOLUTE(.); + + /* should be placed after coredump mapping */ *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.data EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.data.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .rtc.rodata EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .rtc.rodata.*) *libfreertos.a:queue.*( .rtc.data.* .rtc.rodata.*) *libfreertos.a:queue.*(.rtc.data.xQueueGenericCreateStatic .rtc.rodata.xQueueGenericCreateStatic) @@ -177,14 +194,13 @@ SECTIONS *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.*( .literal .literal.* .text .text.*) *libapp_trace.a:app_trace.*( .literal .literal.* .text .text.*) *libapp_trace.a:app_trace_util.*( .literal .literal.* .text .text.*) - *libdriver.a:gpio.*(.literal.gpio_iomux_in .text.gpio_iomux_in) - *libdriver.a:gpio.*(.literal.gpio_iomux_out .text.gpio_iomux_out) *libesp_common.a:esp_err.*( .literal .literal.* .text .text.*) *libesp_event.a:default_event_loop.*(.literal.esp_event_isr_post .text.esp_event_isr_post) *libesp_event.a:esp_event.*(.literal.esp_event_isr_post_to .text.esp_event_isr_post_to) *libesp_ringbuf.a:( .literal .literal.* .text .text.*) *libesp_system.a:panic.*( .literal .literal.* .text .text.*) *libesp_system.a:panic_handler.*( .literal .literal.* .text .text.*) + *libesp_system.a:reset_reason.*( .literal .literal.* .text .text.*) *libesp_system.a:system_api.*(.literal.esp_system_abort .text.esp_system_abort) *libfreertos.a:( .literal EXCLUDE_FILE(*libfreertos.a:queue.*) .literal.* .text EXCLUDE_FILE(*libfreertos.a:queue.*) .text.*) *libfreertos.a:queue.*( .iram1.* .literal.prvIsQueueFull .literal.prvCopyDataToQueue .literal.prvNotifyQueueSetContainer .literal.prvCopyDataFromQueue .literal.xQueueGenericReset .literal.prvInitialiseNewQueue .literal.xQueueGenericCreate .literal.xQueueGetMutexHolder .literal.xQueueCreateCountingSemaphoreStatic .literal.xQueueCreateCountingSemaphore .literal.xQueueGenericSend .literal.prvInitialiseMutex .literal.xQueueCreateMutex .literal.xQueueCreateMutexStatic .literal.xQueueGiveMutexRecursive .literal.xQueueGenericSendFromISR .literal.xQueueGiveFromISR .literal.xQueueGenericReceive .literal.xQueueTakeMutexRecursive .literal.xQueueReceiveFromISR .literal.xQueuePeekFromISR .literal.uxQueueMessagesWaiting .literal.uxQueueSpacesAvailable .literal.uxQueueMessagesWaitingFromISR .literal.vQueueDelete .literal.xQueueIsQueueEmptyFromISR .literal.xQueueIsQueueFullFromISR .literal.vQueueWaitForMessageRestricted .literal.xQueueCreateSet .literal.xQueueAddToSet .literal.xQueueRemoveFromSet .literal.xQueueSelectFromSet .literal.xQueueSelectFromSetFromISR .text.prvIsQueueEmpty .text.prvIsQueueFull .text.prvCopyDataToQueue .text.prvNotifyQueueSetContainer .text.prvCopyDataFromQueue .text.xQueueGenericReset .text.prvInitialiseNewQueue .text.xQueueGenericCreate .text.xQueueGetMutexHolder .text.xQueueCreateCountingSemaphoreStatic .text.xQueueCreateCountingSemaphore .text.xQueueGenericSend .text.prvInitialiseMutex .text.xQueueCreateMutex .text.xQueueCreateMutexStatic .text.xQueueGiveMutexRecursive .text.xQueueGenericSendFromISR .text.xQueueGiveFromISR .text.xQueueGenericReceive .text.xQueueTakeMutexRecursive .text.xQueueReceiveFromISR .text.xQueuePeekFromISR .text.uxQueueMessagesWaiting .text.uxQueueSpacesAvailable .text.uxQueueMessagesWaitingFromISR .text.vQueueDelete .text.xQueueIsQueueEmptyFromISR .text.xQueueIsQueueFullFromISR .text.vQueueWaitForMessageRestricted .text.xQueueCreateSet .text.xQueueAddToSet .text.xQueueRemoveFromSet .text.xQueueSelectFromSet .text.xQueueSelectFromSetFromISR) @@ -211,8 +227,6 @@ SECTIONS *libsoc.a:ledc_hal_iram.*( .literal .literal.* .text .text.*) *libsoc.a:lldesc.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_clk.*( .literal .literal.* .text .text.*) - *libsoc.a:rtc_clk_init.*( .literal .literal.* .text .text.*) - *libsoc.a:rtc_init.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_periph.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_pm.*( .literal .literal.* .text .text.*) *libsoc.a:rtc_sleep.*( .literal .literal.* .text .text.*) @@ -226,6 +240,7 @@ SECTIONS *libsoc.a:systimer_hal.*( .literal .literal.* .text .text.*) *libsoc.a:uart_hal_iram.*( .iram1 .iram1.*) *libsoc.a:wdt_hal_iram.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_init.*(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config) *libspi_flash.a:memspi_host_driver.*( .literal .literal.* .text .text.*) *libspi_flash.a:spi_flash_chip_gd.*( .literal .literal.* .text .text.*) *libspi_flash.a:spi_flash_chip_generic.*( .literal .literal.* .text .text.*) @@ -235,6 +250,10 @@ SECTIONS *libxtensa.a:eri.*( .literal .literal.* .text .text.*) *libxtensa.a:stdatomic.*( .literal .literal.* .text .text.*) + /* added to maintain compability */ + _coredump_iram_start = 0; + _coredump_iram_end = 0; + /* align + add 16B for the possibly overlapping instructions */ . = ALIGN(4) + 16; _iram_text_end = ABSOLUTE(.); @@ -249,14 +268,6 @@ SECTIONS .dram0.data : { _data_start = ABSOLUTE(.); - _bt_data_start = ABSOLUTE(.); - *libbt.a:(.data .data.*) - . = ALIGN (4); - _bt_data_end = ABSOLUTE(.); - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); *(.gnu.linkonce.d.*) *(.data1) *(.sdata) @@ -267,6 +278,19 @@ SECTIONS *(.gnu.linkonce.s2.*) *(.jcr) + /* coredump mapping */ + _coredump_dram_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .dram1.coredump EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.coredump.*) + *libfreertos.a:queue.*( .dram1.coredump.*) + *libfreertos.a:queue.*(.dram1.coredump.xQueueGenericCreateStatic) + *libsoc.a:uart_hal_iram.*( .dram1.coredump .dram1.coredump.*) + _coredump_dram_end = ABSOLUTE(.); + + /* should be placed after coredump mapping */ + _esp_system_init_fn_array_start = ABSOLUTE(.); + KEEP (*(SORT(.esp_system_init_fn) SORT(.esp_system_init_fn.*))) + _esp_system_init_fn_array_end = ABSOLUTE(.); + *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .data EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .data.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .dram1 EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .dram1.*) *libapp_trace.a:SEGGER_RTT_esp32.*( .rodata .rodata.*) *libapp_trace.a:SEGGER_SYSVIEW.*( .rodata .rodata.*) @@ -274,13 +298,12 @@ SECTIONS *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.*( .rodata .rodata.*) *libapp_trace.a:app_trace.*( .rodata .rodata.*) *libapp_trace.a:app_trace_util.*( .rodata .rodata.*) - *libdriver.a:gpio.*(.rodata.gpio_iomux_in) - *libdriver.a:gpio.*(.rodata.gpio_iomux_out) *libesp_common.a:esp_err.*( .rodata .rodata.*) *libesp_event.a:default_event_loop.*(.rodata.esp_event_isr_post) *libesp_event.a:esp_event.*(.rodata.esp_event_isr_post_to) *libesp_system.a:panic.*( .rodata .rodata.*) *libesp_system.a:panic_handler.*( .rodata .rodata.*) + *libesp_system.a:reset_reason.*( .rodata .rodata.*) *libesp_system.a:system_api.*(.rodata.esp_system_abort) *libfreertos.a:queue.*( .data.* .dram1.*) *libfreertos.a:queue.*(.data.xQueueGenericCreateStatic .dram1.xQueueGenericCreateStatic) @@ -309,6 +332,7 @@ SECTIONS *libsoc.a:systimer_hal.*( .rodata .rodata.*) *libsoc.a:uart_hal_iram.*( .data .data.* .dram1 .dram1.*) *libsoc.a:wdt_hal_iram.*( .rodata .rodata.*) + *libsoc.a:rtc_init.*(.rodata.rtc_vddsdio_set_config) *libspi_flash.a:memspi_host_driver.*( .rodata .rodata.*) *libspi_flash.a:spi_flash_chip_gd.*( .rodata .rodata.*) *libspi_flash.a:spi_flash_chip_generic.*( .rodata .rodata.*) @@ -341,14 +365,6 @@ SECTIONS . = ALIGN (8); _bss_start = ABSOLUTE(.); *(.ext_ram.bss*) - _bt_bss_start = ABSOLUTE(.); - *libbt.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _bt_bss_end = ABSOLUTE(.); - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); *(EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .bss EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .bss.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) COMMON) *libfreertos.a:queue.*( .bss.*) @@ -369,8 +385,6 @@ SECTIONS . = ALIGN (8); _bss_end = ABSOLUTE(.); - /* The heap starts right after end of this section */ - _heap_start = ABSOLUTE(.); } > dram0_0_seg /* When modifying the alignment, update tls_section_alignment in pxPortInitialiseStack */ @@ -382,15 +396,15 @@ SECTIONS *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:ledc_hal_iram.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *liblog.a:log_freertos.* *liblog.a:log.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:ledc_hal_iram.* *libdriver.a:gpio.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libfreertos.a:queue.* *libphy.a) .rodata.*) - *libdriver.a:gpio.*(.rodata.gpio_input_enable.str1.4 .rodata.gpio_output_enable.str1.4 .rodata.gpio_set_intr_type.str1.4 .rodata.gpio_set_pull_mode.str1.4 .rodata.gpio_set_direction.str1.4 .rodata.gpio_config.str1.4 .rodata.gpio_reset_pin.str1.4 .rodata.gpio_isr_handler_add.str1.4 .rodata.gpio_isr_register.str1.4 .rodata.gpio_install_isr_service.str1.4 .rodata.gpio_wakeup_enable.str1.4 .rodata.gpio_set_drive_capability.str1.4 .rodata.gpio_get_drive_capability.str1.4 .rodata.gpio_hold_en.str1.4 .rodata.__FUNCTION__$7299 .rodata.__FUNCTION__$7294 .rodata.__FUNCTION__$7289 .rodata.__FUNCTION__$7283 .rodata.__FUNCTION__$7277 .rodata.__FUNCTION__$7272 .rodata.__FUNCTION__$7265 .rodata.__FUNCTION__$7250 .rodata.__FUNCTION__$7246 .rodata.__FUNCTION__$7239 .rodata.__func__$7220 .rodata.__FUNCTION__$7173 .rodata.__FUNCTION__$7177 .rodata.__FUNCTION__$7165 .rodata.__FUNCTION__$7169 .rodata.__FUNCTION__$7157 .rodata.__FUNCTION__$7161 .rodata.__FUNCTION__$7202 .rodata.__FUNCTION__$7190 .rodata.__FUNCTION__$7182 .rodata.__FUNCTION__$7153 .rodata.__FUNCTION__$7145 .rodata.__FUNCTION__$7149 .rodata.__FUNCTION__$7140 .rodata.__FUNCTION__$7135 .rodata.__FUNCTION__$7131 .rodata.__FUNCTION__$7127 .rodata.__FUNCTION__$7123) + *(EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:spi_hal_iram.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libphy.a) .rodata EXCLUDE_FILE(*libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log_freertos.* *liblog.a:log.* *libesp_event.a:esp_event.* *libesp_event.a:default_event_loop.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:spi_hal_iram.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libfreertos.a:queue.* *libphy.a) .rodata.*) *libesp_event.a:default_event_loop.*(.rodata.esp_event_loop_create_default.str1.4 .rodata.esp_event_send_to_default_loop) - *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$9784 .rodata.__func__$9771 .rodata.__func__$9738 .rodata.__func__$9706 .rodata.__func__$9681 .rodata.__func__$9640 .rodata.__func__$9631) + *libesp_event.a:esp_event.*(.rodata.base_node_add_handler.str1.4 .rodata.loop_node_add_handler.str1.4 .rodata.esp_event_loop_create.str1.4 .rodata.esp_event_loop_run.str1.4 .rodata.esp_event_loop_run_task.str1.4 .rodata.esp_event_handler_register_with_internal.str1.4 .rodata.esp_event_handler_unregister_with_internal.str1.4 .rodata.__func__$9830 .rodata.__func__$9817 .rodata.__func__$9784 .rodata.__func__$9752 .rodata.__func__$9727 .rodata.__func__$9686 .rodata.__func__$9677) *libesp_system.a:system_api.*(.rodata.esp_get_idf_version.str1.4) - *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.xQueueGenericReset.str1.4 .rodata.__FUNCTION__$5259 .rodata.__FUNCTION__$5249 .rodata.__FUNCTION__$5229 .rodata.__FUNCTION__$5224 .rodata.__FUNCTION__$5218 .rodata.__FUNCTION__$5212 .rodata.__FUNCTION__$5206 .rodata.__FUNCTION__$5197 .rodata.__FUNCTION__$5187 .rodata.__FUNCTION__$5176 .rodata.__FUNCTION__$5168 .rodata.__FUNCTION__$5295 .rodata.__FUNCTION__$5157 .rodata.__FUNCTION__$5146 .rodata.__FUNCTION__$5140 .rodata.__FUNCTION__$5133 .rodata.__FUNCTION__$5126 .rodata.__FUNCTION__$5092 .rodata.__FUNCTION__$5082 .rodata.__func__$4285 .rodata.__FUNCTION__$5073) + *libfreertos.a:queue.*(.rodata.prvNotifyQueueSetContainer.str1.4 .rodata.xQueueGenericReset.str1.4 .rodata.__FUNCTION__$5270 .rodata.__FUNCTION__$5260 .rodata.__FUNCTION__$5240 .rodata.__FUNCTION__$5235 .rodata.__FUNCTION__$5229 .rodata.__FUNCTION__$5223 .rodata.__FUNCTION__$5217 .rodata.__FUNCTION__$5208 .rodata.__FUNCTION__$5198 .rodata.__FUNCTION__$5187 .rodata.__FUNCTION__$5179 .rodata.__FUNCTION__$5306 .rodata.__FUNCTION__$5168 .rodata.__FUNCTION__$5157 .rodata.__FUNCTION__$5151 .rodata.__FUNCTION__$5144 .rodata.__FUNCTION__$5137 .rodata.__FUNCTION__$5103 .rodata.__FUNCTION__$5093 .rodata.__func__$4295 .rodata.__FUNCTION__$5084) *libfreertos.a:queue.*(.rodata.xQueueGenericCreateStatic) - *liblog.a:log.*(.rodata.esp_log_level_set.str1.4 .rodata.__func__$3532 .rodata.__func__$3503) + *liblog.a:log.*(.rodata.esp_log_level_set.str1.4 .rodata.__func__$3542 .rodata.__func__$3513) *liblog.a:log_freertos.*(.rodata.esp_log_system_timestamp.str1.4) + *libsoc.a:rtc_init.*( .rodata.*) *libsoc.a:uart_hal_iram.*( .rodata .rodata.*) *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ @@ -453,15 +467,15 @@ SECTIONS _instruction_reserved_start = ABSOLUTE(.); _text_start = ABSOLUTE(.); - *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:systimer_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:rtc_wdt.* *libsoc.a:soc_hal.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:systimer_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:rtc_wdt.* *libsoc.a:soc_hal.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libdriver.a:gpio.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:systimer_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:rtc_wdt.* *libsoc.a:soc_hal.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:app_trace_util.* *libapp_trace.a:app_trace.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_generic.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_gd.* *libsoc.a:wdt_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:rtc_time.* *libsoc.a:systimer_hal.* *libsoc.a:cpu_hal.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:uart_hal_iram.* *libsoc.a:rtc_wdt.* *libsoc.a:soc_hal.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:rtc_init.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libsoc.a:ledc_hal_iram.* *libdriver.a:gpio.* *libxtensa.a:eri.* *libxtensa.a:stdatomic.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libsoc.a:uart_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifirxiram.*) - *libdriver.a:gpio.*(.literal.gpio_input_enable .literal.gpio_input_disable .literal.gpio_output_disable .literal.gpio_od_enable .literal.gpio_od_disable .literal.gpio_intr_enable_on_core .literal.gpio_output_enable .literal.gpio_isr_register_on_core_static .literal.gpio_pullup_en .literal.gpio_pullup_dis .literal.gpio_pulldown_en .literal.gpio_pulldown_dis .literal.gpio_set_intr_type .literal.gpio_intr_enable .literal.gpio_intr_disable .literal.gpio_set_level .literal.gpio_get_level .literal.gpio_set_pull_mode .literal.gpio_set_direction .literal.gpio_config .literal.gpio_reset_pin .literal.gpio_isr_handler_add .literal.gpio_isr_handler_remove .literal.gpio_uninstall_isr_service .literal.gpio_isr_register .literal.gpio_install_isr_service .literal.gpio_wakeup_enable .literal.gpio_wakeup_disable .literal.gpio_set_drive_capability .literal.gpio_get_drive_capability .literal.gpio_hold_en .literal.gpio_hold_dis .literal.gpio_deep_sleep_hold_en .literal.gpio_deep_sleep_hold_dis .literal.gpio_force_hold_all .literal.gpio_force_unhold_all .text.gpio_input_enable .text.gpio_input_disable .text.gpio_output_disable .text.gpio_od_enable .text.gpio_od_disable .text.gpio_intr_enable_on_core .text.gpio_output_enable .text.gpio_isr_register_on_core_static .text.gpio_pullup_en .text.gpio_pullup_dis .text.gpio_pulldown_en .text.gpio_pulldown_dis .text.gpio_set_intr_type .text.gpio_intr_enable .text.gpio_intr_disable .text.gpio_set_level .text.gpio_get_level .text.gpio_set_pull_mode .text.gpio_set_direction .text.gpio_config .text.gpio_reset_pin .text.gpio_isr_handler_add .text.gpio_isr_handler_remove .text.gpio_uninstall_isr_service .text.gpio_isr_register .text.gpio_install_isr_service .text.gpio_wakeup_enable .text.gpio_wakeup_disable .text.gpio_set_drive_capability .text.gpio_get_drive_capability .text.gpio_hold_en .text.gpio_hold_dis .text.gpio_deep_sleep_hold_en .text.gpio_deep_sleep_hold_dis .text.gpio_force_hold_all .text.gpio_force_unhold_all) + *(EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .literal.* EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *libgcc.a:lib2funcs.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text EXCLUDE_FILE(*libesp_ringbuf.a *libgcov.a *libapp_trace.a:SEGGER_RTT_esp32.* *libapp_trace.a:SEGGER_SYSVIEW_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW_Config_FreeRTOS.* *libapp_trace.a:SEGGER_SYSVIEW.* *libapp_trace.a:app_trace.* *libapp_trace.a:app_trace_util.* *liblog.a:log.* *liblog.a:log_freertos.* *libgcc.a:lib2funcs.* *libesp_event.a:default_event_loop.* *libesp_event.a:esp_event.* *librtc.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.* *libesp_system.a:system_api.* *libesp_system.a:panic_handler.* *libesp_system.a:reset_reason.* *libesp_system.a:panic.* *libesp_common.a:esp_err.* *libspi_flash.a:spi_flash_chip_mxic.* *libspi_flash.a:spi_flash_chip_issi.* *libspi_flash.a:spi_flash_rom_patch.* *libspi_flash.a:spi_flash_chip_gd.* *libspi_flash.a:memspi_host_driver.* *libspi_flash.a:spi_flash_chip_generic.* *libsoc.a:rtc_init.* *libsoc.a:ledc_hal_iram.* *libsoc.a:spi_flash_hal_iram.* *libsoc.a:cpu_hal.* *libsoc.a:wdt_hal_iram.* *libsoc.a:cpu_util.* *libsoc.a:uart_hal_iram.* *libsoc.a:i2c_hal_iram.* *libsoc.a:soc_hal.* *libsoc.a:spi_flash_hal_gpspi.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_clk.* *libsoc.a:spi_slave_hal_iram.* *libsoc.a:lldesc.* *libsoc.a:systimer_hal.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_time.* *libsoc.a:spi_hal_iram.* *libsoc.a:rtc_periph.* *libxtensa.a:stdatomic.* *libxtensa.a:eri.* *libnewlib.a:heap.* *libnewlib.a:abort.* *libhal.a *libfreertos.a) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a *libsoc.a:uart_hal_iram.*) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a *libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifi0iram.* EXCLUDE_FILE(*libsoc.a:uart_hal_iram.*) .wifirxiram EXCLUDE_FILE(*libsoc.a:uart_hal_iram.* *libfreertos.a:queue.*) .wifirxiram.*) *libesp_event.a:default_event_loop.*(.literal.esp_event_handler_register .literal.esp_event_handler_instance_register .literal.esp_event_handler_unregister .literal.esp_event_handler_instance_unregister .literal.esp_event_post .literal.esp_event_loop_create_default .literal.esp_event_loop_delete_default .literal.esp_event_send_to_default_loop .text.esp_event_handler_register .text.esp_event_handler_instance_register .text.esp_event_handler_unregister .text.esp_event_handler_instance_unregister .text.esp_event_post .text.esp_event_loop_create_default .text.esp_event_loop_delete_default .text.esp_event_send_to_default_loop) *libesp_event.a:esp_event.*(.literal.handler_instances_remove_all .literal.base_node_remove_all_handler .literal.loop_node_remove_all_handler .literal.handler_instances_add .literal.base_node_add_handler .literal.loop_node_add_handler .literal.handler_instances_remove .literal.base_node_remove_handler .literal.loop_node_remove_handler .literal.esp_event_loop_create .literal.esp_event_loop_run .literal.esp_event_loop_run_task .literal.esp_event_loop_delete .literal.esp_event_handler_register_with_internal .literal.esp_event_handler_register_with .literal.esp_event_handler_instance_register_with .literal.esp_event_handler_unregister_with_internal .literal.esp_event_handler_unregister_with .literal.esp_event_handler_instance_unregister_with .literal.esp_event_post_to .text.handler_execute .text.handler_instances_remove_all .text.base_node_remove_all_handler .text.loop_node_remove_all_handler .text.handler_instances_add .text.base_node_add_handler .text.loop_node_add_handler .text.handler_instances_remove .text.base_node_remove_handler .text.loop_node_remove_handler .text.esp_event_loop_create .text.esp_event_loop_run .text.esp_event_loop_run_task .text.esp_event_loop_delete .text.esp_event_handler_register_with_internal .text.esp_event_handler_register_with .text.esp_event_handler_instance_register_with .text.esp_event_handler_unregister_with_internal .text.esp_event_handler_unregister_with .text.esp_event_handler_instance_unregister_with .text.esp_event_post_to .text.esp_event_dump) - *libesp_system.a:system_api.*(.literal.esp_register_shutdown_handler .literal.esp_unregister_shutdown_handler .literal.esp_get_free_heap_size .literal.esp_get_minimum_free_heap_size .literal.esp_get_idf_version .text.esp_register_shutdown_handler .text.esp_unregister_shutdown_handler .text.esp_get_free_heap_size .text.esp_get_minimum_free_heap_size .text.esp_get_idf_version) + *libesp_system.a:system_api.*(.literal.esp_register_shutdown_handler .literal.esp_unregister_shutdown_handler .literal.esp_get_free_heap_size .literal.esp_get_free_internal_heap_size .literal.esp_get_minimum_free_heap_size .literal.esp_get_idf_version .text.esp_register_shutdown_handler .text.esp_unregister_shutdown_handler .text.esp_get_free_heap_size .text.esp_get_free_internal_heap_size .text.esp_get_minimum_free_heap_size .text.esp_get_idf_version) *libfreertos.a:queue.*( .wifi0iram.* .wifirxiram.*) *libfreertos.a:queue.*(.literal.xQueueGenericCreateStatic .text.xQueueGenericCreateStatic .wifi0iram.xQueueGenericCreateStatic .wifirxiram.xQueueGenericCreateStatic) *liblog.a:log.*(.literal.heap_bubble_down .literal.esp_log_set_vprintf .literal.esp_log_level_set .literal.esp_log_writev .text.heap_bubble_down .text.esp_log_set_vprintf .text.esp_log_level_set .text.esp_log_writev) *liblog.a:log_freertos.*(.literal.esp_log_system_timestamp .text.esp_log_system_timestamp) + *libsoc.a:rtc_init.*(.literal.rtc_init .literal.rtc_vddsdio_get_config .text.rtc_init .text.rtc_vddsdio_get_config) *libsoc.a:uart_hal_iram.*( .literal .literal.* .text .text.* .wifi0iram .wifi0iram.* .wifirxiram .wifirxiram.*) *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) diff --git a/tools/sdk/esp32s2/ld/esp32s2.rom.api.ld b/tools/sdk/esp32s2/ld/esp32s2.rom.api.ld new file mode 100644 index 00000000..c96a54fe --- /dev/null +++ b/tools/sdk/esp32s2/ld/esp32s2.rom.api.ld @@ -0,0 +1,37 @@ +/** + * ROM APIs + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig ); +PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */ +/* so here we directly assign the symbols with the ROM API address */ +PROVIDE ( esp_rom_md5_init = 0x4000526c ); +PROVIDE ( esp_rom_md5_update = 0x4000528c ); +PROVIDE ( esp_rom_md5_final = 0x4000530c ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); diff --git a/tools/sdk/esp32s2/ld/esp32s2.rom.ld b/tools/sdk/esp32s2/ld/esp32s2.rom.ld index 5583e5c1..445d033b 100644 --- a/tools/sdk/esp32s2/ld/esp32s2.rom.ld +++ b/tools/sdk/esp32s2/ld/esp32s2.rom.ld @@ -570,6 +570,11 @@ PROVIDE ( rom_txiq_set_reg = 0x4000bf64 ); PROVIDE ( rom_tx_paon_set = 0x40009db8 ); PROVIDE ( rom_tx_pwr_backoff = 0x4000ceb8 ); PROVIDE ( rom_txtone_linear_pwr = 0x4000c0b0 ); +PROVIDE ( rom_usb_dev = 0x3ffffb9c ); /* static "usb_dev" */ +PROVIDE ( rom_usb_dev_end = 0x3ffffc78 ); /* end of "usb_dev" */ +PROVIDE ( rom_usb_dw_ctrl = 0x3ffffa74 ); /* static "usb_dw_ctrl" */ +PROVIDE ( rom_usb_dw_ctrl_end = 0x3ffffb9c ); /* end of "usb_dw_ctrl" */ +PROVIDE ( rom_usb_curr_desc = 0x3ffffa54 ); /* static "s_curr_descr" */ PROVIDE ( rom_wait_rfpll_cal_end = 0x4000af3c ); PROVIDE ( rom_wifi_11g_rate_chg = 0x4000d260 ); PROVIDE ( rom_wifi_rifs_mode_en = 0x40009d2c ); @@ -646,7 +651,7 @@ PROVIDE ( string0_descr = 0x3ffaeeae ); PROVIDE ( str_manu_descr = 0x3ffaee9a ); PROVIDE ( str_prod_descr = 0x3ffaee88 ); PROVIDE ( str_serial_descr = 0x3ffaee84 ); -PROVIDE ( s_usb_osglue = 0x3ffffcdc ); +PROVIDE ( rom_usb_osglue = 0x3ffffcdc ); PROVIDE ( _SyscallException = 0x4000732a ); PROVIDE ( syscall_table_ptr_pro = 0x3ffffd78 ); PROVIDE ( tdefl_compress = 0x400041dc ); diff --git a/tools/sdk/esp32s2/ld/esp32s2_out.ld b/tools/sdk/esp32s2/ld/esp32s2_out.ld index 7d6e5ec6..b9acc20c 100644 --- a/tools/sdk/esp32s2/ld/esp32s2_out.ld +++ b/tools/sdk/esp32s2/ld/esp32s2_out.ld @@ -19,7 +19,7 @@ MEMORY of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but are connected to the data port of the CPU and eg allow bytewise access. */ /* IRAM for CPU.*/ - iram0_0_seg (RX) : org = (0x40020000 + 0x2000 + 0x2000), len = 0x3FFE4000 - (0x3FFB0000 + 0x2000 + 0x2000) + iram0_0_seg (RX) : org = (0x40020000 + 0x2000 + 0x2000), len = 0x3FFE0000 - (0x3FFB0000 + 0x2000 + 0x2000) /* Even though the segment name is iram, it is actually mapped to flash */ iram0_2_seg (RX) : org = 0x40080020, len = 0x780000-0x20 @@ -31,7 +31,7 @@ MEMORY constraint that (paddr % 64KB == vaddr % 64KB).) */ /* Shared data RAM, excluding memory reserved for bootloader and ROM bss/data/stack. */ - dram0_0_seg (RW) : org = (0x3FFB0000 + 0x2000 + 0x2000), len = 0x3FFE4000 - (0x3FFB0000 + 0x2000 + 0x2000) + dram0_0_seg (RW) : org = (0x3FFB0000 + 0x2000 + 0x2000), len = 0x3FFE0000 - (0x3FFB0000 + 0x2000 + 0x2000) - 0 /* Flash mapped constant data */ drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20 /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ diff --git a/tools/sdk/esp32s2/lib/libapp_trace.a b/tools/sdk/esp32s2/lib/libapp_trace.a index 0b1e2899..240df991 100644 Binary files a/tools/sdk/esp32s2/lib/libapp_trace.a and b/tools/sdk/esp32s2/lib/libapp_trace.a differ diff --git a/tools/sdk/esp32s2/lib/libapp_update.a b/tools/sdk/esp32s2/lib/libapp_update.a index 5d1de6f4..2c21bd8e 100644 Binary files a/tools/sdk/esp32s2/lib/libapp_update.a and b/tools/sdk/esp32s2/lib/libapp_update.a differ diff --git a/tools/sdk/esp32s2/lib/libasio.a b/tools/sdk/esp32s2/lib/libasio.a index 48fb57db..bd0c298f 100644 Binary files a/tools/sdk/esp32s2/lib/libasio.a and b/tools/sdk/esp32s2/lib/libasio.a differ diff --git a/tools/sdk/esp32s2/lib/libbootloader_support.a b/tools/sdk/esp32s2/lib/libbootloader_support.a index 7d008ea6..44ea7076 100644 Binary files a/tools/sdk/esp32s2/lib/libbootloader_support.a and b/tools/sdk/esp32s2/lib/libbootloader_support.a differ diff --git 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+37,7 @@ CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 # # Bootloader config # +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set # CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set @@ -48,7 +49,6 @@ CONFIG_BOOTLOADER_LOG_LEVEL_NONE=y # CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set # CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set CONFIG_BOOTLOADER_LOG_LEVEL=0 -CONFIG_BOOTLOADER_SPI_WP_PIN=7 CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y # CONFIG_BOOTLOADER_FACTORY_RESET is not set # CONFIG_BOOTLOADER_APP_TEST is not set @@ -64,6 +64,7 @@ CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 # # Security features # +CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set # CONFIG_SECURE_BOOT is not set # CONFIG_SECURE_FLASH_ENC_ENABLED is not set @@ -75,7 +76,7 @@ CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0x10 # Serial flasher config # CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 -CONFIG_ESPTOOLPY_WITH_STUB=y +# CONFIG_ESPTOOLPY_NO_STUB is not set CONFIG_ESPTOOLPY_FLASHMODE_QIO=y # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set # CONFIG_ESPTOOLPY_FLASHMODE_DIO is not set @@ -99,6 +100,7 @@ CONFIG_ESPTOOLPY_BEFORE="default_reset" CONFIG_ESPTOOLPY_AFTER_RESET=y # CONFIG_ESPTOOLPY_AFTER_NORESET is not set CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set # CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set # CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y @@ -200,7 +202,15 @@ CONFIG_APPTRACE_DEST_NONE=y CONFIG_APPTRACE_LOCK_ENABLE=y # end of Application Level Tracing +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 +CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 +CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 @@ -264,9 +274,9 @@ CONFIG_ESP_TLS_SERVER=y # ESP32S2-specific # # CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 is not set -CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160=y -# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 is not set -CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=160 +# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160 is not set +CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240=y +CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=240 # # Memory protection @@ -310,7 +320,6 @@ CONFIG_DEFAULT_PSRAM_CS_IO=26 # CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set # CONFIG_SPIRAM_RODATA is not set -# CONFIG_SPIRAM_USE_AHB_DBUS3 is not set CONFIG_SPIRAM_SPEED_80M=y # CONFIG_SPIRAM_SPEED_40M is not set # CONFIG_SPIRAM_SPEED_26M is not set @@ -354,7 +363,9 @@ CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y # CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 # CONFIG_ESP32S2_NO_BLOBS is not set +CONFIG_ESP32S2_KEEP_USB_ALIVE=y # CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set # end of ESP32S2-specific # @@ -363,6 +374,11 @@ CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 # CONFIG_PM_ENABLE is not set # end of Power Management +# +# ADC-Calibration +# +# end of ADC-Calibration + # # Common ESP-related # @@ -374,10 +390,9 @@ CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 CONFIG_ESP_CONSOLE_UART_DEFAULT=y # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set -# CONFIG_ESP_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_UART=y CONFIG_ESP_CONSOLE_UART_NUM=0 -CONFIG_ESP_CONSOLE_UART_TX_GPIO=43 -CONFIG_ESP_CONSOLE_UART_RX_GPIO=44 CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 CONFIG_ESP_INT_WDT=y CONFIG_ESP_INT_WDT_TIMEOUT_MS=1000 @@ -385,6 +400,7 @@ CONFIG_ESP_TASK_WDT=y CONFIG_ESP_TASK_WDT_PANIC=y CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 # CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y # end of Common ESP-related @@ -457,6 +473,7 @@ CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y # end of ESP System Settings # @@ -475,6 +492,7 @@ CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32 # CONFIG_ESP32_WIFI_CSI_ENABLED is not set CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y CONFIG_ESP32_WIFI_TX_BA_WIN=6 @@ -547,16 +565,20 @@ CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y # # Modbus configuration # +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 CONFIG_FMB_COMM_MODE_RTU_EN=y CONFIG_FMB_COMM_MODE_ASCII_EN=y CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 CONFIG_FMB_QUEUE_LENGTH=20 -CONFIG_FMB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 CONFIG_FMB_SERIAL_BUF_SIZE=256 CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 -CONFIG_FMB_SERIAL_TASK_PRIO=10 +CONFIG_FMB_PORT_TASK_PRIO=10 # CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT is not set CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 @@ -661,8 +683,10 @@ CONFIG_LWIP_SO_REUSE=y CONFIG_LWIP_SO_REUSE_RXTOALL=y CONFIG_LWIP_SO_RCVBUF=y # CONFIG_LWIP_NETBUF_RECVINFO is not set -# CONFIG_LWIP_IP_FRAG is not set -# CONFIG_LWIP_IP_REASSEMBLY is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set # CONFIG_LWIP_IP_FORWARD is not set # CONFIG_LWIP_STATS is not set CONFIG_LWIP_ETHARP_TRUST_IP_MAC=y @@ -704,6 +728,7 @@ CONFIG_LWIP_TCP_OVERSIZE_MSS=y # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set # CONFIG_LWIP_WND_SCALE is not set +CONFIG_LWIP_TCP_RTO_TIME=3000 # end of TCP # @@ -719,12 +744,15 @@ CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0=y CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x0 CONFIG_LWIP_PPP_SUPPORT=y CONFIG_LWIP_PPP_ENABLE_IPV6=y +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 # CONFIG_LWIP_PPP_NOTIFY_PHASE_SUPPORT is not set CONFIG_LWIP_PPP_PAP_SUPPORT=y CONFIG_LWIP_PPP_CHAP_SUPPORT=y CONFIG_LWIP_PPP_MSCHAP_SUPPORT=y CONFIG_LWIP_PPP_MPPE_SUPPORT=y # CONFIG_LWIP_PPP_DEBUG_ON is not set +# CONFIG_LWIP_SLIP_SUPPORT is not set # # ICMP @@ -747,6 +775,20 @@ CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 # end of SNTP CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Debug +# +# CONFIG_LWIP_NETIF_DEBUG is not set +# CONFIG_LWIP_PBUF_DEBUG is not set +# CONFIG_LWIP_ETHARP_DEBUG is not set +# CONFIG_LWIP_API_LIB_DEBUG is not set +# CONFIG_LWIP_SOCKETS_DEBUG is not set +# CONFIG_LWIP_IP_DEBUG is not set +# CONFIG_LWIP_ICMP_DEBUG is not set +# CONFIG_LWIP_IP6_DEBUG is not set +# CONFIG_LWIP_ICMP6_DEBUG is not set +# end of Debug # end of LWIP # @@ -914,6 +956,7 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y # OpenSSL # # CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y CONFIG_OPENSSL_ASSERT_DO_NOTHING=y # CONFIG_OPENSSL_ASSERT_EXIT is not set # end of OpenSSL @@ -942,6 +985,7 @@ CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 # # Auto-detect flash chips @@ -988,45 +1032,77 @@ CONFIG_SPIFFS_USE_MTIME=y # end of Debug Configuration # end of SPIFFS Configuration +# +# TCP Transport +# +CONFIG_WS_BUFFER_SIZE=1024 +# end of TCP Transport + # # TinyUSB # CONFIG_USB_ENABLED=y -CONFIG_USB_MAX_POWER_USAGE=100 -# CONFIG_USB_USE_BUILTIN_DESCRIPTORS is not set -CONFIG_USB_DYNAMIC_DRIVER_LOADING=y -CONFIG_USB_DYNAMIC_DRIVER_MAX=16 -CONFIG_USB_CDC_ENABLED=y -CONFIG_USB_CDC_RX_BUFSIZE=64 -CONFIG_USB_CDC_TX_BUFSIZE=64 -CONFIG_USB_DFU_RT_ENABLED=y -CONFIG_USB_MSC_ENABLED=y -CONFIG_USB_MSC_BUFSIZE=512 -CONFIG_USB_HID_ENABLED=y -CONFIG_USB_HID_BUFSIZE=16 -CONFIG_USB_MIDI_ENABLED=y -CONFIG_USB_MIDI_RX_BUFSIZE=64 -CONFIG_USB_MIDI_TX_BUFSIZE=64 -CONFIG_USB_VENDOR_ENABLED=y -# CONFIG_USB_CUSTOM_CLASS_ENABLED is not set -# CONFIG_USB_DEBUG is not set # -# Descriptor configuration +# USB task configuration # -CONFIG_USB_DESC_USE_ESPRESSIF_VID=y -CONFIG_USB_DESC_USE_DEFAULT_PID=y -CONFIG_USB_DESC_BCDDEVICE=0x0100 -CONFIG_USB_DESC_MANUFACTURER_STRING="Espressif Systems" -CONFIG_USB_DESC_PRODUCT_STRING="Espressif Device" -CONFIG_USB_DESC_SERIAL_STRING="0" +CONFIG_USB_DO_NOT_CREATE_TASK=y +CONFIG_USB_TASK_PRIORITY=5 +# end of USB task configuration + +CONFIG_USB_CUSTOM=y + +# +# Serial (CDC) driver +# +CONFIG_USB_CDC_ENABLED=y CONFIG_USB_DESC_CDC_STRING="Espressif CDC Device" -CONFIG_USB_DESC_DFU_RT_STRING="Espressif DFU Device" +CONFIG_USB_CDC_RX_BUFSIZE=64 +CONFIG_USB_CDC_TX_BUFSIZE=64 +# end of Serial (CDC) driver + +# +# Mass Storage (MSC) driver +# +CONFIG_USB_MSC_ENABLED=y CONFIG_USB_DESC_MSC_STRING="Espressif MSC Device" -CONFIG_USB_DESC_MIDI_STRING="Espressif MIDI Device" +CONFIG_USB_MSC_BUFSIZE=512 +# end of Mass Storage (MSC) driver + +# +# Human Interface (HID) driver +# +CONFIG_USB_HID_ENABLED=y CONFIG_USB_DESC_HID_STRING="Espressif HID Device" +CONFIG_USB_HID_BUFSIZE=64 +# end of Human Interface (HID) driver + +# +# MIDI driver +# +CONFIG_USB_MIDI_ENABLED=y +CONFIG_USB_DESC_MIDI_STRING="Espressif MIDI Device" +CONFIG_USB_MIDI_RX_BUFSIZE=64 +CONFIG_USB_MIDI_TX_BUFSIZE=64 +# end of MIDI driver + +# +# DFU Runtime driver +# +CONFIG_USB_DFU_RT_ENABLED=y +CONFIG_USB_DESC_DFU_RT_STRING="Espressif DFU Device" +# end of DFU Runtime driver + +# +# VENDOR driver +# +CONFIG_USB_VENDOR_ENABLED=y CONFIG_USB_DESC_VENDOR_STRING="Espressif VENDOR Device" -# end of Descriptor configuration +CONFIG_USB_VENDOR_RX_BUFSIZE=64 +CONFIG_USB_VENDOR_TX_BUFSIZE=64 +# end of VENDOR driver + +CONFIG_USB_DEBUG_LEVEL=0 # end of TinyUSB # @@ -1078,7 +1154,6 @@ CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 CONFIG_WPA_MBEDTLS_CRYPTO=y # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set -# CONFIG_WPA_TLS_V12 is not set # CONFIG_WPA_WPS_WARS is not set # end of Supplicant # end of Component config @@ -1141,10 +1216,9 @@ CONFIG_MAIN_TASK_STACK_SIZE=4096 CONFIG_IPC_TASK_STACK_SIZE=1024 CONFIG_CONSOLE_UART_DEFAULT=y # CONFIG_CONSOLE_UART_CUSTOM is not set -# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART=y CONFIG_CONSOLE_UART_NUM=0 -CONFIG_CONSOLE_UART_TX_GPIO=43 -CONFIG_CONSOLE_UART_RX_GPIO=44 CONFIG_CONSOLE_UART_BAUDRATE=115200 CONFIG_INT_WDT=y CONFIG_INT_WDT_TIMEOUT_MS=1000 @@ -1163,7 +1237,7 @@ CONFIG_TIMER_TASK_STACK_SIZE=4096 CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150 CONFIG_MB_MASTER_DELAY_MS_CONVERT=200 CONFIG_MB_QUEUE_LENGTH=20 -CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096 CONFIG_MB_SERIAL_BUF_SIZE=256 CONFIG_MB_SERIAL_TASK_PRIO=10 # CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set