Initial Esp32c3 Support (#5060)

tools/sdk/esp32c3/ld/esp32c3.ld

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+/**
+ *                    ESP32-C3 Linker Script Memory Layout
+ * This file describes the memory layout (memory blocks) by virtual memory addresses.
+ * This linker script is passed through the C preprocessor to include configuration options.
+ * Please use preprocessor features sparingly!
+ * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
+ */
+
+#include "sdkconfig.h"
+
+#define SRAM_IRAM_START     0x4037C000
+#define SRAM_DRAM_START     0x3FC7C000
+#define ICACHE_SIZE         0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
+#define I_D_SRAM_OFFSET     (SRAM_IRAM_START - SRAM_DRAM_START)
+#define SRAM_DRAM_END       0x403D0000 - I_D_SRAM_OFFSET  /* 2nd stage bootloader iram_loader_seg start address */
+
+#define SRAM_IRAM_ORG       (SRAM_IRAM_START + ICACHE_SIZE)
+#define SRAM_DRAM_ORG       (SRAM_DRAM_START + ICACHE_SIZE)
+
+#define I_D_SRAM_SIZE       SRAM_DRAM_END - SRAM_DRAM_ORG
+
+#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE
+ASSERT((CONFIG_ESP32C3_FIXED_STATIC_RAM_SIZE <= I_D_SRAM_SIZE), "Fixed static ram data does not fit.")
+#define DRAM0_0_SEG_LEN CONFIG_ESP3C3_FIXED_STATIC_RAM_SIZE
+#else
+#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE
+#endif // CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE
+MEMORY
+{
+  /**
+   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+   *  are connected to the data port of the CPU and eg allow byte-wise access.
+   */
+
+  /* IRAM for PRO CPU. */
+  iram0_0_seg (RX) :                 org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE
+
+#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+  /* Flash mapped instruction data */
+  iram0_2_seg (RX) :                 org = 0x42000020, len = 0x8000000-0x20
+
+  /**
+   * (0x20 offset above is a convenience for the app binary image generation.
+   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+   * header. Setting this offset makes it simple to meet the flash cache MMU's
+   * constraint that (paddr % 64KB == vaddr % 64KB).)
+   */
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
+  /**
+   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
+   */
+  dram0_0_seg (RW) :                 org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN
+
+#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+  /* Flash mapped constant data */
+  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x8000000-0x20
+
+  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
+  /**
+   * RTC fast memory (executable). Persists over deep sleep.
+   */
+  rtc_iram_seg(RWX) :                org = 0x50000000, len = 0x2000
+}
+
+#if CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE
+/* static data ends at defined address */
+_static_data_end = 0x3FCA0000 + DRAM0_0_SEG_LEN;
+#else
+_static_data_end = _bss_end;
+#endif // CONFIG_ESP32C3_USE_FIXED_STATIC_RAM_SIZE
+
+/* Heap ends at top of dram0_0_seg */
+_heap_end = 0x40000000;
+
+_data_seg_org = ORIGIN(rtc_data_seg);
+
+/**
+ *  The lines below define location alias for .rtc.data section
+ *  As C3 only has RTC fast memory, this is not configurable like on other targets
+ */
+REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
+REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
+REGION_ALIAS("rtc_data_location", rtc_iram_seg );
+
+#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+  REGION_ALIAS("default_code_seg", iram0_2_seg);
+#else
+  REGION_ALIAS("default_code_seg", iram0_0_seg);
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+
+#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
+  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+#else
+  REGION_ALIAS("default_rodata_seg", dram0_0_seg);
+#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS

tools/sdk/esp32c3/ld/esp32c3.peripherals.ld

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+PROVIDE ( UART0 = 0x60000000 );
+PROVIDE ( UART1 = 0x60010000 );
+PROVIDE ( UART2 = 0x6002e000 );
+PROVIDE ( SPIMEM1 = 0x60002000 );
+PROVIDE ( SPIMEM0 = 0x60003000 );
+PROVIDE ( GPIO = 0x60004000 );
+PROVIDE ( SIGMADELTA = 0x60004f00 );
+PROVIDE ( RTCCNTL = 0x60008000 );
+PROVIDE ( RTCIO = 0x60008400 );
+PROVIDE ( HINF = 0x6000B000 );
+PROVIDE ( I2S1  = 0x6002d000 );
+PROVIDE ( I2C0  = 0x60013000 );
+PROVIDE ( UHCI0  = 0x60014000 );
+PROVIDE ( UHCI1  = 0x6000c000 );
+PROVIDE ( HOST = 0x60015000 );
+PROVIDE ( RMT = 0x60016000 );
+PROVIDE ( RMTMEM = 0x60016400 );
+PROVIDE ( PCNT = 0x60017000 );
+PROVIDE ( SLC = 0x60018000 );
+PROVIDE ( LEDC = 0x60019000 );
+PROVIDE ( TIMERG0 = 0x6001F000 );
+PROVIDE ( TIMERG1 = 0x60020000 );
+PROVIDE ( GPSPI2  = 0x60024000 );
+PROVIDE ( GPSPI3  = 0x60025000 );
+PROVIDE ( SYSCON = 0x60026000 );
+PROVIDE ( TWAI   = 0x6002B000 );
+PROVIDE ( GPSPI4 = 0x60037000 );
+PROVIDE ( APB_SARADC = 0x60040000 );
+PROVIDE ( GDMA    = 0x6003F000 );

tools/sdk/esp32c3/ld/esp32c3.rom.api.ld

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+/** ROM APIs
+ */
+PROVIDE ( esp_rom_crc32_le = crc32_le );
+PROVIDE ( esp_rom_crc16_le = crc16_le );
+PROVIDE ( esp_rom_crc8_le  = crc8_le );
+PROVIDE ( esp_rom_crc32_be = crc32_be );
+PROVIDE ( esp_rom_crc16_be = crc16_be );
+PROVIDE ( esp_rom_crc8_be  = crc8_be );
+
+PROVIDE ( esp_rom_gpio_pad_select_gpio    = gpio_pad_select_gpio );
+PROVIDE ( esp_rom_gpio_pad_pullup_only    = gpio_pad_pullup );
+PROVIDE ( esp_rom_gpio_pad_set_drv        = gpio_pad_set_drv );
+PROVIDE ( esp_rom_gpio_pad_unhold         = gpio_pad_unhold );
+PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
+
+PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
+PROVIDE ( esp_rom_efuse_get_flash_gpio_info    = ets_efuse_get_spiconfig );
+PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
+PROVIDE ( esp_rom_efuse_get_flash_wp_gpio      = ets_efuse_get_wp_pad );
+
+PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
+
+
+PROVIDE ( esp_rom_md5_init   = MD5Init );
+PROVIDE ( esp_rom_md5_update = MD5Update );
+PROVIDE ( esp_rom_md5_final  = MD5Final );
+
+PROVIDE ( esp_rom_printf   = ets_printf );
+PROVIDE ( esp_rom_delay_us = ets_delay_us );

tools/sdk/esp32c3/ld/esp32c3.rom.eco3.ld

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+/*
+ESP32C3 ECO3 ROM address table
+Version 3 API's imported from the ROM
+*/
+
+esf_buf_alloc_dynamic = 0x400015c0;
+esf_buf_recycle = 0x400015c4;
+/*lmacTxDone = 0x4000162c;*/
+ppMapTxQueue = 0x400016d8;
+rcGetSched = 0x40001764;
+wDevCheckBlockError = 0x400017b4;
+ppProcTxDone = 0x40001804;
+sta_input = rom_sta_input;
+
+/***************************************
+ Group rom_phy
+ ***************************************/
+
+/* Functions */
+rom_index_to_txbbgain = 0x40001964;
+rom_pbus_xpd_tx_on = 0x400019b0;
+rom_set_tx_dig_gain = 0x400019f0;
+rom_set_txcap_reg = 0x400019f4;
+rom_txbbgain_to_index = 0x40001a0c;
+rom_agc_reg_init = 0x40001a54;
+rom_bb_reg_init = 0x40001a58;
+rom_set_pbus_reg = 0x40001a70;
+rom_phy_xpd_rf = 0x40001a78;
+rom_write_txrate_power_offset = 0x40001a8c;
+rom_temp_to_power = 0x40001ab4;
+rom_open_i2c_xpd = 0x40001af8;
+rom_tsens_read_init = 0x40001b00;
+rom_tsens_code_read = 0x40001b04;
+rom_tsens_dac_cal = 0x40001b10;
+rom_pll_vol_cal = 0x40001b28;
+
+/***************************************
+   Group eco3_wifi
+ ***************************************/
+
+/* Functions */
+wdev_is_data_in_rxlist = 0x40001b2c;
+ppProcTxCallback = 0x40001b30;
+ieee80211_gettid = 0x40001b34;
+
+
+/***************************************
+   Group eco3_bluetooth
+ ***************************************/
+
+/* Functions */
+r_lld_legacy_adv_dynamic_pti_get = 0x40001b38;
+r_lld_legacy_adv_dynamic_pti_process = 0x40001b3c;
+r_lld_ext_adv_dynamic_pti_get = 0x40001b40;
+r_lld_ext_adv_dynamic_aux_pti_process = 0x40001b44;
+r_lld_ext_adv_dynamic_pti_process = 0x40001b48;
+r_lld_adv_ext_pkt_prepare_set = 0x40001b4c;
+r_lld_adv_ext_chain_none_construct = 0x40001b50;
+r_lld_adv_ext_chain_connectable_construct = 0x40001b54;
+r_lld_adv_ext_chain_scannable_construct = 0x40001b58;
+r_lld_adv_pkt_rx_connect_post = 0x40001b5c;
+r_lld_adv_start_init_evt_param = 0x40001b60;
+r_lld_adv_start_set_cs = 0x40001b64;
+r_lld_adv_start_update_filter_policy = 0x40001b68;
+r_lld_adv_start_schedule_asap = 0x40001b6c;
+r_lld_con_tx_prog_new_packet_coex = 0x40001b70;
+r_lld_con_tx_prog_new_packet = 0x40001b74;
+r_lld_per_adv_dynamic_pti_get = 0x40001b78;
+r_lld_per_adv_evt_start_chm_upd = 0x40001b7c;
+r_lld_ext_scan_dynamic_pti_get = 0x40001b80;
+r_lld_scan_try_sched = 0x40001b84;
+r_lld_sync_insert = 0x40001b88;
+r_sch_prog_ble_push = 0x40001b8c;
+r_sch_prog_bt_push = 0x40001b90;
+r_lld_init_evt_end_type_set = 0x40001b94;
+r_lld_init_evt_end_type_get = 0x40001b98;
+r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40001b9c;
+r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x40001ba0;
+r_lld_init_evt_end_type_check_state_set = 0x40001ba4;
+r_lld_init_evt_end_type_check_state_get = 0x40001ba8;
+
+
+/***************************************
+   Group eco3_phy
+ ***************************************/
+
+/* Functions */
+rom_wrtie_pll_cap = 0x40001bac;
+rom_set_tx_gain_mem = 0x40001bb0;
+rom_bt_tx_dig_gain = 0x40001bb4;
+rom_bt_get_tx_gain = 0x40001bb8;
+rom_get_chan_target_power = 0x40001bbc;
+rom_get_tx_gain_value = 0x40001bc0;
+rom_wifi_tx_dig_gain = 0x40001bc4;
+rom_wifi_get_tx_gain = 0x40001bc8;
+rom_fe_i2c_reg_renew = 0x40001bcc;
+rom_wifi_agc_sat_gain = 0x40001bd0;
+rom_i2c_master_reset = 0x40001bd4;
+rom_bt_filter_reg = 0x40001bd8;
+rom_phy_bbpll_cal = 0x40001bdc;
+rom_i2c_sar2_init_code = 0x40001be0;
+rom_phy_param_addr = 0x40001be4;
+rom_phy_reg_init = 0x40001be8;
+rom_set_chan_reg = 0x40001bec;
+rom_phy_wakeup_init = 0x40001bf0;
+rom_phy_i2c_init1 = 0x40001bf4;
+rom_tsens_temp_read = 0x40001bf8;
+rom_bt_track_pll_cap = 0x40001bfc;
+rom_wifi_track_pll_cap = 0x40001c00;
+rom_wifi_set_tx_gain = 0x40001c04;
+rom_txpwr_cal_track = 0x40001c08;
+rom_tx_pwctrl_background = 0x40001c0c;
+rom_bt_set_tx_gain = 0x40001c10;
+rom_noise_check_loop = 0x40001c14;
+rom_phy_close_rf = 0x40001c18;
+rom_phy_xpd_tsens = 0x40001c1c;
+rom_phy_freq_mem_backup = 0x40001c20;
+rom_phy_ant_init = 0x40001c24;
+rom_bt_track_tx_power = 0x40001c28;
+rom_wifi_track_tx_power = 0x40001c2c;
+rom_phy_dig_reg_backup = 0x40001c30;
+chip726_phyrom_version_num = 0x40001c34;
+/* Data (.data, .bss, .rodata) */
+phy_param_rom = 0x3fcdf830;
+
+/***************************************
+   Group eco3_esp_flash
+ ***************************************/
+
+/* Functions */
+PROVIDE( esp_flash_read_chip_id = 0x40001c38 );
+PROVIDE( detect_spi_flash_chip = 0x40001c3c );
+PROVIDE( esp_rom_spiflash_write_disable = 0x40001c40 );

tools/sdk/esp32c3/ld/esp32c3.rom.libgcc.ld

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+/* ROM function interface esp32c3.rom.libgcc.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libgcc
+ ***************************************/
+
+/* Functions */
+__absvdi2 = 0x40000764;
+__absvsi2 = 0x40000768;
+__adddf3 = 0x4000076c;
+__addsf3 = 0x40000770;
+__addvdi3 = 0x40000774;
+__addvsi3 = 0x40000778;
+__ashldi3 = 0x4000077c;
+__ashrdi3 = 0x40000780;
+__bswapdi2 = 0x40000784;
+__bswapsi2 = 0x40000788;
+__clear_cache = 0x4000078c;
+__clrsbdi2 = 0x40000790;
+__clrsbsi2 = 0x40000794;
+__clzdi2 = 0x40000798;
+__clzsi2 = 0x4000079c;
+__cmpdi2 = 0x400007a0;
+__ctzdi2 = 0x400007a4;
+__ctzsi2 = 0x400007a8;
+__divdc3 = 0x400007ac;
+__divdf3 = 0x400007b0;
+__divdi3 = 0x400007b4;
+__divsc3 = 0x400007b8;
+__divsf3 = 0x400007bc;
+__divsi3 = 0x400007c0;
+__eqdf2 = 0x400007c4;
+__eqsf2 = 0x400007c8;
+__extendsfdf2 = 0x400007cc;
+__ffsdi2 = 0x400007d0;
+__ffssi2 = 0x400007d4;
+__fixdfdi = 0x400007d8;
+__fixdfsi = 0x400007dc;
+__fixsfdi = 0x400007e0;
+__fixsfsi = 0x400007e4;
+__fixunsdfsi = 0x400007e8;
+__fixunssfdi = 0x400007ec;
+__fixunssfsi = 0x400007f0;
+__floatdidf = 0x400007f4;
+__floatdisf = 0x400007f8;
+__floatsidf = 0x400007fc;
+__floatsisf = 0x40000800;
+__floatundidf = 0x40000804;
+__floatundisf = 0x40000808;
+__floatunsidf = 0x4000080c;
+__floatunsisf = 0x40000810;
+__gcc_bcmp = 0x40000814;
+__gedf2 = 0x40000818;
+__gesf2 = 0x4000081c;
+__gtdf2 = 0x40000820;
+__gtsf2 = 0x40000824;
+__ledf2 = 0x40000828;
+__lesf2 = 0x4000082c;
+__lshrdi3 = 0x40000830;
+__ltdf2 = 0x40000834;
+__ltsf2 = 0x40000838;
+__moddi3 = 0x4000083c;
+__modsi3 = 0x40000840;
+__muldc3 = 0x40000844;
+__muldf3 = 0x40000848;
+__muldi3 = 0x4000084c;
+__mulsc3 = 0x40000850;
+__mulsf3 = 0x40000854;
+__mulsi3 = 0x40000858;
+__mulvdi3 = 0x4000085c;
+__mulvsi3 = 0x40000860;
+__nedf2 = 0x40000864;
+__negdf2 = 0x40000868;
+__negdi2 = 0x4000086c;
+__negsf2 = 0x40000870;
+__negvdi2 = 0x40000874;
+__negvsi2 = 0x40000878;
+__nesf2 = 0x4000087c;
+__paritysi2 = 0x40000880;
+__popcountdi2 = 0x40000884;
+__popcountsi2 = 0x40000888;
+__powidf2 = 0x4000088c;
+__powisf2 = 0x40000890;
+__subdf3 = 0x40000894;
+__subsf3 = 0x40000898;
+__subvdi3 = 0x4000089c;
+__subvsi3 = 0x400008a0;
+__truncdfsf2 = 0x400008a4;
+__ucmpdi2 = 0x400008a8;
+__udivdi3 = 0x400008ac;
+__udivmoddi4 = 0x400008b0;
+__udivsi3 = 0x400008b4;
+__udiv_w_sdiv = 0x400008b8;
+__umoddi3 = 0x400008bc;
+__umodsi3 = 0x400008c0;
+__unorddf2 = 0x400008c4;
+__unordsf2 = 0x400008c8;

tools/sdk/esp32c3/ld/esp32c3.rom.newlib-nano.ld

@@ -0,0 +1,27 @@
+/* ROM function interface esp32c3.rom.newlib-nano.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib_nano_format
+ ***************************************/
+
+/* Functions */
+__sprint_r = 0x40000480;
+_fiprintf_r = 0x40000484;
+_fprintf_r = 0x40000488;
+_printf_common = 0x4000048c;
+_printf_i = 0x40000490;
+_vfiprintf_r = 0x40000494;
+_vfprintf_r = 0x40000498;
+fiprintf = 0x4000049c;
+fprintf = 0x400004a0;
+printf = 0x400004a4;
+vfiprintf = 0x400004a8;
+vfprintf = 0x400004ac;

tools/sdk/esp32c3/ld/esp32c3.rom.newlib.ld

@@ -0,0 +1,94 @@
+/* ROM function interface esp32c3.rom.newlib.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib
+ ***************************************/
+
+/* Functions */
+esp_rom_newlib_init_common_mutexes = 0x40000350;
+memset = 0x40000354;
+memcpy = 0x40000358;
+memmove = 0x4000035c;
+memcmp = 0x40000360;
+strcpy = 0x40000364;
+strncpy = 0x40000368;
+strcmp = 0x4000036c;
+strncmp = 0x40000370;
+strlen = 0x40000374;
+strstr = 0x40000378;
+bzero = 0x4000037c;
+_isatty_r = 0x40000380;
+sbrk = 0x40000384;
+isalnum = 0x40000388;
+isalpha = 0x4000038c;
+isascii = 0x40000390;
+isblank = 0x40000394;
+iscntrl = 0x40000398;
+isdigit = 0x4000039c;
+islower = 0x400003a0;
+isgraph = 0x400003a4;
+isprint = 0x400003a8;
+ispunct = 0x400003ac;
+isspace = 0x400003b0;
+isupper = 0x400003b4;
+toupper = 0x400003b8;
+tolower = 0x400003bc;
+toascii = 0x400003c0;
+memccpy = 0x400003c4;
+memchr = 0x400003c8;
+memrchr = 0x400003cc;
+strcasecmp = 0x400003d0;
+strcasestr = 0x400003d4;
+strcat = 0x400003d8;
+strdup = 0x400003dc;
+strchr = 0x400003e0;
+strcspn = 0x400003e4;
+strcoll = 0x400003e8;
+strlcat = 0x400003ec;
+strlcpy = 0x400003f0;
+strlwr = 0x400003f4;
+strncasecmp = 0x400003f8;
+strncat = 0x400003fc;
+strndup = 0x40000400;
+strnlen = 0x40000404;
+strrchr = 0x40000408;
+strsep = 0x4000040c;
+strspn = 0x40000410;
+strtok_r = 0x40000414;
+strupr = 0x40000418;
+longjmp = 0x4000041c;
+setjmp = 0x40000420;
+abs = 0x40000424;
+div = 0x40000428;
+labs = 0x4000042c;
+ldiv = 0x40000430;
+qsort = 0x40000434;
+rand_r = 0x40000438;
+rand = 0x4000043c;
+srand = 0x40000440;
+utoa = 0x40000444;
+itoa = 0x40000448;
+atoi = 0x4000044c;
+atol = 0x40000450;
+strtol = 0x40000454;
+strtoul = 0x40000458;
+PROVIDE( fflush = 0x4000045c );
+PROVIDE( _fflush_r = 0x40000460 );
+PROVIDE( _fwalk = 0x40000464 );
+PROVIDE( _fwalk_reent = 0x40000468 );
+PROVIDE( __smakebuf_r = 0x4000046c );
+PROVIDE( __swhatbuf_r = 0x40000470 );
+PROVIDE( __swbuf_r = 0x40000474 );
+__swbuf = 0x40000478;
+PROVIDE( __swsetup_r = 0x4000047c );
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x3fcdffe0;
+_global_impure_ptr = 0x3fcdffdc;

tools/sdk/esp32c3/ld/esp32c3.rom.version.ld

@@ -0,0 +1,8 @@
+/* ROM version variables for esp32c3
+ *
+ * These addresses should be compatible with any ROM version for this chip.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+_rom_chip_id = 0x40000010;
+_rom_eco_version = 0x40000014;

tools/sdk/esp32c3/ld/esp32c3_out.ld

@@ -0,0 +1,57 @@
+/**
+ *                    ESP32-C3 Linker Script Memory Layout
+ * This file describes the memory layout (memory blocks) by virtual memory addresses.
+ * This linker script is passed through the C preprocessor to include configuration options.
+ * Please use preprocessor features sparingly!
+ * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
+ */
+/*
+ * Automatically generated file. DO NOT EDIT.
+ * Espressif IoT Development Framework (ESP-IDF) Configuration Header
+ */
+       
+/* List of deprecated options */
+MEMORY
+{
+  /**
+   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+   *  are connected to the data port of the CPU and eg allow byte-wise access.
+   */
+  /* IRAM for PRO CPU. */
+  iram0_0_seg (RX) : org = (0x4037C000 + 0x4000), len = 0x403D0000 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
+  /* Flash mapped instruction data */
+  iram0_2_seg (RX) : org = 0x42000020, len = 0x8000000-0x20
+  /**
+   * (0x20 offset above is a convenience for the app binary image generation.
+   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+   * header. Setting this offset makes it simple to meet the flash cache MMU's
+   * constraint that (paddr % 64KB == vaddr % 64KB).)
+   */
+  /**
+   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
+   */
+  dram0_0_seg (RW) : org = (0x3FC7C000 + 0x4000), len = 0x403D0000 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
+  /* Flash mapped constant data */
+  drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20
+  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+  /**
+   * RTC fast memory (executable). Persists over deep sleep.
+   */
+  rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000
+}
+_static_data_end = _bss_end;
+/* Heap ends at top of dram0_0_seg */
+_heap_end = 0x40000000;
+_data_seg_org = ORIGIN(rtc_data_seg);
+/**
+ *  The lines below define location alias for .rtc.data section
+ *  As C3 only has RTC fast memory, this is not configurable like on other targets
+ */
+REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
+REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
+REGION_ALIAS("rtc_data_location", rtc_iram_seg );
+  REGION_ALIAS("default_code_seg", iram0_2_seg);
+  REGION_ALIAS("default_rodata_seg", drom0_0_seg);