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Update IDF Libs

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This commit is contained in:
me-no-dev
2020-06-28 15:38:58 +03:00
parent 7611f483ae
commit 47b34df897
259 changed files with 1671 additions and 836 deletions
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7
tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h
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@ -17,13 +17,12 @@ void adc_hal_init(void);
void adc_hal_deinit(void);
/**
* Set adc sample cycle for digital controller.
* Set adc sample cycle.
*
* @note Normally, please use default value.
* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
* Range: 2 ~ 0xFF.
* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
*/
#define adc_hal_digi_set_sample_cycle(sample_cycle) adc_ll_digi_set_sample_cycle(sample_cycle)
#define adc_hal_set_sample_cycle(sample_cycle) adc_ll_set_sample_cycle(sample_cycle)
/**
* Set ADC module power management.

153
tools/sdk/esp32s2/include/soc/include/hal/adc_types.h
View File

@ -13,7 +13,7 @@ typedef enum {
ADC_UNIT_1 = 1, /*!< SAR ADC 1. */
ADC_UNIT_2 = 2, /*!< SAR ADC 2. */
ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */
ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode, not supported yet */
ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode. */
ADC_UNIT_MAX,
} adc_unit_t;
@ -75,29 +75,58 @@ typedef enum {
ADC_WIDTH_MAX,
} adc_bits_width_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: In multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note ESP32S2:
* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val;
};
} adc_digi_output_data_t;
#ifdef CONFIG_IDF_TARGET_ESP32S2
/**
* @brief ADC digital controller (DMA mode) clock system setting.
* Expression: controller_clk = (`APLL` or `APB`) * (div_num + div_b / div_a).
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*/
typedef struct {
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
uint32_t div_num; /*!<Division factor. Range: 1 ~ 255. */
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
Note: When a higher frequency clock is used (the division factor is less than 9),
the ADC reading value will be slightly offset. */
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
} adc_digi_clk_t;
/**
* @brief ADC digital controller (DMA mode) clock system default setting.
*/
#define ADC_DIGITAL_CLK_DEFAULT() { \
.use_apll = 0, \
.div_num = 40, \
.div_b = 1, \
.div_a = 1, \
}
/**
* @brief ADC arbiter work mode option.
*
@ -116,7 +145,7 @@ typedef enum {
* @note ESP32S2: Only ADC2 support arbiter.
*/
typedef struct {
adc_arbiter_mode_t mode; /*!<Refer to `adc_arbiter_mode_t`. Note: only support ADC2. */
adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */
uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
@ -137,7 +166,11 @@ typedef struct {
/**
* @brief ADC digital controller (DMA mode) work mode.
*
* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
* @note The conversion mode affects the sampling frequency:
* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
*/
typedef enum {
ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */
@ -147,42 +180,6 @@ typedef enum {
ADC_CONV_UNIT_MAX,
} adc_digi_convert_mode_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: In multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val;
};
} adc_digi_output_data_t;
/**
* @brief ADC digital controller (DMA mode) conversion rules setting.
*/
@ -212,26 +209,54 @@ typedef enum {
/**
* @brief ADC digital controller (DMA mode) configuration parameters.
*
* Example setting: Use ADC1 channel0 to measure voltage, the sampling rate is required to be 1KHz:
* +---------------------+--------+--------+--------+
* | sample rate | 1KHz | 1KHz | 1KHz |
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* | adc1_pattern_len | 1 | 1 | 1 |
* | dig_clk.use_apll | 0 | 0 | 0 |
* | dig_clk.div_num | 99 | 99 | 99 |
* | dig_clk.div_b | 0 | 0 | 0 |
* | dig_clk.div_a | 0 | 0 | 0 |
* | interval | 400 | 400 | 200 |
* +---------------------+--------+--------+--------+
* | `trigger_meas_freq` | 1KHz | 1KHz | 2KHz |
* +---------------------+--------+--------+--------+
*
* Explain the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA output:
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* +---------------------+--------+--------+--------+
* | trigger meas times | 1 | 1 | 1 |
* +---------------------+--------+--------+--------+
* | conv_limit_num | +1 | +1 | +1 |
* | dma_eof_num | +1 | +2 | +1 |
* | dma output (byte) | +2 | +4 | +2 |
* +---------------------+--------+--------+--------+
*/
typedef struct {
bool conv_limit_en; /*!<Enable max conversion number detection for digital controller.
If the number of ADC conversion is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<ADC max conversion number for digital controller. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16.
bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
uint32_t adc2_pattern_len; /*!<Refer to `adc1_pattern_len` */
uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to ``adc1_pattern`` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
The unit is the divided clock. Range: 40 ~ 4095. */
adc_digi_clk_t dig_clk; /*!<Refer to `adc_digi_clk_t` */
The unit is the divided clock. Range: 40 ~ 4095.
Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t`` */
uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
If the number of measurements reaches `dma_eof_num`,
then `dma_in_suc_eof` signal is generated. */
If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
} adc_digi_config_t;
/**

9
tools/sdk/esp32s2/include/soc/include/hal/dac_hal.h
View File

@ -39,6 +39,15 @@
*/
#define dac_hal_power_down(channel) dac_ll_power_down(channel)
/**
* Enable/disable the synchronization operation function of ADC1 and DAC.
*
* @note If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
*
* @param enable Enable or disable adc and dac synchronization function.
*/
#define dac_hal_rtc_sync_by_adc(enable) dac_ll_rtc_sync_by_adc(enable)
/**
* Output voltage with value (8 bit).
*

4
tools/sdk/esp32s2/include/soc/include/hal/gpio_types.h
View File

@ -26,6 +26,8 @@ typedef enum {
GPIO_PORT_MAX,
} gpio_port_t;
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */
#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */
#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */
@ -130,6 +132,8 @@ typedef enum {
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#endif
/** @endcond */
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */

78
tools/sdk/esp32s2/include/soc/include/hal/i2s_types.h
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@ -1,4 +1,4 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -34,9 +34,6 @@ typedef enum {
I2S_NUM_MAX, /*!< I2S port max */
} i2s_port_t;
#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
/**
* @brief I2S bit width per sample.
*
@ -62,14 +59,21 @@ typedef enum {
*
*/
typedef enum {
I2S_COMM_FORMAT_I2S = 0x01, /*!< I2S communication format I2S*/
I2S_COMM_FORMAT_I2S_MSB = 0x02, /*!< I2S format MSB*/
I2S_COMM_FORMAT_I2S_LSB = 0x04, /*!< I2S format LSB*/
I2S_COMM_FORMAT_PCM = 0x08, /*!< I2S communication format PCM*/
I2S_COMM_FORMAT_PCM_SHORT = 0x10, /*!< PCM Short*/
I2S_COMM_FORMAT_PCM_LONG = 0x20, /*!< PCM Long*/
} i2s_comm_format_t;
// In order to keep compatibility, remain the old definitions and introduce new definitions,
I2S_COMM_FORMAT_STAND_I2S = 0X01, /*!< I2S communication I2S Philips standard, data launch at second BCK*/
I2S_COMM_FORMAT_STAND_MSB = 0X03, /*!< I2S communication MSB alignment standard, data launch at first BCK*/
I2S_COMM_FORMAT_STAND_PCM_SHORT = 0x04, /*!< PCM Short standard*/
I2S_COMM_FORMAT_STAND_PCM_LONG = 0x0C, /*!< PCM Long standard*/
I2S_COMM_FORMAT_STAND_MAX, /*!< standard max*/
//old definition will be removed in the future.
I2S_COMM_FORMAT_I2S __attribute__((deprecated)) = 0x01, /*!< I2S communication format I2S, correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_MSB __attribute__((deprecated)) = 0x01, /*!< I2S format MSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_MSB) correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_LSB __attribute__((deprecated)) = 0x02, /*!< I2S format LSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_LSB) correspond to `I2S_COMM_FORMAT_STAND_MSB`*/
I2S_COMM_FORMAT_PCM __attribute__((deprecated)) = 0x04, /*!< I2S communication format PCM, correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_SHORT __attribute__((deprecated)) = 0x04, /*!< PCM Short, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_SHORT) correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_LONG __attribute__((deprecated)) = 0x08, /*!< PCM Long, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_LONG) correspond to `I2S_COMM_FORMAT_STAND_PCM_LONG`*/
} i2s_comm_format_t;
/**
* @brief I2S channel format type
@ -82,26 +86,6 @@ typedef enum {
I2S_CHANNEL_FMT_ONLY_LEFT,
} i2s_channel_fmt_t;
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief PDM sample rate ratio, measured in Hz.
*
*/
typedef enum {
PDM_SAMPLE_RATE_RATIO_64,
PDM_SAMPLE_RATE_RATIO_128,
} pdm_sample_rate_ratio_t;
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
PDM_PCM_CONV_ENABLE,
PDM_PCM_CONV_DISABLE,
} pdm_pcm_conv_t;
#endif
/**
* @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
*
@ -109,19 +93,29 @@ typedef enum {
*
*/
typedef enum {
I2S_MODE_MASTER = 1,
I2S_MODE_SLAVE = 2,
I2S_MODE_TX = 4,
I2S_MODE_RX = 8,
I2S_MODE_MASTER = 1, /*!< Master mode*/
I2S_MODE_SLAVE = 2, /*!< Slave mode*/
I2S_MODE_TX = 4, /*!< TX mode*/
I2S_MODE_RX = 8, /*!< RX mode*/
#if SOC_I2S_SUPPORTS_ADC_DAC
I2S_MODE_DAC_BUILT_IN = 16, /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
I2S_MODE_ADC_BUILT_IN = 32, /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
#endif
#if SOC_I2S_SUPPORTS_PDM
I2S_MODE_PDM = 64,
I2S_MODE_PDM = 64, /*!< PDM mode*/
#endif
} i2s_mode_t;
/**
* @brief I2S source clock
*
*/
typedef enum {
I2S_CLK_D2CLK = 0, /*!< Clock from PLL_D2_CLK(160M)*/
I2S_CLK_APLL, /*!< Clock from APLL*/
} i2s_clock_src_t;
/**
* @brief I2S configuration parameters for i2s_param_config function
*
@ -193,12 +187,16 @@ typedef enum {
I2S_PDM_DSR_16S, /*!< downsampling number is 16 for PDM RX mode*/
I2S_PDM_DSR_MAX,
} i2s_pdm_dsr_t;
#endif
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
I2S_CLK_D2CLK = 0,
I2S_CLK_APLL,
} i2s_clock_src_t;
PDM_PCM_CONV_ENABLE, /*!< Enable PDM PCM convert*/
PDM_PCM_CONV_DISABLE, /*!< Disable PDM PCM convert*/
} pdm_pcm_conv_t;
#endif
#ifdef __cplusplus

10
tools/sdk/esp32s2/include/soc/include/hal/rmt_hal.h
View File

@ -39,13 +39,6 @@ typedef struct {
*/
void rmt_hal_init(rmt_hal_context_t *hal);
/**
* @brief Reset RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_reset(rmt_hal_context_t *hal);
/**
* @brief Reset RMT Channel specific HAL driver
*
@ -133,7 +126,8 @@ uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t
* @param channel: RMT channel number
* @param src: RMT items to transmit
* @param length: length of RMT items to transmit
* @param offset: offset of RMT internal memory to store the items
* @param offset: offset of RMT internal memory to store the items.
* Note: the caller should ensure that (length + offset) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS).
*/
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset);

4
tools/sdk/esp32s2/include/soc/include/hal/spi_types.h
View File

@ -27,6 +27,8 @@ typedef enum {
SPI3_HOST=2, ///< SPI3
} spi_host_device_t;
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
//alias for different chips
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_HOST SPI1_HOST
@ -38,3 +40,5 @@ typedef enum {
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI3_HOST
#endif
/** @endcond */

2
tools/sdk/esp32s2/include/soc/include/hal/touch_sensor_types.h
View File

@ -265,7 +265,7 @@ typedef struct touch_filter_config {
uint32_t hysteresis_thr; /*!<Hysteresis threshold coefficient. hysteresis = hysteresis coefficient * touch threshold.
If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched.
If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released.
Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 2/32; 3: OFF */
Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 1/32; 3: OFF */
uint32_t noise_thr; /*!<Noise threshold coefficient. noise = noise coefficient * touch threshold.
If (raw data - baseline) > (noise), the baseline stop updating.
If (raw data - baseline) < (noise), the baseline start updating.

1
tools/sdk/esp32s2/include/soc/include/hal/uart_hal.h
View File

@ -150,6 +150,7 @@ void uart_hal_write_txfifo(uart_hal_context_t *hal, const uint8_t *buf, uint32_t
/**
* @brief Reset the UART txfifo
* @note On ESP32, this function is reserved for UART1 and UART2.
*
* @param hal Context of the HAL layer
*

12
tools/sdk/esp32s2/include/soc/include/soc/soc_memory_layout.h
View File

@ -176,6 +176,12 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
intptr_t ip = (intptr_t) p;
bool r;
r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
#if CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
* for single core configuration (where it gets added to system heap) following
* additional check is required */
r |= (ip >= SOC_RTC_DRAM_LOW && ip < SOC_RTC_DRAM_HIGH);
#endif
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
@ -190,6 +196,12 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
bool r;
r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
#if CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
* for single core configuration (where it gets added to system heap) following
* additional check is required */
r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
#endif
return r;
}

2
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/adc_caps.h
View File

@ -14,7 +14,7 @@
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (3)
/**
* Check if adc support digital controller (DMA) mode.

524
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/i2s_struct.h
View File

@ -1,9 +1,9 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -22,33 +22,33 @@ typedef volatile struct {
uint32_t reserved_4;
union {
struct {
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
uint32_t tx_fifo_reset: 1; /*Set this bit to reset txFIFO*/
uint32_t rx_fifo_reset: 1; /*Set this bit to reset rxFIFO*/
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
uint32_t tx_right_first: 1; /*Set this bit to transmit right channel data first*/
uint32_t rx_right_first: 1; /*Set this bit to receive right channel data first*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t tx_short_sync: 1; /*Set this bit to enable transmitter in PCM standard mode*/
uint32_t rx_short_sync: 1; /*Set this bit to enable receiver in PCM standard mode*/
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
uint32_t tx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the transmit FIFO.*/
uint32_t rx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the receive FIFO.*/
uint32_t tx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t rx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t sig_loopback: 1; /*Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t tx_fifo_reset_st: 1; /*1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok*/
uint32_t rx_fifo_reset_st: 1; /*1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok*/
uint32_t tx_reset_st: 1; /*1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok*/
uint32_t tx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t rx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t pre_req_en: 1; /*set this bit to enable i2s to prepare data earlier*/
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
uint32_t tx_fifo_reset: 1; /*Set this bit to reset txFIFO*/
uint32_t rx_fifo_reset: 1; /*Set this bit to reset rxFIFO*/
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
uint32_t tx_right_first: 1; /*Set this bit to transmit right channel data first*/
uint32_t rx_right_first: 1; /*Set this bit to receive right channel data first*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
uint32_t tx_short_sync: 1; /*Set this bit to enable transmitter in PCM standard mode*/
uint32_t rx_short_sync: 1; /*Set this bit to enable receiver in PCM standard mode*/
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
uint32_t tx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the transmit FIFO.*/
uint32_t rx_msb_right: 1; /*Set this bit to place right channel data at the MSB in the receive FIFO.*/
uint32_t tx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t rx_lsb_first_dma: 1; /*1:the data in DMA/APB transform from low bits*/
uint32_t sig_loopback: 1; /*Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
uint32_t tx_fifo_reset_st: 1; /*1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok*/
uint32_t rx_fifo_reset_st: 1; /*1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok*/
uint32_t tx_reset_st: 1; /*1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok*/
uint32_t tx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t rx_dma_equal: 1; /*1:data in left channel is equal to data in right channel*/
uint32_t pre_req_en: 1; /*set this bit to enable i2s to prepare data earlier*/
uint32_t tx_big_endian: 1;
uint32_t rx_big_endian: 1;
uint32_t rx_reset_st: 1;
@ -58,167 +58,171 @@ typedef volatile struct {
} conf;
union {
struct {
uint32_t rx_take_data: 1; /*The raw interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The raw interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The raw interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The raw interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The raw interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The raw interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The raw interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The raw interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The raw interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t rx_take_data: 1; /*The raw interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The raw interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The raw interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The raw interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The raw interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The raw interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The raw interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The raw interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The raw interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The raw interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*The raw interrupt status bit for the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_take_data: 1; /*The masked interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The masked interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The masked interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The masked interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The masked interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The masked interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The masked interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The masked interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The masked interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The masked interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The masked interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The masked interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t rx_take_data: 1; /*The masked interrupt status bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The masked interrupt status bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The masked interrupt status bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The masked interrupt status bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The masked interrupt status bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The masked interrupt status bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The masked interrupt status bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The masked interrupt status bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The masked interrupt status bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The masked interrupt status bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The masked interrupt status bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The masked interrupt status bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The masked interrupt status bit for the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*The masked interrupt status bit for the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rx_take_data: 1; /*The interrupt enable bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The interrupt enable bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The interrupt enable bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The interrupt enable bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The interrupt enable bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The interrupt enable bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The interrupt enable bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The interrupt enable bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The interrupt enable bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The interrupt enable bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The interrupt enable bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The interrupt enable bit for the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t rx_take_data: 1; /*The interrupt enable bit for the i2s_rx_take_data_int interrupt*/
uint32_t tx_put_data: 1; /*The interrupt enable bit for the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*The interrupt enable bit for the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*The interrupt enable bit for the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*The interrupt enable bit for the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*The interrupt enable bit for the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*The interrupt enable bit for the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*The interrupt enable bit for the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*The interrupt enable bit for the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*The interrupt enable bit for the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*The interrupt enable bit for the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*The interrupt enable bit for the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*The interrupt enable bit for the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t take_data: 1; /*Set this bit to clear the i2s_rx_take_data_int interrupt*/
uint32_t put_data: 1; /*Set this bit to clear the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*Set this bit to clear the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*Set this bit to clear the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*Set this bit to clear the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*Set this bit to clear the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*Set this bit to clear the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*Set this bit to clear the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*Set this bit to clear the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*Set this bit to clear the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*Set this bit to clear the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*Set this bit to clear the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*Set this bit to clear the i2s_out_total_eof_int interrupt*/
uint32_t reserved17: 15;
uint32_t take_data: 1; /*Set this bit to clear the i2s_rx_take_data_int interrupt*/
uint32_t put_data: 1; /*Set this bit to clear the i2s_tx_put_data_int interrupt*/
uint32_t rx_wfull: 1; /*Set this bit to clear the i2s_rx_wfull_int interrupt*/
uint32_t rx_rempty: 1; /*Set this bit to clear the i2s_rx_rempty_int interrupt*/
uint32_t tx_wfull: 1; /*Set this bit to clear the i2s_tx_wfull_int interrupt*/
uint32_t tx_rempty: 1; /*Set this bit to clear the i2s_tx_rempty_int interrupt*/
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
uint32_t in_done: 1; /*Set this bit to clear the i2s_in_done_int interrupt*/
uint32_t in_suc_eof: 1; /*Set this bit to clear the i2s_in_suc_eof_int interrupt*/
uint32_t in_err_eof: 1; /*don't use*/
uint32_t out_done: 1; /*Set this bit to clear the i2s_out_done_int interrupt*/
uint32_t out_eof: 1; /*Set this bit to clear the i2s_out_eof_int interrupt*/
uint32_t in_dscr_err: 1; /*Set this bit to clear the i2s_in_dscr_err_int interrupt*/
uint32_t out_dscr_err: 1; /*Set this bit to clear the i2s_out_dscr_err_int interrupt*/
uint32_t in_dscr_empty: 1; /*Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
uint32_t out_total_eof: 1; /*Set this bit to clear the i2s_out_total_eof_int interrupt*/
uint32_t v_sync: 1; /*Set this bit to clear the i2s_v_sync_int interrupt*/
uint32_t reserved18: 14;
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t tx_bck_in_delay: 2; /*Number of delay cycles for BCK into the transmitter*/
uint32_t tx_ws_in_delay: 2; /*Number of delay cycles for WS into the transmitter*/
uint32_t rx_bck_in_delay: 2; /*Number of delay cycles for BCK into the receiver*/
uint32_t rx_ws_in_delay: 2; /*Number of delay cycles for WS into the receiver*/
uint32_t rx_sd_in_delay: 2; /*Number of delay cycles for SD into the receiver*/
uint32_t tx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the transmitter*/
uint32_t tx_ws_out_delay: 2; /*Number of delay cycles for WS out of the transmitter*/
uint32_t tx_sd_out_delay: 2; /*Number of delay cycles for SD out of the transmitter*/
uint32_t rx_ws_out_delay: 2; /*Number of delay cycles for WS out of the receiver*/
uint32_t rx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the receiver*/
uint32_t tx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the transmitter*/
uint32_t rx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the receiver*/
uint32_t data_enable_delay: 2; /*Number of delay cycles for data valid flag.*/
uint32_t tx_bck_in_inv: 1; /*Set this bit to invert BCK signal input to the slave transmitter*/
uint32_t tx_bck_in_delay: 2; /*Number of delay cycles for BCK into the transmitter*/
uint32_t tx_ws_in_delay: 2; /*Number of delay cycles for WS into the transmitter*/
uint32_t rx_bck_in_delay: 2; /*Number of delay cycles for BCK into the receiver*/
uint32_t rx_ws_in_delay: 2; /*Number of delay cycles for WS into the receiver*/
uint32_t rx_sd_in_delay: 2; /*Number of delay cycles for SD into the receiver*/
uint32_t tx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the transmitter*/
uint32_t tx_ws_out_delay: 2; /*Number of delay cycles for WS out of the transmitter*/
uint32_t tx_sd_out_delay: 2; /*Number of delay cycles for SD out of the transmitter*/
uint32_t rx_ws_out_delay: 2; /*Number of delay cycles for WS out of the receiver*/
uint32_t rx_bck_out_delay: 2; /*Number of delay cycles for BCK out of the receiver*/
uint32_t tx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the transmitter*/
uint32_t rx_dsync_sw: 1; /*Set this bit to synchronize signals with the double sync method into the receiver*/
uint32_t data_enable_delay: 2; /*Number of delay cycles for data valid flag.*/
uint32_t tx_bck_in_inv: 1; /*Set this bit to invert BCK signal input to the slave transmitter*/
uint32_t reserved25: 7;
};
uint32_t val;
} timing;
union {
struct {
uint32_t rx_data_num: 6; /*Threshold of data length in receiver FIFO*/
uint32_t tx_data_num: 6; /*Threshold of data length in transmitter FIFO*/
uint32_t dscr_en: 1; /*Set this bit to enable I2S DMA mode*/
uint32_t tx_fifo_mod: 3; /*Transmitter FIFO mode configuration bits*/
uint32_t rx_fifo_mod: 3; /*Receiver FIFO mode configuration bits*/
uint32_t tx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_sync: 1; /*force write back rx data to memory*/
uint32_t rx_24msb_en: 1; /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t rx_data_num: 6; /*Threshold of data length in receiver FIFO*/
uint32_t tx_data_num: 6; /*Threshold of data length in transmitter FIFO*/
uint32_t dscr_en: 1; /*Set this bit to enable I2S DMA mode*/
uint32_t tx_fifo_mod: 3; /*Transmitter FIFO mode configuration bits*/
uint32_t rx_fifo_mod: 3; /*Receiver FIFO mode configuration bits*/
uint32_t tx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_mod_force_en: 1; /*The bit should always be set to 1*/
uint32_t rx_fifo_sync: 1; /*force write back rx data to memory*/
uint32_t rx_24msb_en: 1; /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t tx_24msb_en: 1; /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo*/
uint32_t reserved24: 8;
};
uint32_t val;
} fifo_conf;
uint32_t rx_eof_num; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
uint32_t rx_eof_num; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
union {
struct {
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t rx_chan_mod: 2; /*I2S receiver channel mode configuration bits.*/
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
uint32_t rx_chan_mod: 2; /*I2S receiver channel mode configuration bits.*/
uint32_t reserved5: 27;
};
uint32_t val;
} conf_chan;
union {
struct {
uint32_t addr: 20; /*The address of first outlink descriptor*/
uint32_t addr: 20; /*The address of first outlink descriptor*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop outlink descriptor*/
uint32_t start: 1; /*Set this bit to start outlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart outlink descriptor*/
uint32_t stop: 1; /*Set this bit to stop outlink descriptor*/
uint32_t start: 1; /*Set this bit to start outlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart outlink descriptor*/
uint32_t park: 1;
};
uint32_t val;
} out_link;
union {
struct {
uint32_t addr: 20; /*The address of first inlink descriptor*/
uint32_t addr: 20; /*The address of first inlink descriptor*/
uint32_t reserved20: 8;
uint32_t stop: 1; /*Set this bit to stop inlink descriptor*/
uint32_t start: 1; /*Set this bit to start inlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart inlink descriptor*/
uint32_t stop: 1; /*Set this bit to stop inlink descriptor*/
uint32_t start: 1; /*Set this bit to start inlink descriptor*/
uint32_t restart: 1; /*Set this bit to restart inlink descriptor*/
uint32_t park: 1;
};
uint32_t val;
} in_link;
uint32_t out_eof_des_addr; /*The address of outlink descriptor that produces EOF*/
uint32_t in_eof_des_addr; /*The address of inlink descriptor that produces EOF*/
uint32_t out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produces EOF*/
uint32_t out_eof_des_addr; /*The address of outlink descriptor that produces EOF*/
uint32_t in_eof_des_addr; /*The address of inlink descriptor that produces EOF*/
uint32_t out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produces EOF*/
union {
struct {
uint32_t mode: 3;
@ -228,29 +232,29 @@ typedef volatile struct {
};
uint32_t val;
} ahb_test;
uint32_t in_link_dscr; /*The address of current inlink descriptor*/
uint32_t in_link_dscr_bf0; /*The address of next inlink descriptor*/
uint32_t in_link_dscr_bf1; /*The address of next inlink data buffer*/
uint32_t out_link_dscr; /*The address of current outlink descriptor*/
uint32_t out_link_dscr_bf0; /*The address of next outlink descriptor*/
uint32_t out_link_dscr_bf1; /*The address of next outlink data buffer*/
uint32_t in_link_dscr; /*The address of current inlink descriptor*/
uint32_t in_link_dscr_bf0; /*The address of next inlink descriptor*/
uint32_t in_link_dscr_bf1; /*The address of next inlink data buffer*/
uint32_t out_link_dscr; /*The address of current outlink descriptor*/
uint32_t out_link_dscr_bf0; /*The address of next outlink descriptor*/
uint32_t out_link_dscr_bf1; /*The address of next outlink data buffer*/
union {
struct {
uint32_t in_rst: 1; /*Set this bit to reset in dma FSM*/
uint32_t out_rst: 1; /*Set this bit to reset out dma FSM*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset ahb interface cmdFIFO of DMA*/
uint32_t ahbm_rst: 1; /*Set this bit to reset ahb interface of DMA*/
uint32_t out_loop_test: 1; /*Set this bit to loop test inlink*/
uint32_t in_loop_test: 1; /*Set this bit to loop test outlink*/
uint32_t out_auto_wrback: 1; /*Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO 0:when ahb has pushed all data to the FIFO*/
uint32_t outdscr_burst_en: 1; /*DMA outlink descriptor transfer mode configuration bit. 1: to prepare outlink descriptor with burst mode 0: to prepare outlink descriptor with byte mode*/
uint32_t indscr_burst_en: 1; /*DMA inlink descriptor transfer mode configuration bit. 1: to prepare inlink descriptor with burst mode 0: to prepare inlink descriptor with byte mode*/
uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/
uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/
uint32_t mem_trans_en: 1; /*don't use*/
uint32_t ext_mem_bk_size: 2; /*DMA access external memory block size. 0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/
uint32_t in_rst: 1; /*Set this bit to reset in dma FSM*/
uint32_t out_rst: 1; /*Set this bit to reset out dma FSM*/
uint32_t ahbm_fifo_rst: 1; /*Set this bit to reset ahb interface cmdFIFO of DMA*/
uint32_t ahbm_rst: 1; /*Set this bit to reset ahb interface of DMA*/
uint32_t out_loop_test: 1; /*Set this bit to loop test inlink*/
uint32_t in_loop_test: 1; /*Set this bit to loop test outlink*/
uint32_t out_auto_wrback: 1; /*Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.*/
uint32_t out_no_restart_clr: 1; /*don't use*/
uint32_t out_eof_mode: 1; /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO 0:when ahb has pushed all data to the FIFO*/
uint32_t outdscr_burst_en: 1; /*DMA outlink descriptor transfer mode configuration bit. 1: to prepare outlink descriptor with burst mode 0: to prepare outlink descriptor with byte mode*/
uint32_t indscr_burst_en: 1; /*DMA inlink descriptor transfer mode configuration bit. 1: to prepare inlink descriptor with burst mode 0: to prepare inlink descriptor with byte mode*/
uint32_t out_data_burst_en: 1; /*Transmitter data transfer mode configuration bit. 1: to prepare out data with burst mode 0: to prepare out data with byte mode*/
uint32_t check_owner: 1; /*Set this bit to enable check owner bit by hardware*/
uint32_t mem_trans_en: 1; /*don't use*/
uint32_t ext_mem_bk_size: 2; /*DMA access external memory block size. 0: 16 bytes 1: 32 bytes 2:64 bytes 3:reserved*/
uint32_t reserved16: 16;
};
uint32_t val;
@ -280,7 +284,7 @@ typedef volatile struct {
uint32_t out_state: 3;
uint32_t cnt: 7;
uint32_t out_full: 1;
uint32_t out_empty: 1; /*DMA transmitter status register*/
uint32_t out_empty: 1; /*DMA transmitter status register*/
};
uint32_t val;
} lc_state0;
@ -291,134 +295,66 @@ typedef volatile struct {
uint32_t in_state: 3;
uint32_t cnt_debug: 7;
uint32_t in_full: 1;
uint32_t in_empty: 1; /*DMA receiver status register*/
uint32_t in_empty: 1; /*DMA receiver status register*/
};
uint32_t val;
} lc_state1;
union {
struct {
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
uint32_t reserved12: 20;
};
uint32_t val;
} lc_hung_conf;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
union {
struct {
uint32_t y_max: 16; /*don't use*/
uint32_t y_min: 16; /*don't use*/
};
uint32_t val;
} cvsd_conf0;
union {
struct {
uint32_t sigma_max: 16; /*don't use*/
uint32_t sigma_min: 16; /*don't use*/
};
uint32_t val;
} cvsd_conf1;
union {
struct {
uint32_t cvsd_k: 3; /*don't use*/
uint32_t cvsd_j: 3; /*don't use*/
uint32_t cvsd_beta: 10; /*don't use*/
uint32_t cvsd_h: 3; /*don't use*/
uint32_t reserved19:13; /*don't use*/
};
uint32_t val;
} cvsd_conf2;
union {
struct {
uint32_t good_pack_max: 6; /*don't use*/
uint32_t n_err_seg: 3; /*don't use*/
uint32_t shift_rate: 3; /*don't use*/
uint32_t max_slide_sample: 8; /*don't use*/
uint32_t pack_len_8k: 5; /*don't use*/
uint32_t n_min_err: 3; /*don't use*/
uint32_t reserved28: 4; /*don't use*/
};
uint32_t val;
} plc_conf0;
union {
struct {
uint32_t bad_cef_atten_para: 8; /*don't use*/
uint32_t bad_cef_atten_para_shift: 4; /*don't use*/
uint32_t bad_ola_win2_para_shift: 4; /*don't use*/
uint32_t bad_ola_win2_para: 8; /*don't use*/
uint32_t slide_win_len: 8; /*don't use*/
};
uint32_t val;
} plc_conf1;
union {
struct {
uint32_t cvsd_seg_mod: 2; /*don't use*/
uint32_t min_period: 5; /*don't use*/
uint32_t reserved7: 25; /*don't use*/
};
uint32_t val;
} plc_conf2;
union {
struct {
uint32_t en: 1; /*don't use*/
uint32_t chan_mod: 1; /*don't use*/
uint32_t cvsd_dec_pack_err: 1; /*don't use*/
uint32_t cvsd_pack_len_8k: 5; /*don't use*/
uint32_t cvsd_inf_en: 1; /*don't use*/
uint32_t cvsd_dec_start: 1; /*don't use*/
uint32_t cvsd_dec_reset: 1; /*don't use*/
uint32_t plc_en: 1; /*don't use*/
uint32_t plc2dma_en: 1; /*don't use*/
uint32_t reserved13: 19; /*don't use*/
};
uint32_t val;
} esco_conf0;
union {
struct {
uint32_t with_en: 1; /*don't use*/
uint32_t no_en: 1; /*don't use*/
uint32_t cvsd_enc_start: 1; /*don't use*/
uint32_t cvsd_enc_reset: 1; /*don't use*/
uint32_t reserved4: 28; /*don't use*/
};
uint32_t val;
} sco_conf0;
union {
struct {
uint32_t tx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t rx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t tx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data*/
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
uint32_t rx_pcm_conf: 3; /*Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data*/
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
uint32_t tx_zeros_rm_en: 1; /*don't use*/
uint32_t reserved10: 22;
};
uint32_t val;
} conf1;
union {
struct {
uint32_t fifo_force_pd: 1; /*Force FIFO power-down*/
uint32_t fifo_force_pu: 1; /*Force FIFO power-up*/
uint32_t fifo_force_pd: 1; /*Force FIFO power-down*/
uint32_t fifo_force_pu: 1; /*Force FIFO power-up*/
uint32_t plc_mem_force_pd: 1;
uint32_t plc_mem_force_pu: 1;
uint32_t reserved4: 28;
uint32_t dma_ram_force_pd: 1;
uint32_t dma_ram_force_pu: 1;
uint32_t dma_ram_clk_fo: 1;
uint32_t reserved7: 25;
};
uint32_t val;
} pd_conf;
union {
struct {
uint32_t camera_en: 1; /*Set this bit to enable camera mode*/
uint32_t lcd_tx_wrx2_en: 1; /*LCD WR double for one datum.*/
uint32_t lcd_tx_sdx2_en: 1; /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
uint32_t data_enable_test_en: 1; /*for debug camera mode enable*/
uint32_t data_enable: 1; /*for debug camera mode enable*/
uint32_t lcd_en: 1; /*Set this bit to enable LCD mode*/
uint32_t ext_adc_start_en: 1; /*Set this bit to enable the function that ADC mode is triggered by external signal.*/
uint32_t inter_valid_en: 1; /*Set this bit to enable camera internal valid*/
uint32_t cam_sync_fifo_reset: 1; /*Set this bit to reset cam_sync_fifo*/
uint32_t cam_clk_loopback: 1; /*Set this bit to loopback cam_clk from i2s_rx*/
uint32_t camera_en: 1; /*Set this bit to enable camera mode*/
uint32_t lcd_tx_wrx2_en: 1; /*LCD WR double for one datum.*/
uint32_t lcd_tx_sdx2_en: 1; /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
uint32_t data_enable_test_en: 1; /*for debug camera mode enable*/
uint32_t data_enable: 1; /*for debug camera mode enable*/
uint32_t lcd_en: 1; /*Set this bit to enable LCD mode*/
uint32_t ext_adc_start_en: 1; /*Set this bit to enable the function that ADC mode is triggered by external signal.*/
uint32_t inter_valid_en: 1; /*Set this bit to enable camera internal valid*/
uint32_t cam_sync_fifo_reset: 1; /*Set this bit to reset cam_sync_fifo*/
uint32_t cam_clk_loopback: 1; /*Set this bit to loopback cam_clk from i2s_rx*/
uint32_t i_v_sync_filter_en: 1;
uint32_t i_v_sync_filter_thres: 3;
uint32_t reserved14: 18;
@ -427,57 +363,31 @@ typedef volatile struct {
} conf2;
union {
struct {
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
uint32_t reserved23: 9;
};
uint32_t val;
} clkm_conf;
union {
struct {
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t tx_bits_mod: 6; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t rx_bits_mod: 6; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
uint32_t tx_bits_mod: 6; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t rx_bits_mod: 6; /*Set the bits to configure bit length of I2S receiver channel.*/
uint32_t reserved24: 8;
};
uint32_t val;
} sample_rate_conf;
uint32_t reserved_b4;
uint32_t reserved_b8;
union {
struct {
uint32_t tx_pdm_en: 1; /*Set this bit to enable transmitter PDM mode*/
uint32_t rx_pdm_en: 1; /*Set this bit to enable receiver PDM mode*/
uint32_t pcm2pdm_conv_en: 1; /*Set this bit to enable PCM-to-PDM converter*/
uint32_t pdm2pcm_conv_en: 1; /*Set this bit to enable PDM-to-PCM converter*/
uint32_t tx_sinc_osr2: 4; /*upsample rate = 64 * reg_tx_pdm_sinc_osr2*/
uint32_t tx_prescale: 8; /*set to 0*/
uint32_t tx_hp_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_lp_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_sinc_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t tx_sigmadelta_in_shift: 2; /*Adjust size of input signal to filter module. 0: divided by 2 1:multiplied by 1 2:multiplied by 2 3:multiplied by 4*/
uint32_t rx_sinc_dsr_16_en: 1; /*PDM down-sampling rate for filter group1 in receiver mode. 0: downsample rate = 64 1:downsample rate = 128*/
uint32_t txhp_bypass: 1; /*Set this bit to enable tx pdm hp filter bypass*/
uint32_t tx_chan_mod: 2; /*pdm tx channel mode*/
uint32_t tx_way_mode: 2; /*0/1 pdm rx use one-way*/
uint32_t rx_way_mode: 2; /*0/1 pdm rx use one-way*/
};
uint32_t val;
} pdm_conf;
union {
struct {
uint32_t tx_pdm_fs: 10; /*PCM-to-PDM converter PCM frequency parameter*/
uint32_t tx_pdm_fp: 10; /*PCM-to-PDM converter PDM frequency parameter*/
uint32_t reserved20:12;
};
uint32_t val;
} pdm_freq_conf;
union {
struct {
uint32_t tx_idle: 1; /*1: i2s_tx is idle state*/
uint32_t reserved1: 31;
uint32_t tx_idle: 1;
uint32_t reserved1: 31; /*1: i2s_tx is idle state*/
};
uint32_t val;
} state;
@ -496,12 +406,14 @@ typedef volatile struct {
uint32_t reserved_f0;
uint32_t reserved_f4;
uint32_t reserved_f8;
uint32_t date; /**/
uint32_t date; /**/
} i2s_dev_t;
extern i2s_dev_t I2S0;
extern i2s_dev_t I2S1;
_Static_assert(sizeof(i2s_dev_t)==0x100, "invalid i2s_dev_t size");
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2S_STRUCT_H_ */
#endif /* _SOC_I2S_STRUCT_H_ */

4
tools/sdk/esp32s2/include/soc/soc/esp32s2/include/soc/soc_caps.h
View File

@ -5,4 +5,6 @@
#pragma once
#define SOC_CPU_CORES_NUM 1
#define SOC_CPU_CORES_NUM 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1

9
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_hal.h
View File

@ -61,6 +61,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
/**
* Sets the number of interval clock cycles for the digital controller to trigger the measurement.
* Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
*
* @note The trigger interval should not be less than the sampling time of the SAR ADC.
* @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095.
@ -80,9 +81,9 @@ void adc_hal_digi_disable(void);
/**
* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
* Enable clock and select clock source for ADC digital controller.
* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*
* @param clk Refer to `adc_digi_clk_t`.
* @param clk Refer to ``adc_digi_clk_t``.
*/
void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);
@ -133,7 +134,7 @@ void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);
*
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
* @param adc_n ADC unit.
* @param config Refer to `adc_digi_monitor_t`.
* @param config Refer to ``adc_digi_monitor_t``.
*/
void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config);
@ -223,7 +224,7 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
* @note Default priority: Wi-Fi > RTC > Digital;
*
* @param config Refer to `adc_arbiter_t`.
* @param config Refer to ``adc_arbiter_t``.
*/
void adc_hal_arbiter_config(adc_arbiter_t *config);

149
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_ll.h
View File

@ -1,11 +1,13 @@
#pragma once
#include <stdbool.h>
#include "soc/adc_periph.h"
#include "hal/adc_types.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include <stdbool.h>
#include "soc/rtc_cntl_reg.h"
#include "i2c_rtc_clk.h"
#ifdef __cplusplus
extern "C" {
@ -51,7 +53,7 @@ typedef struct {
/**
* @brief ADC controller type selection.
*
*
* @note For ADC2, use the force option with care. The system power consumption detection will use ADC2.
* If it is forced to switch to another controller, it may cause the system to obtain incorrect values.
* @note Normally, there is no need to switch the controller manually.
@ -67,6 +69,49 @@ typedef enum {
ADC2_CTRL_FORCE_DIG = 6, /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
} adc_controller_t;
/* ADC calibration defines. */
#define ADC_LL_I2C_ADC 0X69
#define ADC_LL_I2C_ADC_HOSTID 0
#define ADC_LL_ANA_CONFIG2_REG 0x6000E048
#define ADC_LL_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_LL_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_LL_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_LL_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_LL_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_LL_SAR2_ENCAL_GND_ADDR_LSB 7
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_LL_SAR1_DREF_ADDR 0x2
#define ADC_LL_SAR1_DREF_ADDR_MSB 0x6
#define ADC_LL_SAR1_DREF_ADDR_LSB 0x4
#define ADC_LL_SAR2_DREF_ADDR 0x5
#define ADC_LL_SAR2_DREF_ADDR_MSB 0x6
#define ADC_LL_SAR2_DREF_ADDR_LSB 0x4
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
/* ADC calibration defines end. */
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
@ -89,15 +134,21 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
}
/**
* Set adc sample cycle for digital controller.
* Set adc sample cycle.
*
* @note Normally, please use default value.
* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
* Range: 2 ~ 0xFF.
* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
*/
static inline void adc_ll_digi_set_sample_cycle(uint32_t sample_cycle)
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
{
APB_SARADC.fsm.sample_cycle = sample_cycle;
/* Should be called before writing I2C registers. */
void phy_get_romfunc_addr(void);
phy_get_romfunc_addr();
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
}
/**
@ -263,6 +314,7 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
/**
* Sets the number of interval clock cycles for the digital controller to trigger the measurement.
* Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
*
* @note The trigger interval should not be less than the sampling time of the SAR ADC.
* @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095.
@ -292,11 +344,11 @@ static inline void adc_ll_digi_trigger_disable(void)
/**
* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*
* @param div_num Division factor. Range: 1 ~ 255.
* @param div_num Division factor. Range: 0 ~ 255.
* @param div_b Division factor. Range: 1 ~ 63.
* @param div_a Division factor. Range: 1 ~ 63.
* @param div_a Division factor. Range: 0 ~ 63.
*/
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
@ -1027,7 +1079,7 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_controller_t ct
* @note Only ADC2 support arbiter.
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
*
* @param mode Refer to `adc_arbiter_mode_t`.
* @param mode Refer to ``adc_arbiter_mode_t``.
*/
static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode)
{
@ -1092,7 +1144,7 @@ static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig,
* In sleep mode, the arbiter is in power-down mode.
* Need to switch the controller to RTC to shield the control of the arbiter.
* After waking up, it needs to switch to arbiter control.
*
*
* @note The hardware will do this automatically. In normal use, there is no need to call this interface to manually switch the controller.
* @note Only support ADC2.
*/
@ -1116,47 +1168,6 @@ static inline void adc_ll_disable_sleep_controller(void)
}
/* ADC calibration code. */
#include "soc/rtc_cntl_reg.h"
#include "i2c_rtc_clk.h"
#define I2C_ADC 0X69
#define I2C_ADC_HOSTID 0
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M (BIT(18))
#define SAR1_ENCAL_GND_ADDR 0x7
#define SAR1_ENCAL_GND_ADDR_MSB 5
#define SAR1_ENCAL_GND_ADDR_LSB 5
#define SAR2_ENCAL_GND_ADDR 0x7
#define SAR2_ENCAL_GND_ADDR_MSB 7
#define SAR2_ENCAL_GND_ADDR_LSB 7
#define SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define SAR1_DREF_ADDR 0x2
#define SAR1_DREF_ADDR_MSB 0x6
#define SAR1_DREF_ADDR_LSB 0x4
#define SAR2_DREF_ADDR 0x5
#define SAR2_DREF_ADDR_MSB 0x6
#define SAR2_DREF_ADDR_LSB 0x4
/**
* Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration.
*
@ -1169,28 +1180,28 @@ static inline void adc_ll_disable_sleep_controller(void)
*/
static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
{
/* Enable i2s_write_reg function. */
/* Should be called before writing I2C registers. */
void phy_get_romfunc_addr(void);
phy_get_romfunc_addr();
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
/* Enable/disable internal connect GND (for calibration). */
if (adc_n == ADC_NUM_1) {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_DREF_ADDR, 4);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 4);
if (internal_gnd) {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_ENCAL_GND_ADDR, 1);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 1);
} else {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
}
} else {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_DREF_ADDR, 4);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 4);
if (internal_gnd) {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_ENCAL_GND_ADDR, 1);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 1);
} else {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
}
}
}
@ -1203,9 +1214,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
{
if (adc_n == ADC_NUM_1) {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_ENCAL_GND_ADDR, 0);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
} else {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_ENCAL_GND_ADDR, 0);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
}
}
@ -1220,19 +1231,19 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
{
uint8_t msb = param >> 8;
uint8_t lsb = param & 0xFF;
/* Enable i2s_write_reg function. */
/* Should be called before writing I2C registers. */
void phy_get_romfunc_addr(void);
phy_get_romfunc_addr();
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
if (adc_n == ADC_NUM_1) {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_INITIAL_CODE_HIGH_ADDR, msb);
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR1_INITIAL_CODE_LOW_ADDR, lsb);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
} else {
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_INITIAL_CODE_HIGH_ADDR, msb);
I2C_WRITEREG_MASK_RTC(I2C_ADC, SAR2_INITIAL_CODE_LOW_ADDR, lsb);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
}
}
/* Temp code end. */

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cpu_ll.h
View File

@ -110,7 +110,7 @@ static inline void cpu_ll_set_watchpoint(int id,
//We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
for (int x = 0; x < 7; x++) {
if (size == (1 << x)) {
if (size == (size_t)(1 << x)) {
break;
}
dbreakc <<= 1;

12
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/dac_ll.h
View File

@ -86,6 +86,18 @@ static inline void dac_ll_rtc_reset(void)
SENS.sar_dac_ctrl1.dac_reset = 0;
}
/**
* Enable/disable the synchronization operation function of ADC1 and DAC.
*
* @note If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
*
* @param enable Enable or disable adc and dac synchronization function.
*/
static inline void dac_ll_rtc_sync_by_adc(bool enable)
{
SENS.sar_amp_ctrl3.sar1_dac_xpd_fsm = enable;
}
/************************************/
/* DAC cosine wave generator API's */
/************************************/

132
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/i2s_ll.h
View File

@ -529,50 +529,6 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val)
hw->conf2.camera_en = val;
}
/**
* @brief Set I2S tx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx msb shift
*/
static inline void i2s_ll_set_tx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_msb_shift = val;
}
/**
* @brief Set I2S rx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx msb shift
*/
static inline void i2s_ll_set_rx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_msb_shift = val;
}
/**
* @brief Set I2S tx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx short sync
*/
static inline void i2s_ll_set_tx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_short_sync = val;
}
/**
* @brief Set I2S rx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx short sync
*/
static inline void i2s_ll_set_rx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_short_sync = val;
}
/**
* @brief Set I2S tx fifo mod force en
*
@ -716,6 +672,94 @@ static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val)
hw->conf.sig_loopback = val;
}
/**
* @brief Set I2S TX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 1;
}
/**
* @brief Set I2S RX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 1;
}
/**
* @brief Set I2S TX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 1;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 1;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
#ifdef __cplusplus
}
#endif

6
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rmt_ll.h
View File

@ -21,6 +21,9 @@ extern "C" {
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
#define RMT_LL_HW_BASE (&RMT)
#define RMT_LL_MEM_BASE (&RMTMEM)
static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
{
dev->apb_conf.clk_en = enable; // register clock gating
@ -367,9 +370,10 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan
dev->conf_ch[channel].conf0.carrier_eff_en = !enable;
}
//Writes items to the specified TX channel memory with the given offset and writen length.
//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS)
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
{
length = (off + length) > SOC_RMT_CHANNEL_MEM_WORDS ? (SOC_RMT_CHANNEL_MEM_WORDS - off) : length;
for (uint32_t i = 0; i < length; i++) {
mem->chan[channel].data32[i + off].val = data[i].val;
}

6
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_hal.h
View File

@ -202,14 +202,14 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info);
* Set filter mode. The input to the filter is raw data and the output is the baseline value.
* Larger filter coefficients increase the stability of the baseline.
*
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
*/
#define touch_hal_filter_set_filter_mode(mode) touch_ll_filter_set_filter_mode(mode)
/**
* Get filter mode. The input to the filter is raw data and the output is the baseline value.
*
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
*/
#define touch_hal_filter_get_filter_mode(mode) touch_ll_filter_get_filter_mode(mode)
@ -566,7 +566,7 @@ void touch_hal_sleep_channel_get_config(touch_pad_sleep_channel_t *slp_config);
* After the sleep channel is configured, users should query the channel reading using a specific function.
*
* @note ESP32S2 only support one channel to be set sleep channel.
*
*
* @param pad_num touch sleep pad number.
* @param enable Enable/disable sleep pad function.
*/

8
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_ll.h
View File

@ -669,7 +669,7 @@ static inline void touch_ll_filter_reset_baseline(touch_pad_t touch_num)
* Set filter mode. The input to the filter is raw data and the output is the baseline value.
* Larger filter coefficients increase the stability of the baseline.
*
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
*/
static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
{
@ -679,7 +679,7 @@ static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
/**
* Get filter mode. The input to the filter is raw data and the output is the baseline value.
*
* @param mode Filter mode type. Refer to `touch_filter_mode_t`.
* @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
*/
static inline void touch_ll_filter_get_filter_mode(touch_filter_mode_t *mode)
{
@ -690,7 +690,7 @@ static inline void touch_ll_filter_get_filter_mode(touch_filter_mode_t *mode)
* Set filter mode. The input to the filter is raw data and the output is the smooth data.
* The smooth data is used to determine the touch status.
*
* @param mode Filter mode type. Refer to `touch_smooth_mode_t`.
* @param mode Filter mode type. Refer to ``touch_smooth_mode_t``.
*/
static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
{
@ -700,7 +700,7 @@ static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
/**
* Get filter mode. The smooth data is used to determine the touch status.
*
* @param mode Filter mode type. Refer to `touch_smooth_mode_t`.
* @param mode Filter mode type. Refer to ``touch_smooth_mode_t``.
*/
static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
{