feedc0de/arduino-esp32
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Update IDF Libs

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This commit is contained in:
me-no-dev
2020-06-28 15:38:58 +03:00
parent 7611f483ae
commit 47b34df897
259 changed files with 1671 additions and 836 deletions
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8
platform.txt
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File diff suppressed because one or more lines are too long

41
tools/esptool.py
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@ -257,6 +257,8 @@ class ESPLoader(object):
with ones which throw NotImplementedInROMError().
"""
self.secure_download_mode = False # flag is set to True if esptool detects the ROM is in Secure Download Mode
if isinstance(port, basestring):
self._port = serial.serial_for_url(port)
else:
@ -309,6 +311,9 @@ class ESPLoader(object):
inst = cls(detect_port._port, baud, trace_enabled=trace_enabled)
print(' %s' % inst.CHIP_NAME, end='')
return inst
except UnsupportedCommandError:
raise FatalError("Unsupported Command Error received. Probably this means Secure Download Mode is enabled, " +
"autodetection will not work. Need to manually specify the chip.")
finally:
print('') # end line
raise FatalError("Unexpected UART datecode value 0x%08x. Failed to autodetect chip type." % (date_reg))
@ -381,7 +386,8 @@ class ESPLoader(object):
if op is None or op_ret == op:
return val, data
if byte(data, 0) != 0 and byte(data, 1) == self.ROM_INVALID_RECV_MSG:
raise UnsupportedCommandError()
self.flush_input() # Unsupported read_reg can result in more than one error response for some reason
raise UnsupportedCommandError(self)
finally:
if new_timeout != saved_timeout:
@ -515,6 +521,7 @@ class ESPLoader(object):
raise FatalError('Failed to connect to %s: %s' % (self.CHIP_NAME, last_error))
if not detecting:
try:
# check the date code registers match what we expect to see
date_reg = self.read_reg(self.UART_DATE_REG_ADDR)
date_reg2 = self.read_reg(self.UART_DATE_REG2_ADDR)
@ -529,6 +536,8 @@ class ESPLoader(object):
"Probably it is unsupported by this version of esptool.") % (self.CHIP_NAME, date_reg, date_reg2))
else:
raise FatalError("This chip is %s not %s. Wrong --chip argument?" % (actually.CHIP_NAME, self.CHIP_NAME))
except UnsupportedCommandError:
self.secure_download_mode = True
def read_reg(self, addr):
""" Read memory address in target """
@ -1497,7 +1506,12 @@ class ESP32S2ROM(ESP32ROM):
return "ESP32-S2"
def get_chip_features(self):
return ["WiFi"]
result = ["WiFi"]
if self.secure_download_mode:
result.append("Secure Download Mode Enabled")
return result
def get_crystal_freq(self):
# ESP32-S2 XTAL is fixed to 40MHz
@ -1549,6 +1563,7 @@ class ESP32StubLoader(ESP32ROM):
IS_STUB = True
def __init__(self, rom_loader):
self.secure_download_mode = rom_loader.secure_download_mode
self._port = rom_loader._port
self._trace_enabled = rom_loader._trace_enabled
self.flush_input() # resets _slip_reader
@ -1568,6 +1583,7 @@ class ESP32S2StubLoader(ESP32S2ROM):
IS_STUB = True
def __init__(self, rom_loader):
self.secure_download_mode = rom_loader.secure_download_mode
self._port = rom_loader._port
self._trace_enabled = rom_loader._trace_enabled
self.flush_input() # resets _slip_reader
@ -2433,10 +2449,14 @@ class UnsupportedCommandError(FatalError):
"""
Wrapper class for when ROM loader returns an invalid command response.
Usually this indicates the loader is running in a reduced mode.
Usually this indicates the loader is running in Secure Download Mode.
"""
def __init__(self):
FatalError.__init__(self, "Invalid (unsupported) command")
def __init__(self, esp):
if esp.secure_download_mode:
msg = "This command is not supported in Secure Download Mode"
else:
msg = "Invalid (unsupported) command"
FatalError.__init__(self, msg)
def load_ram(esp, args):
@ -2484,6 +2504,8 @@ def dump_mem(esp, args):
def detect_flash_size(esp, args):
if args.flash_size == 'detect':
if esp.secure_download_mode:
raise FatalError("Detecting flash size is not supported in secure download mode. Need to manually specify flash size.")
flash_id = esp.flash_id()
size_id = flash_id >> 16
args.flash_size = DETECTED_FLASH_SIZES.get(size_id)
@ -2644,7 +2666,7 @@ def write_flash(esp, args):
speed_msg = " (%.1f kbit/s)" % (written / t * 8 / 1000)
print_overwrite('Wrote %d bytes at 0x%08x in %.1f seconds%s...' % (written, address, t, speed_msg), last_line=True)
if not args.encrypt:
if not args.encrypt and not esp.secure_download_mode:
try:
res = esp.flash_md5sum(address, uncsize)
if res != calcmd5:
@ -3186,9 +3208,16 @@ def main(custom_commandline=None):
print("Crystal is %dMHz" % esp.get_crystal_freq())
try:
read_mac(esp, args)
except UnsupportedCommandError:
pass # can't get this data in Secure Download Mode
if not args.no_stub:
if esp.secure_download_mode:
print("WARNING: Stub loader is not supported in Secure Download Mode, setting --no-stub")
args.no_stub = True
else:
esp = esp.run_stub()
if args.override_vddsdio:

5
tools/platformio-build-esp32.py
View File

@ -131,6 +131,7 @@ env.Append(
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "efuse", "esp32", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "espcoredump", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_timer", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "esp_ipc", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "soc", "esp32"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "soc", "esp32", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32", "include", "soc", "soc", "include"),
@ -214,7 +215,7 @@ env.Append(
],
LIBS=[
"-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lbt", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lspiffs", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lbt", "-lbtdm_app", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc"
"-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lbt", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_adc_cal", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lspiffs", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lbt", "-lbtdm_app", "-lesp_adc_cal", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lperfmon", "-lesp32", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc"
],
CPPDEFINES=[
@ -223,7 +224,7 @@ env.Append(
"UNITY_INCLUDE_CONFIG_H",
"WITH_POSIX",
"_GNU_SOURCE",
("IDF_VER", '\\"v4.2-dev-1660-g7d7521367\\"'),
("IDF_VER", '\\"v4.2-dev-1905-g625bd5eb1-dirty\\"'),
"ESP_PLATFORM",
"ARDUINO_ARCH_ESP32",
"ESP32",

5
tools/platformio-build-esp32s2.py
View File

@ -126,6 +126,7 @@ env.Append(
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "efuse", "esp32s2", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "espcoredump", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_timer", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "esp_ipc", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "soc", "esp32s2"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "soc", "esp32s2", "include"),
join(FRAMEWORK_DIR, "tools", "sdk", "esp32s2", "include", "soc", "soc", "include"),
@ -212,7 +213,7 @@ env.Append(
],
LIBS=[
"-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lperfmon", "-lspiffs", "-ltinyusb", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_https_server", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lperfmon", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-ltinyusb", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc"
"-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lasio", "-lcbor", "-lcoap", "-lconsole", "-lnghttp", "-lesp-tls", "-lesp_gdbstub", "-lesp_hid", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lesp_https_ota", "-lesp_https_server", "-lprotobuf-c", "-lprotocomm", "-lmdns", "-lesp_local_ctrl", "-lsdmmc", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lwear_levelling", "-lfatfs", "-lfreemodbus", "-ljsmn", "-ljson", "-llibsodium", "-lmqtt", "-lopenssl", "-lperfmon", "-lspiffs", "-ltinyusb", "-lulp", "-lunity", "-lwifi_provisioning", "-lfb_gfx", "-lasio", "-lcbor", "-lcoap", "-lesp_gdbstub", "-lesp_hid", "-lesp_https_ota", "-lesp_local_ctrl", "-lesp_https_server", "-lesp_serial_slave_link", "-lesp_websocket_client", "-lexpat", "-lfreemodbus", "-ljsmn", "-llibsodium", "-lmqtt", "-lperfmon", "-lunity", "-lwifi_provisioning", "-lprotocomm", "-lprotobuf-c", "-ljson", "-lfb_gfx", "-lmdns", "-lconsole", "-lfatfs", "-lsdmmc", "-lwear_levelling", "-lopenssl", "-lspiffs", "-ltinyusb", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lxtensa", "-lmbedtls", "-lefuse", "-lbootloader_support", "-lapp_update", "-lesp_ipc", "-lspi_flash", "-lesp_system", "-lsoc", "-lvfs", "-lesp_eth", "-ltcpip_adapter", "-lesp_netif", "-lesp_event", "-lwpa_supplicant", "-lnvs_flash", "-lesp_wifi", "-llwip", "-llog", "-lheap", "-lesp_ringbuf", "-ldriver", "-lpthread", "-lespcoredump", "-lesp32s2", "-lesp_common", "-lesp_timer", "-lfreertos", "-lnewlib", "-lcxx", "-lapp_trace", "-lnghttp", "-lesp-tls", "-ltcp_transport", "-lesp_http_client", "-lesp_http_server", "-lulp", "-lmbedtls", "-lmbedcrypto", "-lmbedx509", "-lsoc_esp32s2", "-lcoexist", "-lcore", "-lespnow", "-lmesh", "-lnet80211", "-lpp", "-lrtc", "-lsmartconfig", "-lphy", "-lhal", "-lm", "-lnewlib", "-lgcc", "-lstdc++", "-lpthread", "-lapp_trace", "-lgcov", "-lapp_trace", "-lgcov", "-lc"
],
CPPDEFINES=[
@ -221,7 +222,7 @@ env.Append(
"UNITY_INCLUDE_CONFIG_H",
"WITH_POSIX",
"_GNU_SOURCE",
("IDF_VER", '\\"v4.2-dev-1660-g7d7521367-dirty\\"'),
("IDF_VER", '\\"v4.2-dev-1905-g625bd5eb1-dirty\\"'),
"ESP_PLATFORM",
("CFG_TUSB_MCU", 'OPT_MCU_ESP32_S2'),
"ARDUINO_ARCH_ESP32",

BIN
tools/sdk/esp32/bin/bootloader_dio_40m.bin
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tools/sdk/esp32/bin/bootloader_dio_80m.bin
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tools/sdk/esp32/bin/bootloader_dout_40m.bin
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tools/sdk/esp32/bin/bootloader_dout_80m.bin
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tools/sdk/esp32/bin/bootloader_qio_40m.bin
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tools/sdk/esp32/bin/bootloader_qio_80m.bin
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tools/sdk/esp32/bin/bootloader_qout_40m.bin
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tools/sdk/esp32/bin/bootloader_qout_80m.bin
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23
tools/sdk/esp32/include/app_update/include/esp_ota_ops.h
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@ -117,6 +117,29 @@ esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp
*/
esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);
/**
* @brief Write OTA update data to partition
*
* This function can write data in non contiguous manner.
* If flash encryption is enabled, data should be 16 byte aligned.
*
* @param handle Handle obtained from esp_ota_begin
* @param data Data buffer to write
* @param size Size of data buffer in bytes
* @param offset Offset in flash partition
*
* @note While performing OTA, if the packets arrive out of order, esp_ota_write_with_offset() can be used to write data in non contiguous manner.
* Use of esp_ota_write_with_offset() in combination with esp_ota_write() is not recommended.
*
* @return
* - ESP_OK: Data was written to flash successfully.
* - ESP_ERR_INVALID_ARG: handle is invalid.
* - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
* - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
* - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
*/
esp_err_t esp_ota_write_with_offset(esp_ota_handle_t handle, const void *data, size_t size, uint32_t offset);
/**
* @brief Finish OTA update and validate newly written app image.
*

4
tools/sdk/esp32/include/bootloader_support/include/esp_flash_encrypt.h
View File

@ -128,6 +128,10 @@ esp_err_t esp_flash_encrypt_region(uint32_t src_addr, size_t data_length);
* is enabled but secure boot is not used. This should protect against
* serial re-flashing of an unauthorised code in absence of secure boot.
*
* @note On ESP32 V3 only, write protecting FLASH_CRYPT_CNT will also prevent
* disabling UART Download Mode. If both are wanted, call
* esp_efuse_disable_rom_download_mode() before calling this function.
*
*/
void esp_flash_write_protect_crypt_cnt(void);

10
tools/sdk/esp32/include/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h
View File

@ -977,6 +977,16 @@ esp_err_t esp_ble_gap_config_local_icon (uint16_t icon);
*/
esp_err_t esp_ble_gap_update_whitelist(bool add_remove, esp_bd_addr_t remote_bda, esp_ble_wl_addr_type_t wl_addr_type);
/**
* @brief Clear all white list
*
* @return
* - ESP_OK : success
* - other : failed
*
*/
esp_err_t esp_ble_gap_clear_whitelist(void);
/**
* @brief Get the whitelist size in the controller
*

2
tools/sdk/esp32/include/config/sdkconfig.h
View File

@ -22,6 +22,7 @@
#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x0
#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
#define CONFIG_ESPTOOLPY_WITH_STUB 1
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1
@ -187,6 +188,7 @@
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT_OFFSET 2
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ETH_ENABLED 1
#define CONFIG_ETH_USE_ESP32_EMAC 1

6
tools/sdk/esp32/include/driver/include/driver/adc_common.h
View File

@ -158,7 +158,7 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit);
* When enabling power for any of these peripherals, ignore input from GPIO36 and GPIO39.
* Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
*
* @note Call adc1_config_width() before the first time this
* @note Call ``adc1_config_width()`` before the first time this
* function is called.
*
* @note For any given channel, adc1_config_channel_atten(channel)
@ -230,9 +230,9 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit);
* @brief Configure ADC1 to be usable by the ULP
*
* This function reconfigures ADC1 to be controlled by the ULP.
* Effect of this function can be reverted using adc1_get_raw function.
* Effect of this function can be reverted using ``adc1_get_raw()`` function.
*
* Note that adc1_config_channel_atten, adc1_config_width functions need
* Note that adc1_config_channel_atten, ``adc1_config_width()`` functions need
* to be called to configure ADC1 channels, before ADC1 is used by the ULP.
*/
void adc1_ulp_enable(void);

6
tools/sdk/esp32/include/driver/include/driver/i2s.h
View File

@ -1,4 +1,4 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -33,6 +33,8 @@
extern "C" {
#endif
#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
typedef intr_handle_t i2s_isr_handle_t;
/**
@ -194,7 +196,7 @@ esp_err_t i2s_write_expand(i2s_port_t i2s_num, const void *src, size_t size, siz
*
* @param ticks_to_wait RX buffer wait timeout in RTOS ticks. If this many ticks pass without bytes becoming available in the DMA receive buffer, then the function will return (note that if data is read from the DMA buffer in pieces, the overall operation may still take longer than this timeout.) Pass portMAX_DELAY for no timeout.
*
* @note If the built-in ADC mode is enabled, we should call i2s_adc_start and i2s_adc_stop around the whole reading process,
* @note If the built-in ADC mode is enabled, we should call i2s_adc_enable and i2s_adc_disable around the whole reading process,
* to prevent the data getting corrupted.
*
* @return

5
tools/sdk/esp32/include/efuse/esp32/include/esp_efuse_table.h
View File

@ -17,7 +17,7 @@ extern "C" {
#endif
// md5_digest_table 2e23344575b3d07f01ecb695294e9770
// md5_digest_table 11b691b6fa8546a3862a7a876be5f758
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -36,9 +36,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_DOWNLOAD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[];

74
tools/sdk/esp32/include/efuse/include/esp_efuse.h
View File

@ -21,6 +21,7 @@ extern "C" {
#include <stdint.h>
#include "esp_err.h"
#include "esp_log.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/esp_efuse.h"
@ -66,6 +67,23 @@ typedef struct esp_efuse_desc_s esp_efuse_desc_t;
*/
esp_err_t esp_efuse_read_field_blob(const esp_efuse_desc_t* field[], void* dst, size_t dst_size_bits);
/**
* @brief Read a single bit eFuse field as a boolean value.
*
* @note The value must exist and must be a single bit wide. If there is any possibility of an error
* in the provided arguments, call esp_efuse_read_field_blob() and check the returned value instead.
*
* @note If assertions are enabled and the parameter is invalid, execution will abort
*
* @param[in] field A pointer to the structure describing the fields of efuse.
* @return
* - true: The field parameter is valid and the bit is set.
* - false: The bit is not set, or the parameter is invalid and assertions are disabled.
*
*/
bool esp_efuse_read_field_bit(const esp_efuse_desc_t *field[]);
/**
* @brief Reads bits from EFUSE field and returns number of bits programmed as "1".
*
@ -114,6 +132,23 @@ esp_err_t esp_efuse_write_field_blob(const esp_efuse_desc_t* field[], const void
*/
esp_err_t esp_efuse_write_field_cnt(const esp_efuse_desc_t* field[], size_t cnt);
/**
* @brief Write a single bit eFuse field to 1
*
* For use with eFuse fields that are a single bit. This function will write the bit to value 1 if
* it is not already set, or does nothing if the bit is already set.
*
* This is equivalent to calling esp_efuse_write_field_cnt() with the cnt parameter equal to 1,
* except that it will return ESP_OK if the field is already set to 1.
*
* @param[in] field Pointer to the structure describing the efuse field.
*
* @return
* - ESP_OK: The operation was successfully completed, or the bit was already set to value 1.
* - ESP_ERR_INVALID_ARG: Error in the passed arugments, including if the efuse field is not 1 bit wide.
*/
esp_err_t esp_efuse_write_field_bit(const esp_efuse_desc_t* field[]);
/**
* @brief Sets a write protection for the whole block.
*
@ -274,15 +309,48 @@ void esp_efuse_reset(void);
* By default, if booting from flash fails the ESP32 will boot a
* BASIC console in ROM.
*
* Call this function (from bootloader or app) to permanently
* disable the console on this chip.
*
* Call this function (from bootloader or app) to permanently disable the console on this chip.
*
*/
void esp_efuse_disable_basic_rom_console(void);
#endif
/* @brief Disable ROM Download Mode via eFuse
*
* Permanently disables the ROM Download Mode feature. Once disabled, if the SoC is booted with
* strapping pins set for ROM Download Mode then an error is printed instead.
*
* @note Not all SoCs support this option. An error will be returned if called on an ESP32
* with a silicon revision lower than 3, as these revisions do not support this option.
*
* @note If ROM Download Mode is already disabled, this function does nothing and returns success.
*
* @return
* - ESP_OK If the eFuse was successfully burned, or had already been burned.
* - ESP_ERR_NOT_SUPPORTED (ESP32 only) This SoC is not capable of disabling UART download mode
* - ESP_ERR_INVALID_STATE (ESP32 only) This eFuse is write protected and cannot be written
*/
esp_err_t esp_efuse_disable_rom_download_mode(void);
#if SOC_SUPPORTS_SECURE_DL_MODE
/* @brief Switch ROM Download Mode to Secure Download mode via eFuse
*
* Permanently enables Secure Download mode. This mode limits the use of ROM Download Mode functions
* to simple flash read, write and erase operations, plus a command to return a summary of currently
* enabled security features.
*
* @note If Secure Download mode is already enabled, this function does nothing and returns success.
*
* @note Disabling the ROM Download Mode also disables Secure Download Mode.
*
* @return
* - ESP_OK If the eFuse was successfully burned, or had already been burned.
* - ESP_ERR_INVALID_STATE ROM Download Mode has been disabled via eFuse, so Secure Download mode is unavailable.
*/
esp_err_t esp_efuse_enable_rom_secure_download_mode(void);
#endif
/* @brief Write random data to efuse key block write registers
*
* @note Caller is responsible for ensuring efuse

10
tools/sdk/esp32/include/esp_common/include/esp_crc.h
View File

@ -24,6 +24,10 @@ extern "C" {
#include "esp32/rom/crc.h"
#endif
#if defined(CONFIG_IDF_TARGET_ESP32S2)
#include "esp32s2/rom/crc.h"
#endif
/******************* Polynomials Used in the CRC APIs ****************************
* CRC-8 x8+x2+x1+1 0x07
* CRC16-CCITT x16+x12+x5+1 0x1021
@ -43,6 +47,7 @@ static inline uint32_t esp_crc32_le(uint32_t crc, uint8_t const *buf, uint32_t l
return crc32_le(crc, buf, len);
}
#if defined(CONFIG_IDF_TARGET_ESP32)
/**
* @brief CRC32 value in big endian.
*
@ -55,6 +60,7 @@ static inline uint32_t esp_crc32_be(uint32_t crc, uint8_t const *buf, uint32_t l
{
return crc32_be(crc, buf, len);
}
#endif
/**
* @brief CRC16 value in little endian.
@ -69,6 +75,7 @@ static inline uint16_t esp_crc16_le(uint16_t crc, uint8_t const *buf, uint32_t l
return crc16_le(crc, buf, len);
}
#if defined(CONFIG_IDF_TARGET_ESP32)
/**
* @brief CRC16 value in big endian.
*
@ -81,6 +88,7 @@ static inline uint16_t esp_crc16_be(uint16_t crc, uint8_t const *buf, uint32_t l
{
return crc16_be(crc, buf, len);
}
#endif
/**
* @brief CRC8 value in little endian.
@ -95,6 +103,7 @@ static inline uint8_t esp_crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len)
return crc8_le(crc, buf, len);
}
#if defined(CONFIG_IDF_TARGET_ESP32)
/**
* @brief CRC8 value in big endian.
*
@ -107,6 +116,7 @@ static inline uint8_t esp_crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len)
{
return crc8_be(crc, buf, len);
}
#endif
#ifdef __cplusplus
}

1
tools/sdk/esp32/include/esp_eth/include/esp_eth_mac.h
View File

@ -279,6 +279,7 @@ typedef struct {
} eth_mac_config_t;
#define ETH_MAC_FLAG_WORK_WITH_CACHE_DISABLE (1 << 0) /*!< MAC driver can work when cache is disabled */
#define ETH_MAC_FLAG_PIN_TO_CORE (1 << 1) /*!< Pin MAC task to the CPU core where driver installation happened */
/**
* @brief Default configuration for Ethernet MAC object

13
tools/sdk/esp32/include/esp_http_client/include/esp_http_client.h
View File

@ -525,6 +525,19 @@ int esp_http_client_read_response(esp_http_client_handle_t client, char *buffer,
esp_err_t esp_http_client_get_url(esp_http_client_handle_t client, char *url, const int len);
/**
* @brief Get Chunk-Length from client
*
* @param[in] client The esp_http_client handle
* @param[out] len Variable to store length
*
* @return
* - ESP_OK If successful, len will have length of current chunk
* - ESP_FAIL If the server is not a chunked server
* - ESP_ERR_INVALID_ARG If the client or len are NULL
*/
esp_err_t esp_http_client_get_chunk_length(esp_http_client_handle_t client, int *len);
#ifdef __cplusplus
}
#endif

0
tools/sdk/esp32/include/esp_common/include/esp_ipc.h → tools/sdk/esp32/include/esp_ipc/include/esp_ipc.h
View File

1
tools/sdk/esp32/include/esp_wifi/include/esp_wifi_types.h
View File

@ -94,6 +94,7 @@ typedef enum {
WIFI_REASON_ASSOC_FAIL = 203,
WIFI_REASON_HANDSHAKE_TIMEOUT = 204,
WIFI_REASON_CONNECTION_FAIL = 205,
WIFI_REASON_AUTH_CHANGED = 206,
} wifi_err_reason_t;
typedef enum {

5
tools/sdk/esp32/include/lwip/port/esp32/include/lwipopts.h
View File

@ -562,6 +562,11 @@
*/
#define LWIP_TCP_KEEPALIVE 1
/**
* LWIP_SO_LINGER==1: Enable SO_LINGER processing.
*/
#define LWIP_SO_LINGER CONFIG_LWIP_SO_LINGER
/**
* LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
*/

10
tools/sdk/esp32/include/mbedtls/port/include/mbedtls/bignum.h
View File

@ -1,4 +1,4 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -11,10 +11,10 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef __ESP_MBEDTLS_BIGNUM_H__
#define __ESP_MBEDTLS_BIGNUM_H__
#pragma once
#include_next "mbedtls/bignum.h"
#include "sdkconfig.h"
/**
* This is a wrapper for the main mbedtls/bignum.h. This wrapper
@ -58,6 +58,8 @@ void esp_mpi_acquire_hardware(void);
*/
void esp_mpi_release_hardware(void);
#if CONFIG_MBEDTLS_HARDWARE_MPI
/* @brief MPI modular mupltiplication function
*
* Calculates Z = (X * Y) mod M using MPI hardware acceleration.
@ -75,4 +77,4 @@ void esp_mpi_release_hardware(void);
*/
int esp_mpi_mul_mpi_mod(mbedtls_mpi *Z, const mbedtls_mpi *X, const mbedtls_mpi *Y, const mbedtls_mpi *M);
#endif
#endif // CONFIG_MBEDTLS_HARDWARE_MPI

34
tools/sdk/esp32/include/nvs_flash/include/nvs_flash.h
View File

@ -61,6 +61,20 @@ esp_err_t nvs_flash_init(void);
*/
esp_err_t nvs_flash_init_partition(const char *partition_label);
/**
* @brief Initialize NVS flash storage for the partition specified by partition pointer.
*
* @param[in] partition pointer to a partition obtained by the ESP partition API.
*
* @return
* - ESP_OK if storage was successfully initialized
* - ESP_ERR_NVS_NO_FREE_PAGES if the NVS storage contains no empty pages
* (which may happen if NVS partition was truncated)
* - ESP_ERR_INVALID_ARG in case partition is NULL
* - one of the error codes from the underlying flash storage driver
*/
esp_err_t nvs_flash_init_partition_ptr(const esp_partition_t *partition);
/**
* @brief Deinitialize NVS storage for the default NVS partition
*
@ -118,6 +132,26 @@ esp_err_t nvs_flash_erase(void);
*/
esp_err_t nvs_flash_erase_partition(const char *part_name);
/**
* @brief Erase custom partition.
*
* Erase all content of specified custom partition.
*
* @note
* If the partition is initialized, this function first de-initializes it.
* Afterwards, the partition has to be initialized again to be used.
*
* @param[in] partition pointer to a partition obtained by the ESP partition API.
*
* @return
* - ESP_OK on success
* - ESP_ERR_NOT_FOUND if there is no partition with the specified
* parameters in the partition table
* - ESP_ERR_INVALID_ARG in case partition is NULL
* - one of the error codes from the underlying flash storage driver
*/
esp_err_t nvs_flash_erase_partition_ptr(const esp_partition_t *partition);
/**
* @brief Initialize the default NVS partition.
*

20
tools/sdk/esp32/include/nvs_flash/include/nvs_handle.hpp
View File

@ -47,9 +47,11 @@ public:
* @param[in] key Key name. Maximal length is determined by the underlying
* implementation, but is guaranteed to be at least
* 15 characters. Shouldn't be empty.
* @param[in] value The value to set. Allowed types are the ones declared in ItemType.
* @param[in] value The value to set. Allowed types are the ones declared in ItemType as well as enums.
* For strings, the maximum length (including null character) is
* 4000 bytes.
* Note that enums loose their type information when stored in NVS. Ensure that the correct
* enum type is used during retrieval with \ref get_item!
*
* @return
* - ESP_OK if value was set successfully
@ -80,7 +82,9 @@ public:
* @param[in] key Key name. Maximal length is determined by the underlying
* implementation, but is guaranteed to be at least
* 15 characters. Shouldn't be empty.
* @param value The output value.
* @param value The output value. All integral types which are declared in ItemType as well as enums
* are allowed. Note however that enums lost their type information when stored in NVS.
* Ensure that the correct enum type is used during retrieval with \ref get_item!
*
* @return
* - ESP_OK if the value was retrieved successfully
@ -233,12 +237,24 @@ std::unique_ptr<NVSHandle> open_nvs_handle(const char *ns_name,
esp_err_t *err = nullptr);
// Helper functions for template usage
/**
* Help to translate all integral types into ItemType.
*/
template<typename T, typename std::enable_if<std::is_integral<T>::value, void*>::type = nullptr>
constexpr ItemType itemTypeOf()
{
return static_cast<ItemType>(((std::is_signed<T>::value)?0x10:0x00) | sizeof(T));
}
/**
* Help to translate all enum types into integral ItemType.
*/
template<typename T, typename std::enable_if<std::is_enum<T>::value, int>::type = 0>
constexpr ItemType itemTypeOf()
{
return static_cast<ItemType>(((std::is_signed<T>::value)?0x10:0x00) | sizeof(T));
}
template<typename T>
constexpr ItemType itemTypeOf(const T&)
{

7
tools/sdk/esp32/include/soc/include/hal/adc_hal.h
View File

@ -17,13 +17,12 @@ void adc_hal_init(void);
void adc_hal_deinit(void);
/**
* Set adc sample cycle for digital controller.
* Set adc sample cycle.
*
* @note Normally, please use default value.
* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
* Range: 2 ~ 0xFF.
* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
*/
#define adc_hal_digi_set_sample_cycle(sample_cycle) adc_ll_digi_set_sample_cycle(sample_cycle)
#define adc_hal_set_sample_cycle(sample_cycle) adc_ll_set_sample_cycle(sample_cycle)
/**
* Set ADC module power management.

153
tools/sdk/esp32/include/soc/include/hal/adc_types.h
View File

@ -13,7 +13,7 @@ typedef enum {
ADC_UNIT_1 = 1, /*!< SAR ADC 1. */
ADC_UNIT_2 = 2, /*!< SAR ADC 2. */
ADC_UNIT_BOTH = 3, /*!< SAR ADC 1 and 2. */
ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode, not supported yet */
ADC_UNIT_ALTER = 7, /*!< SAR ADC 1 and 2 alternative mode. */
ADC_UNIT_MAX,
} adc_unit_t;
@ -75,29 +75,58 @@ typedef enum {
ADC_WIDTH_MAX,
} adc_bits_width_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: In multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note ESP32S2:
* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val;
};
} adc_digi_output_data_t;
#ifdef CONFIG_IDF_TARGET_ESP32S2
/**
* @brief ADC digital controller (DMA mode) clock system setting.
* Expression: controller_clk = (`APLL` or `APB`) * (div_num + div_b / div_a).
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*/
typedef struct {
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
uint32_t div_num; /*!<Division factor. Range: 1 ~ 255. */
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
Note: When a higher frequency clock is used (the division factor is less than 9),
the ADC reading value will be slightly offset. */
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
} adc_digi_clk_t;
/**
* @brief ADC digital controller (DMA mode) clock system default setting.
*/
#define ADC_DIGITAL_CLK_DEFAULT() { \
.use_apll = 0, \
.div_num = 40, \
.div_b = 1, \
.div_a = 1, \
}
/**
* @brief ADC arbiter work mode option.
*
@ -116,7 +145,7 @@ typedef enum {
* @note ESP32S2: Only ADC2 support arbiter.
*/
typedef struct {
adc_arbiter_mode_t mode; /*!<Refer to `adc_arbiter_mode_t`. Note: only support ADC2. */
adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */
uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
@ -137,7 +166,11 @@ typedef struct {
/**
* @brief ADC digital controller (DMA mode) work mode.
*
* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
* @note The conversion mode affects the sampling frequency:
* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
*/
typedef enum {
ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */
@ -147,42 +180,6 @@ typedef enum {
ADC_CONV_UNIT_MAX,
} adc_digi_convert_mode_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: In multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val;
};
} adc_digi_output_data_t;
/**
* @brief ADC digital controller (DMA mode) conversion rules setting.
*/
@ -212,26 +209,54 @@ typedef enum {
/**
* @brief ADC digital controller (DMA mode) configuration parameters.
*
* Example setting: Use ADC1 channel0 to measure voltage, the sampling rate is required to be 1KHz:
* +---------------------+--------+--------+--------+
* | sample rate | 1KHz | 1KHz | 1KHz |
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* | adc1_pattern_len | 1 | 1 | 1 |
* | dig_clk.use_apll | 0 | 0 | 0 |
* | dig_clk.div_num | 99 | 99 | 99 |
* | dig_clk.div_b | 0 | 0 | 0 |
* | dig_clk.div_a | 0 | 0 | 0 |
* | interval | 400 | 400 | 200 |
* +---------------------+--------+--------+--------+
* | `trigger_meas_freq` | 1KHz | 1KHz | 2KHz |
* +---------------------+--------+--------+--------+
*
* Explain the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA output:
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* +---------------------+--------+--------+--------+
* | trigger meas times | 1 | 1 | 1 |
* +---------------------+--------+--------+--------+
* | conv_limit_num | +1 | +1 | +1 |
* | dma_eof_num | +1 | +2 | +1 |
* | dma output (byte) | +2 | +4 | +2 |
* +---------------------+--------+--------+--------+
*/
typedef struct {
bool conv_limit_en; /*!<Enable max conversion number detection for digital controller.
If the number of ADC conversion is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<ADC max conversion number for digital controller. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16.
bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
uint32_t adc2_pattern_len; /*!<Refer to `adc1_pattern_len` */
uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to ``adc1_pattern`` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
The unit is the divided clock. Range: 40 ~ 4095. */
adc_digi_clk_t dig_clk; /*!<Refer to `adc_digi_clk_t` */
The unit is the divided clock. Range: 40 ~ 4095.
Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t`` */
uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
If the number of measurements reaches `dma_eof_num`,
then `dma_in_suc_eof` signal is generated. */
If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
} adc_digi_config_t;
/**

9
tools/sdk/esp32/include/soc/include/hal/dac_hal.h
View File

@ -39,6 +39,15 @@
*/
#define dac_hal_power_down(channel) dac_ll_power_down(channel)
/**
* Enable/disable the synchronization operation function of ADC1 and DAC.
*
* @note If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
*
* @param enable Enable or disable adc and dac synchronization function.
*/
#define dac_hal_rtc_sync_by_adc(enable) dac_ll_rtc_sync_by_adc(enable)
/**
* Output voltage with value (8 bit).
*

4
tools/sdk/esp32/include/soc/include/hal/gpio_types.h
View File

@ -26,6 +26,8 @@ typedef enum {
GPIO_PORT_MAX,
} gpio_port_t;
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
#define GPIO_SEL_0 (BIT(0)) /*!< Pin 0 selected */
#define GPIO_SEL_1 (BIT(1)) /*!< Pin 1 selected */
#define GPIO_SEL_2 (BIT(2)) /*!< Pin 2 selected */
@ -130,6 +132,8 @@ typedef enum {
#define GPIO_PIN_REG_46 IO_MUX_GPIO46_REG
#endif
/** @endcond */
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */

78
tools/sdk/esp32/include/soc/include/hal/i2s_types.h
View File

@ -1,4 +1,4 @@
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
@ -34,9 +34,6 @@ typedef enum {
I2S_NUM_MAX, /*!< I2S port max */
} i2s_port_t;
#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
/**
* @brief I2S bit width per sample.
*
@ -62,14 +59,21 @@ typedef enum {
*
*/
typedef enum {
I2S_COMM_FORMAT_I2S = 0x01, /*!< I2S communication format I2S*/
I2S_COMM_FORMAT_I2S_MSB = 0x02, /*!< I2S format MSB*/
I2S_COMM_FORMAT_I2S_LSB = 0x04, /*!< I2S format LSB*/
I2S_COMM_FORMAT_PCM = 0x08, /*!< I2S communication format PCM*/
I2S_COMM_FORMAT_PCM_SHORT = 0x10, /*!< PCM Short*/
I2S_COMM_FORMAT_PCM_LONG = 0x20, /*!< PCM Long*/
} i2s_comm_format_t;
// In order to keep compatibility, remain the old definitions and introduce new definitions,
I2S_COMM_FORMAT_STAND_I2S = 0X01, /*!< I2S communication I2S Philips standard, data launch at second BCK*/
I2S_COMM_FORMAT_STAND_MSB = 0X03, /*!< I2S communication MSB alignment standard, data launch at first BCK*/
I2S_COMM_FORMAT_STAND_PCM_SHORT = 0x04, /*!< PCM Short standard*/
I2S_COMM_FORMAT_STAND_PCM_LONG = 0x0C, /*!< PCM Long standard*/
I2S_COMM_FORMAT_STAND_MAX, /*!< standard max*/
//old definition will be removed in the future.
I2S_COMM_FORMAT_I2S __attribute__((deprecated)) = 0x01, /*!< I2S communication format I2S, correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_MSB __attribute__((deprecated)) = 0x01, /*!< I2S format MSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_MSB) correspond to `I2S_COMM_FORMAT_STAND_I2S`*/
I2S_COMM_FORMAT_I2S_LSB __attribute__((deprecated)) = 0x02, /*!< I2S format LSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_LSB) correspond to `I2S_COMM_FORMAT_STAND_MSB`*/
I2S_COMM_FORMAT_PCM __attribute__((deprecated)) = 0x04, /*!< I2S communication format PCM, correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_SHORT __attribute__((deprecated)) = 0x04, /*!< PCM Short, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_SHORT) correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/
I2S_COMM_FORMAT_PCM_LONG __attribute__((deprecated)) = 0x08, /*!< PCM Long, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_LONG) correspond to `I2S_COMM_FORMAT_STAND_PCM_LONG`*/
} i2s_comm_format_t;
/**
* @brief I2S channel format type
@ -82,26 +86,6 @@ typedef enum {
I2S_CHANNEL_FMT_ONLY_LEFT,
} i2s_channel_fmt_t;
#if SOC_I2S_SUPPORTS_PDM
/**
* @brief PDM sample rate ratio, measured in Hz.
*
*/
typedef enum {
PDM_SAMPLE_RATE_RATIO_64,
PDM_SAMPLE_RATE_RATIO_128,
} pdm_sample_rate_ratio_t;
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
PDM_PCM_CONV_ENABLE,
PDM_PCM_CONV_DISABLE,
} pdm_pcm_conv_t;
#endif
/**
* @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
*
@ -109,19 +93,29 @@ typedef enum {
*
*/
typedef enum {
I2S_MODE_MASTER = 1,
I2S_MODE_SLAVE = 2,
I2S_MODE_TX = 4,
I2S_MODE_RX = 8,
I2S_MODE_MASTER = 1, /*!< Master mode*/
I2S_MODE_SLAVE = 2, /*!< Slave mode*/
I2S_MODE_TX = 4, /*!< TX mode*/
I2S_MODE_RX = 8, /*!< RX mode*/
#if SOC_I2S_SUPPORTS_ADC_DAC
I2S_MODE_DAC_BUILT_IN = 16, /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
I2S_MODE_ADC_BUILT_IN = 32, /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/
#endif
#if SOC_I2S_SUPPORTS_PDM
I2S_MODE_PDM = 64,
I2S_MODE_PDM = 64, /*!< PDM mode*/
#endif
} i2s_mode_t;
/**
* @brief I2S source clock
*
*/
typedef enum {
I2S_CLK_D2CLK = 0, /*!< Clock from PLL_D2_CLK(160M)*/
I2S_CLK_APLL, /*!< Clock from APLL*/
} i2s_clock_src_t;
/**
* @brief I2S configuration parameters for i2s_param_config function
*
@ -193,12 +187,16 @@ typedef enum {
I2S_PDM_DSR_16S, /*!< downsampling number is 16 for PDM RX mode*/
I2S_PDM_DSR_MAX,
} i2s_pdm_dsr_t;
#endif
/**
* @brief PDM PCM convter enable/disable.
*
*/
typedef enum {
I2S_CLK_D2CLK = 0,
I2S_CLK_APLL,
} i2s_clock_src_t;
PDM_PCM_CONV_ENABLE, /*!< Enable PDM PCM convert*/
PDM_PCM_CONV_DISABLE, /*!< Disable PDM PCM convert*/
} pdm_pcm_conv_t;
#endif
#ifdef __cplusplus

10
tools/sdk/esp32/include/soc/include/hal/rmt_hal.h
View File

@ -39,13 +39,6 @@ typedef struct {
*/
void rmt_hal_init(rmt_hal_context_t *hal);
/**
* @brief Reset RMT HAL driver
*
* @param hal: RMT HAL context
*/
void rmt_hal_reset(rmt_hal_context_t *hal);
/**
* @brief Reset RMT Channel specific HAL driver
*
@ -133,7 +126,8 @@ uint32_t rmt_hal_receive(rmt_hal_context_t *hal, uint32_t channel, rmt_item32_t
* @param channel: RMT channel number
* @param src: RMT items to transmit
* @param length: length of RMT items to transmit
* @param offset: offset of RMT internal memory to store the items
* @param offset: offset of RMT internal memory to store the items.
* Note: the caller should ensure that (length + offset) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS).
*/
void rmt_hal_transmit(rmt_hal_context_t *hal, uint32_t channel, const rmt_item32_t *src, uint32_t length, uint32_t offset);

4
tools/sdk/esp32/include/soc/include/hal/spi_types.h
View File

@ -27,6 +27,8 @@ typedef enum {
SPI3_HOST=2, ///< SPI3
} spi_host_device_t;
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
//alias for different chips
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_HOST SPI1_HOST
@ -38,3 +40,5 @@ typedef enum {
#define FSPI_HOST SPI2_HOST
#define HSPI_HOST SPI3_HOST
#endif
/** @endcond */

2
tools/sdk/esp32/include/soc/include/hal/touch_sensor_types.h
View File

@ -265,7 +265,7 @@ typedef struct touch_filter_config {
uint32_t hysteresis_thr; /*!<Hysteresis threshold coefficient. hysteresis = hysteresis coefficient * touch threshold.
If (raw data - baseline) > (touch threshold + hysteresis), the touch channel be touched.
If (raw data - baseline) < (touch threshold - hysteresis), the touch channel be released.
Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 2/32; 3: OFF */
Range: 0 ~ 3. The coefficient is 0: 4/32; 1: 3/32; 2: 1/32; 3: OFF */
uint32_t noise_thr; /*!<Noise threshold coefficient. noise = noise coefficient * touch threshold.
If (raw data - baseline) > (noise), the baseline stop updating.
If (raw data - baseline) < (noise), the baseline start updating.

1
tools/sdk/esp32/include/soc/include/hal/uart_hal.h
View File

@ -150,6 +150,7 @@ void uart_hal_write_txfifo(uart_hal_context_t *hal, const uint8_t *buf, uint32_t
/**
* @brief Reset the UART txfifo
* @note On ESP32, this function is reserved for UART1 and UART2.
*
* @param hal Context of the HAL layer
*

12
tools/sdk/esp32/include/soc/include/soc/soc_memory_layout.h
View File

@ -176,6 +176,12 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
intptr_t ip = (intptr_t) p;
bool r;
r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
#if CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
* for single core configuration (where it gets added to system heap) following
* additional check is required */
r |= (ip >= SOC_RTC_DRAM_LOW && ip < SOC_RTC_DRAM_HIGH);
#endif
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
@ -190,6 +196,12 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
bool r;
r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
r |= ((intptr_t)p >= SOC_RTC_DATA_LOW && (intptr_t)p < SOC_RTC_DATA_HIGH);
#if CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP
/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
* for single core configuration (where it gets added to system heap) following
* additional check is required */
r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
#endif
return r;
}

2
tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_hal.h
View File

@ -43,7 +43,7 @@ typedef struct {
adc_hal_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
adc_hal_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
adc_hal_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. ESP32 only support ADC1 single mode. */
adc_hal_digi_output_format_t format; /*!<ADC output data format for digital controller. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. */
uint32_t clk_div; /*!< ADC module clock division factor. ADC clock divided from APB clock.*/
} adc_hal_digi_config_t;

19
tools/sdk/esp32/include/soc/src/esp32/include/hal/adc_ll.h
View File

@ -8,14 +8,6 @@
extern "C" {
#endif
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!< ADC to I2S data format, [15:12]-channel [11:0]-12 bits ADC data.
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!< ADC to I2S data format, [15]-adc unit [14:11]-channel [10:0]-11 bits ADC data.
Note: In multi convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_hal_digi_output_format_t;
typedef enum {
ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1*/
ADC_CONV_SINGLE_UNIT_2 = 2, /*!< SAR ADC 2, not supported yet*/
@ -94,13 +86,12 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
}
/**
* Set adc sample cycle for digital controller.
* Set adc sample cycle.
*
* @note Normally, please use default value.
* @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
* Range: 2 ~ 0xFF.
* @param sample_cycle The number of ADC sampling cycles. Range: 1 ~ 7.
*/
static inline void adc_ll_digi_set_sample_cycle(uint32_t sample_cycle)
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
{
SYSCON.saradc_fsm.sample_cycle = sample_cycle;
}
@ -119,9 +110,9 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
/**
* Set adc output data format for digital controller.
*
* @param format Output data format, see ``adc_hal_digi_output_format_t``.
* @param format Output data format, see ``adc_digi_output_format_t``.
*/
static inline void adc_ll_digi_set_output_format(adc_hal_digi_output_format_t format)
static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format)
{
SYSCON.saradc_ctrl.data_sar_sel = format;
}

2
tools/sdk/esp32/include/soc/src/esp32/include/hal/cpu_ll.h
View File

@ -116,7 +116,7 @@ static inline void cpu_ll_set_watchpoint(int id,
//We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
for (int x = 0; x < 7; x++) {
if (size == (1 << x)) {
if (size == (size_t)(1 << x)) {
break;
}
dbreakc <<= 1;

12
tools/sdk/esp32/include/soc/src/esp32/include/hal/dac_ll.h
View File

@ -69,6 +69,18 @@ static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t val
}
}
/**
* Enable/disable the synchronization operation function of ADC1 and DAC.
*
* @note If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
*
* @param enable Enable or disable adc and dac synchronization function.
*/
static inline void dac_ll_rtc_sync_by_adc(bool enable)
{
SENS.sar_meas_ctrl2.sar1_dac_xpd_fsm = enable;
}
/************************************/
/* DAC cosine wave generator API's */
/************************************/

188
tools/sdk/esp32/include/soc/src/esp32/include/hal/i2s_ll.h
View File

@ -621,50 +621,6 @@ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val)
hw->pdm_conf.tx_pdm_en = val;
}
/**
* @brief Set I2S tx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx msb shift
*/
static inline void i2s_ll_set_tx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_msb_shift = val;
}
/**
* @brief Set I2S rx msb shift
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx msb shift
*/
static inline void i2s_ll_set_rx_msb_shift(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_msb_shift = val;
}
/**
* @brief Set I2S tx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set tx short sync
*/
static inline void i2s_ll_set_tx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.tx_short_sync = val;
}
/**
* @brief Set I2S rx short sync
*
* @param hw Peripheral I2S hardware instance address.
* @param val value to set rx short sync
*/
static inline void i2s_ll_set_rx_short_sync(i2s_dev_t *hw, uint32_t val)
{
hw->conf.rx_short_sync = val;
}
/**
* @brief Set I2S tx fifo mod force en
*
@ -819,6 +775,150 @@ static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val)
hw->conf.sig_loopback = val;
}
/**
* @brief Set I2S TX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 1;
}
/**
* @brief Set I2S RX to philip standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 1;
}
/**
* @brief Set I2S TX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to MSB Alignment Standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 1;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM short standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 1;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Set I2S TX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw)
{
hw->conf.tx_short_sync = 0;
hw->conf.tx_msb_shift = 0;
}
/**
* @brief Set I2S RX to PCM long standard
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw)
{
hw->conf.rx_short_sync = 0;
hw->conf.rx_msb_shift = 0;
}
/**
* @brief Configure I2S TX pdm
*
* @param sample_rate The sample rate to be set.
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_tx_pdm_cfg(i2s_dev_t *hw, uint32_t sample_rate)
{
uint32_t fp = 96;
uint32_t fs = sample_rate / 1000 * 10;
hw->pdm_freq_conf.tx_pdm_fp = fp;
hw->pdm_freq_conf.tx_pdm_fs = fs;
hw->pdm_conf.tx_sinc_osr2 = fp/fs;
hw->pdm_conf.pcm2pdm_conv_en = 1;
hw->pdm_conf.tx_pdm_en = 1;
}
/**
* @brief Configure I2S TX pdm
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_rx_pdm_cfg(i2s_dev_t *hw)
{
hw->pdm_conf.rx_sinc_dsr_16_en = 0;
hw->pdm_conf.pdm2pcm_conv_en = 1;
hw->pdm_conf.rx_pdm_en = 1;
}
/**
* @brief Enable I2S build in ADC mode
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_build_in_adc_ena(i2s_dev_t *hw)
{
hw->conf2.lcd_en = 1;
hw->conf2.camera_en = 0;
hw->conf.rx_msb_shift = 0;
hw->conf.rx_short_sync = 0;
}
/**
* @brief Enable I2S build in DAC mode
*
* @param hw Peripheral I2S hardware instance address.
*/
static inline void i2s_ll_build_in_dac_ena(i2s_dev_t *hw)
{
hw->conf2.lcd_en = 1;
hw->conf2.camera_en = 0;
hw->conf.tx_right_first = 1;
hw->conf.tx_msb_shift = 0;
hw->conf.tx_short_sync = 0;
}
#ifdef __cplusplus
}
#endif

6
tools/sdk/esp32/include/soc/src/esp32/include/hal/rmt_ll.h
View File

@ -21,6 +21,9 @@ extern "C" {
#include "soc/rmt_struct.h"
#include "soc/rmt_caps.h"
#define RMT_LL_HW_BASE (&RMT)
#define RMT_LL_MEM_BASE (&RMTMEM)
static inline void rmt_ll_enable_drive_clock(rmt_dev_t *dev, bool enable)
{
dev->conf_ch[0].conf0.clk_en = enable;
@ -276,9 +279,10 @@ static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel,
dev->conf_ch[channel].conf0.carrier_out_lv = level;
}
//Writes items to the specified TX channel memory with the given offset and writen length.
//the caller should ensure that (length + off) <= (memory block * SOC_RMT_CHANNEL_MEM_WORDS)
static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
{
length = (off + length) > SOC_RMT_CHANNEL_MEM_WORDS ? (SOC_RMT_CHANNEL_MEM_WORDS - off) : length;
for (uint32_t i = 0; i < length; i++) {
mem->chan[channel].data32[i + off].val = data[i].val;
}

22
tools/sdk/esp32/include/soc/src/esp32/include/hal/uart_ll.h
View File

@ -219,15 +219,21 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
/**
* @brief Reset the UART hw txfifo.
*
* Note: Due to hardware issue, reset UART1's txfifo will also reset UART2's txfifo.
* So reserve this function for UART1 and UART2. Please do DPORT reset for UART and its memory at chip startup
* to ensure the TX FIFO is reset correctly at the beginning.
*
* @param hw Beginning address of the peripheral registers.
*
* @return None
*/
static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
{
if (hw == &UART0) {
hw->conf0.txfifo_rst = 1;
hw->conf0.txfifo_rst = 0;
}
}
/**
* @brief Get the length of readable data in UART rxfifo.
@ -238,7 +244,21 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
return hw->status.rxfifo_cnt;
uint32_t fifo_cnt = hw->status.rxfifo_cnt;
typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
uint32_t len = 0;
// When using DPort to read fifo, fifo_cnt is not credible, we need to calculate the real cnt based on the fifo read and write pointer.
// When using AHB to read FIFO, we can use fifo_cnt to indicate the data length in fifo.
if (rx_status.wr_addr > rx_status.rd_addr) {
len = rx_status.wr_addr - rx_status.rd_addr;
} else if (rx_status.wr_addr < rx_status.rd_addr) {
len = (rx_status.wr_addr + 128) - rx_status.rd_addr;
} else {
len = fifo_cnt > 0 ? 128 : 0;
}
return len;
}
/**

74
tools/sdk/esp32/include/xtensa/include/xt_instr_macros.h
View File

@ -22,3 +22,77 @@
#define WITLB(at, as) asm volatile ("witlb %0, %1; \n isync \n " : : "r" (at), "r" (as))
#define WDTLB(at, as) asm volatile ("wdtlb %0, %1; \n dsync \n " : : "r" (at), "r" (as))
/* The SET_STACK implements a setting a new stack pointer (sp or a1).
* to do this the need reset PS_WOE, reset WINDOWSTART, update SP, and return PS_WOE.
*
* Note: It has 2 implementations one for using in assembler files (*.S) and one for using in C.
*
* C code prototype for SET_STACK:
* uint32_t ps_reg;
* uint32_t w_base;
* RSR(PS, ps_reg);
* ps_reg &= ~(PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK);
* WSR(PS, ps_reg);
*
* RSR(WINDOWBASE, w_base);
* WSR(WINDOWSTART, (1 << w_base));
*
* asm volatile ( "movi sp, "XTSTR( (SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2) )"");
*
* RSR(PS, ps_reg);
* ps_reg |= (PS_WOE_MASK);
* WSR(PS, ps_reg);
*/
#ifdef __ASSEMBLER__
.macro SET_STACK new_sp tmp1 tmp2
rsr.ps \tmp1
movi \tmp2, ~(PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK)
and \tmp1, \tmp1, \tmp2
wsr.ps \tmp1
rsync
rsr.windowbase \tmp1
ssl \tmp1
movi \tmp1, 1
sll \tmp1, \tmp1
wsr.windowstart \tmp1
rsync
mov sp, \new_sp
rsr.ps \tmp1
movi \tmp2, (PS_WOE)
or \tmp1, \tmp1, \tmp2
wsr.ps \tmp1
rsync
.endm
#else
#define SET_STACK(new_sp) \
do { \
uint32_t tmp1 = 0, tmp2 = 0; \
asm volatile ( \
"rsr.ps %1 \n"\
"movi %2, ~" XTSTR( PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK ) " \n"\
"and %1, %1, %2 \n"\
"wsr.ps %1 \n"\
"rsync \n"\
" \n"\
"rsr.windowbase %1 \n"\
"ssl %1 \n"\
"movi %1, 1 \n"\
"sll %1, %1 \n"\
"wsr.windowstart %1 \n"\
"rsync \n"\
" \n"\
"mov sp, %0 \n"\
"rsr.ps %1 \n"\
" \n"\
"movi %2, " XTSTR( PS_WOE_MASK ) "\n"\
" \n"\
"or %1, %1, %2 \n"\
"wsr.ps %1 \n"\
"rsync \n"\
: "+r"(new_sp), "+r"(tmp1), "+r"(tmp2)); \
} while (0);
#endif // __ASSEMBLER__

6
tools/sdk/esp32/ld/esp32.project.ld
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5
tools/sdk/esp32/ld/esp32.rom.ld
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@ -707,6 +707,11 @@ PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c );
PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 );
PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 );
PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 );
PROVIDE ( ld_acl_frm_cbk = 0x40034414 );
PROVIDE ( ld_acl_rsw_end = 0x40032bc0 );
PROVIDE ( ld_acl_end = 0x40033140 );
PROVIDE ( ld_acl_resched = 0x40033814 );
PROVIDE ( ld_acl_test_mode_update = 0x40032050 );
PROVIDE ( r_ld_acl_unsniff = 0x400361e0 );
PROVIDE ( r_ld_active_check = 0x4003cac4 );
PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec );

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