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v2.0.0 Add support for ESP32S2 and update ESP-IDF to 4.4 (#4996)

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This is very much still work in progress and much more will change before the final 2.0.0

Some APIs have changed. New libraries have been added. LittleFS included.

Co-authored-by: Seon Rozenblum <seonr@3sprockets.com>
Co-authored-by: Me No Dev <me-no-dev@users.noreply.github.com>
Co-authored-by: geeksville <kevinh@geeksville.com>
Co-authored-by: Mike Dunston <m_dunston@comcast.net>
Co-authored-by: Unexpected Maker <seon@unexpectedmaker.com>
Co-authored-by: Seon Rozenblum <seonr@3sprockets.com>
Co-authored-by: microDev <70126934+microDev1@users.noreply.github.com>
Co-authored-by: tobozo <tobozo@users.noreply.github.com>
Co-authored-by: bobobo1618 <bobobo1618@users.noreply.github.com>
Co-authored-by: lorol <lorolouis@gmail.com>
Co-authored-by: geeksville <kevinh@geeksville.com>
Co-authored-by: Limor "Ladyada" Fried <limor@ladyada.net>
Co-authored-by: Sweety <switi.mhaiske@espressif.com>
Co-authored-by: Loick MAHIEUX <loick111@gmail.com>
Co-authored-by: Larry Bernstone <lbernstone@gmail.com>
Co-authored-by: Valerii Koval <valeros@users.noreply.github.com>
Co-authored-by: 快乐的我531 <2302004040@qq.com>
Co-authored-by: chegewara <imperiaonline4@gmail.com>
Co-authored-by: Clemens Kirchgatterer <clemens@1541.org>
Co-authored-by: Aron Rubin <aronrubin@gmail.com>
Co-authored-by: Pete Lewis <601236+lewispg228@users.noreply.github.com>
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Me No Dev
2021-04-05 14:23:58 +03:00
committed by GitHub
parent 46d5afb17f
commit 5502879a5b
5209 changed files with 826360 additions and 322816 deletions
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tools/sdk/esp32/include/xtensa/esp32/include/xtensa/config/core-isa.h Normal file
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/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_FP 1 /* single prec floating point */
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
(1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 1100003 /* sw version of this header */
#define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
#define XCHAL_HW_REL_LX6 1
#define XCHAL_HW_REL_LX6_0 1
#define XCHAL_HW_REL_LX6_0_3 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
#define XCHAL_HAVE_AXI 0 /* AXI bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 0
#define XCHAL_DCACHE_SETWIDTH 0
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 1
#define XCHAL_DCACHE_WAYS 1
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
/* Instruction ROM 0: */
#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Data ROM 0: */
#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */
#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */
#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x000637FF
#define XCHAL_INTLEVEL2_MASK 0x00380000
#define XCHAL_INTLEVEL3_MASK 0x28C08800
#define XCHAL_INTLEVEL4_MASK 0x53000000
#define XCHAL_INTLEVEL5_MASK 0x84010000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00004000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 3
#define XCHAL_INT12_LEVEL 1
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 7
#define XCHAL_INT15_LEVEL 3
#define XCHAL_INT16_LEVEL 5
#define XCHAL_INT17_LEVEL 1
#define XCHAL_INT18_LEVEL 1
#define XCHAL_INT19_LEVEL 2
#define XCHAL_INT20_LEVEL 2
#define XCHAL_INT21_LEVEL 2
#define XCHAL_INT22_LEVEL 3
#define XCHAL_INT23_LEVEL 3
#define XCHAL_INT24_LEVEL 4
#define XCHAL_INT25_LEVEL 4
#define XCHAL_INT26_LEVEL 5
#define XCHAL_INT27_LEVEL 3
#define XCHAL_INT28_LEVEL 4
#define XCHAL_INT29_LEVEL 3
#define XCHAL_INT30_LEVEL 4
#define XCHAL_INT31_LEVEL 5
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/*
* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) or TX */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0x40000340
#define XCHAL_USER_VECTOR_PADDR 0x40000340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x000002C0
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG MODULE
----------------------------------------------------------------------*/
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
/* TRAX (in core) */
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

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/*
* xtensa/config/core-matmap.h -- Memory access and translation mapping
* parameters (CHAL) of the Xtensa processor core configuration.
*
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
* this file) for more details.
*
* In the Xtensa processor products released to date, all parameters
* defined in this file are derivable (at least in theory) from
* information contained in the core-isa.h header file.
* In particular, the following core configuration parameters are relevant:
* XCHAL_HAVE_CACHEATTR
* XCHAL_HAVE_MIMIC_CACHEATTR
* XCHAL_HAVE_XLT_CACHEATTR
* XCHAL_HAVE_PTP_MMU
* XCHAL_ITLB_ARF_ENTRIES_LOG2
* XCHAL_DTLB_ARF_ENTRIES_LOG2
* XCHAL_DCACHE_IS_WRITEBACK
* XCHAL_ICACHE_SIZE (presence of I-cache)
* XCHAL_DCACHE_SIZE (presence of D-cache)
* XCHAL_HW_VERSION_MAJOR
* XCHAL_HW_VERSION_MINOR
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION
#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION
/*
* Specific encoded cache attribute values of general interest.
* If a specific cache mode is not available, the closest available
* one is returned instead (eg. writethru instead of writeback,
* bypass instead of writethru).
*/
#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
#define XCHAL_CA_BYPASSBUF 6 /* cache disabled (bypassed) bufferable mode */
#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */
#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */
#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
#define XCHAL_CA_WRITEBACK_NOALLOC 2 /* cache enabled (write-back no-allocate) mode */
#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */
#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */
#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */
#define XCHAL_CA_WRITEBACK_NOALLOC_RW 0 /* cache enabled (write-back no-allocate) mode (no exec) */
#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/*
* General notes on MMU parameters.
*
* Terminology:
* ASID = address-space ID (acts as an "extension" of virtual addresses)
* VPN = virtual page number
* PPN = physical page number
* CA = encoded cache attribute (access modes)
* TLB = translation look-aside buffer (term is stretched somewhat here)
* I = instruction (fetch accesses)
* D = data (load and store accesses)
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
* that simultaneously match the virtual address of an access;
* a TLB successfully translates a virtual address if exactly
* one way matches the vaddr; if none match, it is a miss;
* if multiple match, one gets a "multihit" exception;
* each way can be independently configured in terms of number of
* entries, page sizes, which fields are writable or constant, etc.
* set = group of contiguous ways with exactly identical parameters
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
* from the page table and storing it in one of the auto-refill ways;
* if this PTE load also misses, a miss exception is posted for s/w.
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
* page arbitrarily under program control; it has a single entry,
* is non-auto-refill (some other way(s) must be auto-refill),
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
* restriction is that this be the only page size it supports).
*
* TLB way entries are virtually indexed.
* TLB ways that support multiple page sizes:
* - must have all writable VPN and PPN fields;
* - can only use one page size at any given time (eg. setup at startup),
* selected by the respective ITLBCFG or DTLBCFG special register,
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
* this list may be sparse for auto-refill ways because auto-refill
* ways have independent lists of supported page sizes sharing a
* common encoding with PTE entries; the encoding is the index into
* this list; unsupported sizes for a given way are zero in the list;
* selecting unsupported sizes results in undefined hardware behaviour;
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
*/
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
/*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_ITLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* ITLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000
/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
/*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_DTLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* DTLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000
/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/

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/* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/* NOTE: This file exists only for backward compatibility with T1050
and earlier Xtensa releases. It includes only a subset of the
available header files. */
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_misc.h>
#include <xtensa/tie/xt_booleans.h>
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */

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/*
* ESP32 External Register symbolic names
*/
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define DSRSET 0x10200C

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/*
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Include these special register bitfield definitions, for historical reasons: */
#include <xtensa/corebits.h>
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define WINDOWBASE 72
#define WINDOWSTART 73
#define IBREAKENABLE 96
#define MEMCTL 97
#define ATOMCTL 99
#define DDR 104
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define CONFIGID0 176
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define CONFIGID1 208
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
/* Special names for read-only and write-only interrupt registers: */
#define INTREAD 226
#define INTSET 226
#define INTCLEAR 227
#endif /* XTENSA_SPECREG_H */

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/*
* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
*
* NOTE: The location and contents of this file are highly subject to change.
*
* Source for configuration-independent binaries (which link in a
* configuration-specific HAL library) must NEVER include this file.
* The HAL itself has historically included this file in some instances,
* but this is not appropriate either, because the HAL is meant to be
* core-specific but system independent.
*/
/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H
/*#include <xtensa/hal.h>*/
/*----------------------------------------------------------------------
CONFIGURED SOFTWARE OPTIONS
----------------------------------------------------------------------*/
#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
/* The above maps to one of the following constants: */
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
/* Alternatives: */
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */
#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
/* The above maps to one of the following constants: */
#define XTHAL_CLIB_NEWLIB 0
#define XTHAL_CLIB_UCLIBC 1
#define XTHAL_CLIB_XCLIB 2
/* Alternatives: */
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */
/*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */
#define XSHAL_USE_FLOATING_POINT 1
#define XSHAL_FLOATING_POINT_ABI 0
/* SW workarounds enabled for HW errata: */
/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
/*
* Strange place to find these, but the configuration GUI
* allows moving these around to account for various core
* configurations. Specific boards (and their BSP software)
* will have specific meanings for these components.
*/
/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
/* System ROM: */
#define XSHAL_ROM_VADDR 0x50000000
#define XSHAL_ROM_PADDR 0x50000000
#define XSHAL_ROM_SIZE 0x01000000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0x50000000
#define XSHAL_ROM_AVAIL_VSIZE 0x01000000
/* System RAM: */
#define XSHAL_RAM_VADDR 0x60000000
#define XSHAL_RAM_PADDR 0x60000000
#define XSHAL_RAM_VSIZE 0x20000000
#define XSHAL_RAM_PSIZE 0x20000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0x60000000
#define XSHAL_RAM_AVAIL_VSIZE 0x20000000
/*
* Shadow system RAM (same device as system RAM, at different address).
* (Emulation boards need this for the SONIC Ethernet driver
* when data caches are configured for writeback mode.)
* NOTE: on full MMU configs, this points to the BYPASS virtual address
* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0xA0000000
#define XSHAL_RAM_BYPASS_PADDR 0xA0000000
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
/* Alternate system RAM (different device than system RAM): */
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/
/* Some available location in which to place devices in a simulation (eg. XTMP): */
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
#define XSHAL_SIMIO_PADDR 0xC0000000
#define XSHAL_SIMIO_SIZE 0x20000000
/*----------------------------------------------------------------------
* For use by reference testbench exit and diagnostic routines.
*/
#define XSHAL_MAGIC_EXIT 0x0
/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
* Values written to CACHEATTR special register (or its equivalent)
* to enable and disable caches in various modes.
*----------------------------------------------------------------------*/
/*----------------------------------------------------------------------
BACKWARD COMPATIBILITY ...
----------------------------------------------------------------------*/
/*
* NOTE: the following two macros are DEPRECATED. Use the latter
* board-specific macros instead, which are specially tuned for the
* particular target environments' memory maps.
*/
#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
/*----------------------------------------------------------------------
GENERIC
----------------------------------------------------------------------*/
/* For the following, a 512MB region is used if it contains a system (PIF) RAM,
* system (PIF) ROM, local memory, or XLMI. */
/* These set any unused 512MB region to cache-BYPASS attribute: */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22221112 /* enable caches in write-back mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22221112 /* enable caches in write-allocate mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22221112 /* enable caches in write-through mode */
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* These set any unused 512MB region to ILLEGAL attribute: */
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFFFF111F /* enable caches in write-back mode */
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFFFF111F /* enable caches in write-allocate mode */
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFFFF111F /* enable caches in write-through mode */
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFFFF222F /* disable caches in bypass mode */
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */
/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
* NULL-pointer dereference bugs; all other unused 512MB regions are set
* to cache-BYPASS attribute: */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2222111F /* enable caches in write-back mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2222111F /* enable caches in write-allocate mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2222111F /* enable caches in write-through mode */
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */
/*----------------------------------------------------------------------
ISS (Instruction Set Simulator) SPECIFIC ...
----------------------------------------------------------------------*/
/* For now, ISS defaults to the TRAPNULL settings: */
#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS
#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
#define XSHAL_ISS_PIPE_REGIONS 0
#define XSHAL_ISS_SDRAM_REGIONS 0
/*----------------------------------------------------------------------
XT2000 BOARD SPECIFIC ...
----------------------------------------------------------------------*/
/* For the following, a 512MB region is used if it contains any system RAM,
* system ROM, local memory, XLMI, or other XT2000 board device or memory.
* Regions containing devices are forced to cache-BYPASS mode regardless
* of whether the macro is _WRITEBACK vs. _BYPASS etc. */
/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF22111F /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF22111F /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF22111F /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000440 /* BusInt SDRAM regions */
/*----------------------------------------------------------------------
VECTOR INFO AND SIZES
----------------------------------------------------------------------*/
#define XSHAL_VECTORS_PACKED 0
#define XSHAL_STATIC_VECTOR_SELECT 1
#define XSHAL_RESET_VECTOR_VADDR 0x40000400
#define XSHAL_RESET_VECTOR_PADDR 0x40000400
/*
* Sizes allocated to vectors by the system (memory map) configuration.
* These sizes are constrained by core configuration (eg. one vector's
* code cannot overflow into another vector) but are dependent on the
* system or board (or LSP) memory map configuration.
*
* Whether or not each vector happens to be in a system ROM is also
* a system configuration matter, sometimes useful, included here also:
*/
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
#define XSHAL_RESET_VECTOR_ISROM 0
#define XSHAL_USER_VECTOR_SIZE 0x00000038
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
#define XSHAL_NMI_VECTOR_ISROM 0
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE
#endif /*XTENSA_CONFIG_SYSTEM_H*/

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/*
* tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file contains assembly-language definitions (assembly
macros, etc.) for this specific Xtensa processor's TIE extensions
and options. It is customized to this Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTENSA_CORE_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/*
* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to store. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 // threadptr option
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
rsr.ACCLO \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.ACCHI \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
rsr.BR \at1 // boolean option
s32i \at1, \ptr, .Lxchal_ofs_+0
rsr.SCOMPARE1 \at1 // conditional store option
s32i \at1, \ptr, .Lxchal_ofs_+4
rsr.M0 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+8
rsr.M1 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+12
rsr.M2 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+16
rsr.M3 \at1 // MAC16 option
s32i \at1, \ptr, .Lxchal_ofs_+20
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1008, 4, 4
rur.F64R_LO \at1 // ureg 234
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.F64R_HI \at1 // ureg 235
s32i \at1, \ptr, .Lxchal_ofs_+4
rur.F64S \at1 // ureg 236
s32i \at1, \ptr, .Lxchal_ofs_+8
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1008, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.endif
.endm // xchal_ncp_store
/*
* Macro to load all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set to 1
* if this is not the first in the sequence. Defaults to 0.
* ofs Offset from start of larger sequence (from value of first ptr
* in sequence) at which to load. Defaults to next available space
* (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a bitmask
* (see XTHAL_SAS_xxx constants). Defaults to all registers.
* alloc Select what category(ies) of registers to allocate; if any
* category is selected here that is not in <select>, space for
* the corresponding registers is skipped without doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Optional global registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 // threadptr option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
// Optional caller-saved registers used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1012, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.ACCLO \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.ACCHI \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1012, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
.endif
// Optional caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 996, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wsr.BR \at1 // boolean option
l32i \at1, \ptr, .Lxchal_ofs_+4
wsr.SCOMPARE1 \at1 // conditional store option
l32i \at1, \ptr, .Lxchal_ofs_+8
wsr.M0 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+12
wsr.M1 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+16
wsr.M2 \at1 // MAC16 option
l32i \at1, \ptr, .Lxchal_ofs_+20
wsr.M3 \at1 // MAC16 option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 996, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 24
.endif
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 1008, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.F64R_LO \at1 // ureg 234
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.F64R_HI \at1 // ureg 235
l32i \at1, \ptr, .Lxchal_ofs_+8
wur.F64S \at1 // ureg 236
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1008, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 12
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1
/*
* Macro to store the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_store.
*/
#define xchal_cp_FPU_store xchal_cp0_store
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
rur.FCR \at1 // ureg 232
s32i \at1, \ptr, .Lxchal_ofs_+0
rur.FSR \at1 // ureg 233
s32i \at1, \ptr, .Lxchal_ofs_+4
ssi f0, \ptr, .Lxchal_ofs_+8
ssi f1, \ptr, .Lxchal_ofs_+12
ssi f2, \ptr, .Lxchal_ofs_+16
ssi f3, \ptr, .Lxchal_ofs_+20
ssi f4, \ptr, .Lxchal_ofs_+24
ssi f5, \ptr, .Lxchal_ofs_+28
ssi f6, \ptr, .Lxchal_ofs_+32
ssi f7, \ptr, .Lxchal_ofs_+36
ssi f8, \ptr, .Lxchal_ofs_+40
ssi f9, \ptr, .Lxchal_ofs_+44
ssi f10, \ptr, .Lxchal_ofs_+48
ssi f11, \ptr, .Lxchal_ofs_+52
ssi f12, \ptr, .Lxchal_ofs_+56
ssi f13, \ptr, .Lxchal_ofs_+60
ssi f14, \ptr, .Lxchal_ofs_+64
ssi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_store
/*
* Macro to load the state of TIE coprocessor FPU.
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
* registers are clobbered, the remaining are unused).
* Optional parameters are the same as for xchal_ncp_load.
*/
#define xchal_cp_FPU_load xchal_cp0_load
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
// Custom caller-saved registers not used by default by the compiler:
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
xchal_sa_align \ptr, 0, 948, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.FCR \at1 // ureg 232
l32i \at1, \ptr, .Lxchal_ofs_+4
wur.FSR \at1 // ureg 233
lsi f0, \ptr, .Lxchal_ofs_+8
lsi f1, \ptr, .Lxchal_ofs_+12
lsi f2, \ptr, .Lxchal_ofs_+16
lsi f3, \ptr, .Lxchal_ofs_+20
lsi f4, \ptr, .Lxchal_ofs_+24
lsi f5, \ptr, .Lxchal_ofs_+28
lsi f6, \ptr, .Lxchal_ofs_+32
lsi f7, \ptr, .Lxchal_ofs_+36
lsi f8, \ptr, .Lxchal_ofs_+40
lsi f9, \ptr, .Lxchal_ofs_+44
lsi f10, \ptr, .Lxchal_ofs_+48
lsi f11, \ptr, .Lxchal_ofs_+52
lsi f12, \ptr, .Lxchal_ofs_+56
lsi f13, \ptr, .Lxchal_ofs_+60
lsi f14, \ptr, .Lxchal_ofs_+64
lsi f15, \ptr, .Lxchal_ofs_+68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 948, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_load
#define XCHAL_CP0_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/

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/*
* tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*/
/* This header file describes this specific Xtensa processor's TIE extensions
that extend basic Xtensa core functionality. It is customized to this
Xtensa processor configuration.
Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_CORE_TIE_H
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 48
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
/*
* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 12
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_XTENSA_CORE_TIE_H*/

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#ifndef ERI_H
#define ERI_H
#include <stdint.h>
/*
The ERI is a bus internal to each Xtensa core. It connects, amongst others, to the debug interface, where it
allows reading/writing the same registers as available over JTAG.
*/
/**
* @brief Perform an ERI read
* @param addr : ERI register to read from
*
* @return Value read
*/
uint32_t eri_read(int addr);
/**
* @brief Perform an ERI write
* @param addr : ERI register to write to
* @param data : Value to write
*
* @return Value read
*/
void eri_write(int addr, uint32_t data);
#endif

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#pragma once
#warning "esp_panic.h is deprecated, please use esp_debug_helpers.h or/and esp_private/panic_reason.h"
#include "esp_private/panic_reason.h"
#include "esp_debug_helpers.h"

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#pragma once
#define PANIC_RSN_NONE 0
#define PANIC_RSN_DEBUGEXCEPTION 1
#define PANIC_RSN_DOUBLEEXCEPTION 2
#define PANIC_RSN_KERNELEXCEPTION 3
#define PANIC_RSN_COPROCEXCEPTION 4
#define PANIC_RSN_INTWDT_CPU0 5
#define PANIC_RSN_INTWDT_CPU1 6
#define PANIC_RSN_CACHEERR 7
#define PANIC_RSN_MAX 7

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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define RSR(reg, at) asm volatile ("rsr %0, %1" : "=r" (at) : "i" (reg))
#define WSR(reg, at) asm volatile ("wsr %0, %1" : : "r" (at), "i" (reg))
#define XSR(reg, at) asm volatile ("xsr %0, %1" : "+r" (at) : "i" (reg))
#define RER(reg, at) asm volatile ("rer %0, %1" : "=r" (at) : "r" (reg))
#define WITLB(at, as) asm volatile ("witlb %0, %1; \n isync \n " : : "r" (at), "r" (as))
#define WDTLB(at, as) asm volatile ("wdtlb %0, %1; \n dsync \n " : : "r" (at), "r" (as))
/* The SET_STACK implements a setting a new stack pointer (sp or a1).
* to do this the need reset PS_WOE, reset WINDOWSTART, update SP, and return PS_WOE.
*
* Note: It has 2 implementations one for using in assembler files (*.S) and one for using in C.
*
* C code prototype for SET_STACK:
* uint32_t ps_reg;
* uint32_t w_base;
* RSR(PS, ps_reg);
* ps_reg &= ~(PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK);
* WSR(PS, ps_reg);
*
* RSR(WINDOWBASE, w_base);
* WSR(WINDOWSTART, (1 << w_base));
*
* asm volatile ( "movi sp, "XTSTR( (SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2) )"");
*
* RSR(PS, ps_reg);
* ps_reg |= (PS_WOE_MASK);
* WSR(PS, ps_reg);
*/
#ifdef __ASSEMBLER__
.macro SET_STACK new_sp tmp1 tmp2
rsr.ps \tmp1
movi \tmp2, ~(PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK)
and \tmp1, \tmp1, \tmp2
wsr.ps \tmp1
rsync
rsr.windowbase \tmp1
ssl \tmp1
movi \tmp1, 1
sll \tmp1, \tmp1
wsr.windowstart \tmp1
rsync
mov sp, \new_sp
rsr.ps \tmp1
movi \tmp2, (PS_WOE)
or \tmp1, \tmp1, \tmp2
wsr.ps \tmp1
rsync
.endm
#else
#define SET_STACK(new_sp) \
do { \
uint32_t tmp1 = 0, tmp2 = 0; \
asm volatile ( \
"rsr.ps %1 \n"\
"movi %2, ~" XTSTR( PS_WOE_MASK | PS_OWB_MASK | PS_CALLINC_MASK ) " \n"\
"and %1, %1, %2 \n"\
"wsr.ps %1 \n"\
"rsync \n"\
" \n"\
"rsr.windowbase %1 \n"\
"ssl %1 \n"\
"movi %1, 1 \n"\
"sll %1, %1 \n"\
"wsr.windowstart %1 \n"\
"rsync \n"\
" \n"\
"mov sp, %0 \n"\
"rsr.ps %1 \n"\
" \n"\
"movi %2, " XTSTR( PS_WOE_MASK ) "\n"\
" \n"\
"or %1, %1, %2 \n"\
"wsr.ps %1 \n"\
"rsync \n"\
: "+r"(new_sp), "+r"(tmp1), "+r"(tmp2)); \
} while (0);
#endif // __ASSEMBLER__

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdbool.h>
#include "eri.h"
#include "xtensa-debug-module.h"
// Low-level Xtensa TRAX utils
/**
* @brief Start a Trax trace on the current CPU with instructions as unit of delay.
* Memory blocks to be used as Trax memory must be enabled before
* calling this function, if needed.
*/
void xt_trax_start_trace_instructions(void);
/**
* @brief Start a Trax trace on the current CPU with words as unit of delay.
* Memory blocks to be used as Trax memory must be enabled before
* calling this function, if needed.
*/
void xt_trax_start_trace_words(void);
/**
* @brief Check if Trax trace is active on current CPU.
*
* @return bool. Return true if trace is active.
*/
bool xt_trax_trace_is_active(void);
/**
* @brief Trigger a Trax trace stop after the indicated delay. If this is called
* before and the previous delay hasn't ended yet, this will overwrite
* that delay with the new value. The delay will always start at the time
* the function is called.
*
* @param delay : The delay to stop the trace in, in the unit indicated to
* trax_start_trace. Note: the trace memory has 4K words available.
*/
void xt_trax_trigger_traceend_after_delay(int delay);

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#ifndef XTENSA_DEBUG_MODULE_H
#define XTENSA_DEBUG_MODULE_H
/*
ERI registers / OCD offsets and field definitions
*/
#define ERI_DEBUG_OFFSET 0x100000
#define ERI_TRAX_OFFSET (ERI_DEBUG_OFFSET+0)
#define ERI_PERFMON_OFFSET (ERI_DEBUG_OFFSET+0x1000)
#define ERI_OCDREG_OFFSET (ERI_DEBUG_OFFSET+0x2000)
#define ERI_MISCDBG_OFFSET (ERI_DEBUG_OFFSET+0x3000)
#define ERI_CORESIGHT_OFFSET (ERI_DEBUG_OFFSET+0x3F00)
#define ERI_TRAX_TRAXID (ERI_TRAX_OFFSET+0x00)
#define ERI_TRAX_TRAXCTRL (ERI_TRAX_OFFSET+0x04)
#define ERI_TRAX_TRAXSTAT (ERI_TRAX_OFFSET+0x08)
#define ERI_TRAX_TRAXDATA (ERI_TRAX_OFFSET+0x0C)
#define ERI_TRAX_TRAXADDR (ERI_TRAX_OFFSET+0x10)
#define ERI_TRAX_TRIGGERPC (ERI_TRAX_OFFSET+0x14)
#define ERI_TRAX_PCMATCHCTRL (ERI_TRAX_OFFSET+0x18)
#define ERI_TRAX_DELAYCNT (ERI_TRAX_OFFSET+0x1C)
#define ERI_TRAX_MEMADDRSTART (ERI_TRAX_OFFSET+0x20)
#define ERI_TRAX_MEMADDREND (ERI_TRAX_OFFSET+0x24)
#define TRAXCTRL_TREN (1<<0) //Trace enable. Tracing starts on 0->1
#define TRAXCTRL_TRSTP (1<<1) //Trace Stop. Make 1 to stop trace.
#define TRAXCTRL_PCMEN (1<<2) //PC match enable
#define TRAXCTRL_PTIEN (1<<4) //Processor-trigger enable
#define TRAXCTRL_CTIEN (1<<5) //Cross-trigger enable
#define TRAXCTRL_TMEN (1<<7) //Tracemem Enable. Always set.
#define TRAXCTRL_CNTU (1<<9) //Post-stop-trigger countdown units; selects when DelayCount-- happens.
//0 - every 32-bit word written to tracemem, 1 - every cpu instruction
#define TRAXCTRL_TSEN (1<<11) //Undocumented/deprecated?
#define TRAXCTRL_SMPER_SHIFT 12 //Send sync every 2^(9-smper) messages. 7=reserved, 0=no sync msg
#define TRAXCTRL_SMPER_MASK 0x7 //Synchronization message period
#define TRAXCTRL_PTOWT (1<<16) //Processor Trigger Out (OCD halt) enabled when stop triggered
#define TRAXCTRL_PTOWS (1<<17) //Processor Trigger Out (OCD halt) enabled when trace stop completes
#define TRAXCTRL_CTOWT (1<<20) //Cross-trigger Out enabled when stop triggered
#define TRAXCTRL_CTOWS (1<<21) //Cross-trigger Out enabled when trace stop completes
#define TRAXCTRL_ITCTO (1<<22) //Integration mode: cross-trigger output
#define TRAXCTRL_ITCTIA (1<<23) //Integration mode: cross-trigger ack
#define TRAXCTRL_ITATV (1<<24) //replaces ATID when in integration mode: ATVALID output
#define TRAXCTRL_ATID_MASK 0x7F //ARB source ID
#define TRAXCTRL_ATID_SHIFT 24
#define TRAXCTRL_ATEN (1<<31) //ATB interface enable
#define TRAXSTAT_TRACT (1<<0) //Trace active flag.
#define TRAXSTAT_TRIG (1<<1) //Trace stop trigger. Clears on TREN 1->0
#define TRAXSTAT_PCMTG (1<<2) //Stop trigger caused by PC match. Clears on TREN 1->0
#define TRAXSTAT_PJTR (1<<3) //JTAG transaction result. 1=err in preceding jtag transaction.
#define TRAXSTAT_PTITG (1<<4) //Stop trigger caused by Processor Trigger Input. Clears on TREN 1->0
#define TRAXSTAT_CTITG (1<<5) //Stop trigger caused by Cross-Trigger Input. Clears on TREN 1->0
#define TRAXSTAT_MEMSZ_SHIFT 8 //Traceram size inducator. Usable trace ram is 2^MEMSZ bytes.
#define TRAXSTAT_MEMSZ_MASK 0x1F
#define TRAXSTAT_PTO (1<<16) //Processor Trigger Output: current value
#define TRAXSTAT_CTO (1<<17) //Cross-Trigger Output: current value
#define TRAXSTAT_ITCTOA (1<<22) //Cross-Trigger Out Ack: current value
#define TRAXSTAT_ITCTI (1<<23) //Cross-Trigger Input: current value
#define TRAXSTAT_ITATR (1<<24) //ATREADY Input: current value
#define TRAXADDR_TADDR_SHIFT 0 //Trax memory address, in 32-bit words.
#define TRAXADDR_TADDR_MASK 0x1FFFFF //Actually is only as big as the trace buffer size max addr.
#define TRAXADDR_TWRAP_SHIFT 21 //Amount of times TADDR has overflown
#define TRAXADDR_TWRAP_MASK 0x3FF
#define TRAXADDR_TWSAT (1<<31) //1 if TWRAP has overflown, clear by disabling tren.
#define PCMATCHCTRL_PCML_SHIFT 0 //Amount of lower bits to ignore in pc trigger register
#define PCMATCHCTRL_PCML_MASK 0x1F
#define PCMATCHCTRL_PCMS (1<<31) //PC Match Sense, 0 - match when procs PC is in-range, 1 - match when
//out-of-range
// Global control/status for all performance counters
#define ERI_PERFMON_PGM (ERI_PERFMON_OFFSET+0x0000)
//PC at the cycle of the event that caused PerfMonInt assertion
#define ERI_PERFMON_INTPC (ERI_PERFMON_OFFSET+0x0010)
// Maximum amount of counter (depends on chip)
#define ERI_PERFMON_MAX XCHAL_NUM_PERF_COUNTERS
// Performance counter value
#define ERI_PERFMON_PM0 (ERI_PERFMON_OFFSET+0x0080)
// Performance counter control register
#define ERI_PERFMON_PMCTRL0 (ERI_PERFMON_OFFSET+0x0100)
// Performance counter status register
#define ERI_PERFMON_PMSTAT0 (ERI_PERFMON_OFFSET+0x0180)
#define PMCTRL_INTEN (1<<0) // Enables assertion of PerfMonInt output when overflow happens
#define PMCTRL_KRNLCNT (1<<3) // Enables counting when CINTLEVEL* >
// TRACELEVEL (i.e. If this bit is set, this counter
// counts only when CINTLEVEL >TRACELEVEL;
// if this bit is cleared, this counter counts only when
// CINTLEVEL ≤ TRACELEVEL)
#define PMCTRL_KRNLCNT_SHIFT 3
#define PMCTRL_TRACELEVEL_SHIFT 4 // Compares this value to CINTLEVEL* when deciding whether to count
#define PMCTRL_TRACELEVEL_MASK 0xf
#define PMCTRL_SELECT_SHIFT 8 // Selects input to be counted by the counter
#define PMCTRL_SELECT_MASK 0x1f
#define PMCTRL_MASK_SHIFT 16 // Selects input subsets to be counted (counter will
// increment only once even if more than one condition
// corresponding to a mask bit occurs)
#define PMCTRL_MASK_MASK 0xffff
#define PMSTAT_OVFL (1<<0) // Counter Overflow. Sticky bit set when a counter rolls over
// from 0xffffffff to 0x0.
#define PMSTAT_INTSTART (1<<4) // This counter’s overflow caused PerfMonInt to be asserted.
#define PGM_PMEN (1<<0) // Overall enable for all performance counting
#endif

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/*
* xtensa/cacheasm.h -- assembler-specific cache related definitions
* that depend on CORE configuration
*
* This file is logically part of xtensa/coreasm.h ,
* but is kept separate for modularity / compilation-performance.
*/
/*
* Copyright (c) 2001-2014 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHEASM_H
#define XTENSA_CACHEASM_H
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/xtensa-xer.h>
#include <xtensa/xtensa-versions.h>
/*
* This header file defines assembler macros of the form:
* <x>cache_<func>
* where <x> is 'i' or 'd' for instruction and data caches,
* and <func> indicates the function of the macro.
*
* The following functions <func> are defined,
* and apply only to the specified cache (I or D):
*
* reset
* Resets the cache.
*
* sync
* Makes sure any previous cache instructions have been completed;
* ie. makes sure any previous cache control operations
* have had full effect and been synchronized to memory.
* Eg. any invalidate completed [so as not to generate a hit],
* any writebacks or other pipelined writes written to memory, etc.
*
* invalidate_line (single cache line)
* invalidate_region (specified memory range)
* invalidate_all (entire cache)
* Invalidates all cache entries that cache
* data from the specified memory range.
* NOTE: locked entries are not invalidated.
*
* writeback_line (single cache line)
* writeback_region (specified memory range)
* writeback_all (entire cache)
* Writes back to memory all dirty cache entries
* that cache data from the specified memory range,
* and marks these entries as clean.
* NOTE: on some future implementations, this might
* also invalidate.
* NOTE: locked entries are written back, but never invalidated.
* NOTE: instruction caches never implement writeback.
*
* writeback_inv_line (single cache line)
* writeback_inv_region (specified memory range)
* writeback_inv_all (entire cache)
* Writes back to memory all dirty cache entries
* that cache data from the specified memory range,
* and invalidates these entries (including all clean
* cache entries that cache data from that range).
* NOTE: locked entries are written back but not invalidated.
* NOTE: instruction caches never implement writeback.
*
* lock_line (single cache line)
* lock_region (specified memory range)
* Prefetch and lock the specified memory range into cache.
* NOTE: if any part of the specified memory range cannot
* be locked, a Load/Store Error (for dcache) or Instruction
* Fetch Error (for icache) exception occurs. These macros don't
* do anything special (yet anyway) to handle this situation.
*
* unlock_line (single cache line)
* unlock_region (specified memory range)
* unlock_all (entire cache)
* Unlock cache entries that cache the specified memory range.
* Entries not already locked are unaffected.
*
* coherence_on
* coherence_off
* Turn off and on cache coherence
*
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* The following macros assume the following cache size/parameter limits
* in the current Xtensa core implementation:
* cache size: 1024 bytes minimum
* line size: 16 - 64 bytes
* way count: 1 - 4
*
* Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
* Hence the assumption that each loop can execute four cache instructions.
*
* Correspondingly, the offset range of instructions is assumed able to cover
* four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
* both hit and indexed cache instructions. Ie. these offsets are all
* valid: 0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
* This is true of all original cache instructions
* (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
* of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
* This is also true of subsequent cache instructions
* (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
* of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
*
* (Maximum cache size, currently 32k, doesn't affect the following macros.
* Cache ways > MMU min page size cause aliasing but that's another matter.)
*/
/*
* Macro to apply an 'indexed' cache instruction to the entire cache.
*
* Parameters:
* cainst instruction/ that takes an address register parameter
* and an offset parameter (in range 0 .. 3*linesize).
* size size of cache in bytes
* linesize size of cache line in bytes (always power-of-2)
* assoc_or1 number of associativities (ways/sets) in cache
* if all sets affected by cainst,
* or 1 if only one set (or not all sets) of the cache
* is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
* aa, ab unique address registers (temporaries).
* awb set to other than a0 if wb type of instruction
* loopokay 1 allows use of zero-overhead loops, 0 does not
* immrange range (max value) of cainst's immediate offset parameter, in bytes
* (NOTE: macro assumes immrange allows power-of-2 number of lines)
*/
.macro cache_index_all cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
// Number of indices in cache (lines per way):
.set .Lindices, (\size / (\linesize * \assoc_or1))
// Number of indices processed per loop iteration (max 4):
.set .Lperloop, .Lindices
.ifgt .Lperloop - 4
.set .Lperloop, 4
.endif
// Also limit instructions per loop if cache line size exceeds immediate range:
.set .Lmaxperloop, (\maxofs / \linesize) + 1
.ifgt .Lperloop - .Lmaxperloop
.set .Lperloop, .Lmaxperloop
.endif
// Avoid addi of 128 which takes two instructions (addmi,addi):
.ifeq .Lperloop*\linesize - 128
.ifgt .Lperloop - 1
.set .Lperloop, .Lperloop / 2
.endif
.endif
// \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
// XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
.ifne (\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
movi \aa, .Lindices / .Lperloop // number of loop iterations
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
loop \aa, .Lend_cachex\@
.set .Li, 0 ; .rept .Lperloop
\cainst \ab, .Li*\linesize
.set .Li, .Li+1 ; .endr
addi \ab, \ab, .Lperloop*\linesize // move to next line
.Lend_cachex\@:
.else
movi \aa, (\size / \assoc_or1)
// Possible improvement: need only loop if \aa > 1 ;
// however \aa == 1 is highly unlikely.
movi \ab, 0 // to iterate over cache
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
movi \awb, 0
.endif
.Lstart_cachex\@:
.set .Li, 0 ; .rept .Lperloop
\cainst \ab, .Li*\linesize
.set .Li, .Li+1 ; .endr
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
addi \awb, \awb, .Lperloop
blti \awb, 8, .Lstart_memw\@
memw
movi \awb, 0
.Lstart_memw\@:
.endif
addi \ab, \ab, .Lperloop*\linesize // move to next line
bltu \ab, \aa, .Lstart_cachex\@
.endif
.endm
/*
* Macro to apply a 'hit' cache instruction to a memory region,
* ie. to any cache entries that cache a specified portion (region) of memory.
* Takes care of the unaligned cases, ie. may apply to one
* more cache line than $asize / lineSize if $aaddr is not aligned.
*
*
* Parameters are:
* cainst instruction/macro that takes an address register parameter
* and an offset parameter (currently always zero)
* and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
* linesize_log2 log2(size of cache line in bytes)
* addr register containing start address of region (clobbered)
* asize register containing size of the region in bytes (clobbered)
* askew unique register used as temporary
* awb unique register used as temporary for erratum 497.
*
* Note: A possible optimization to this macro is to apply the operation
* to the entire cache if the region exceeds the size of the cache
* by some empirically determined amount or factor. Some experimentation
* is required to determine the appropriate factors, which also need
* to be tunable if required.
*/
.macro cache_hit_region cainst, linesize_log2, addr, asize, askew, awb=a0
// Make \asize the number of iterations:
extui \askew, \addr, 0, \linesize_log2 // get unalignment amount of \addr
add \asize, \asize, \askew // ... and add it to \asize
addi \asize, \asize, (1 << \linesize_log2) - 1 // round up!
srli \asize, \asize, \linesize_log2
// Iterate over region:
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // don't use awb if set to a0
movi \awb, 0
.endif
floopnez \asize, cacheh\@
\cainst \addr, 0
.ifne ((\awb !=a0) & XCHAL_ERRATUM_497) // do memw after 8 cainst wb instructions
addi \awb, \awb, 1
blti \awb, 8, .Lstart_memw\@
memw
movi \awb, 0
.Lstart_memw\@:
.endif
addi \addr, \addr, (1 << \linesize_log2) // move to next line
floopend \asize, cacheh\@
.endm
/*************************** INSTRUCTION CACHE ***************************/
/*
* Reset/initialize the instruction cache by simply invalidating it:
* (need to unlock first also, if cache locking implemented):
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_reset aa, ab, loopokay=0
icache_unlock_all \aa, \ab, \loopokay
icache_invalidate_all \aa, \ab, \loopokay
.endm
/*
* Synchronize after an instruction cache operation,
* to be sure everything is in sync with memory as to be
* expected following any previous instruction cache control operations.
*
* Even if a config doesn't have caches, an isync is still needed
* when instructions in any memory are modified, whether by a loader
* or self-modifying code. Therefore, this macro always produces
* an isync, whether or not an icache is present.
*
* Parameters are:
* ar an address register (temporary) (currently unused, but may be used in future)
*/
.macro icache_sync ar
isync
.endm
/*
* Invalidate a single line of the instruction cache.
* Parameters are:
* ar address register that contains (virtual) address to invalidate
* (may get clobbered in a future implementation, but not currently)
* offset (optional) offset to add to \ar to compute effective address to invalidate
* (note: some number of lsbits are ignored)
*/
.macro icache_invalidate_line ar, offset
#if XCHAL_ICACHE_SIZE > 0
ihi \ar, \offset // invalidate icache line
icache_sync \ar
#endif
.endm
/*
* Invalidate instruction cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_invalidate_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0
// Instruction cache region invalidation:
cache_hit_region ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region invalidation
#endif
.endm
/*
* Invalidate entire instruction cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_invalidate_all aa, ab, loopokay=1
#if XCHAL_ICACHE_SIZE > 0
// Instruction cache invalidation:
cache_index_all iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
icache_sync \aa
// End of instruction cache invalidation
#endif
.endm
/*
* Lock (prefetch & lock) a single line of the instruction cache.
*
* Parameters are:
* ar address register that contains (virtual) address to lock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to lock
* (note: some number of lsbits are ignored)
*/
.macro icache_lock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ipfl \ar, \offset /* prefetch and lock icache line */
icache_sync \ar
#endif
.endm
/*
* Lock (prefetch & lock) a specified portion of memory into the instruction cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_lock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache region lock:
cache_hit_region ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region lock
#endif
.endm
/*
* Unlock a single line of the instruction cache.
*
* Parameters are:
* ar address register that contains (virtual) address to unlock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to unlock
* (note: some number of lsbits are ignored)
*/
.macro icache_unlock_line ar, offset
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
ihu \ar, \offset /* unlock icache line */
icache_sync \ar
#endif
.endm
/*
* Unlock a specified portion of memory from the instruction cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro icache_unlock_region astart, asize, ac
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache region unlock:
cache_hit_region ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
icache_sync \ac
// End of instruction cache region unlock
#endif
.endm
/*
* Unlock entire instruction cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro icache_unlock_all aa, ab, loopokay=1
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
// Instruction cache unlock:
cache_index_all iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
icache_sync \aa
// End of instruction cache unlock
#endif
.endm
/*************************** DATA CACHE ***************************/
/*
* Reset/initialize the data cache by simply invalidating it
* (need to unlock first also, if cache locking implemented):
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_reset aa, ab, loopokay=0
dcache_unlock_all \aa, \ab, \loopokay
dcache_invalidate_all \aa, \ab, \loopokay
.endm
/*
* Synchronize after a data cache operation,
* to be sure everything is in sync with memory as to be
* expected following any previous data cache control operations.
*
* Parameters are:
* ar an address register (temporary) (currently unused, but may be used in future)
*/
.macro dcache_sync ar, wbtype=0
#if XCHAL_DCACHE_SIZE > 0
// No synchronization is needed.
// (memw may be desired e.g. after writeback operation to help ensure subsequent
// external accesses are seen to follow that writeback, however that's outside
// the scope of this macro)
//dsync
.ifne (\wbtype & XCHAL_ERRATUM_497)
memw
.endif
#endif
.endm
/*
* Turn on cache coherence.
*
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
* to change MEMCTL will see its changes dropped if the interrupt comes
* in the middle of this routine. If this might be an issue, call this
* routine with interrupts disabled.
*
* Parameters are:
* ar,at two scratch address registers (both clobbered)
*/
.macro cache_coherence_on ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Enable snoop responses. */
rsr.memctl \ar
movi \at, MEMCTL_SNOOP_EN
or \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt into coherence for MX (for backward compatibility / testing). */
movi \ar, 1
movi \at, XER_CCON
wer \ar, \at
extw
# endif
#endif
.endm
/*
* Turn off cache coherence.
*
* NOTE: this is generally preceded by emptying the cache;
* see xthal_cache_coherence_optout() in hal/coherence.c for details.
*
* WARNING: for RE-201x.x and later hardware, any interrupt that tries
* to change MEMCTL will see its changes dropped if the interrupt comes
* in the middle of this routine. If this might be an issue, call this
* routine with interrupts disabled.
*
* Parameters are:
* ar,at two scratch address registers (both clobbered)
*/
.macro cache_coherence_off ar at
#if XCHAL_DCACHE_IS_COHERENT
# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/* Have MEMCTL. Disable snoop responses. */
rsr.memctl \ar
movi \at, ~MEMCTL_SNOOP_EN
and \ar, \ar, \at
wsr.memctl \ar
# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
/* Opt out of coherence, for MX (for backward compatibility / testing). */
extw
movi \at, 0
movi \ar, XER_CCON
wer \at, \ar
extw
# endif
#endif
.endm
/*
* Synchronize after a data store operation,
* to be sure the stored data is completely off the processor
* (and assuming there is no buffering outside the processor,
* that the data is in memory). This may be required to
* ensure that the processor's write buffers are emptied.
* A MEMW followed by a read guarantees this, by definition.
* We also try to make sure the read itself completes.
*
* Parameters are:
* ar an address register (temporary)
*/
.macro write_sync ar
memw // ensure previous memory accesses are complete prior to subsequent memory accesses
l32i \ar, sp, 0 // completing this read ensures any previous write has completed, because of MEMW
//slot
add \ar, \ar, \ar // use the result of the read to help ensure the read completes (in future architectures)
.endm
/*
* Invalidate a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to invalidate
* (may get clobbered in a future implementation, but not currently)
* offset (optional) offset to add to \ar to compute effective address to invalidate
* (note: some number of lsbits are ignored)
*/
.macro dcache_invalidate_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhi \ar, \offset
dcache_sync \ar
#endif
.endm
/*
* Invalidate data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_invalidate_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0
// Data cache region invalidation:
cache_hit_region dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region invalidation
#endif
.endm
/*
* Invalidate entire data cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_invalidate_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache invalidation:
cache_index_all dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
dcache_sync \aa
// End of data cache invalidation
#endif
.endm
/*
* Writeback a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to writeback
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to writeback
* (note: some number of lsbits are ignored)
*/
.macro dcache_writeback_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
dhwb \ar, \offset
dcache_sync \ar, wbtype=1
#endif
.endm
/*
* Writeback dirty data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_writeback_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
// Data cache region writeback:
cache_hit_region dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
dcache_sync \ac, wbtype=1
// End of data cache region writeback
#endif
.endm
/*
* Writeback entire data cache.
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_writeback_all aa, ab, awb, loopokay=1
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
// Data cache writeback:
cache_index_all diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
dcache_sync \aa, wbtype=1
// End of data cache writeback
#endif
.endm
/*
* Writeback and invalidate a single line of the data cache.
* Parameters are:
* ar address register that contains (virtual) address to writeback and invalidate
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to writeback and invalidate
* (note: some number of lsbits are ignored)
*/
.macro dcache_writeback_inv_line ar, offset
#if XCHAL_DCACHE_SIZE > 0
dhwbi \ar, \offset /* writeback and invalidate dcache line */
dcache_sync \ar, wbtype=1
#endif
.endm
/*
* Writeback and invalidate data cache entries that cache a specified portion of memory.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_writeback_inv_region astart, asize, ac, awb
#if XCHAL_DCACHE_SIZE > 0
// Data cache region writeback and invalidate:
cache_hit_region dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
dcache_sync \ac, wbtype=1
// End of data cache region writeback and invalidate
#endif
.endm
/*
* Writeback and invalidate entire data cache.
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_writeback_inv_all aa, ab, awb, loopokay=1
#if XCHAL_DCACHE_SIZE > 0
// Data cache writeback and invalidate:
#if XCHAL_DCACHE_IS_WRITEBACK
cache_index_all diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
dcache_sync \aa, wbtype=1
#else /*writeback*/
// Data cache does not support writeback, so just invalidate: */
dcache_invalidate_all \aa, \ab, \loopokay
#endif /*writeback*/
// End of data cache writeback and invalidate
#endif
.endm
/*
* Lock (prefetch & lock) a single line of the data cache.
*
* Parameters are:
* ar address register that contains (virtual) address to lock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to lock
* (note: some number of lsbits are ignored)
*/
.macro dcache_lock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dpfl \ar, \offset /* prefetch and lock dcache line */
dcache_sync \ar
#endif
.endm
/*
* Lock (prefetch & lock) a specified portion of memory into the data cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_lock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache region lock:
cache_hit_region dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region lock
#endif
.endm
/*
* Unlock a single line of the data cache.
*
* Parameters are:
* ar address register that contains (virtual) address to unlock
* (may get clobbered in a future implementation, but not currently)
* offset offset to add to \ar to compute effective address to unlock
* (note: some number of lsbits are ignored)
*/
.macro dcache_unlock_line ar, offset
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
dhu \ar, \offset /* unlock dcache line */
dcache_sync \ar
#endif
.endm
/*
* Unlock a specified portion of memory from the data cache.
* Parameters are:
* astart start address (register gets clobbered)
* asize size of the region in bytes (register gets clobbered)
* ac unique register used as temporary
*/
.macro dcache_unlock_region astart, asize, ac
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache region unlock:
cache_hit_region dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
dcache_sync \ac
// End of data cache region unlock
#endif
.endm
/*
* Unlock entire data cache.
*
* Parameters:
* aa, ab unique address registers (temporaries)
*/
.macro dcache_unlock_all aa, ab, loopokay=1
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
// Data cache unlock:
cache_index_all diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
dcache_sync \aa
// End of data cache unlock
#endif
.endm
/*
* Get the number of enabled icache ways. Note that this may
* be different from the value read from the MEMCTL register.
*
* Parameters:
* aa address register where value is returned
*/
.macro icache_get_ways aa
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr.memctl \aa
extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
blti \aa, XCHAL_ICACHE_WAYS, .Licgw
movi \aa, XCHAL_ICACHE_WAYS
.Licgw:
#else
// All ways are always enabled
movi \aa, XCHAL_ICACHE_WAYS
#endif
#else
// No icache
movi \aa, 0
#endif
.endm
/*
* Set the number of enabled icache ways.
*
* Parameters:
* aa address register specifying number of ways (trashed)
* ab,ac address register for scratch use (trashed)
*/
.macro icache_set_ways aa, ab, ac
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22
rsr.memctl \ab
and \ab, \ab, \ac
movi \ac, MEMCTL_INV_EN // set bit 23
slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot
or \ab, \ab, \aa
or \ab, \ab, \ac
wsr.memctl \ab
isync
#else
// All ways are always enabled
#endif
#else
// No icache
#endif
.endm
/*
* Get the number of enabled dcache ways. Note that this may
* be different from the value read from the MEMCTL register.
*
* Parameters:
* aa address register where value is returned
*/
.macro dcache_get_ways aa
#if XCHAL_DCACHE_SIZE > 0
#if XCHAL_HAVE_DCACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr.memctl \aa
extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw
movi \aa, XCHAL_DCACHE_WAYS
.Ldcgw:
#else
// All ways are always enabled
movi \aa, XCHAL_DCACHE_WAYS
#endif
#else
// No dcache
movi \aa, 0
#endif
.endm
/*
* Set the number of enabled dcache ways.
*
* Parameters:
* aa address register specifying number of ways (trashed)
* ab,ac address register for scratch use (trashed)
*/
.macro dcache_set_ways aa, ab, ac
#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17
rsr.memctl \ab
and \ab, \ab, \ac // clear ways allocatable
slli \ac, \aa, MEMCTL_DCWA_SHIFT
or \ab, \ab, \ac // set ways allocatable
wsr.memctl \ab
#if XCHAL_DCACHE_IS_WRITEBACK
// Check if the way count is increasing or decreasing
extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use
bge \aa, \ac, .Ldsw3 // equal or increasing
slli \ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // start way number
slli \ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH // end way number
.Ldsw1:
diwbui.p \ab // auto-increments ab
bge \ab, \ac, .Ldsw2
beqz \ab, .Ldsw2
j .Ldsw1
.Ldsw2:
rsr.memctl \ab
#endif
.Ldsw3:
// No dirty data to write back, just set the new number of ways
movi \ac, MEMCTL_DCWU_CLR_MASK // set up to clear bits 8-12
and \ab, \ab, \ac // clear ways in use
movi \ac, MEMCTL_INV_EN
or \ab, \ab, \ac // set bit 23
slli \aa, \aa, MEMCTL_DCWU_SHIFT
or \ab, \ab, \aa // set ways in use
wsr.memctl \ab
#else
// No dcache or no way disable support
#endif
.endm
#endif /*XTENSA_CACHEASM_H*/

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/*
* xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
* that depend on CORE configuration
*
* This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
* but is kept separate for modularity / compilation-performance.
*/
/*
* Copyright (c) 2001-2009 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHEATTRASM_H
#define XTENSA_CACHEATTRASM_H
#include <xtensa/coreasm.h>
/* Determine whether cache attributes are controlled using eight 512MB entries: */
#define XCHAL_CA_8X512 (XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
/*
* This header file defines assembler macros of the form:
* <x>cacheattr_<func>
* where:
* <x> is 'i', 'd' or absent for instruction, data
* or both caches; and
* <func> indicates the function of the macro.
*
* The following functions are defined:
*
* icacheattr_get
* Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
*
* dcacheattr_get
* Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
* (Note: for configs with a real CACHEATTR register, the
* above two macros are identical.)
*
* cacheattr_set
* Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
* Works even when changing one's own code's attributes.
*
* icacheattr_is_enabled label
* Branches to \label if I-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* dcacheattr_is_enabled label
* Branches to \label if D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* cacheattr_is_enabled label
* Branches to \label if either I-cache or D-cache appears to have been enabled
* (eg. if CACHEATTR contains a cache-enabled attribute).
* (clobbers a2-a5,SAR)
*
* The following macros are only defined under certain conditions:
*
* icacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
*
* dcacheattr_set (if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
* Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
*/
/*************************** GENERIC -- ALL CACHES ***************************/
/*
* _cacheattr_get
*
* (Internal macro.)
* Returns value of CACHEATTR register (or closest equivalent) in a2.
*
* Entry:
* (none)
* Exit:
* a2 value read from CACHEATTR
* a3-a5 clobbered (temporaries)
*/
.macro _cacheattr_get tlb
#if XCHAL_HAVE_CACHEATTR
rsr.cacheattr a2
#elif XCHAL_CA_8X512
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
// DTLB and ITLB are independent, so there's no single
// cache attribute that can describe both. So for now
// just return the DTLB state.
movi a5, 0xE0000000
movi a2, 0
movi a3, XCHAL_SPANNING_WAY
1: add a3, a3, a5 // next segment
r&tlb&1 a4, a3 // get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
dsync // interlock???
slli a2, a2, 4
extui a4, a4, 0, 4 // extract CA
or a2, a2, a4
bgeui a3, 16, 1b
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Just return zero.
movi a2, 0
#endif
.endm
.macro icacheattr_get
_cacheattr_get itlb
.endm
.macro dcacheattr_get
_cacheattr_get dtlb
.endm
/* Default (powerup/reset) value of CACHEATTR,
all BYPASS mode (ie. disabled/bypassed caches): */
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_CACHEATTR_ALL_BYPASS 0x33333333
#else
# define XCHAL_CACHEATTR_ALL_BYPASS 0x22222222
#endif
#if XCHAL_CA_8X512
#if XCHAL_HAVE_PTP_MMU
# define XCHAL_FCA_ENAMASK 0x0AA0 /* bitmap of fetch attributes that require enabled icache */
# define XCHAL_LCA_ENAMASK 0x0FF0 /* bitmap of load attributes that require enabled dcache */
# define XCHAL_SCA_ENAMASK 0x0CC0 /* bitmap of store attributes that require enabled dcache */
#else
# define XCHAL_FCA_ENAMASK 0x003A /* bitmap of fetch attributes that require enabled icache */
# define XCHAL_LCA_ENAMASK 0x0033 /* bitmap of load attributes that require enabled dcache */
# define XCHAL_SCA_ENAMASK 0x0033 /* bitmap of store attributes that require enabled dcache */
#endif
#define XCHAL_LSCA_ENAMASK (XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK) /* l/s attrs requiring enabled dcache */
#define XCHAL_ALLCA_ENAMASK (XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK) /* all attrs requiring enabled caches */
/*
* _cacheattr_is_enabled
*
* (Internal macro.)
* Branches to \label if CACHEATTR in a2 indicates an enabled
* cache, using mask in a3.
*
* Parameters:
* label where to branch to if cache is enabled
* Entry:
* a2 contains CACHEATTR value used to determine whether
* caches are enabled
* a3 16-bit constant where each bit correspond to
* one of the 16 possible CA values (in a CACHEATTR mask);
* CA values that indicate the cache is enabled
* have their corresponding bit set in this mask
* (eg. use XCHAL_xCA_ENAMASK , above)
* Exit:
* a2,a4,a5 clobbered
* SAR clobbered
*/
.macro _cacheattr_is_enabled label
movi a4, 8 // loop 8 times
.Lcaife\@:
extui a5, a2, 0, 4 // get CA nibble
ssr a5 // index into mask according to CA...
srl a5, a3 // ...and get CA's mask bit in a5 bit 0
bbsi.l a5, 0, \label // if CA indicates cache enabled, jump to label
srli a2, a2, 4 // next nibble
addi a4, a4, -1
bnez a4, .Lcaife\@ // loop for each nibble
.endm
#else /* XCHAL_CA_8X512 */
.macro _cacheattr_is_enabled label
j \label // macro not applicable, assume caches always enabled
.endm
#endif /* XCHAL_CA_8X512 */
/*
* icacheattr_is_enabled
*
* Branches to \label if I-cache is enabled.
*
* Parameters:
* label where to branch to if icache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro icacheattr_is_enabled label
#if XCHAL_CA_8X512
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* dcacheattr_is_enabled
*
* Branches to \label if D-cache is enabled.
*
* Parameters:
* label where to branch to if dcache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro dcacheattr_is_enabled label
#if XCHAL_CA_8X512
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* cacheattr_is_enabled
*
* Branches to \label if either I-cache or D-cache is enabled.
*
* Parameters:
* label where to branch to if a cache is enabled
* Entry:
* (none)
* Exit:
* a2-a5, SAR clobbered (temporaries)
*/
.macro cacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR
rsr.cacheattr a2
movi a3, XCHAL_ALLCA_ENAMASK
#elif XCHAL_CA_8X512
icacheattr_get
movi a3, XCHAL_FCA_ENAMASK
_cacheattr_is_enabled \label
dcacheattr_get
movi a3, XCHAL_LSCA_ENAMASK
#endif
_cacheattr_is_enabled \label
.endm
/*
* The ISA does not have a defined way to change the
* instruction cache attributes of the running code,
* ie. of the memory area that encloses the current PC.
* However, each micro-architecture (or class of
* configurations within a micro-architecture)
* provides a way to deal with this issue.
*
* Here are a few macros used to implement the relevant
* approach taken.
*/
#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
/*
* icacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro icacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a6, 3f // PC where ITLB is set
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
and a6, a6, a5 // upper 3 bits of local PC area
j 3f
// Use micro-architecture specific method.
// The following 4-instruction sequence is aligned such that
// it all fits within a single I-cache line. Sixteen byte
// alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
// actually causes problems because that can be greater than
// the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/
1: witlb a4, a3 // write wired PTE (CA, no PPN) of 512MB segment to ITLB
isync
.end no-transform
nop
nop
sub a3, a3, a5 // next segment (add 0x20000000)
bltui a3, 16, 4f // done?
// Note that in the WITLB loop, we don't do any load/stores
// (may not be an issue here, but it is important in the DTLB case).
2: srli a7, a7, 4 // next CA
3:
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
ritlb1 a8, a3 // get current PPN+CA of segment
//dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# endif
beq a3, a6, 1b // current PC's region? if so, do it in a safe way
witlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to ITLB
sub a3, a3, a5 // next segment (add 0x20000000)
bgeui a3, 16, 2b
isync // make sure all ifetch changes take effect
4:
.endm // icacheattr_set
/*
* dcacheattr_set
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro dcacheattr_set
movi a5, 0xE0000000 // mask of upper 3 bits
movi a3, XCHAL_SPANNING_WAY // start at region 0 (0 .. 7)
mov a7, a2 // copy a2 so it doesn't get clobbered
// Note that in the WDTLB loop, we don't do any load/stores
2: // (including implicit l32r via movi) because it isn't safe.
# if XCHAL_HAVE_MIMIC_CACHEATTR
extui a4, a7, 0, 4 // extract CA to set
# else /* have translation, preserve it: */
rdtlb1 a8, a3 // get current PPN+CA of segment
//dsync // interlock???
extui a4, a7, 0, 4 // extract CA to set
srli a8, a8, 4 // clear CA but keep PPN ...
slli a8, a8, 4 // ...
add a4, a4, a8 // combine new CA with PPN to preserve
# endif
wdtlb a4, a3 // write wired PTE (CA [+PPN]) of 512MB segment to DTLB
sub a3, a3, a5 // next segment (add 0x20000000)
srli a7, a7, 4 // next CA
bgeui a3, 16, 2b
dsync // make sure all data path changes take effect
.endm // dcacheattr_set
#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
/*
* cacheattr_set
*
* Macro that sets the current CACHEATTR safely
* (both i and d) according to the current contents of a2.
* It works even when changing the cache attributes of
* the currently running code.
*
* Entry:
* a2 cacheattr value to set
* Exit:
* a2 unchanged
* a3-a8 clobbered (temporaries)
*/
.macro cacheattr_set
#if XCHAL_HAVE_CACHEATTR
# if XCHAL_ICACHE_LINESIZE < 4
// No i-cache, so can always safely write to CACHEATTR:
wsr.cacheattr a2
# else
// The Athens micro-architecture, when using the old
// exception architecture option (ie. with the CACHEATTR register)
// allows changing the cache attributes of the running code
// using the following exact sequence aligned to be within
// an instruction cache line. (NOTE: using XCHAL_ICACHE_LINESIZE
// alignment actually causes problems because that can be greater
// than the alignment of the reset vector, where this macro is often
// invoked, which would cause the linker to align the reset
// vector code away from the reset vector!!).
j 1f
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
1: wsr.cacheattr a2
isync
.end no-transform
nop
nop
# endif
#elif XCHAL_CA_8X512
// DTLB and ITLB are independent, but to keep semantics
// of this macro we simply write to both.
icacheattr_set
dcacheattr_set
#else
// This macro isn't applicable to arbitrary MMU configurations.
// Do nothing in this case.
#endif
.endm
#endif /*XTENSA_CACHEATTRASM_H*/

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@ -0,0 +1,505 @@
/*
* xtensa/core-macros.h -- C specific definitions
* that depend on CORE configuration
*/
/*
* Copyright (c) 2012 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_CACHE_H
#define XTENSA_CACHE_H
#include <xtensa/config/core.h>
/* Only define things for C code. */
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
/*************************** CACHE ***************************/
/* All the macros are in the lower case now and some of them
* share the name with the existing functions from hal.h.
* Including this header file will define XTHAL_USE_CACHE_MACROS
* which directs hal.h not to use the functions.
*
*
* Single-cache-line operations in C-callable inline assembly.
* Essentially macro versions (uppercase) of:
*
* xthal_icache_line_invalidate(void *addr);
* xthal_icache_line_lock(void *addr);
* xthal_icache_line_unlock(void *addr);
* xthal_icache_sync(void);
*
* NOTE: unlike the above functions, the following macros do NOT
* execute the xthal_icache_sync() as part of each line operation.
* This sync must be called explicitly by the caller. This is to
* allow better optimization when operating on more than one line.
*
* xthal_dcache_line_invalidate(void *addr);
* xthal_dcache_line_writeback(void *addr);
* xthal_dcache_line_writeback_inv(void *addr);
* xthal_dcache_line_lock(void *addr);
* xthal_dcache_line_unlock(void *addr);
* xthal_dcache_sync(void);
* xthal_dcache_line_prefetch_for_write(void *addr);
* xthal_dcache_line_prefetch_for_read(void *addr);
*
* All are made memory-barriers, given that's how they're typically used
* (ops operate on a whole line, so clobbers all memory not just *addr).
*
* NOTE: All the block block cache ops and line prefetches are implemented
* using intrinsics so they are better optimized regarding memory barriers etc.
*
* All block downgrade functions exist in two forms: with and without
* the 'max' parameter: This parameter allows compiler to optimize
* the functions whenever the parameter is smaller than the cache size.
*
* xthal_dcache_block_invalidate(void *addr, unsigned size);
* xthal_dcache_block_writeback(void *addr, unsigned size);
* xthal_dcache_block_writeback_inv(void *addr, unsigned size);
* xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
* xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
* xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
*
* xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
* xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
* xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
* xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
*
* xthal_dcache_block_wait();
* xthal_dcache_block_required_wait();
* xthal_dcache_block_abort();
* xthal_dcache_block_prefetch_end();
* xthal_dcache_block_newgrp();
*/
/*** INSTRUCTION CACHE ***/
#define XTHAL_USE_CACHE_MACROS
#if XCHAL_ICACHE_SIZE > 0
# define xthal_icache_line_invalidate(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_icache_line_invalidate(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
# define xthal_icache_line_lock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_icache_line_unlock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_icache_line_lock(addr) do {/*nothing*/} while(0)
# define xthal_icache_line_unlock(addr) do {/*nothing*/} while(0)
#endif
/*
* Even if a config doesn't have caches, an isync is still needed
* when instructions in any memory are modified, whether by a loader
* or self-modifying code. Therefore, this macro always produces
* an isync, whether or not an icache is present.
*/
#define xthal_icache_sync() \
__asm__ __volatile__("isync":::"memory")
/*** DATA CACHE ***/
#if XCHAL_DCACHE_SIZE > 0
# include <xtensa/tie/xt_datacache.h>
# define xthal_dcache_line_invalidate(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_writeback(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_writeback_inv(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_sync() \
__asm__ __volatile__("" /*"dsync"?*/:::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do { \
XT_DPFR((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_invalidate(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_writeback_inv(addr) do {/*nothing*/} while(0)
# define xthal_dcache_sync() __asm__ __volatile__("":::"memory")
# define xthal_dcache_line_prefetch_for_read(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
# define xthal_dcache_line_lock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); \
} while(0)
# define xthal_dcache_line_unlock(addr) do { void *__a = (void*)(addr); \
__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); \
} while(0)
#else
# define xthal_dcache_line_lock(addr) do {/*nothing*/} while(0)
# define xthal_dcache_line_unlock(addr) do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_line_prefetch_for_write(addr) do { \
XT_DPFW((const int*)addr, 0); \
} while(0)
#else
# define xthal_dcache_line_prefetch_for_write(addr) do {/*nothing*/} while(0)
#endif
/***** Block Operations *****/
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
/* upgrades */
# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type) \
{ \
type((const int*)addr, size); \
}
/*downgrades */
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
unsigned _s = size; \
unsigned _a = (unsigned) addr; \
do { \
unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
XCHAL_DCACHE_SIZE : _s; \
type((const int*)_a, __s); \
_s -= __s; \
_a += __s; \
} while(_s > 0);
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
if (max <= XCHAL_DCACHE_SIZE) { \
unsigned _s = size; \
unsigned _a = (unsigned) addr; \
type((const int*)_a, _s); \
} \
else { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type); \
}
# define xthal_dcache_block_invalidate(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B); \
} while(0)
# define xthal_dcache_block_writeback(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B); \
} while(0)
# define xthal_dcache_block_writeback_inv(addr, size) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B); \
} while(0)
# define xthal_dcache_block_invalidate_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max); \
} while(0)
# define xthal_dcache_block_writeback_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max); \
} while(0)
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do { \
_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max); \
} while(0)
/* upgrades that are performed even with write-thru caches */
# define xthal_dcache_block_prefetch_read_write(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
} while(0)
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
} while(0)
# define xthal_dcache_block_prefetch_for_read(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B); \
} while(0)
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF); \
} while(0)
/* abort all or end optional block cache operations */
# define xthal_dcache_block_abort() do { \
XT_PFEND_A(); \
} while(0)
# define xthal_dcache_block_end() do { \
XT_PFEND_O(); \
} while(0)
/* wait for all/required block cache operations to finish */
# define xthal_dcache_block_wait() do { \
XT_PFWAIT_A(); \
} while(0)
# define xthal_dcache_block_required_wait() do { \
XT_PFWAIT_R(); \
} while(0)
/* Start a new group */
# define xthal_dcache_block_newgrp() do { \
XT_PFNXT_F(); \
} while(0)
#else
# define xthal_dcache_block_invalidate(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_inv(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_invalidate_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_writeback_inv_max(addr, size, max) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_read_write(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_read(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_end() do {/*nothing*/} while(0)
# define xthal_dcache_block_abort() do {/*nothing*/} while(0)
# define xthal_dcache_block_wait() do {/*nothing*/} while(0)
# define xthal_dcache_block_required_wait() do {/*nothing*/} while(0)
# define xthal_dcache_block_newgrp() do {/*nothing*/} while(0)
#endif
#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
# define xthal_dcache_block_prefetch_for_write(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B); \
} while(0)
# define xthal_dcache_block_prefetch_modify(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B); \
} while(0)
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF); \
} while(0)
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do { \
_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF); \
} while(0)
#else
# define xthal_dcache_block_prefetch_for_write(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_modify(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {/*nothing*/} while(0)
# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {/*nothing*/} while(0)
#endif
/*************************** INTERRUPTS ***************************/
/*
* Macro versions of:
* unsigned xthal_get_intenable( void );
* void xthal_set_intenable( unsigned );
* unsigned xthal_get_interrupt( void );
* void xthal_set_intset( unsigned );
* void xthal_set_intclear( unsigned );
* unsigned xthal_get_ccount(void);
* void xthal_set_ccompare(int, unsigned);
* unsigned xthal_get_ccompare(int);
*
* NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
*/
#if XCHAL_HAVE_INTERRUPTS
# define XTHAL_GET_INTENABLE() ({ int __intenable; \
__asm__("rsr.intenable %0" : "=a"(__intenable)); \
__intenable; })
# define XTHAL_SET_INTENABLE(v) do { int __intenable = (int)(v); \
__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
} while(0)
# define XTHAL_GET_INTERRUPT() ({ int __interrupt; \
__asm__ __volatile__("rsr.interrupt %0" : "=a"(__interrupt)); \
__interrupt; })
# define XTHAL_SET_INTSET(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_SET_INTCLEAR(v) do { int __interrupt = (int)(v); \
__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
} while(0)
# define XTHAL_GET_CCOUNT() ({ int __ccount; \
__asm__ __volatile__("rsr.ccount %0" : "=a"(__ccount)); \
__ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
} while(0)
# define _XTHAL_GET_CCOMPARE(n) ({ int __ccompare; \
__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
__ccompare; })
# define XTHAL_GET_CCOMPARE(n) _XTHAL_GET_CCOMPARE(n)
# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
} while(0)
# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
#else
# define XTHAL_GET_INTENABLE() 0
# define XTHAL_SET_INTENABLE(v) do {/*nothing*/} while(0)
# define XTHAL_GET_INTERRUPT() 0
# define XTHAL_SET_INTSET(v) do {/*nothing*/} while(0)
# define XTHAL_SET_INTCLEAR(v) do {/*nothing*/} while(0)
# define XTHAL_GET_CCOUNT() 0
# define XTHAL_SET_CCOUNT(v) do {/*nothing*/} while(0)
# define XTHAL_GET_CCOMPARE(n) 0
# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
#endif
/* New functions added to accomodate XEA3 and allow deprecation of older
functions. For this release they just map to the older ones. */
/* Enables the specified interrupt. */
static inline void xthal_interrupt_enable(unsigned intnum)
{
xthal_int_enable(1 << intnum);
}
/* Disables the specified interrupt. */
static inline void xthal_interrupt_disable(unsigned intnum)
{
xthal_int_disable(1 << intnum);
}
/* Triggers the specified interrupt. */
static inline void xthal_interrupt_trigger(unsigned intnum)
{
xthal_set_intset(1 << intnum);
}
/* Clears the specified interrupt. */
static inline void xthal_interrupt_clear(unsigned intnum)
{
xthal_set_intclear(1 << intnum);
}
/*************************** MISC ***************************/
/*
* Macro or inline versions of:
* void xthal_clear_regcached_code( void );
* unsigned xthal_get_prid( void );
* unsigned xthal_compare_and_set( int *addr, int testval, int setval );
*/
#if XCHAL_HAVE_LOOPS
# define XTHAL_CLEAR_REGCACHED_CODE() \
__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
#else
# define XTHAL_CLEAR_REGCACHED_CODE() do {/*nothing*/} while(0)
#endif
#if XCHAL_HAVE_PRID
# define XTHAL_GET_PRID() ({ int __prid; \
__asm__("rsr.prid %0" : "=a"(__prid)); \
__prid; })
#else
# define XTHAL_GET_PRID() 0
#endif
static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
{
int result;
#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
__asm__ __volatile__ (
" wsr.scompare1 %2 \n"
" s32c1i %0, %3, 0 \n"
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
: "memory");
#elif XCHAL_HAVE_INTERRUPTS
int tmp;
__asm__ __volatile__ (
" rsil %4, 15 \n" // %4 == saved ps
" l32i %0, %3, 0 \n" // %0 == value to test, return val
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: wsr.ps %4 ; rsync \n" // restore the PS
: "=a"(result)
: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
: "memory");
#else
__asm__ __volatile__ (
" l32i %0, %3, 0 \n" // %0 == value to test, return val
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: \n"
: "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
: "memory");
#endif
return result;
}
#if XCHAL_HAVE_EXTERN_REGS
static inline unsigned XTHAL_RER (unsigned int reg)
{
unsigned result;
__asm__ __volatile__ (
" rer %0, %1"
: "=a" (result) : "a" (reg) : "memory");
return result;
}
static inline void XTHAL_WER (unsigned reg, unsigned value)
{
__asm__ __volatile__ (
" wer %0, %1"
: : "a" (value), "a" (reg) : "memory");
}
#endif /* XCHAL_HAVE_EXTERN_REGS */
/*
* Sets a single entry at 'index' within the MPU
*
* The caller must ensure that the resulting MPU map is ordered.
*/
static inline void xthal_mpu_set_entry (xthal_MPU_entry entry)
{
#if XCHAL_HAVE_MPU
__asm__ __volatile__("j 1f\n\t.align 8\n\t1: memw\n\twptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
#endif
}
/* Same as xthal_mpu_set_entry except that this function must not be used to change the MPU entry
* for the currently executing instruction ... use xthal_mpu_set_entry instead. */
static inline void xthal_mpu_set_entry_ (xthal_MPU_entry entry)
{
#if XCHAL_HAVE_MPU
__asm__ __volatile__("wptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
#endif
}
#endif /* C code */
#endif /*XTENSA_CACHE_H*/

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/*
* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
*
* (In previous releases, these were defined in specreg.h, a generated file.
* This file is not generated, ie. it is processor configuration independent.)
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/corebits.h#1 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_COREBITS_H
#define XTENSA_COREBITS_H
/* EXCCAUSE register fields: */
#define EXCCAUSE_EXCCAUSE_SHIFT 0
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
/* EXCCAUSE register values: */
/*
* General Exception Causes
* (values of EXCCAUSE special register set by general exceptions,
* which vector to the user, kernel, or double-exception vectors).
*/
#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
# define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (deprecated) */
#define EXCCAUSE_PC_ERROR 7 /* Next PC Value Illegal */
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
#define EXCCAUSE_EXTREG_PRIVILEGE 10 /* External Register Privilege Error */
#define EXCCAUSE_EXCLUSIVE_ERROR 11 /* Load exclusive to unsupported memory type or unaligned address */
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
/* Reserved 21..23 */
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
/* Reserved 30..31 */
#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
/* Reserved 40..63 */
/* PS register fields: */
#define PS_WOE_SHIFT 18
#define PS_WOE_MASK 0x00040000
#define PS_WOE PS_WOE_MASK
#define PS_CALLINC_SHIFT 16
#define PS_CALLINC_MASK 0x00030000
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
#define PS_OWB_SHIFT 8
#define PS_OWB_MASK 0x00000F00
#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
#define PS_RING_SHIFT 6
#define PS_RING_MASK 0x000000C0
#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
#define PS_UM_SHIFT 5
#define PS_UM_MASK 0x00000020
#define PS_UM PS_UM_MASK
#define PS_EXCM_SHIFT 4
#define PS_EXCM_MASK 0x00000010
#define PS_EXCM PS_EXCM_MASK
#define PS_INTLEVEL_SHIFT 0
#define PS_INTLEVEL_MASK 0x0000000F
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
/* ABI-derived field values: */
#ifdef __XTENSA_CALL0_ABI__
#define PS_WOE_ABI 0
#define PS_WOECALL4_ABI 0
#else
#define PS_WOE_ABI PS_WOE /* 0x40000 */
#define PS_WOECALL4_ABI (PS_WOE | PS_CALLINC(1)) /* 0x50000, per call4 */
#endif
/* Backward compatibility (deprecated): */
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
#define PS_PROGSTACK_MASK PS_UM_MASK
#define PS_PROG_SHIFT PS_UM_SHIFT
#define PS_PROG_MASK PS_UM_MASK
#define PS_PROG PS_UM
/* DBREAKCn register fields: */
#define DBREAKC_MASK_SHIFT 0
#define DBREAKC_MASK_MASK 0x0000003F
#define DBREAKC_LOADBREAK_SHIFT 30
#define DBREAKC_LOADBREAK_MASK 0x40000000
#define DBREAKC_STOREBREAK_SHIFT 31
#define DBREAKC_STOREBREAK_MASK 0x80000000
/* DEBUGCAUSE register fields: */
#define DEBUGCAUSE_DEBUGINT_SHIFT 5
#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
#define DEBUGCAUSE_BREAKN_SHIFT 4
#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
#define DEBUGCAUSE_BREAK_SHIFT 3
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
#define DEBUGCAUSE_DBREAK_SHIFT 2
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
#define DEBUGCAUSE_IBREAK_SHIFT 1
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
#define DEBUGCAUSE_ICOUNT_SHIFT 0
#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
/* MESR register fields: */
#define MESR_MEME 0x00000001 /* memory error */
#define MESR_MEME_SHIFT 0
#define MESR_DME 0x00000002 /* double memory error */
#define MESR_DME_SHIFT 1
#define MESR_RCE 0x00000010 /* recorded memory error */
#define MESR_RCE_SHIFT 4
#define MESR_LCE
#define MESR_LCE_SHIFT ?
#define MESR_LCE_L
#define MESR_ERRENAB 0x00000100
#define MESR_ERRENAB_SHIFT 8
#define MESR_ERRTEST 0x00000200
#define MESR_ERRTEST_SHIFT 9
#define MESR_DATEXC 0x00000400
#define MESR_DATEXC_SHIFT 10
#define MESR_INSEXC 0x00000800
#define MESR_INSEXC_SHIFT 11
#define MESR_WAYNUM_SHIFT 16
#define MESR_ACCTYPE_SHIFT 20
#define MESR_MEMTYPE_SHIFT 24
#define MESR_ERRTYPE_SHIFT 30
/* MEMCTL register fields: */
#define MEMCTL_SNOOP_EN_SHIFT 1
#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
#define MEMCTL_L0IBUF_EN_SHIFT 0
#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
#define MEMCTL_INV_EN_SHIFT 23
#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
#define MEMCTL_DCWU_SHIFT 8
#define MEMCTL_DCWU_BITS 5
#define MEMCTL_DCWA_SHIFT 13
#define MEMCTL_DCWA_BITS 5
#define MEMCTL_ICWU_SHIFT 18
#define MEMCTL_ICWU_BITS 5
#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
#endif /*XTENSA_COREBITS_H*/

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/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _IDMAASM_H_
#define _IDMAASM_H_
#if XCHAL_HAVE_IDMA
#include <xtensa/idma.h>
#endif
/*
* Macro for restore IDMA regs
*
* Parameters:
* a_save => address register containing pointer to IDMA save area
* a_temp1, a_temp2, a_temp3. => address register temporaries
*/
// IDMA_REG_SETTINGS,
// IDMA_REG_TIMEOUT,
// IDMA_REG_DESC_START,
// IDMA_REG_CONTROL,
// IDMA_REG_USERPRIV,
.macro _idma_restore a_save, a_temp1, a_temp2, a_temp3
#if XCHAL_HAVE_IDMA
l32i \a_temp1, \a_save, 0
movi \a_temp3, idmareg_base
movi \a_temp2, IDMA_REG_SETTINGS
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 4
movi \a_temp2, IDMA_REG_TIMEOUT
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 8
movi \a_temp2, IDMA_REG_DESC_START
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 12
movi \a_temp2, IDMA_REG_CONTROL
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 16
movi \a_temp2, IDMA_REG_USERPRIV
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
#endif
.endm
#endif //_IDMAASM_H_

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/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _MPUASM_H_
#define _MPUASM_H_
#include <xtensa/config/core.h>
/*
* Macro for writing MPU map.
*
* Parameters:
* a_map => address register containing pointer to MPU map
* a_num_entries => number of entries in the forementioned map
* a_temp1, a_temp2. => address register temporaries
* a_temp3, a_temp4
*/
.macro mpu_write_map a_map, a_num_entries, a_temp1, a_temp2, a_temp3, a_temp4
#if XCHAL_HAVE_MPU
movi \a_temp1, 0
wsr.cacheadrdis \a_temp1 // enable the cache in all regions
wsr.mpuenb \a_temp1 // disable all foreground entries
// Clear out the unused entries.
//
// Currently we are clearing out all the entries because currently
// the entries must be ordered even if they are all disabled.
// If out of order entries were permitted when all are disabled,
// performance could be improved by clearing XCHAL_MPU_ENTRIES - n
// (n = number of entries) rather than XCHAL_MPU_ENTRIES - 1 entries.
//
movi \a_temp2, 0
movi \a_temp3, XCHAL_MPU_ENTRIES - 1
j 1f
.align 16 // this alignment is done to ensure that
1:
memw // todo currently wptlb must be preceeded by a memw. The instructions must
// be aligned to ensure that both are in the same cache line. These statements should be
// properly conditionalized when that restriction is removed from the HW
wptlb \a_temp2, \a_temp1
addi \a_temp2, \a_temp2, 1
bltu \a_temp2, \a_temp3, 1b
// Write the new entries.
//
beqz \a_num_entries, 4f // if no entries, skip loop
addx8 \a_map, \a_num_entries, \a_map // compute end of provided map
j 3f
.align 16
2: memw // todo currently wptlb must be preceeded by a memw. The instructions must
// be aligned to ensure that both are in the same cache line. These statements should be
// properly conditionalized when that restriction is removed from the HW
wptlb \a_temp2, \a_temp4
addi \a_temp3, \a_temp3, -1
beqz \a_num_entries, 4f // loop until done
3: addi \a_map, \a_map, -8
l32i \a_temp2, \a_map, 4 // get at (acc.rights, memtype)
l32i \a_temp4, \a_map, 0 // get as (vstart, valid)
addi \a_num_entries, \a_num_entries, -1
extui \a_temp1, \a_temp2, 0, 5 // entry index portion
xor \a_temp2, \a_temp2, \a_temp1 // zero it
or \a_temp2, \a_temp2, \a_temp3 // set index = \a_temp3
j 2b
4:
#endif
.endm
/*
* Macro for reading MPU map
*
* Parameters:
* a_map_ptr => address register pointing to memory where map is written
* a_temp1, a_temp2 => address register temporaries
*/
.macro mpu_read_map a_map_ptr, a_temp1, a_temp2
#if XCHAL_HAVE_MPU
movi \a_temp1, XCHAL_MPU_ENTRIES // set index to last entry + 1
addx8 \a_map_ptr, \a_temp1, \a_map_ptr // set map ptr to last entry + 1
1: addi \a_temp1, \a_temp1, -1 // decrement index
addi \a_map_ptr, \a_map_ptr, -8 // decrement index
rptlb0 \a_temp2, \a_temp1 // read 1/2 of entry
s32i \a_temp2, \a_map_ptr, 0 // write 1/2 of entry
rptlb1 \a_temp2, \a_temp1
s32i \a_temp2, \a_map_ptr, 4
bnez \a_temp1, 1b // loop until done
#endif
.endm
#endif

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/*
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/specreg.h#1 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_SPECREG_H
#define XTENSA_SPECREG_H
/* Special registers: */
#define LBEG 0
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define LITBASE 5
#define SCOMPARE1 12
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define PREFCTL 40
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define MEMCTL 97
#define CACHEATTR 98 /* until T1050, XEA1 */
#define CACHEADRDIS 98 /* LX7+ */
#define ATOMCTL 99
#define DDR 104
#define MECR 110
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
#define DBREAKA_1 145
#define DBREAKC_0 160
#define DBREAKC_1 161
#define CONFIGID0 176
#define EPC_1 177
#define EPC_2 178
#define EPC_3 179
#define EPC_4 180
#define EPC_5 181
#define EPC_6 182
#define EPC_7 183
#define DEPC 192
#define EPS_2 194
#define EPS_3 195
#define EPS_4 196
#define EPS_5 197
#define EPS_6 198
#define EPS_7 199
#define CONFIGID1 208
#define EXCSAVE_1 209
#define EXCSAVE_2 210
#define EXCSAVE_3 211
#define EXCSAVE_4 212
#define EXCSAVE_5 213
#define EXCSAVE_6 214
#define EXCSAVE_7 215
#define CPENABLE 224
#define INTERRUPT 226
#define INTREAD INTERRUPT /* alternate name for backward compatibility */
#define INTSET INTERRUPT /* alternate name for backward compatibility */
#define INTCLEAR 227
#define INTENABLE 228
#define PS 230
#define VECBASE 231
#define EXCCAUSE 232
#define DEBUGCAUSE 233
#define CCOUNT 234
#define PRID 235
#define ICOUNT 236
#define ICOUNTLEVEL 237
#define EXCVADDR 238
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242
#define MISC_REG_0 244
#define MISC_REG_1 245
#define MISC_REG_2 246
#define MISC_REG_3 247
/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
#define EPC 176
#define EPS 192
#define EXCSAVE 208
#define CCOMPARE 240
#define MISC_REG 244
/* Tensilica-defined user registers: */
#if 0
/*#define ... 21..24 */ /* (545CK) */
/*#define ... 140..143 */ /* (545CK) */
#define EXPSTATE 230 /* Diamond */
#define THREADPTR 231 /* threadptr option */
#define FCR 232 /* FPU */
#define FSR 233 /* FPU */
#define AE_OVF_SAR 240 /* HiFi2 */
#define AE_BITHEAD 241 /* HiFi2 */
#define AE_TS_FTS_BU_BP 242 /* HiFi2 */
#define AE_SD_NO 243 /* HiFi2 */
#define VSAR 240 /* VectraLX */
#define ROUND_LO 242 /* VectraLX */
#define ROUND_HI 243 /* VectraLX */
#define CBEGIN 246 /* VectraLX */
#define CEND 247 /* VectraLX */
#endif
#endif /* XTENSA_SPECREG_H */

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/* TRAX register definitions
Copyright (c) 2006-2012 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _TRAX_REGISTERS_H_
#define _TRAX_REGISTERS_H_
#define SHOW 1
#define HIDE 0
#define RO 0
#define RW 1
/* TRAX Register Numbers (from possible range of 0..127) */
#if 0
#define TRAXREG_ID 0
#define TRAXREG_CONTROL 1
#define TRAXREG_STATUS 2
#define TRAXREG_DATA 3
#define TRAXREG_ADDRESS 4
#define TRAXREG_TRIGGER 5
#define TRAXREG_MATCH 6
#define TRAXREG_DELAY 7
#define TRAXREG_STARTADDR 8
#define TRAXREG_ENDADDR 9
/* Internal use only (unpublished): */
#define TRAXREG_P4CHANGE 16
#define TRAXREG_P4REV 17
#define TRAXREG_P4DATE 18
#define TRAXREG_P4TIME 19
#define TRAXREG_PDSTATUS 20
#define TRAXREG_PDDATA 21
#define TRAXREG_STOP_PC 22
#define TRAXREG_STOP_ICNT 23
#define TRAXREG_MSG_STATUS 24
#define TRAXREG_FSM_STATUS 25
#define TRAXREG_IB_STATUS 26
#define TRAXREG_MAX 27
#define TRAXREG_ITCTRL 96
#endif
/* The registers above match the NAR addresses. So, their values are used for NAR access */
/* TRAX Register Fields */
/* TRAX ID register fields: */
#define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */
#define TRAX_ID_PRODOPT 0x0f000000 /* product options */
#define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */
#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options, internal (VER_2_0 or later)*/
#define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f)
#define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07)
#define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id))
#define TRAX_ID_STDCFG 0x00010000 /* standard config */
#define TRAX_ID_CFGID 0x0000ffff /* TRAX configuration ID */
#define TRAX_ID_MEMSHARED 0x00001000 /* Memshared option in TRAX */
#define TRAX_ID_FROM_VER(ver) ((((ver) & 0xf0) << 16) | (((ver) & 0x7) << 17))
/* Other TRAX ID register macros: */
/* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */
#define TRAX_VER_1_0 0x10 /* RA */
#define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */
#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0, RD-2011.1 */
#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and later */
#define TRAX_VER_3_0 0x30 /* RE-2012.0 */
#define TRAX_VER_3_1 0x31 /* RE-2012.1 */
#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224, 24880 */
/* TRAX version 1.0 requires a couple software workarounds: */
#define TRAX_ID_1_0_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_1_0)
/* TRAX version 2.0 requires software workaround for PR 22161: */
#define TRAX_ID_MEMSZ_ERRATUM(id) (TRAX_ID_VER(id) == TRAX_VER_2_0)
/* TRAX Control register fields: */
#define TRAX_CONTROL_TREN 0x00000001
#define TRAX_CONTROL_TRSTP 0x00000002
#define TRAX_CONTROL_PCMEN 0x00000004
#define TRAX_CONTROL_PTIEN 0x00000010
#define TRAX_CONTROL_CTIEN 0x00000020
#define TRAX_CONTROL_TMEN 0x00000080 /* 2.0+ */
#define TRAX_CONTROL_CNTU 0x00000200
#define TRAX_CONTROL_BIEN 0x00000400
#define TRAX_CONTROL_BOEN 0x00000800
#define TRAX_CONTROL_TSEN 0x00000800
#define TRAX_CONTROL_SMPER 0x00007000
#define TRAX_CONTROL_SMPER_SHIFT 12
#define TRAX_CONTROL_PTOWT 0x00010000
#define TRAX_CONTROL_CTOWT 0x00020000
#define TRAX_CONTROL_PTOWS 0x00100000
#define TRAX_CONTROL_CTOWS 0x00200000
#define TRAX_CONTROL_ATID 0x7F000000 /* 2.0+, amtrax */
#define TRAX_CONTROL_ATID_SHIFT 24
#define TRAX_CONTROL_ATEN 0x80000000 /* 2.0+, amtrax */
#define TRAX_CONTROL_PTOWS_ER 0x00020000 /* For 3.0 */
#define TRAX_CONTROL_CTOWT_ER 0x00100000 /* For 3.0 */
#define TRAX_CONTROL_ITCTO 0x00400000 /* For 3.0 */
#define TRAX_CONTROL_ITCTIA 0x00800000 /* For 3.0 */
#define TRAX_CONTROL_ITATV 0x01000000 /* For 3.0 */
/* TRAX Status register fields: */
#define TRAX_STATUS_TRACT 0x00000001
#define TRAX_STATUS_TRIG 0x00000002
#define TRAX_STATUS_PCMTG 0x00000004
#define TRAX_STATUS_BUSY 0x00000008 /* ER ??? */
#define TRAX_STATUS_PTITG 0x00000010
#define TRAX_STATUS_CTITG 0x00000020
#define TRAX_STATUS_MEMSZ 0x00001F00
#define TRAX_STATUS_MEMSZ_SHIFT 8
#define TRAX_STATUS_PTO 0x00010000
#define TRAX_STATUS_CTO 0x00020000
#define TRAX_STATUS_ITCTOA 0x00400000 /* For 3.0 */
#define TRAX_STATUS_ITCTI 0x00800000 /* For 3.0 */
#define TRAX_STATUS_ITATR 0x01000000 /* For 3.0 */
/* TRAX Address register fields: */
#define TRAX_ADDRESS_TWSAT 0x80000000
#define TRAX_ADDRESS_TWSAT_SHIFT 31
#define TRAX_ADDRESS_TOTALMASK 0x00FFFFFF
// !!! VUakiVU. added for new TRAX:
#define TRAX_ADDRESS_WRAPCNT 0x7FE00000 /* version ???... */
#define TRAX_ADDRESS_WRAP_SHIFT 21
/* TRAX PCMatch register fields: */
#define TRAX_PCMATCH_PCML 0x0000001F
#define TRAX_PCMATCH_PCML_SHIFT 0
#define TRAX_PCMATCH_PCMS 0x80000000
/* Compute trace ram buffer size (in bytes) from status register: */
#define TRAX_MEM_SIZE(status) (1L << (((status) & TRAX_STATUS_MEMSZ) >> TRAX_STATUS_MEMSZ_SHIFT))
#if 0
/* Describes a field within a register: */
typedef struct {
const char* name;
// unsigned width;
// unsigned shift;
char width;
char shift;
char visible; /* 0 = internal use only, 1 = shown */
char reserved;
} trax_regfield_t;
#endif
/* Describes a TRAX register: */
typedef struct {
const char* name;
unsigned id;
char width;
char visible;
char writable;
char reserved;
//const trax_regfield_t * fieldset;
} trax_regdef_t;
extern const trax_regdef_t trax_reglist[];
extern const signed int trax_readable_regs[];
extern const signed int trax_unamed_header_regs[];
#ifdef __cplusplus
extern "C" {
#endif
/* Prototypes: */
extern int trax_find_reg(char * regname, char **errmsg);
extern const char * trax_regname(int regno);
#ifdef __cplusplus
}
#endif
#endif /* _TRAX_REGISTERS_H_ */

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/* xdm-regs.h - Common register and related definitions for the XDM
(Xtensa Debug Module) */
/* Copyright (c) 2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XDM_REGS_H_
#define _XDM_REGS_H_
/* NOTE: This header file is included by C, assembler, and other sources.
So any C-specific or asm-specific content must be appropriately #ifdef'd. */
/*
* XDM registers can be accessed using APB, ERI, or JTAG (via NAR).
* Address offsets for APB and ERI are the same, and for JTAG
* is different (due to the limited 7-bit NAR addressing).
*
* Here, we first provide the constants as APB / ERI address offsets.
* This is necessary for assembler code (which accesses XDM via ERI),
* because complex conversion macros between the two address maps
* don't work in the assembler.
* Conversion macros are used to convert these to/from JTAG (NAR),
* addresses, for software using JTAG.
*/
/* FIXME: maybe provide only MISC+CS registers here, and leave specific
subsystem registers in separate headers? eg. for TRAX, PERF, OCD */
/* XDM_.... ERI addr [NAR addr] Description...... */
/* TRAX */
#define XDM_TRAX_ID 0x100000 /*[0x00] ID */
#define XDM_TRAX_CONTROL 0x100004 /*[0x01] Control */
#define XDM_TRAX_STATUS 0x100008 /*[0x02] Status */
#define XDM_TRAX_DATA 0x10000C /*[0x03] Data */
#define XDM_TRAX_ADDRESS 0x100010 /*[0x04] Address */
#define XDM_TRAX_TRIGGER 0x100014 /*[0x05] Stop PC */
#define XDM_TRAX_MATCH 0x100018 /*[0x06] Stop PC Range */
#define XDM_TRAX_DELAY 0x10001C /*[0x07] Post Stop Trigger Capture Size */
#define XDM_TRAX_STARTADDR 0x100020 /*[0x08] Trace Memory Start */
#define XDM_TRAX_ENDADDR 0x100024 /*[0x09] Trace Memory End */
#define XDM_TRAX_DEBUGPC 0x10003C /*[0x0F] Debug PC */
#define XDM_TRAX_P4CHANGE 0x100040 /*[0x10] X */
#define XDM_TRAX_TIME0 0x100040 /*[0x10] First Time Register */
#define XDM_TRAX_P4REV 0x100044 /*[0x11] X */
#define XDM_TRAX_TIME1 0x100044 /*[0x11] Second Time Register */
#define XDM_TRAX_P4DATE 0x100048 /*[0x12] X */
#define XDM_TRAX_INTTIME_MAX 0x100048 /*[0x12] maximal Value of Timestamp IntTime */
#define XDM_TRAX_P4TIME 0x10004C /*[0x13] X */
#define XDM_TRAX_PDSTATUS 0x100050 /*[0x14] Sample of PDebugStatus */
#define XDM_TRAX_PDDATA 0x100054 /*[0x15] Sample of PDebugData */
#define XDM_TRAX_STOP_PC 0x100058 /*[0x16] X */
#define XDM_TRAX_STOP_ICNT 0x10005C /*[0x16] X */
#define XDM_TRAX_MSG_STATUS 0x100060 /*[0x17] X */
#define XDM_TRAX_FSM_STATUS 0x100064 /*[0x18] X */
#define XDM_TRAX_IB_STATUS 0x100068 /*[0x19] X */
#define XDM_TRAX_STOPCNT 0x10006C /*[0x1A] X */
/* Performance Monitoring Counters */
#define XDM_PERF_PMG 0x101000 /*[0x20] perf. mon. global control register */
#define XDM_PERF_INTPC 0x101010 /*[0x24] perf. mon. interrupt PC */
#define XDM_PERF_PM0 0x101080 /*[0x28] perf. mon. counter 0 value */
#define XDM_PERF_PM1 0x101084 /*[0x29] perf. mon. counter 1 value */
#define XDM_PERF_PM2 0x101088 /*[0x2A] perf. mon. counter 2 value */
#define XDM_PERF_PM3 0x10108C /*[0x2B] perf. mon. counter 3 value */
#define XDM_PERF_PM4 0x101090 /*[0x2C] perf. mon. counter 4 value */
#define XDM_PERF_PM5 0x101094 /*[0x2D] perf. mon. counter 5 value */
#define XDM_PERF_PM6 0x101098 /*[0x2E] perf. mon. counter 6 value */
#define XDM_PERF_PM7 0x10109C /*[0x2F] perf. mon. counter 7 value */
#define XDM_PERF_PM(n) (0x101080+((n)<<2)) /* perfmon cnt n=0..7 value */
#define XDM_PERF_PMCTRL0 0x101100 /*[0x30] perf. mon. counter 0 control */
#define XDM_PERF_PMCTRL1 0x101104 /*[0x31] perf. mon. counter 1 control */
#define XDM_PERF_PMCTRL2 0x101108 /*[0x32] perf. mon. counter 2 control */
#define XDM_PERF_PMCTRL3 0x10110C /*[0x33] perf. mon. counter 3 control */
#define XDM_PERF_PMCTRL4 0x101110 /*[0x34] perf. mon. counter 4 control */
#define XDM_PERF_PMCTRL5 0x101114 /*[0x35] perf. mon. counter 5 control */
#define XDM_PERF_PMCTRL6 0x101118 /*[0x36] perf. mon. counter 6 control */
#define XDM_PERF_PMCTRL7 0x10111C /*[0x37] perf. mon. counter 7 control */
#define XDM_PERF_PMCTRL(n) (0x101100+((n)<<2)) /* perfmon cnt n=0..7 control */
#define XDM_PERF_PMSTAT0 0x101180 /*[0x38] perf. mon. counter 0 status */
#define XDM_PERF_PMSTAT1 0x101184 /*[0x39] perf. mon. counter 1 status */
#define XDM_PERF_PMSTAT2 0x101188 /*[0x3A] perf. mon. counter 2 status */
#define XDM_PERF_PMSTAT3 0x10118C /*[0x3B] perf. mon. counter 3 status */
#define XDM_PERF_PMSTAT4 0x101190 /*[0x3C] perf. mon. counter 4 status */
#define XDM_PERF_PMSTAT5 0x101194 /*[0x3D] perf. mon. counter 5 status */
#define XDM_PERF_PMSTAT6 0x101198 /*[0x3E] perf. mon. counter 6 status */
#define XDM_PERF_PMSTAT7 0x10119C /*[0x3F] perf. mon. counter 7 status */
#define XDM_PERF_PMSTAT(n) (0x101180+((n)<<2)) /* perfmon cnt n=0..7 status */
/* On-Chip-Debug (OCD) */
#define XDM_OCD_ID 0x102000 /*[0x40] ID register */
#define XDM_OCD_DCR_CLR 0x102008 /*[0x42] Debug Control reg clear */
#define XDM_OCD_DCR_SET 0x10200C /*[0x43] Debug Control reg set */
#define XDM_OCD_DSR 0x102010 /*[0x44] Debug Status reg */
#define XDM_OCD_DDR 0x102014 /*[0x45] Debug Data reg */
#define XDM_OCD_DDREXEC 0x102018 /*[0x46] Debug Data reg + execute-DIR */
#define XDM_OCD_DIR0EXEC 0x10201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
#define XDM_OCD_DIR0 0x102020 /*[0x48] Debug Instruction reg, word 1 */
#define XDM_OCD_DIR1 0x102024 /*[0x49] Debug Instruction reg, word 2 */
#define XDM_OCD_DIR2 0x102028 /*[0x4A] Debug Instruction reg, word 3 */
#define XDM_OCD_DIR3 0x10202C /*[0x49] Debug Instruction reg, word 4 */
#define XDM_OCD_DIR4 0x102030 /*[0x4C] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR5 0x102034 /*[0x4D] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR6 0x102038 /*[0x4E] Debug Instruction reg, word 6 */
#define XDM_OCD_DIR7 0x10203C /*[0x4F] Debug Instruction reg, word 7 */
/* Miscellaneous Registers */
#define XDM_MISC_PWRCTL 0x103020 /*[0x58] Power and Reset Control */
#define XDM_MISC_PWRSTAT 0x103024 /*[0x59] Power and Reset Status */
#define XDM_MISC_ERISTAT 0x103028 /*[0x5A] ERI Transaction Status */
#define XDM_MISC_DATETIME 0x103034
#define XDM_MISC_CONFIGID1_V0 0x103034 /*[0x5D] [INTERNAL] ConfigID1 in XDM v0/1 */
#define XDM_MISC_CONFIGID1_V2 0x10007c /*[0x1F] [INTERNAL] ConfigID1 since XDM v2 */
#define XDM_MISC_CONFIGID0_V2 0x100078 /*[0x1E] [INTERNAL] ConfigID0 since XDM v2 */
#define XDM_MISC_UBID 0x103038 /*[0x5E] [INTERNAL] Build Unique ID */
#define XDM_MISC_CID 0x10303C /*[0x5F] [INTERNAL] Customer ID */
/* CoreSight compatibility */
#define XDM_CS_ITCTRL 0x103F00 /*[0x60] InTegration Mode control reg */
#define XDM_CS_CLAIMSET 0x103FA0 /*[0x68] Claim Tag Set reg */
#define XDM_CS_CLAIMCLR 0x103FA4 /*[0x69] Claim Tag Clear reg */
#define XDM_CS_LOCK_ACCESS 0x103FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
#define XDM_CS_LOCK_STATUS 0x103FB4 /*[0x6D] Lock Status */
#define XDM_CS_AUTH_STATUS 0x103FB8 /*[0x6E] Authentication Status */
#define XDM_CS_DEV_ID 0x103FC8 /*[0x72] Device ID */
#define XDM_CS_DEV_TYPE 0x103FCC /*[0x73] Device Type */
#define XDM_CS_PER_ID4 0x103FD0 /*[0x74] Peripheral ID reg byte 4 */
#define XDM_CS_PER_ID5 0x103FD4 /*[0x75] Peripheral ID reg byte 5 */
#define XDM_CS_PER_ID6 0x103FD8 /*[0x76] Peripheral ID reg byte 6 */
#define XDM_CS_PER_ID7 0x103FDC /*[0x77] Peripheral ID reg byte 7 */
#define XDM_CS_PER_ID0 0x103FE0 /*[0x78] Peripheral ID reg byte 0 */
#define XDM_CS_PER_ID1 0x103FE4 /*[0x79] Peripheral ID reg byte 1 */
#define XDM_CS_PER_ID2 0x103FE8 /*[0x7A] Peripheral ID reg byte 2 */
#define XDM_CS_PER_ID3 0x103FEC /*[0x7B] Peripheral ID reg byte 3 */
#define XDM_CS_COMP_ID0 0x103FF0 /*[0x7C] Component ID reg byte 0 */
#define XDM_CS_COMP_ID1 0x103FF4 /*[0x7D] Component ID reg byte 1 */
#define XDM_CS_COMP_ID2 0x103FF8 /*[0x7E] Component ID reg byte 2 */
#define XDM_CS_COMP_ID3 0x103FFC /*[0x7F] Component ID reg byte 3 */
#define CS_PER_ID0 0x00000003
#define CS_PER_ID1 0x00000021
#define CS_PER_ID2 0x0000000f
#define CS_PER_ID3 0x00000000
#define CS_PER_ID4 0x00000024
#define CS_COMP_ID0 0x0000000d
#define CS_COMP_ID1 0x00000090
#define CS_COMP_ID2 0x00000005
#define CS_COMP_ID3 0x000000b1
#define CS_DEV_TYPE 0x00000015
#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !)
#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF)
#define CS_DEV_ID XTENSA_IDCODE //FIXME - for XDM v0 only, for v2 is the new ID, that includes vars like PRID but also can be custom
#define CS_DEV_ID_v0_MASK 0x00000FFF // can compare only the lower 12 bits
#define CS_DEV_ID_v2_MASK 0xF0000000 // can compare only the upper 4 bits
#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F))
#define NXS_TRAX_REG(val) val <= 0x3F
#define ERI_TRAX_REG(val) ((val & 0xFFFF) < 0x1000)
#define ERI_OCD_REG(val) ((val & 0xFFFF) >= 0x2000) && ((val & 0xFFFF) < 0x4000))
/* Convert above 14-bit ERI/APB address/offset to 7-bit NAR address: */
#define _XDM_ERI_TO_NAR(a) ( ((a)&0x3F80)==0x0000 ? (((a)>>2) & 0x1F) \
: ((a)&0x3E00)==0x1000 ? (0x20 | (((a)>>2) & 7) | (((a)>>4) & 0x18)) \
: ((a)&0x3FC0)==0x2000 ? (0x40 | (((a)>>2) & 0xF)) \
: ((a)&0x3FE0)==0x3020 ? (0x50 | (((a)>>2) & 0xF)) \
: ((a)&0x3FFC)==0x3F00 ? 0x60 \
: ((a)&0x3F80)==0x3F80 ? (0x60 | (((a)>>2) & 0x1F)) \
: -1 )
#define XDM_ERI_TO_NAR(a) _XDM_ERI_TO_NAR(a & 0xFFFF)
/* Convert 7-bit NAR address back to ERI/APB address/offset: */
#define _XDM_NAR_TO_APB(a) ((a) <= 0x1f ? ((a) << 2) \
:(a) >= 0x20 && (a) <= 0x3F ? (0x1000 | (((a)& 7) << 2) | (((a)&0x18)<<4)) \
:(a) >= 0x40 && (a) <= 0x4F ? (0x2000 | (((a)&0xF) << 2)) \
:(a) >= 0x58 && (a) <= 0x5F ? (0x3000 | (((a)&0xF) << 2)) \
:(a) == 0x60 ? (0x3F00) \
:(a) >= 0x68 && (a) <= 0x7F ? (0x3F80 | (((a)&0x1F) << 2)) \
: -1)
#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF))
#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x100000
/* Convert APB to ERI address */
#define XDM_APB_TO_ERI(a) ((a) | (0x100000))
#define XDM_ERI_TO_APB(a) ((a) & (0x0FFFFF))
/*********** Bit definitions within some of the above registers ***********/
#define OCD_ID_LSDDRP 0x01000000
#define OCD_ID_LSDDRP_SHIFT 24
#define OCD_ID_ENDIANESS 0x00000001
#define OCD_ID_ENDIANESS_SHIFT 0
#define OCD_ID_PSO 0x0000000C
#define OCD_ID_PSO_SHIFT 2
#define OCD_ID_TRACEPORT 0x00000080
#define OCD_ID_TRACEPORT_SHIFT 7
#define OCD_ID_LSDDRP_XEA3 0x00000400
/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
/* ERI/APB: */
#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
#define PWRSTAT_CORE_DOMAIN_ON_SHIFT 0
#define PWRSTAT_WAKEUP_RESET 0x00000002 /* [ERI only] 0=cold start, 1=PSO wakeup */
#define PWRSTAT_WAKEUP_RESET_SHIFT 1
#define PWRSTAT_CACHES_LOST_POWER 0x00000004 /* [ERI only] set if caches (/localmems?) lost power */
/* FIXME: does this include local memories? */
#define PWRSTAT_CACHES_LOST_POWER_SHIFT 2
#define PWRSTAT_CORE_STILL_NEEDED 0x00000010 /* set if others keeping core awake */
#define PWRSTAT_CORE_STILL_NEEDED_SHIFT 4
#define PWRSTAT_MEM_DOMAIN_ON 0x00000100 /* set if memory domain is powered on */
#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8
#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */
#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12
#define PWRSTAT_ALL_ON (PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON)
#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */
#define PWRSTAT_CORE_WAS_RESET_SHIFT 16
#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */
#define PWRSTAT_DEBUG_WAS_RESET_SHIFT 28
/* JTAG: */
#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */
#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */
#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */
#define J_PWRSTAT_ALL_ON (J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON)
#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */
#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */
#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */
/* Power Control register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
/* ERI/APB: */
#define PWRCTL_CORE_SHUTOFF 0x00000001 /* [ERI only] core wants to shut off on WAITI */
#define PWRCTL_CORE_SHUTOFF_SHIFT 0
#define PWRCTL_CORE_WAKEUP 0x00000001 /* [APB only] set to force core to stay powered on */
#define PWRCTL_CORE_WAKEUP_SHIFT 0
#define PWRCTL_MEM_WAKEUP 0x00000100 /* set to force memory domain to stay powered on */
#define PWRCTL_MEM_WAKEUP_SHIFT 8
#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */
#define PWRCTL_DEBUG_WAKEUP_SHIFT 12
#define PWRCTL_ALL_ON (PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP)
#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */
#define PWRCTL_CORE_RESET_SHIFT 16
#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */
#define PWRCTL_DEBUG_RESET_SHIFT 28
/* JTAG: */
#define J_PWRCTL_CORE_WAKEUP 0x01 /* set to force core to stay powered on */
#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */
#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */
#define J_DEBUG_USE 0x80 /* */
#define J_PWRCTL_ALL_ON (J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP)
#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */
#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */
#define J_PWRCTL_WRITE_MASK 0xFF
#define J_PWRSTAT_WRITE_MASK 0xFF
#define PWRCTL_WRITE_MASK ~0
#define PWRSTAT_WRITE_MASK ~0
/************ The following are only relevant for JTAG, so perhaps belong in OCD only **************/
/* XDM 5-bit JTAG Instruction Register (IR) values: */
#define XDM_IR_PWRCTL 0x08 /* select 8-bit Power/Reset Control (PRC) */
#define XDM_IR_PWRSTAT 0x09 /* select 8-bit Power/Reset Status (PRS) */
#define XDM_IR_NAR_SEL 0x1c /* select altern. 8-bit NAR / 32-bit NDR (Nexus-style) */
#define XDM_IR_NDR_SEL 0x1d /* select altern. 32-bit NDR / 8-bit NAR
(FIXME - functionality not yet in HW) */
#define XDM_IR_IDCODE 0x1e /* select 32-bit JTAG IDCODE */
#define XDM_IR_BYPASS 0x1f /* select 1-bit bypass */
#define XDM_IR_WIDTH 5 /* width of IR for Xtensa TAP */
/* NAR register bits: */
#define XDM_NAR_WRITE 0x01
#define XDM_NAR_ADDR_MASK 0xFE
#define XDM_NAR_ADDR_SHIFT 1
#define XDM_NAR_BUSY 0x02
#define XDM_NAR_ERROR 0x01
#define NEXUS_DIR_READ 0x00
#define NEXUS_DIR_WRITE 0x01
/************ Define DCR register bits **************/
#define DCR_ENABLEOCD 0x0000001
#define DCR_ENABLEOCD_SHIFT 0
#define DCR_DEBUG_INT 0x0000002
#define DCR_DEBUG_INT_SHIFT 1
#define DCR_DEBUG_OVERRIDE 0x0000004 //ER or later
#define DCR_DEBUG_OVERRIDE_SHIFT 2
#define DCR_DEBUG_SS_REQ 0x0000008
#define DCR_DEBUG_SS_REQ_SHIFT 3
#define DCR_DEBUG_OVERRIDE_CW 0x0000010 //RD and earlier
#define DCR_DEBUG_OVERRIDE_CW_SHIFT 4
#define DCR_MASK_NMI 0x0000020
#define DCR_MASK_NMI_SHIFT 5
#define DCR_STEP_ENABLE 0x0000040
#define DCR_STEP_ENABLE_SHIFT 6
#define DCR_BREAK_IN_EN 0x0010000
#define DCR_BREAK_IN_EN_SHIFT 16
#define DCR_BREAK_OUT_EN 0x0020000
#define DCR_BREAK_OUT_EN_SHIFT 17
#define DCR_DEBUG_INT_EN 0x0040000
#define DCR_DEBUG_INT_EN_SHIFT 18
#define DCR_DBG_SW_ACTIVE 0x0100000
#define DCR_DBG_SW_ACTIVE_SHIFT 20
#define DCR_STALL_IN_EN 0x0200000
#define DCR_STALL_IN_EN_SHIFT 21
#define DCR_DEBUG_OUT_EN 0x0400000
#define DCR_DEBUG_OUT_EN_SHIFT 22
#define DCR_BREAK_OUT_ITO 0x1000000
#define DCR_STALL_OUT_ITO 0x2000000
#define DCR_STALL_OUT_ITO_SHIFT 25
/************ Define DSR register bits **************/
#define DOSR_STOP_CAUSE_SHIFT 5
#define DOSR_STOP_CAUSE_MASK 0xF
#define DOSR_EXECDONE_SHIFT 0
#define DOSR_EXECDONE_ER 0x01
#define DOSR_EXECDONE_SHIFT 0
#define DOSR_EXCEPTION_ER 0x02
#define DOSR_EXCEPTION_SHIFT 1
#define DOSR_BUSY 0x04
#define DOSR_BUSY_SHIFT 2
#define DOSR_OVERRUN 0x08
#define DOSR_OVERRUN_SHIFT 3
#define DOSR_INOCDMODE_ER 0x10
#define DOSR_INOCDMODE_SHIFT 4
#define DOSR_CORE_WROTE_DDR_ER 0x400
#define DOSR_CORE_WROTE_DDR_SHIFT 10
#define DOSR_CORE_READ_DDR_ER 0x800
#define DOSR_CORE_READ_DDR_SHIFT 11
#define DOSR_HOST_WROTE_DDR_ER 0x4000
#define DOSR_HOST_WROTE_DDR_SHIFT 14
#define DOSR_HOST_READ_DDR_ER 0x8000
#define DOSR_HOST_READ_DDR_SHIFT 15
#define DOSR_DEBUG_PEND_BIN 0x10000
#define DOSR_DEBUG_PEND_HOST 0x20000
#define DOSR_DEBUG_PEND_TRAX 0x40000
#define DOSR_DEBUG_BIN 0x100000
#define DOSR_DEBUG_HOST 0x200000
#define DOSR_DEBUG_TRAX 0x400000
#define DOSR_DEBUG_PEND_BIN_SHIFT 16
#define DOSR_DEBUG_PEND_HOST_SHIFT 17
#define DOSR_DEBUG_PEND_TRAX_SHIFT 18
#define DOSR_DEBUG_BREAKIN 0x0100000
#define DOSR_DEBUG_BREAKIN_SHIFT 20
#define DOSR_DEBUG_HOST_SHIFT 21
#define DOSR_DEBUG_TRAX_SHIFT 22
#define DOSR_DEBUG_STALL 0x1000000
#define DOSR_DEBUG_STALL_SHIFT 24
#define DOSR_CORE_ON 0x40000000
#define DOSR_CORE_ON_SHIFT 30
#define DOSR_DEBUG_ON 0x80000000
#define DOSR_DEBUG_ON_SHIFT 31
/********** Performance monitor registers bits **********/
#define PERF_PMG_ENABLE 0x00000001 /* global enable bit */
#define PERF_PMG_ENABLE_SHIFT 0
#define PERF_PMCTRL_INT_ENABLE 0x00000001 /* assert interrupt on overflow */
#define PERF_PMCTRL_INT_ENABLE_SHIFT 0
#define PERF_PMCTRL_KRNLCNT 0x00000008 /* ignore TRACELEVEL */
#define PERF_PMCTRL_KRNLCNT_SHIFT 3
#define PERF_PMCTRL_TRACELEVEL 0x000000F0 /* count when CINTLEVEL <= TRACELEVEL */
#define PERF_PMCTRL_TRACELEVEL_SHIFT 4
#define PERF_PMCTRL_SELECT 0x00001F00 /* events group selector */
#define PERF_PMCTRL_SELECT_SHIFT 8
#define PERF_PMCTRL_MASK 0xFFFF0000 /* events mask */
#define PERF_PMCTRL_MASK_SHIFT 16
#define PERF_PMSTAT_OVERFLOW 0x00000001 /* counter overflowed */
#define PERF_PMSTAT_OVERFLOW_SHIFT 0
#define PERF_PMSTAT_INT 0x00000010 /* interrupt asserted */
#define PERF_PMSTAT_INT_SHIFT 4
#if defined (USE_XDM_REGNAME) || defined (USE_DAP_REGNAME)
/* Describes XDM register: */
typedef struct {
int reg;
char* name;
} regdef_t;
/*
* Returns the name of the specified XDM register number,
* or simply "???" if the register number is not recognized.
* FIXME - requires -1 as the last entry - change to compare the name to ???
* or even better, make the code above to work.
*/
static char*
regname(regdef_t* list, int reg)
{
int i = 0;
while (list[i].reg != -1) {
if (list[i].reg == reg)
break;
i++;
}
return list[i].name;
}
#if defined (USE_XDM_REGNAME)
static regdef_t xdm_reglist[] =
{
{XDM_OCD_DSR ,"DOSR" },
{XDM_OCD_DDR ,"DDR" },
{XDM_OCD_DDREXEC ,"DDREXEC" },
{XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
{XDM_OCD_DCR_CLR ,"DCR_CLR" },
{XDM_OCD_DCR_SET ,"DCR_SET" },
{XDM_TRAX_CONTROL ,"CONTROL" },
{XDM_TRAX_STATUS ,"STATUS" },
{XDM_TRAX_DATA ,"DATA" },
{XDM_TRAX_ADDRESS ,"ADDRESS" },
{XDM_TRAX_ID ,"TRAX_ID" },
{XDM_TRAX_TRIGGER ,"TRIGGER PC" },
{XDM_TRAX_MATCH ,"PC MATCH" },
{XDM_TRAX_DELAY ,"DELAY CNT." },
{XDM_TRAX_STARTADDR ,"START ADDRESS"},
{XDM_TRAX_ENDADDR ,"END ADDRESS" },
{XDM_TRAX_DEBUGPC ,"DEBUG PC" },
{XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
{XDM_TRAX_P4REV ,"P4 REV." },
{XDM_TRAX_P4DATE ,"P4 DATE" },
{XDM_TRAX_P4TIME ,"P4 TIME" },
{XDM_TRAX_PDSTATUS ,"PD STATUS" },
{XDM_TRAX_PDDATA ,"PD DATA" },
{XDM_TRAX_STOP_PC ,"STOP PC" },
{XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
{XDM_TRAX_MSG_STATUS,"MSG STAT." },
{XDM_TRAX_FSM_STATUS,"FSM STAT." },
{XDM_TRAX_IB_STATUS ,"IB STAT." },
{XDM_OCD_ID ,"OCD_ID" },
{XDM_OCD_DIR0 ,"DIR0" },
{XDM_OCD_DIR1 ,"DIR1" },
{XDM_OCD_DIR2 ,"DIR2" },
{XDM_OCD_DIR3 ,"DIR3" },
{XDM_OCD_DIR4 ,"DIR4" },
{XDM_OCD_DIR5 ,"DIR5" },
{XDM_OCD_DIR6 ,"DIR6" },
{XDM_OCD_DIR7 ,"DIR7" },
{XDM_PERF_PMG ,"PMG" },
{XDM_PERF_INTPC ,"INTPC" },
{XDM_PERF_PM0 ,"PM0 " },
{XDM_PERF_PM1 ,"PM1 " },
{XDM_PERF_PM2 ,"PM2 " },
{XDM_PERF_PM3 ,"PM3 " },
{XDM_PERF_PM4 ,"PM4 " },
{XDM_PERF_PM5 ,"PM5 " },
{XDM_PERF_PM6 ,"PM6 " },
{XDM_PERF_PM7 ,"PM7 " },
{XDM_PERF_PMCTRL0 ,"PMCTRL0"},
{XDM_PERF_PMCTRL1 ,"PMCTRL1"},
{XDM_PERF_PMCTRL2 ,"PMCTRL2"},
{XDM_PERF_PMCTRL3 ,"PMCTRL3"},
{XDM_PERF_PMCTRL4 ,"PMCTRL4"},
{XDM_PERF_PMCTRL5 ,"PMCTRL5"},
{XDM_PERF_PMCTRL6 ,"PMCTRL6"},
{XDM_PERF_PMCTRL7 ,"PMCTRL7"},
{XDM_PERF_PMSTAT0 ,"PMSTAT0"},
{XDM_PERF_PMSTAT1 ,"PMSTAT1"},
{XDM_PERF_PMSTAT2 ,"PMSTAT2"},
{XDM_PERF_PMSTAT3 ,"PMSTAT3"},
{XDM_PERF_PMSTAT4 ,"PMSTAT4"},
{XDM_PERF_PMSTAT5 ,"PMSTAT5"},
{XDM_PERF_PMSTAT6 ,"PMSTAT6"},
{XDM_PERF_PMSTAT7 ,"PMSTAT7"},
{XDM_MISC_PWRCTL ,"PWRCTL" },
{XDM_MISC_PWRSTAT ,"PWRSTAT" },
{XDM_MISC_ERISTAT ,"ERISTAT" },
{XDM_MISC_DATETIME ,"DATETIME"},
{XDM_MISC_UBID ,"UBID" },
{XDM_MISC_CID ,"CID" },
{XDM_CS_ITCTRL ,"ITCTRL" },
{XDM_CS_CLAIMSET ,"CLAIMSET" },
{XDM_CS_CLAIMCLR ,"CLAIMCLR" },
{XDM_CS_LOCK_ACCESS ,"LOCK_ACCESS"},
{XDM_CS_LOCK_STATUS ,"LOCK_STATUS"},
{XDM_CS_AUTH_STATUS ,"AUTH_STATUS"},
{XDM_CS_DEV_ID ,"DEV_ID" },
{XDM_CS_DEV_TYPE ,"DEV_TYPE" },
{XDM_CS_PER_ID4 ,"PER_ID4" },
{XDM_CS_PER_ID5 ,"PER_ID5" },
{XDM_CS_PER_ID6 ,"PER_ID6" },
{XDM_CS_PER_ID7 ,"PER_ID7" },
{XDM_CS_PER_ID0 ,"PER_ID0" },
{XDM_CS_PER_ID1 ,"PER_ID1" },
{XDM_CS_PER_ID2 ,"PER_ID2" },
{XDM_CS_PER_ID3 ,"PER_ID3" },
{XDM_CS_COMP_ID0 ,"COMP_ID0" },
{XDM_CS_COMP_ID1 ,"COMP_ID1" },
{XDM_CS_COMP_ID2 ,"COMP_ID2" },
{XDM_CS_COMP_ID3 ,"COMP_ID3" },
{-1 ,"???" },
};
#endif
#endif
#endif /* _XDM_REGS_H_ */

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/*
* Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef __XT_PERF_CONSTS_H__
#define __XT_PERF_CONSTS_H__
#include <xtensa/config/core.h>
/*
* Performance monitor counter selectors
*/
#define XTPERF_CNT_COMMITTED_INSN 0x8002 /* Instructions committed */
#define XTPERF_CNT_BRANCH_PENALTY 0x8003 /* Branch penalty cycles */
#define XTPERF_CNT_PIPELINE_INTERLOCKS 0x8004 /* Pipeline interlocks cycles */
#define XTPERF_CNT_ICACHE_MISSES 0x8005 /* ICache misses penalty in cycles */
#define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */
#define XTPERF_CNT_CYCLES 0 /* Count cycles */
#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */
#define XTPERF_CNT_INSN 2 /* Successfully completed instructions */
#define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */
#define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */
#define XTPERF_CNT_EXR 5 /* Exceptions and pipeline replays */
#define XTPERF_CNT_BUBBLES 6 /* Hold and other bubble cycles */
#define XTPERF_CNT_I_TLB 7 /* Instruction TLB Accesses (per instruction retiring) */
#define XTPERF_CNT_I_MEM 8 /* Instruction memory accesses (per instruction retiring) */
#define XTPERF_CNT_D_TLB 9 /* Data TLB accesses */
#define XTPERF_CNT_D_LOAD_U1 10 /* Data memory load instruction (load-store unit 1) */
#define XTPERF_CNT_D_STORE_U1 11 /* Data memory store instruction (load-store unit 1) */
#define XTPERF_CNT_D_ACCESS_U1 12 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 1) */
#define XTPERF_CNT_D_LOAD_U2 13 /* Data memory load instruction (load-store unit 2) */
#define XTPERF_CNT_D_STORE_U2 14 /* Data memory store instruction (load-store unit 2) */
#define XTPERF_CNT_D_ACCESS_U2 15 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 2) */
#define XTPERF_CNT_D_LOAD_U3 16 /* Data memory load instruction (load-store unit 3) */
#define XTPERF_CNT_D_STORE_U3 17 /* Data memory store instruction (load-store unit 3) */
#define XTPERF_CNT_D_ACCESS_U3 18 /* Data memory accesses (load, store, S32C1I, etc; load-store unit 3) */
#define XTPERF_CNT_MULTIPLE_LS 22 /* Multiple Load/Store */
#define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */
#define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */
#define XTPERF_CNT_PREFETCH 26 /* Prefetch events */
#if XCHAL_HW_VERSION >= 270004
#define XTPERF_CNT_IDMA 27 /* iDMA counters */
#define XTPERF_CNT_INSN_LENGTH 28 /* Instruction length counters */
#endif /* HW version >= 270004 */
/*
* Masks for each of the selector listed above
*/
/* XTPERF_CNT_COMMITTED_INSN selector mask */
#define XTPERF_MASK_COMMITTED_INSN 0x0001
/* XTPERF_CNT_BRANCH_PENALTY selector mask */
#define XTPERF_MASK_BRANCH_PENALTY 0x0001
/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */
#define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001
/* XTPERF_CNT_ICACHE_MISSES selector mask */
#define XTPERF_MASK_ICACHE_MISSES 0x0001
/* XTPERF_CNT_DCACHE_MISSES selector mask */
#define XTPERF_MASK_DCACHE_MISSES 0x0001
/* XTPERF_CNT_CYCLES selector mask */
#define XTPERF_MASK_CYCLES 0x0001
/* XTPERF_CNT_OVERFLOW selector mask */
#define XTPERF_MASK_OVERFLOW 0x0001
/*
* XTPERF_CNT_INSN selector mask
*/
#define XTPERF_MASK_INSN_ALL 0x8DFF
#define XTPERF_MASK_INSN_JX 0x0001 /* JX */
#define XTPERF_MASK_INSN_CALLX 0x0002 /* CALLXn */
#define XTPERF_MASK_INSN_RET 0x0004 /* call return i.e. RET, RETW */
#define XTPERF_MASK_INSN_RF 0x0008 /* supervisor return i.e. RFDE, RFE, RFI, RFWO, RFWU */
#define XTPERF_MASK_INSN_BRANCH_TAKEN 0x0010 /* Conditional branch taken, or loopgtz/loopnez skips loop */
#define XTPERF_MASK_INSN_J 0x0020 /* J */
#define XTPERF_MASK_INSN_CALL 0x0040 /* CALLn */
#define XTPERF_MASK_INSN_BRANCH_NOT_TAKEN 0x0080 /* Conditional branch fall through (aka. not-taken branch) */
#define XTPERF_MASK_INSN_LOOP_TAKEN 0x0100 /* Loop instr falls into loop (aka. taken loop) */
#define XTPERF_MASK_INSN_LOOP_BEG 0x0400 /* Loopback taken to LBEG */
#define XTPERF_MASK_INSN_LOOP_END 0x0800 /* Loopback falls through to LEND */
#define XTPERF_MASK_INSN_NON_BRANCH 0x8000 /* Non-branch instruction (aka. non-CTI) */
/*
* XTPERF_CNT_D_STALL selector mask
*/
#define XTPERF_MASK_D_STALL_ALL 0x01FE
#define XTPERF_MASK_D_STALL_STORE_BUF_FULL 0x0002 /* Store buffer full stall */
#define XTPERF_MASK_D_STALL_STORE_BUF_CONFLICT 0x0004 /* Store buffer conflict stall */
#define XTPERF_MASK_D_STALL_CACHE_MISS 0x0008 /* DCache-miss stall */
#define XTPERF_MASK_D_STALL_BUSY 0x0010 /* Data RAM/ROM/XLMI busy stall */
#define XTPERF_MASK_D_STALL_IN_PIF 0x0020 /* Data inbound-PIF request stall (incl s32c1i) */
#define XTPERF_MASK_D_STALL_MHT_LOOKUP 0x0040 /* MHT lookup stall */
#define XTPERF_MASK_D_STALL_UNCACHED_LOAD 0x0080 /* Uncached load stall (included in MHT lookup stall) */
#define XTPERF_MASK_D_STALL_BANK_CONFLICT 0x0100 /* Bank-conflict stall */
/*
* XTPERF_CNT_I_STALL selector mask
*/
#define XTPERF_MASK_I_STALL_ALL 0x01FF
#define XTPERF_MASK_I_STALL_CACHE_MISS 0x0001 /* ICache-miss stall */
#define XTPERF_MASK_I_STALL_BUSY 0x0002 /* Instruction RAM/ROM busy stall */
#define XTPERF_MASK_I_STALL_IN_PIF 0x0004 /* Instruction RAM inbound-PIF request stall */
#define XTPERF_MASK_I_STALL_TIE_PORT 0x0008 /* TIE port stall */
#define XTPERF_MASK_I_STALL_EXTERNAL_SIGNAL 0x0010 /* External RunStall signal status */
#define XTPERF_MASK_I_STALL_UNCACHED_FETCH 0x0020 /* Uncached fetch stall */
#define XTPERF_MASK_I_STALL_FAST_L32R 0x0040 /* FastL32R stall */
#define XTPERF_MASK_I_STALL_ITERATIVE_MUL 0x0080 /* Iterative multiply stall */
#define XTPERF_MASK_I_STALL_ITERATIVE_DIV 0x0100 /* Iterative divide stall */
/*
* XTPERF_CNT_EXR selector mask
*/
#define XTPERF_MASK_EXR_ALL 0x01FF
#define XTPERF_MASK_EXR_REPLAYS 0x0001 /* Other Pipeline Replay (i.e. excludes $ miss etc.) */
#define XTPERF_MASK_EXR_LEVEL1_INT 0x0002 /* Level-1 interrupt */
#define XTPERF_MASK_EXR_LEVELH_INT 0x0004 /* Greater-than-level-1 interrupt */
#define XTPERF_MASK_EXR_DEBUG 0x0008 /* Debug exception */
#define XTPERF_MASK_EXR_NMI 0x0010 /* NMI */
#define XTPERF_MASK_EXR_WINDOW 0x0020 /* Window exception */
#define XTPERF_MASK_EXR_ALLOCA 0x0040 /* Alloca exception */
#define XTPERF_MASK_EXR_OTHER 0x0080 /* Other exceptions */
#define XTPERF_MASK_EXR_MEM_ERR 0x0100 /* HW-corrected memory error */
/*
* XTPERF_CNT_BUBBLES selector mask
*/
#define XTPERF_MASK_BUBBLES_ALL 0x01FD
#define XTPERF_MASK_BUBBLES_PSO 0x0001 /* Processor domain PSO bubble */
#define XTPERF_MASK_BUBBLES_R_HOLD_D_CACHE_MISS 0x0004 /* R hold caused by DCache miss */
#define XTPERF_MASK_BUBBLES_R_HOLD_STORE_RELEASE 0x0008 /* R hold caused by Store release */
#define XTPERF_MASK_BUBBLES_R_HOLD_REG_DEP 0x0010 /* R hold caused by register dependency */
#define XTPERF_MASK_BUBBLES_R_HOLD_WAIT 0x0020 /* R hold caused by MEMW, EXTW or EXCW */
#define XTPERF_MASK_BUBBLES_R_HOLD_HALT 0x0040 /* R hold caused by Halt instruction (TX only) */
#define XTPERF_MASK_BUBBLES_CTI 0x0080 /* CTI bubble (e.g. branch delay slot) */
#define XTPERF_MASK_BUBBLES_WAITI 0x0100 /* WAITI bubble */
/*
* XTPERF_CNT_I_TLB selector mask
*/
#define XTPERF_MASK_I_TLB_ALL 0x000F
#define XTPERF_MASK_I_TLB_HITS 0x0001 /* Hit */
#define XTPERF_MASK_I_TLB_REPLAYS 0x0002 /* Replay of instruction due to ITLB miss */
#define XTPERF_MASK_I_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
#define XTPERF_MASK_I_TLB_MISSES 0x0008 /* ITLB Miss Exception */
/*
* XTPERF_CNT_I_MEM selector mask
*/
#define XTPERF_MASK_I_MEM_ALL 0x000F
#define XTPERF_MASK_I_MEM_CACHE_HITS 0x0001 /* ICache Hit */
#define XTPERF_MASK_I_MEM_CACHE_MISSES 0x0002 /* ICache Miss (includes uncached) */
#define XTPERF_MASK_I_MEM_IRAM 0x0004 /* InstRAM or InstROM */
#define XTPERF_MASK_I_MEM_BYPASS 0x0008 /* Bypass (i.e. uncached) fetch */
/*
* XTPERF_CNT_D_TLB selector mask
*/
#define XTPERF_MASK_D_TLB_ALL 0x000F
#define XTPERF_MASK_D_TLB_HITS 0x0001 /* Hit */
#define XTPERF_MASK_D_TLB_REPLAYS 0x0002 /* Replay of instruction due to DTLB miss */
#define XTPERF_MASK_D_TLB_REFILLS 0x0004 /* HW-assisted TLB Refill completes */
#define XTPERF_MASK_D_TLB_MISSES 0x0008 /* DTLB Miss Exception */
/*
* XTPERF_CNT_D_LOAD_U* selector mask
*/
#define XTPERF_MASK_D_LOAD_ALL 0x000F
#define XTPERF_MASK_D_LOAD_CACHE_HITS 0x0001 /* Cache Hit */
#define XTPERF_MASK_D_LOAD_CACHE_MISSES 0x0002 /* Cache Miss */
#define XTPERF_MASK_D_LOAD_LOCAL_MEM 0x0004 /* Local memory hit */
#define XTPERF_MASK_D_LOAD_BYPASS 0x0008 /* Bypass (i.e. uncached) load */
/*
* XTPERF_CNT_D_STORE_U* selector mask
*/
#define XTPERF_MASK_D_STORE_ALL 0x000F
#define XTPERF_MASK_D_STORE_CACHE_HITS 0x0001 /* DCache Hit */
#define XTPERF_MASK_D_STORE_CACHE_MISSES 0x0002 /* DCache Miss */
#define XTPERF_MASK_D_STORE_LOCAL_MEM 0x0004 /* Local memory hit */
#define XTPERF_MASK_D_STORE_PIF 0x0008 /* PIF Store */
/*
* XTPERF_CNT_D_ACCESS_U* selector mask
*/
#define XTPERF_MASK_D_ACCESS_ALL 0x000F
#define XTPERF_MASK_D_ACCESS_CACHE_MISSES 0x0001 /* DCache Miss */
#define XTPERF_MASK_D_ACCESS_HITS_SHARED 0x0002 /* Hit Shared */
#define XTPERF_MASK_D_ACCESS_HITS_EXCLUSIVE 0x0004 /* Hit Exclusive */
#define XTPERF_MASK_D_ACCESS_HITS_MODIFIED 0x0008 /* Hit Modified */
/*
* XTPERF_CNT_MULTIPLE_LS selector mask
*/
#define XTPERF_MASK_MULTIPLE_LS_ALL 0x003F
#define XTPERF_MASK_MULTIPLE_LS_0S_0L 0x0001 /* 0 stores and 0 loads */
#define XTPERF_MASK_MULTIPLE_LS_0S_1L 0x0002 /* 0 stores and 1 loads */
#define XTPERF_MASK_MULTIPLE_LS_1S_0L 0x0004 /* 1 stores and 0 loads */
#define XTPERF_MASK_MULTIPLE_LS_1S_1L 0x0008 /* 1 stores and 1 loads */
#define XTPERF_MASK_MULTIPLE_LS_0S_2L 0x0010 /* 0 stores and 2 loads */
#define XTPERF_MASK_MULTIPLE_LS_2S_0L 0x0020 /* 2 stores and 0 loads */
/*
* XTPERF_CNT_OUTBOUND_PIF selector mask
*/
#define XTPERF_MASK_OUTBOUND_PIF_ALL 0x0003
#define XTPERF_MASK_OUTBOUND_PIF_CASTOUT 0x0001 /* Castout */
#define XTPERF_MASK_OUTBOUND_PIF_PREFETCH 0x0002 /* Prefetch */
/*
* XTPERF_CNT_INBOUND_PIF selector mask
*/
#define XTPERF_MASK_INBOUND_PIF_ALL 0x0003
#define XTPERF_MASK_INBOUND_PIF_I_DMA 0x0001 /* Instruction DMA */
#define XTPERF_MASK_INBOUND_PIF_D_DMA 0x0002 /* Data DMA */
/*
* XTPERF_CNT_PREFETCH selector mask
*/
#define XTPERF_MASK_PREFETCH_ALL 0x002F
#define XTPERF_MASK_PREFETCH_I_HIT 0x0001 /* I prefetch-buffer-lookup hit */
#define XTPERF_MASK_PREFETCH_D_HIT 0x0002 /* D prefetch-buffer-lookup hit */
#define XTPERF_MASK_PREFETCH_I_MISS 0x0004 /* I prefetch-buffer-lookup miss */
#define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */
#define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */
#if XCHAL_HW_VERSION >= 270004
/*
* XTPERF_CNT_IDMA selector mask
*/
#define XTPERF_MASK_IDMA_ALL 0x0001
#define XTPERF_MASK_IDMA_ACTIVE_CYCLES 0x0001 /* Active Cycles */
/*
* XTPERF_CNT_INSN_LENGTH selector mask
*/
#define XTPERF_MASK_INSN_LENGTH_ALL 0x7FFF
#define XTPERF_MASK_INSN_LENGTH_16 0x0001 /* 16-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_24 0x0002 /* 24-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_32 0x0004 /* 32-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_40 0x0008 /* 40-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_48 0x0010 /* 48-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_56 0x0020 /* 56-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_64 0x0040 /* 64-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_72 0x0080 /* 72-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_80 0x0100 /* 80-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_88 0x0200 /* 88-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_96 0x0400 /* 96-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_104 0x0800 /* 104-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_112 0x1000 /* 112-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_120 0x2000 /* 120-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_128 0x4000 /* 128-bit instruction length */
#endif /* HW version >= 270004 */
#endif /* __XT_PERF_CONSTS_H__ */

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/*
* xtensa-libdb-macros.h
*/
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
/* Copyright (c) 2004-2008 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef __H_LIBDB_MACROS
#define __H_LIBDB_MACROS
/*
* This header file provides macros used to construct, identify and use
* "target numbers" that are assigned to various types of Xtensa processor
* registers and states. These target numbers are used by GDB in the remote
* protocol, and are thus used by all GDB debugger agents (targets).
* They are also used in ELF debugger information sections (stabs, dwarf, etc).
*
* These macros are separated from xtensa-libdb.h because they are needed
* by certain debugger agents that do not use or have access to libdb,
* e.g. the OCD daemon, RedBoot, XMON, etc.
*
* For the time being, for compatibility with certain 3rd party debugger
* software vendors, target numbers are limited to 16 bits. It is
* conceivable that this will be extended in the future to 32 bits.
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef uint32
#define uint32 unsigned int
#endif
#ifndef int32
#define int32 int
#endif
/*
* Macros to form register "target numbers" for various standard registers/states:
*/
#define XTENSA_DBREGN_INVALID -1 /* not a valid target number */
#define XTENSA_DBREGN_A(n) (0x0000+(n)) /* address registers a0..a15 */
#define XTENSA_DBREGN_B(n) (0x0010+(n)) /* boolean bits b0..b15 */
#define XTENSA_DBREGN_PC 0x0020 /* program counter */
/* 0x0021 RESERVED for use by Tensilica */
#define XTENSA_DBREGN_BO(n) (0x0022+(n)) /* boolean octuple-bits bo0..bo1 */
#define XTENSA_DBREGN_BQ(n) (0x0024+(n)) /* boolean quadruple-bits bq0..bq3 */
#define XTENSA_DBREGN_BD(n) (0x0028+(n)) /* boolean double-bits bd0..bd7 */
#define XTENSA_DBREGN_F(n) (0x0030+(n)) /* floating point registers f0..f15 */
#define XTENSA_DBREGN_VEC(n) (0x0040+(n)) /* Vectra vec regs v0..v15 */
#define XTENSA_DBREGN_VSEL(n) (0x0050+(n)) /* Vectra sel s0..s3 (V1) ..s7 (V2) */
#define XTENSA_DBREGN_VALIGN(n) (0x0058+(n)) /* Vectra valign regs u0..u3 */
#define XTENSA_DBREGN_VCOEFF(n) (0x005C+(n)) /* Vectra I vcoeff regs c0..c1 */
/* 0x005E..0x005F RESERVED for use by Tensilica */
#define XTENSA_DBREGN_AEP(n) (0x0060+(n)) /* HiFi2 Audio Engine regs aep0..aep7 */
#define XTENSA_DBREGN_AEQ(n) (0x0068+(n)) /* HiFi2 Audio Engine regs aeq0..aeq3 */
/* 0x006C..0x00FF RESERVED for use by Tensilica */
#define XTENSA_DBREGN_AR(n) (0x0100+(n)) /* physical address regs ar0..ar63
(note: only with window option) */
/* 0x0140..0x01FF RESERVED for use by Tensilica */
#define XTENSA_DBREGN_SREG(n) (0x0200+(n)) /* special registers 0..255 (core) */
#define XTENSA_DBREGN_BR XTENSA_DBREGN_SREG(0x04) /* all 16 boolean bits, BR */
#define XTENSA_DBREGN_MR(n) XTENSA_DBREGN_SREG(0x20+(n)) /* MAC16 registers m0..m3 */
#define XTENSA_DBREGN_UREG(n) (0x0300+(n)) /* user registers 0..255 (TIE) */
/* 0x0400..0x0FFF RESERVED for use by Tensilica */
/* 0x1000..0x1FFF user-defined regfiles */
/* 0x2000..0xEFFF other states (and regfiles) */
#define XTENSA_DBREGN_DBAGENT(n) (0xF000+(n)) /* non-processor "registers" 0..4095 for
3rd-party debugger agent defined use */
/* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
/*#define XTENSA_DBREGN_CONTEXT(n) (0x02000000+((n)<<20))*/ /* add this macro's value to a target
number to identify a specific context 0..31
for context-replicated registers */
#define XTENSA_DBREGN_MASK 0xFFFF /* mask of valid target_number bits */
#define XTENSA_DBREGN_WRITE_SIDE 0x04000000 /* flag to request write half of a register
split into distinct read and write entries
with the same target number (currently only
valid in a couple of libdb API functions;
see xtensa-libdb.h for details) */
/*
* Macros to identify specific ranges of target numbers (formed above):
* NOTE: any context number (or other upper 12 bits) are considered
* modifiers and are thus stripped out for identification purposes.
*/
#define XTENSA_DBREGN_IS_VALID(tn) (((tn) & ~0xFFFF) == 0) /* just tests it's 16-bit unsigned */
#define XTENSA_DBREGN_IS_A(tn) (((tn) & 0xFFF0)==0x0000) /* is a0..a15 */
#define XTENSA_DBREGN_IS_B(tn) (((tn) & 0xFFF0)==0x0010) /* is b0..b15 */
#define XTENSA_DBREGN_IS_PC(tn) (((tn) & 0xFFFF)==0x0020) /* is program counter */
#define XTENSA_DBREGN_IS_BO(tn) (((tn) & 0xFFFE)==0x0022) /* is bo0..bo1 */
#define XTENSA_DBREGN_IS_BQ(tn) (((tn) & 0xFFFC)==0x0024) /* is bq0..bq3 */
#define XTENSA_DBREGN_IS_BD(tn) (((tn) & 0xFFF8)==0x0028) /* is bd0..bd7 */
#define XTENSA_DBREGN_IS_F(tn) (((tn) & 0xFFF0)==0x0030) /* is f0..f15 */
#define XTENSA_DBREGN_IS_VEC(tn) (((tn) & 0xFFF0)==0x0040) /* is v0..v15 */
#define XTENSA_DBREGN_IS_VSEL(tn) (((tn) & 0xFFF8)==0x0050) /* is s0..s7 (s0..s3 in V1) */
#define XTENSA_DBREGN_IS_VALIGN(tn) (((tn) & 0xFFFC)==0x0058) /* is u0..u3 */
#define XTENSA_DBREGN_IS_VCOEFF(tn) (((tn) & 0xFFFE)==0x005C) /* is c0..c1 */
#define XTENSA_DBREGN_IS_AEP(tn) (((tn) & 0xFFF8)==0x0060) /* is aep0..aep7 */
#define XTENSA_DBREGN_IS_AEQ(tn) (((tn) & 0xFFFC)==0x0068) /* is aeq0..aeq3 */
#define XTENSA_DBREGN_IS_AR(tn) (((tn) & 0xFFC0)==0x0100) /* is ar0..ar63 */
#define XTENSA_DBREGN_IS_SREG(tn) (((tn) & 0xFF00)==0x0200) /* is special register */
#define XTENSA_DBREGN_IS_BR(tn) (((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04)) /* is BR */
#define XTENSA_DBREGN_IS_MR(tn) (((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20)) /* m0..m3 */
#define XTENSA_DBREGN_IS_UREG(tn) (((tn) & 0xFF00)==0x0300) /* is user register */
#define XTENSA_DBREGN_IS_DBAGENT(tn) (((tn) & 0xF000)==0xF000) /* is non-processor */
/*#define XTENSA_DBREGN_IS_CONTEXT(tn) (((tn) & 0x02000000) != 0)*/ /* specifies context # */
/*
* Macros to extract register index from a register "target number"
* when a specific range has been identified using one of the _IS_ macros above.
* These macros only return a useful value if the corresponding _IS_ macro returns true.
*/
#define XTENSA_DBREGN_A_INDEX(tn) ((tn) & 0x0F) /* 0..15 for a0..a15 */
#define XTENSA_DBREGN_B_INDEX(tn) ((tn) & 0x0F) /* 0..15 for b0..b15 */
#define XTENSA_DBREGN_BO_INDEX(tn) ((tn) & 0x01) /* 0..1 for bo0..bo1 */
#define XTENSA_DBREGN_BQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for bq0..bq3 */
#define XTENSA_DBREGN_BD_INDEX(tn) ((tn) & 0x07) /* 0..7 for bd0..bd7 */
#define XTENSA_DBREGN_F_INDEX(tn) ((tn) & 0x0F) /* 0..15 for f0..f15 */
#define XTENSA_DBREGN_VEC_INDEX(tn) ((tn) & 0x0F) /* 0..15 for v0..v15 */
#define XTENSA_DBREGN_VSEL_INDEX(tn) ((tn) & 0x07) /* 0..7 for s0..s7 */
#define XTENSA_DBREGN_VALIGN_INDEX(tn) ((tn) & 0x03) /* 0..3 for u0..u3 */
#define XTENSA_DBREGN_VCOEFF_INDEX(tn) ((tn) & 0x01) /* 0..1 for c0..c1 */
#define XTENSA_DBREGN_AEP_INDEX(tn) ((tn) & 0x07) /* 0..7 for aep0..aep7 */
#define XTENSA_DBREGN_AEQ_INDEX(tn) ((tn) & 0x03) /* 0..3 for aeq0..aeq3 */
#define XTENSA_DBREGN_AR_INDEX(tn) ((tn) & 0x3F) /* 0..63 for ar0..ar63 */
#define XTENSA_DBREGN_SREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for special registers */
#define XTENSA_DBREGN_MR_INDEX(tn) ((tn) & 0x03) /* 0..3 for m0..m3 */
#define XTENSA_DBREGN_UREG_INDEX(tn) ((tn) & 0xFF) /* 0..255 for user registers */
#define XTENSA_DBREGN_DBAGENT_INDEX(tn) ((tn) & 0xFFF) /* 0..4095 for non-processor */
/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn) (((tn) >> 20) & 0x1F)*/ /* 0..31 context numbers */
#ifdef __cplusplus
}
#endif
#endif /* __H_LIBDB_MACROS */

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/*
xtensa-versions.h -- definitions of Xtensa version and release numbers
This file defines most Xtensa-related product versions and releases
that exist so far.
It also provides a bit of information about which ones are current.
This file changes every release, as versions/releases get added.
*/
// $Id: //depot/rel/Foxhill/dot.9/Xtensa/Software/misc/xtensa-versions.h.tpp#1 $
/*
Copyright (c) 2006-2018 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTENSA_VERSIONS_H
#define XTENSA_VERSIONS_H
/*
* NOTE: A "release" is a collection of product versions
* made available at once (together) to customers.
* In the past, release and version names all matched in T####.# form,
* making the distinction irrelevant.
* Starting with the RA-2004.1 release, this is no longer the case.
*/
/* Hardware (Xtensa/Diamond processor) versions: */
#define XTENSA_HWVERSION_T1020_0 102000 /* versions T1020.0 */
#define XTENSA_HWCIDSCHEME_T1020_0 10
#define XTENSA_HWCIDVERS_T1020_0 2
#define XTENSA_HWVERSION_T1020_1 102001 /* versions T1020.1 */
#define XTENSA_HWCIDSCHEME_T1020_1 10
#define XTENSA_HWCIDVERS_T1020_1 3
#define XTENSA_HWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_HWCIDSCHEME_T1020_2 10
#define XTENSA_HWCIDVERS_T1020_2 4
#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_HWCIDSCHEME_T1020_2B 10
#define XTENSA_HWCIDVERS_T1020_2B 5
#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_HWCIDSCHEME_T1020_3 10
#define XTENSA_HWCIDVERS_T1020_3 6
#define XTENSA_HWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_HWCIDSCHEME_T1020_4 10
#define XTENSA_HWCIDVERS_T1020_4 7
#define XTENSA_HWVERSION_T1030_0 103000 /* versions T1030.0 */
#define XTENSA_HWCIDSCHEME_T1030_0 10
#define XTENSA_HWCIDVERS_T1030_0 9
#define XTENSA_HWVERSION_T1030_1 103001 /* versions T1030.1 */
#define XTENSA_HWCIDSCHEME_T1030_1 10
#define XTENSA_HWCIDVERS_T1030_1 10
#define XTENSA_HWVERSION_T1030_2 103002 /* versions T1030.2 */
#define XTENSA_HWCIDSCHEME_T1030_2 10
#define XTENSA_HWCIDVERS_T1030_2 11
#define XTENSA_HWVERSION_T1030_3 103003 /* versions T1030.3 */
#define XTENSA_HWCIDSCHEME_T1030_3 10
#define XTENSA_HWCIDVERS_T1030_3 12
#define XTENSA_HWVERSION_T1040_0 104000 /* versions T1040.0 */
#define XTENSA_HWCIDSCHEME_T1040_0 10
#define XTENSA_HWCIDVERS_T1040_0 15
#define XTENSA_HWVERSION_T1040_1 104001 /* versions T1040.1 */
#define XTENSA_HWCIDSCHEME_T1040_1 1
#define XTENSA_HWCIDVERS_T1040_1 32
#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
#define XTENSA_HWCIDSCHEME_T1040_1P 10
#define XTENSA_HWCIDVERS_T1040_1P 16
#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */
#define XTENSA_HWCIDSCHEME_T1040_2 1
#define XTENSA_HWCIDVERS_T1040_2 33
#define XTENSA_HWVERSION_T1040_3 104003 /* versions T1040.3 */
#define XTENSA_HWCIDSCHEME_T1040_3 1
#define XTENSA_HWCIDVERS_T1040_3 34
#define XTENSA_HWVERSION_T1050_0 105000 /* versions T1050.0 */
#define XTENSA_HWCIDSCHEME_T1050_0 1100
#define XTENSA_HWCIDVERS_T1050_0 1
#define XTENSA_HWVERSION_T1050_1 105001 /* versions T1050.1 */
#define XTENSA_HWCIDSCHEME_T1050_1 1100
#define XTENSA_HWCIDVERS_T1050_1 2
#define XTENSA_HWVERSION_T1050_2 105002 /* versions T1050.2 */
#define XTENSA_HWCIDSCHEME_T1050_2 1100
#define XTENSA_HWCIDVERS_T1050_2 4
#define XTENSA_HWVERSION_T1050_3 105003 /* versions T1050.3 */
#define XTENSA_HWCIDSCHEME_T1050_3 1100
#define XTENSA_HWCIDVERS_T1050_3 6
#define XTENSA_HWVERSION_T1050_4 105004 /* versions T1050.4 */
#define XTENSA_HWCIDSCHEME_T1050_4 1100
#define XTENSA_HWCIDVERS_T1050_4 7
#define XTENSA_HWVERSION_T1050_5 105005 /* versions T1050.5 */
#define XTENSA_HWCIDSCHEME_T1050_5 1100
#define XTENSA_HWCIDVERS_T1050_5 8
#define XTENSA_HWVERSION_RA_2004_1 210000 /* versions LX1.0.0 */
#define XTENSA_HWCIDSCHEME_RA_2004_1 1100
#define XTENSA_HWCIDVERS_RA_2004_1 3
#define XTENSA_HWVERSION_RA_2005_1 210001 /* versions LX1.0.1 */
#define XTENSA_HWCIDSCHEME_RA_2005_1 1100
#define XTENSA_HWCIDVERS_RA_2005_1 20
#define XTENSA_HWVERSION_RA_2005_2 210002 /* versions LX1.0.2 */
#define XTENSA_HWCIDSCHEME_RA_2005_2 1100
#define XTENSA_HWCIDVERS_RA_2005_2 21
#define XTENSA_HWVERSION_RA_2005_3 210003 /* versions LX1.0.3, X6.0.3 */
#define XTENSA_HWCIDSCHEME_RA_2005_3 1100
#define XTENSA_HWCIDVERS_RA_2005_3 22
#define XTENSA_HWVERSION_RA_2006_4 210004 /* versions LX1.0.4, X6.0.4 */
#define XTENSA_HWCIDSCHEME_RA_2006_4 1100
#define XTENSA_HWCIDVERS_RA_2006_4 23
#define XTENSA_HWVERSION_RA_2006_5 210005 /* versions LX1.0.5, X6.0.5 */
#define XTENSA_HWCIDSCHEME_RA_2006_5 1100
#define XTENSA_HWCIDVERS_RA_2006_5 24
#define XTENSA_HWVERSION_RA_2006_6 210006 /* versions LX1.0.6, X6.0.6 */
#define XTENSA_HWCIDSCHEME_RA_2006_6 1100
#define XTENSA_HWCIDVERS_RA_2006_6 25
#define XTENSA_HWVERSION_RA_2007_7 210007 /* versions LX1.0.7, X6.0.7 */
#define XTENSA_HWCIDSCHEME_RA_2007_7 1100
#define XTENSA_HWCIDVERS_RA_2007_7 26
#define XTENSA_HWVERSION_RA_2008_8 210008 /* versions LX1.0.8, X6.0.8 */
#define XTENSA_HWCIDSCHEME_RA_2008_8 1100
#define XTENSA_HWCIDVERS_RA_2008_8 27
#define XTENSA_HWVERSION_RB_2006_0 220000 /* versions LX2.0.0, X7.0.0 */
#define XTENSA_HWCIDSCHEME_RB_2006_0 1100
#define XTENSA_HWCIDVERS_RB_2006_0 48
#define XTENSA_HWVERSION_RB_2007_1 220001 /* versions LX2.0.1, X7.0.1 */
#define XTENSA_HWCIDSCHEME_RB_2007_1 1100
#define XTENSA_HWCIDVERS_RB_2007_1 49
#define XTENSA_HWVERSION_RB_2007_2 221000 /* versions LX2.1.0, X7.1.0 */
#define XTENSA_HWCIDSCHEME_RB_2007_2 1100
#define XTENSA_HWCIDVERS_RB_2007_2 52
#define XTENSA_HWVERSION_RB_2008_3 221001 /* versions LX2.1.1, X7.1.1 */
#define XTENSA_HWCIDSCHEME_RB_2008_3 1100
#define XTENSA_HWCIDVERS_RB_2008_3 53
#define XTENSA_HWVERSION_RB_2008_4 221002 /* versions LX2.1.2, X7.1.2 */
#define XTENSA_HWCIDSCHEME_RB_2008_4 1100
#define XTENSA_HWCIDVERS_RB_2008_4 54
#define XTENSA_HWVERSION_RB_2009_5 221003 /* versions LX2.1.3, X7.1.3 */
#define XTENSA_HWCIDSCHEME_RB_2009_5 1100
#define XTENSA_HWCIDVERS_RB_2009_5 55
#define XTENSA_HWVERSION_RB_2007_2_MP 221100 /* versions LX2.1.8-MP, X7.1.8-MP */
#define XTENSA_HWCIDSCHEME_RB_2007_2_MP 1100
#define XTENSA_HWCIDVERS_RB_2007_2_MP 64
#define XTENSA_HWVERSION_RC_2009_0 230000 /* versions LX3.0.0, X8.0.0, MX1.0.0 */
#define XTENSA_HWCIDSCHEME_RC_2009_0 1100
#define XTENSA_HWCIDVERS_RC_2009_0 65
#define XTENSA_HWVERSION_RC_2010_1 230001 /* versions LX3.0.1, X8.0.1, MX1.0.1 */
#define XTENSA_HWCIDSCHEME_RC_2010_1 1100
#define XTENSA_HWCIDVERS_RC_2010_1 66
#define XTENSA_HWVERSION_RC_2010_2 230002 /* versions LX3.0.2, X8.0.2, MX1.0.2 */
#define XTENSA_HWCIDSCHEME_RC_2010_2 1100
#define XTENSA_HWCIDVERS_RC_2010_2 67
#define XTENSA_HWVERSION_RC_2011_3 230003 /* versions LX3.0.3, X8.0.3, MX1.0.3 */
#define XTENSA_HWCIDSCHEME_RC_2011_3 1100
#define XTENSA_HWCIDVERS_RC_2011_3 68
#define XTENSA_HWVERSION_RD_2010_0 240000 /* versions LX4.0.0, X9.0.0, MX1.1.0, TX1.0.0 */
#define XTENSA_HWCIDSCHEME_RD_2010_0 1100
#define XTENSA_HWCIDVERS_RD_2010_0 80
#define XTENSA_HWVERSION_RD_2011_1 240001 /* versions LX4.0.1, X9.0.1, MX1.1.1, TX1.0.1 */
#define XTENSA_HWCIDSCHEME_RD_2011_1 1100
#define XTENSA_HWCIDVERS_RD_2011_1 81
#define XTENSA_HWVERSION_RD_2011_2 240002 /* versions LX4.0.2, X9.0.2, MX1.1.2, TX1.0.2 */
#define XTENSA_HWCIDSCHEME_RD_2011_2 1100
#define XTENSA_HWCIDVERS_RD_2011_2 82
#define XTENSA_HWVERSION_RD_2011_3 240003 /* versions LX4.0.3, X9.0.3, MX1.1.3, TX1.0.3 */
#define XTENSA_HWCIDSCHEME_RD_2011_3 1100
#define XTENSA_HWCIDVERS_RD_2011_3 83
#define XTENSA_HWVERSION_RD_2012_4 240004 /* versions LX4.0.4, X9.0.4, MX1.1.4, TX1.0.4 */
#define XTENSA_HWCIDSCHEME_RD_2012_4 1100
#define XTENSA_HWCIDVERS_RD_2012_4 84
#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
#define XTENSA_HWCIDSCHEME_RD_2012_5 1100
#define XTENSA_HWCIDVERS_RD_2012_5 85
#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0 */
#define XTENSA_HWCIDSCHEME_RE_2012_0 1100
#define XTENSA_HWCIDVERS_RE_2012_0 96
#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1 */
#define XTENSA_HWCIDSCHEME_RE_2012_1 1100
#define XTENSA_HWCIDVERS_RE_2012_1 97
#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2 */
#define XTENSA_HWCIDSCHEME_RE_2013_2 1100
#define XTENSA_HWCIDVERS_RE_2013_2 98
#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3 */
#define XTENSA_HWCIDSCHEME_RE_2013_3 1100
#define XTENSA_HWCIDVERS_RE_2013_3 99
#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4 */
#define XTENSA_HWCIDSCHEME_RE_2013_4 1100
#define XTENSA_HWCIDVERS_RE_2013_4 100
#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5 */
#define XTENSA_HWCIDSCHEME_RE_2014_5 1100
#define XTENSA_HWCIDVERS_RE_2014_5 101
#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6 */
#define XTENSA_HWCIDSCHEME_RE_2015_6 1100
#define XTENSA_HWCIDVERS_RE_2015_6 102
#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0 */
#define XTENSA_HWCIDSCHEME_RF_2014_0 1100
#define XTENSA_HWCIDVERS_RF_2014_0 112
#define XTENSA_HWVERSION_RF_2014_1 260001 /* versions LX6.0.1, X11.0.1 */
#define XTENSA_HWCIDSCHEME_RF_2014_1 1100
#define XTENSA_HWCIDVERS_RF_2014_1 113
#define XTENSA_HWVERSION_RF_2015_2 260002 /* versions LX6.0.2, X11.0.2 */
#define XTENSA_HWCIDSCHEME_RF_2015_2 1100
#define XTENSA_HWCIDVERS_RF_2015_2 114
#define XTENSA_HWVERSION_RF_2015_3 260003 /* versions LX6.0.3, X11.0.3 */
#define XTENSA_HWCIDSCHEME_RF_2015_3 1100
#define XTENSA_HWCIDVERS_RF_2015_3 115
#define XTENSA_HWVERSION_RF_2016_4 260004 /* versions LX6.0.4, X11.0.4 */
#define XTENSA_HWCIDSCHEME_RF_2016_4 1100
#define XTENSA_HWCIDVERS_RF_2016_4 116
#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0 */
#define XTENSA_HWCIDSCHEME_RG_2015_0 1100
#define XTENSA_HWCIDVERS_RG_2015_0 128
#define XTENSA_HWVERSION_RG_2015_1 270001 /* versions LX7.0.1 */
#define XTENSA_HWCIDSCHEME_RG_2015_1 1100
#define XTENSA_HWCIDVERS_RG_2015_1 129
#define XTENSA_HWVERSION_RG_2015_2 270002 /* versions LX7.0.2 */
#define XTENSA_HWCIDSCHEME_RG_2015_2 1100
#define XTENSA_HWCIDVERS_RG_2015_2 130
#define XTENSA_HWVERSION_RG_2016_3 270003 /* versions LX7.0.3 */
#define XTENSA_HWCIDSCHEME_RG_2016_3 1100
#define XTENSA_HWCIDVERS_RG_2016_3 131
#define XTENSA_HWVERSION_RG_2016_4 270004 /* versions LX7.0.4 */
#define XTENSA_HWCIDSCHEME_RG_2016_4 1100
#define XTENSA_HWCIDVERS_RG_2016_4 132
#define XTENSA_HWVERSION_RG_2017_5 270005 /* versions LX7.0.5 */
#define XTENSA_HWCIDSCHEME_RG_2017_5 1100
#define XTENSA_HWCIDVERS_RG_2017_5 133
#define XTENSA_HWVERSION_RG_2017_6 270006 /* versions LX7.0.6 */
#define XTENSA_HWCIDSCHEME_RG_2017_6 1100
#define XTENSA_HWCIDVERS_RG_2017_6 134
#define XTENSA_HWVERSION_RG_2017_7 270007 /* versions LX7.0.7 */
#define XTENSA_HWCIDSCHEME_RG_2017_7 1100
#define XTENSA_HWCIDVERS_RG_2017_7 135
#define XTENSA_HWVERSION_RG_2017_8 270008 /* versions LX7.0.8 */
#define XTENSA_HWCIDSCHEME_RG_2017_8 1100
#define XTENSA_HWCIDVERS_RG_2017_8 136
#define XTENSA_HWVERSION_RG_2018_9 270009 /* versions LX7.0.9 */
#define XTENSA_HWCIDSCHEME_RG_2018_9 1100
#define XTENSA_HWCIDVERS_RG_2018_9 137
#define XTENSA_HWVERSION_RH_2016_0 280000 /* versions LX8.0.0, NX1.0.0, SX1.0.0 */
#define XTENSA_HWCIDSCHEME_RH_2016_0 1100
#define XTENSA_HWCIDVERS_RH_2016_0 144
/* Software (Xtensa Tools) versions: */
#define XTENSA_SWVERSION_T1020_0 102000 /* versions T1020.0 */
#define XTENSA_SWVERSION_T1020_1 102001 /* versions T1020.1 */
#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 */
#define XTENSA_SWVERSION_T1030_1 103001 /* versions T1030.1 */
#define XTENSA_SWVERSION_T1030_2 103002 /* versions T1030.2 */
#define XTENSA_SWVERSION_T1030_3 103003 /* versions T1030.3 */
#define XTENSA_SWVERSION_T1040_0 104000 /* versions T1040.0 */
#define XTENSA_SWVERSION_T1040_1 104001 /* versions T1040.1 */
#define XTENSA_SWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
#define XTENSA_SWVERSION_T1040_2 104002 /* versions T1040.2 */
#define XTENSA_SWVERSION_T1040_3 104003 /* versions T1040.3 */
#define XTENSA_SWVERSION_T1050_0 105000 /* versions T1050.0 */
#define XTENSA_SWVERSION_T1050_1 105001 /* versions T1050.1 */
#define XTENSA_SWVERSION_T1050_2 105002 /* versions T1050.2 */
#define XTENSA_SWVERSION_T1050_3 105003 /* versions T1050.3 */
#define XTENSA_SWVERSION_T1050_4 105004 /* versions T1050.4 */
#define XTENSA_SWVERSION_T1050_5 105005 /* versions T1050.5 */
#define XTENSA_SWVERSION_RA_2004_1 600000 /* versions 6.0.0 */
#define XTENSA_SWVERSION_RA_2005_1 600001 /* versions 6.0.1 */
#define XTENSA_SWVERSION_RA_2005_2 600002 /* versions 6.0.2 */
#define XTENSA_SWVERSION_RA_2005_3 600003 /* versions 6.0.3 */
#define XTENSA_SWVERSION_RA_2006_4 600004 /* versions 6.0.4 */
#define XTENSA_SWVERSION_RA_2006_5 600005 /* versions 6.0.5 */
#define XTENSA_SWVERSION_RA_2006_6 600006 /* versions 6.0.6 */
#define XTENSA_SWVERSION_RA_2007_7 600007 /* versions 6.0.7 */
#define XTENSA_SWVERSION_RA_2008_8 600008 /* versions 6.0.8 */
#define XTENSA_SWVERSION_RB_2006_0 700000 /* versions 7.0.0 */
#define XTENSA_SWVERSION_RB_2007_1 700001 /* versions 7.0.1 */
#define XTENSA_SWVERSION_RB_2007_2 701000 /* versions 7.1.0 */
#define XTENSA_SWVERSION_RB_2008_3 701001 /* versions 7.1.1 */
#define XTENSA_SWVERSION_RB_2008_4 701002 /* versions 7.1.2 */
#define XTENSA_SWVERSION_RB_2009_5 701003 /* versions 7.1.3 */
#define XTENSA_SWVERSION_RB_2007_2_MP 701100 /* versions 7.1.8-MP */
#define XTENSA_SWVERSION_RC_2009_0 800000 /* versions 8.0.0 */
#define XTENSA_SWVERSION_RC_2010_1 800001 /* versions 8.0.1 */
#define XTENSA_SWVERSION_RC_2010_2 800002 /* versions 8.0.2 */
#define XTENSA_SWVERSION_RC_2011_3 800003 /* versions 8.0.3 */
#define XTENSA_SWVERSION_RD_2010_0 900000 /* versions 9.0.0 */
#define XTENSA_SWVERSION_RD_2011_1 900001 /* versions 9.0.1 */
#define XTENSA_SWVERSION_RD_2011_2 900002 /* versions 9.0.2 */
#define XTENSA_SWVERSION_RD_2011_3 900003 /* versions 9.0.3 */
#define XTENSA_SWVERSION_RD_2012_4 900004 /* versions 9.0.4 */
#define XTENSA_SWVERSION_RD_2012_5 900005 /* versions 9.0.5 */
#define XTENSA_SWVERSION_RE_2012_0 1000000 /* versions 10.0.0 */
#define XTENSA_SWVERSION_RE_2012_1 1000001 /* versions 10.0.1 */
#define XTENSA_SWVERSION_RE_2013_2 1000002 /* versions 10.0.2 */
#define XTENSA_SWVERSION_RE_2013_3 1000003 /* versions 10.0.3 */
#define XTENSA_SWVERSION_RE_2013_4 1000004 /* versions 10.0.4 */
#define XTENSA_SWVERSION_RE_2014_5 1000005 /* versions 10.0.5 */
#define XTENSA_SWVERSION_RE_2015_6 1000006 /* versions 10.0.6 */
#define XTENSA_SWVERSION_RF_2014_0 1100000 /* versions 11.0.0 */
#define XTENSA_SWVERSION_RF_2014_1 1100001 /* versions 11.0.1 */
#define XTENSA_SWVERSION_RF_2015_2 1100002 /* versions 11.0.2 */
#define XTENSA_SWVERSION_RF_2015_3 1100003 /* versions 11.0.3 */
#define XTENSA_SWVERSION_RF_2016_4 1100004 /* versions 11.0.4 */
#define XTENSA_SWVERSION_RG_2015_0 1200000 /* versions 12.0.0 */
#define XTENSA_SWVERSION_RG_2015_1 1200001 /* versions 12.0.1 */
#define XTENSA_SWVERSION_RG_2015_2 1200002 /* versions 12.0.2 */
#define XTENSA_SWVERSION_RG_2016_3 1200003 /* versions 12.0.3 */
#define XTENSA_SWVERSION_RG_2016_4 1200004 /* versions 12.0.4 */
#define XTENSA_SWVERSION_RG_2017_5 1200005 /* versions 12.0.5 */
#define XTENSA_SWVERSION_RG_2017_6 1200006 /* versions 12.0.6 */
#define XTENSA_SWVERSION_RG_2017_7 1200007 /* versions 12.0.7 */
#define XTENSA_SWVERSION_RG_2017_8 1200008 /* versions 12.0.8 */
#define XTENSA_SWVERSION_RG_2018_9 1200009 /* versions 12.0.9 */
#define XTENSA_SWVERSION_RH_2016_0 1300000 /* versions 13.0.0 */
#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWVERSION_T1040_1P /* T1040.1-prehotfix */
#define XTENSA_SWVERSION_6_0_0 XTENSA_SWVERSION_RA_2004_1 /* 6.0.0 */
#define XTENSA_SWVERSION_6_0_1 XTENSA_SWVERSION_RA_2005_1 /* 6.0.1 */
#define XTENSA_SWVERSION_6_0_2 XTENSA_SWVERSION_RA_2005_2 /* 6.0.2 */
#define XTENSA_SWVERSION_6_0_3 XTENSA_SWVERSION_RA_2005_3 /* 6.0.3 */
#define XTENSA_SWVERSION_6_0_4 XTENSA_SWVERSION_RA_2006_4 /* 6.0.4 */
#define XTENSA_SWVERSION_6_0_5 XTENSA_SWVERSION_RA_2006_5 /* 6.0.5 */
#define XTENSA_SWVERSION_6_0_6 XTENSA_SWVERSION_RA_2006_6 /* 6.0.6 */
#define XTENSA_SWVERSION_6_0_7 XTENSA_SWVERSION_RA_2007_7 /* 6.0.7 */
#define XTENSA_SWVERSION_6_0_8 XTENSA_SWVERSION_RA_2008_8 /* 6.0.8 */
#define XTENSA_SWVERSION_7_0_0 XTENSA_SWVERSION_RB_2006_0 /* 7.0.0 */
#define XTENSA_SWVERSION_7_0_1 XTENSA_SWVERSION_RB_2007_1 /* 7.0.1 */
#define XTENSA_SWVERSION_7_1_0 XTENSA_SWVERSION_RB_2007_2 /* 7.1.0 */
#define XTENSA_SWVERSION_7_1_1 XTENSA_SWVERSION_RB_2008_3 /* 7.1.1 */
#define XTENSA_SWVERSION_7_1_2 XTENSA_SWVERSION_RB_2008_4 /* 7.1.2 */
#define XTENSA_SWVERSION_7_1_3 XTENSA_SWVERSION_RB_2009_5 /* 7.1.3 */
#define XTENSA_SWVERSION_7_1_8_MP XTENSA_SWVERSION_RB_2007_2_MP /* 7.1.8-MP */
#define XTENSA_SWVERSION_8_0_0 XTENSA_SWVERSION_RC_2009_0 /* 8.0.0 */
#define XTENSA_SWVERSION_8_0_1 XTENSA_SWVERSION_RC_2010_1 /* 8.0.1 */
#define XTENSA_SWVERSION_8_0_2 XTENSA_SWVERSION_RC_2010_2 /* 8.0.2 */
#define XTENSA_SWVERSION_8_0_3 XTENSA_SWVERSION_RC_2011_3 /* 8.0.3 */
#define XTENSA_SWVERSION_9_0_0 XTENSA_SWVERSION_RD_2010_0 /* 9.0.0 */
#define XTENSA_SWVERSION_9_0_1 XTENSA_SWVERSION_RD_2011_1 /* 9.0.1 */
#define XTENSA_SWVERSION_9_0_2 XTENSA_SWVERSION_RD_2011_2 /* 9.0.2 */
#define XTENSA_SWVERSION_9_0_3 XTENSA_SWVERSION_RD_2011_3 /* 9.0.3 */
#define XTENSA_SWVERSION_9_0_4 XTENSA_SWVERSION_RD_2012_4 /* 9.0.4 */
#define XTENSA_SWVERSION_9_0_5 XTENSA_SWVERSION_RD_2012_5 /* 9.0.5 */
#define XTENSA_SWVERSION_10_0_0 XTENSA_SWVERSION_RE_2012_0 /* 10.0.0 */
#define XTENSA_SWVERSION_10_0_1 XTENSA_SWVERSION_RE_2012_1 /* 10.0.1 */
#define XTENSA_SWVERSION_10_0_2 XTENSA_SWVERSION_RE_2013_2 /* 10.0.2 */
#define XTENSA_SWVERSION_10_0_3 XTENSA_SWVERSION_RE_2013_3 /* 10.0.3 */
#define XTENSA_SWVERSION_10_0_4 XTENSA_SWVERSION_RE_2013_4 /* 10.0.4 */
#define XTENSA_SWVERSION_10_0_5 XTENSA_SWVERSION_RE_2014_5 /* 10.0.5 */
#define XTENSA_SWVERSION_10_0_6 XTENSA_SWVERSION_RE_2015_6 /* 10.0.6 */
#define XTENSA_SWVERSION_11_0_0 XTENSA_SWVERSION_RF_2014_0 /* 11.0.0 */
#define XTENSA_SWVERSION_11_0_1 XTENSA_SWVERSION_RF_2014_1 /* 11.0.1 */
#define XTENSA_SWVERSION_11_0_2 XTENSA_SWVERSION_RF_2015_2 /* 11.0.2 */
#define XTENSA_SWVERSION_11_0_3 XTENSA_SWVERSION_RF_2015_3 /* 11.0.3 */
#define XTENSA_SWVERSION_11_0_4 XTENSA_SWVERSION_RF_2016_4 /* 11.0.4 */
#define XTENSA_SWVERSION_12_0_0 XTENSA_SWVERSION_RG_2015_0 /* 12.0.0 */
#define XTENSA_SWVERSION_12_0_1 XTENSA_SWVERSION_RG_2015_1 /* 12.0.1 */
#define XTENSA_SWVERSION_12_0_2 XTENSA_SWVERSION_RG_2015_2 /* 12.0.2 */
#define XTENSA_SWVERSION_12_0_3 XTENSA_SWVERSION_RG_2016_3 /* 12.0.3 */
#define XTENSA_SWVERSION_12_0_4 XTENSA_SWVERSION_RG_2016_4 /* 12.0.4 */
#define XTENSA_SWVERSION_12_0_5 XTENSA_SWVERSION_RG_2017_5 /* 12.0.5 */
#define XTENSA_SWVERSION_12_0_6 XTENSA_SWVERSION_RG_2017_6 /* 12.0.6 */
#define XTENSA_SWVERSION_12_0_7 XTENSA_SWVERSION_RG_2017_7 /* 12.0.7 */
#define XTENSA_SWVERSION_12_0_8 XTENSA_SWVERSION_RG_2017_8 /* 12.0.8 */
#define XTENSA_SWVERSION_12_0_9 XTENSA_SWVERSION_RG_2018_9 /* 12.0.9 */
#define XTENSA_SWVERSION_13_0_0 XTENSA_SWVERSION_RH_2016_0 /* 13.0.0 */
/* The current release: */
#define XTENSA_RELEASE_NAME "RG-2018.9"
#define XTENSA_RELEASE_CANONICAL_NAME "RG-2018.9"
/* The product versions within the current release: */
#define XTENSA_SWVERSION XTENSA_SWVERSION_RG_2018_9
#define XTENSA_SWVERSION_NAME "12.0.9"
#define XTENSA_SWVERSION_NAME_IDENT 12_0_9
#define XTENSA_SWVERSION_CANONICAL_NAME "12.0.9"
#define XTENSA_SWVERSION_MAJORMID_NAME "12.0"
#define XTENSA_SWVERSION_MAJOR_NAME "12"
/* For product licensing (not necessarily same as *_MAJORMID_NAME): */
#define XTENSA_SWVERSION_LICENSE_NAME "12.0"
/* Note: there may be multiple hardware products in one release,
and software can target older hardware, so the notion of
"current" hardware versions is partially configuration dependent.
For now, "current" hardware product version info is left out
to avoid confusion. */
#endif /*XTENSA_VERSIONS_H*/

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/* xer-constants.h -- various constants describing external registers accessed
via wer and rer.
TODO: find a better prefix. Also conditionalize certain constants based
on number of cores and interrupts actually present.
*/
/*
* Copyright (c) 1999-2008 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <xtensa/config/core.h>
#define NUM_INTERRUPTS 27
#define NUM_CORES 4
/* Routing of NMI (BInterrupt2) and interrupts 0..n-1 (BInterrupt3+)
RER reads
WER writes
*/
#define XER_MIROUT 0x0000
#define XER_MIROUT_LAST (XER_MIROUT + NUM_INTERRUPTS)
/* IPI to core M (all 16 causes).
RER reads
WER clears
*/
#define XER_MIPICAUSE 0x0100
#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
#define XER_MIPICAUSE_FIELD_A_LAST 0x0
#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
#define XER_MIPICAUSE_FIELD_B_LAST 0x3
#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
#define XER_MIPICAUSE_FIELD_C_LAST 0x7
#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
#define XER_MIPICAUSE_FIELD_D_LAST 0xF
/* IPI from cause bit 0..15
RER invalid
WER sets
*/
#define XER_MIPISET 0x0140
#define XER_MIPISET_LAST 0x014F
/* Global enable
RER read
WER clear
*/
#define XER_MIENG 0x0180
/* Global enable
RER invalid
WER set
*/
#define XER_MIENG_SET 0x0184
/* Global assert
RER read
WER clear
*/
#define XER_MIASG 0x0188
/* Global enable
RER invalid
WER set
*/
#define XER_MIASG_SET 0x018C
/* IPI partition register
RER read
WER write
*/
#define XER_PART 0x0190
#define XER_IPI0 0x0
#define XER_IPI1 0x1
#define XER_IPI2 0x2
#define XER_IPI3 0x3
#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D) \
(XER_PART_ROUTE_IPI(TO_A, XER_IPI0) | \
XER_PART_ROUTE_IPI(TO_B, XER_IPI1) | \
XER_PART_ROUTE_IPI(TO_C, XER_IPI2) | \
XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
#define XER_IPI_WAKE_CAUSE XER_MIPICAUSE_FIELD_C_FIRST
#define XER_IPI_WAKE_ADDRESS (XER_MIPISET + XER_IPI_WAKE_CAUSE)
#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
/* System configuration ID
RER read
WER invalid
*/
#define XER_SYSCFGID 0x01A0
/* RunStall to slave processors
RER read
WER write
*/
#define XER_MPSCORE 0x0200
/* Cache coherency ON
RER read
WER write
*/
#define XER_CCON 0x0220

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/*******************************************************************************
Copyright (c) 2006-2015 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
******************************************************************************/
/******************************************************************************
Xtensa-specific API for RTOS ports.
******************************************************************************/
#ifndef __XTENSA_API_H__
#define __XTENSA_API_H__
#include <stdbool.h>
#include <xtensa/hal.h>
#include "xtensa_context.h"
/* Typedef for C-callable interrupt handler function */
typedef void (*xt_handler)(void *);
/* Typedef for C-callable exception handler function */
typedef void (*xt_exc_handler)(XtExcFrame *);
/*
-------------------------------------------------------------------------------
Call this function to set a handler for the specified exception. The handler
will be installed on the core that calls this function.
n - Exception number (type)
f - Handler function address, NULL to uninstall handler.
The handler will be passed a pointer to the exception frame, which is created
on the stack of the thread that caused the exception.
If the handler returns, the thread context will be restored and the faulting
instruction will be retried. Any values in the exception frame that are
modified by the handler will be restored as part of the context. For details
of the exception frame structure see xtensa_context.h.
-------------------------------------------------------------------------------
*/
extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
/*
-------------------------------------------------------------------------------
Call this function to set a handler for the specified interrupt. The handler
will be installed on the core that calls this function.
n - Interrupt number.
f - Handler function address, NULL to uninstall handler.
arg - Argument to be passed to handler.
-------------------------------------------------------------------------------
*/
extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
/*
-------------------------------------------------------------------------------
Call this function to enable the specified interrupts on the core that runs
this code.
mask - Bit mask of interrupts to be enabled.
-------------------------------------------------------------------------------
*/
extern void xt_ints_on(unsigned int mask);
/*
-------------------------------------------------------------------------------
Call this function to disable the specified interrupts on the core that runs
this code.
mask - Bit mask of interrupts to be disabled.
-------------------------------------------------------------------------------
*/
extern void xt_ints_off(unsigned int mask);
/*
-------------------------------------------------------------------------------
Call this function to set the specified (s/w) interrupt.
-------------------------------------------------------------------------------
*/
static inline void xt_set_intset(unsigned int arg)
{
xthal_set_intset(arg);
}
/*
-------------------------------------------------------------------------------
Call this function to clear the specified (s/w or edge-triggered)
interrupt.
-------------------------------------------------------------------------------
*/
static inline void xt_set_intclear(unsigned int arg)
{
xthal_set_intclear(arg);
}
/*
-------------------------------------------------------------------------------
Call this function to get handler's argument for the specified interrupt.
n - Interrupt number.
-------------------------------------------------------------------------------
*/
extern void * xt_get_interrupt_handler_arg(int n);
/*
-------------------------------------------------------------------------------
Call this function to check if the specified interrupt is free to use.
intr - Interrupt number.
cpu - cpu number.
-------------------------------------------------------------------------------
*/
bool xt_int_has_handler(int intr, int cpu);
/*
-------------------------------------------------------------------------------
Call this function to disable non iram located interrupts.
newmask - mask containing the interrupts to disable.
-------------------------------------------------------------------------------
*/
static inline uint32_t xt_int_disable_mask(uint32_t newmask)
{
uint32_t oldint;
asm volatile (
"movi %0,0\n"
"xsr %0,INTENABLE\n" //disable all ints first
"rsync\n"
"and a3,%0,%1\n" //mask ints that need disabling
"wsr a3,INTENABLE\n" //write back
"rsync\n"
:"=&r"(oldint):"r"(newmask):"a3");
return oldint;
}
/*
-------------------------------------------------------------------------------
Call this function to enable non iram located interrupts.
newmask - mask containing the interrupts to enable.
-------------------------------------------------------------------------------
*/
static inline void xt_int_enable_mask(uint32_t newmask)
{
asm volatile (
"movi a3,0\n"
"xsr a3,INTENABLE\n"
"rsync\n"
"or a3,a3,%0\n"
"wsr a3,INTENABLE\n"
"rsync\n"
::"r"(newmask):"a3");
}
#endif /* __XTENSA_API_H__ */

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/*******************************************************************************
Copyright (c) 2006-2015 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
--------------------------------------------------------------------------------
XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
This header contains definitions and macros for use primarily by Xtensa
RTOS assembly coded source files. It includes and uses the Xtensa hardware
abstraction layer (HAL) to deal with config specifics. It may also be
included in C source files.
!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
*******************************************************************************/
#ifndef XTENSA_CONTEXT_H
#define XTENSA_CONTEXT_H
#ifdef __ASSEMBLER__
#include <xtensa/coreasm.h>
#endif
#include <xtensa/config/tie.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include <xtensa/xtruntime-frames.h>
/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
/*
-------------------------------------------------------------------------------
Macros that help define structures for both C and assembler.
-------------------------------------------------------------------------------
*/
#ifdef STRUCT_BEGIN
#undef STRUCT_BEGIN
#undef STRUCT_FIELD
#undef STRUCT_AFIELD
#undef STRUCT_END
#endif
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define STRUCT_BEGIN .pushsection .text; .struct 0
#define STRUCT_FIELD(ctype,size,asname,name) asname: .space size
#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space (size)*(n)
#define STRUCT_END(sname) sname##Size:; .popsection
#else
#define STRUCT_BEGIN typedef struct {
#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
#define STRUCT_END(sname) } sname;
#endif //_ASMLANGUAGE || __ASSEMBLER__
/*
-------------------------------------------------------------------------------
INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
A stack frame of this structure is allocated for any interrupt or exception.
It goes on the current stack. If the RTOS has a system stack for handling
interrupts, every thread stack must allow space for just one interrupt stack
frame, then nested interrupt stack frames go on the system stack.
The frame includes basic registers (explicit) and "extra" registers introduced
by user TIE or the use of the MAC16 option in the user's Xtensa config.
The frame size is minimized by omitting regs not applicable to user's config.
For Windowed ABI, this stack frame includes the interruptee's base save area,
another base save area to manage gcc nested functions, and a little temporary
space to help manage the spilling of the register windows.
-------------------------------------------------------------------------------
*/
STRUCT_BEGIN
STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */
STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */
STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */
STRUCT_FIELD (long, 4, XT_STK_A0, a0)
STRUCT_FIELD (long, 4, XT_STK_A1, a1) /* stack pointer before interrupt */
STRUCT_FIELD (long, 4, XT_STK_A2, a2)
STRUCT_FIELD (long, 4, XT_STK_A3, a3)
STRUCT_FIELD (long, 4, XT_STK_A4, a4)
STRUCT_FIELD (long, 4, XT_STK_A5, a5)
STRUCT_FIELD (long, 4, XT_STK_A6, a6)
STRUCT_FIELD (long, 4, XT_STK_A7, a7)
STRUCT_FIELD (long, 4, XT_STK_A8, a8)
STRUCT_FIELD (long, 4, XT_STK_A9, a9)
STRUCT_FIELD (long, 4, XT_STK_A10, a10)
STRUCT_FIELD (long, 4, XT_STK_A11, a11)
STRUCT_FIELD (long, 4, XT_STK_A12, a12)
STRUCT_FIELD (long, 4, XT_STK_A13, a13)
STRUCT_FIELD (long, 4, XT_STK_A14, a14)
STRUCT_FIELD (long, 4, XT_STK_A15, a15)
STRUCT_FIELD (long, 4, XT_STK_SAR, sar)
STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long, 4, XT_STK_LBEG, lbeg)
STRUCT_FIELD (long, 4, XT_STK_LEND, lend)
STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
#endif
#ifndef __XTENSA_CALL0_ABI__
/* Temporary space for saving stuff during window spill */
STRUCT_FIELD (long, 4, XT_STK_TMP0, tmp0)
STRUCT_FIELD (long, 4, XT_STK_TMP1, tmp1)
STRUCT_FIELD (long, 4, XT_STK_TMP2, tmp2)
#endif
#ifdef XT_USE_SWPRI
/* Storage for virtual priority mask */
STRUCT_FIELD (long, 4, XT_STK_VPRI, vpri)
#endif
#ifdef XT_USE_OVLY
/* Storage for overlay state */
STRUCT_FIELD (long, 4, XT_STK_OVLY, ovly)
#endif
STRUCT_END(XtExcFrame)
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define XT_STK_NEXT1 XtExcFrameSize
#else
#define XT_STK_NEXT1 sizeof(XtExcFrame)
#endif
/* Allocate extra storage if needed */
#if XCHAL_EXTRA_SA_SIZE != 0
#if XCHAL_EXTRA_SA_ALIGN <= 16
#define XT_STK_EXTRA ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
#else
/* If need more alignment than stack, add space for dynamic alignment */
#define XT_STK_EXTRA (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
#endif
#define XT_STK_NEXT2 (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
#else
#define XT_STK_NEXT2 XT_STK_NEXT1
#endif
/*
-------------------------------------------------------------------------------
This is the frame size. Add space for 4 registers (interruptee's base save
area) and some space for gcc nested functions if any.
-------------------------------------------------------------------------------
*/
#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
/*
-------------------------------------------------------------------------------
SOLICITED STACK FRAME FOR A THREAD
A stack frame of this structure is allocated whenever a thread enters the
RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
It goes on the current thread's stack.
The solicited frame only includes registers that are required to be preserved
by the callee according to the compiler's ABI conventions, some space to save
the return address for returning to the caller, and the caller's PS register.
For Windowed ABI, this stack frame includes the caller's base save area.
Note on XT_SOL_EXIT field:
It is necessary to distinguish a solicited from an interrupt stack frame.
This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
always at the same offset (0). It can be written with a code (usually 0)
to distinguish a solicted frame from an interrupt frame. An RTOS port may
opt to ignore this field if it has another way of distinguishing frames.
-------------------------------------------------------------------------------
*/
STRUCT_BEGIN
#ifdef __XTENSA_CALL0_ABI__
STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */
STRUCT_FIELD (long, 4, XT_SOL_A13, a13)
STRUCT_FIELD (long, 4, XT_SOL_A14, a14)
STRUCT_FIELD (long, 4, XT_SOL_A15, a15)
#else
STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */
STRUCT_FIELD (long, 4, XT_SOL_A1, a1)
STRUCT_FIELD (long, 4, XT_SOL_A2, a2)
STRUCT_FIELD (long, 4, XT_SOL_A3, a3)
#endif
STRUCT_END(XtSolFrame)
/* Size of solicited stack frame */
#define XT_SOL_FRMSZ ALIGNUP(0x10, XtSolFrameSize)
/*
-------------------------------------------------------------------------------
CO-PROCESSOR STATE SAVE AREA FOR A THREAD
The RTOS must provide an area per thread to save the state of co-processors
when that thread does not have control. Co-processors are context-switched
lazily (on demand) only when a new thread uses a co-processor instruction,
otherwise a thread retains ownership of the co-processor even when it loses
control of the processor. An Xtensa co-processor exception is triggered when
any co-processor instruction is executed by a thread that is not the owner,
and the context switch of that co-processor is then peformed by the handler.
Ownership represents which thread's state is currently in the co-processor.
Co-processors may not be used by interrupt or exception handlers. If an
co-processor instruction is executed by an interrupt or exception handler,
the co-processor exception handler will trigger a kernel panic and freeze.
This restriction is introduced to reduce the overhead of saving and restoring
co-processor state (which can be quite large) and in particular remove that
overhead from interrupt handlers.
The co-processor state save area may be in any convenient per-thread location
such as in the thread control block or above the thread stack area. It need
not be in the interrupt stack frame since interrupts don't use co-processors.
Along with the save area for each co-processor, two bitmasks with flags per
co-processor (laid out as in the CPENABLE reg) help manage context-switching
co-processors as efficiently as possible:
XT_CPENABLE
The contents of a non-running thread's CPENABLE register.
It represents the co-processors owned (and whose state is still needed)
by the thread. When a thread is preempted, its CPENABLE is saved here.
When a thread solicits a context-swtich, its CPENABLE is cleared - the
compiler has saved the (caller-saved) co-proc state if it needs to.
When a non-running thread loses ownership of a CP, its bit is cleared.
When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
Avoids co-processor exceptions when no change of ownership is needed.
XT_CPSTORED
A bitmask with the same layout as CPENABLE, a bit per co-processor.
Indicates whether the state of each co-processor is saved in the state
save area. When a thread enters the kernel, only the state of co-procs
still enabled in CPENABLE is saved. When the co-processor exception
handler assigns ownership of a co-processor to a thread, it restores
the saved state only if this bit is set, and clears this bit.
XT_CP_CS_ST
A bitmask with the same layout as CPENABLE, a bit per co-processor.
Indicates whether callee-saved state is saved in the state save area.
Callee-saved state is saved by itself on a solicited context switch,
and restored when needed by the coprocessor exception handler.
Unsolicited switches will cause the entire coprocessor to be saved
when necessary.
XT_CP_ASA
Pointer to the aligned save area. Allows it to be aligned more than
the overall save area (which might only be stack-aligned or TCB-aligned).
Especially relevant for Xtensa cores configured with a very large data
path that requires alignment greater than 16 bytes (ABI stack alignment).
-------------------------------------------------------------------------------
*/
#if XCHAL_CP_NUM > 0
/* Offsets of each coprocessor save area within the 'aligned save area': */
#define XT_CP0_SA 0
#define XT_CP1_SA ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
#define XT_CP2_SA ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
#define XT_CP3_SA ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
#define XT_CP4_SA ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
#define XT_CP5_SA ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
#define XT_CP6_SA ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
#define XT_CP7_SA ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
#define XT_CP_SA_SIZE ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
/* Offsets within the overall save area: */
#define XT_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */
#define XT_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */
#define XT_CP_CS_ST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */
#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
/* Overall size allows for dynamic alignment: */
#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
#else
#define XT_CP_SIZE 0
#endif
/*
Macro to get the current core ID. Only uses the reg given as an argument.
Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
bit 13: it's 1 on the APP and 0 on the PRO processor.
*/
#ifdef __ASSEMBLER__
.macro getcoreid reg
rsr.prid \reg
extui \reg,\reg,13,1
.endm
#endif
/* Note: These are different to xCoreID used in ESP-IDF FreeRTOS, most places use
0 and 1 which are determined by checking bit 13 (see previous comment)
*/
#define CORE_ID_REGVAL_PRO 0xCDCD
#define CORE_ID_REGVAL_APP 0xABAB
/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */
#define CORE_ID_PRO CORE_ID_REGVAL_PRO
/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */
#define CORE_ID_APP CORE_ID_REGVAL_APP
/*
-------------------------------------------------------------------------------
MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
Convenient where the frame size requirements are the same for both ABIs.
ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
ENTRY0, RET0 are for frameless functions (no locals, no calls).
where size = size of stack frame in bytes (must be >0 and aligned to 16).
For framed functions the frame is created and the return address saved at
base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
For frameless functions, there is no frame and return address remains in a0.
Note: Because CPP macros expand to a single line, macros requiring multi-line
expansions are implemented as assembler macros.
-------------------------------------------------------------------------------
*/
#ifdef __ASSEMBLER__
#ifdef __XTENSA_CALL0_ABI__
/* Call0 */
#define ENTRY(sz) entry1 sz
.macro entry1 size=0x10
addi sp, sp, -\size
s32i a0, sp, 0
.endm
#define ENTRY0
#define RET(sz) ret1 sz
.macro ret1 size=0x10
l32i a0, sp, 0
addi sp, sp, \size
ret
.endm
#define RET0 ret
#else
/* Windowed */
#define ENTRY(sz) entry sp, sz
#define ENTRY0 entry sp, 0x10
#define RET(sz) retw
#define RET0 retw
#endif
#endif
#endif /* XTENSA_CONTEXT_H */

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/* xtruntime-core-state.h - core state save area (used eg. by PSO) */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
/*
* Copyright (c) 2012-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _XTOS_CORE_STATE_H_
#define _XTOS_CORE_STATE_H_
/* Import STRUCT_xxx macros for defining structures: */
#include <xtensa/xtruntime-frames.h>
#include <xtensa/config/core.h>
#include <xtensa/config/tie.h>
#if XCHAL_HAVE_IDMA
#include <xtensa/idma.h>
#endif
//#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only
#define CORE_STATE_SIGNATURE 0xB1C5AFED // pattern that indicates state was saved
/*
* Save area for saving entire core state, such as across Power Shut-Off (PSO).
*/
STRUCT_BEGIN
STRUCT_FIELD (long,4,CS_SA_,signature) // for checking whether state was saved
STRUCT_FIELD (long,4,CS_SA_,restore_label)
STRUCT_FIELD (long,4,CS_SA_,aftersave_label)
STRUCT_AFIELD(long,4,CS_SA_,areg,XCHAL_NUM_AREGS)
#if XCHAL_HAVE_WINDOWED
STRUCT_AFIELD(long,4,CS_SA_,caller_regs,16) // save a max of 16 caller regs
STRUCT_FIELD (long,4,CS_SA_,caller_regs_saved) // flag to show if caller regs saved
#endif
#if XCHAL_HAVE_PSO_CDM
STRUCT_FIELD (long,4,CS_SA_,pwrctl)
#endif
#if XCHAL_HAVE_WINDOWED
STRUCT_FIELD (long,4,CS_SA_,windowbase)
STRUCT_FIELD (long,4,CS_SA_,windowstart)
#endif
STRUCT_FIELD (long,4,CS_SA_,sar)
#if XCHAL_HAVE_EXCEPTIONS
STRUCT_FIELD (long,4,CS_SA_,epc1)
STRUCT_FIELD (long,4,CS_SA_,ps)
STRUCT_FIELD (long,4,CS_SA_,excsave1)
# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
STRUCT_FIELD (long,4,CS_SA_,depc)
# endif
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
STRUCT_AFIELD(long,4,CS_SA_,epc, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
STRUCT_AFIELD(long,4,CS_SA_,eps, XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
STRUCT_AFIELD(long,4,CS_SA_,excsave,XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI - 1)
#endif
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,CS_SA_,lcount)
STRUCT_FIELD (long,4,CS_SA_,lbeg)
STRUCT_FIELD (long,4,CS_SA_,lend)
#endif
#if XCHAL_HAVE_ABSOLUTE_LITERALS
STRUCT_FIELD (long,4,CS_SA_,litbase)
#endif
#if XCHAL_HAVE_VECBASE
STRUCT_FIELD (long,4,CS_SA_,vecbase)
#endif
#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
STRUCT_FIELD (long,4,CS_SA_,atomctl)
#endif
#if XCHAL_HAVE_PREFETCH
STRUCT_FIELD (long,4,CS_SA_,prefctl)
#endif
#if XCHAL_USE_MEMCTL
STRUCT_FIELD (long,4,CS_SA_,memctl)
#endif
#if XCHAL_HAVE_CCOUNT
STRUCT_FIELD (long,4,CS_SA_,ccount)
STRUCT_AFIELD(long,4,CS_SA_,ccompare, XCHAL_NUM_TIMERS)
#endif
#if XCHAL_HAVE_INTERRUPTS
STRUCT_FIELD (long,4,CS_SA_,intenable)
STRUCT_FIELD (long,4,CS_SA_,interrupt)
#endif
#if XCHAL_HAVE_DEBUG
STRUCT_FIELD (long,4,CS_SA_,icount)
STRUCT_FIELD (long,4,CS_SA_,icountlevel)
STRUCT_FIELD (long,4,CS_SA_,debugcause)
// DDR not saved
# if XCHAL_NUM_DBREAK
STRUCT_AFIELD(long,4,CS_SA_,dbreakc, XCHAL_NUM_DBREAK)
STRUCT_AFIELD(long,4,CS_SA_,dbreaka, XCHAL_NUM_DBREAK)
# endif
# if XCHAL_NUM_IBREAK
STRUCT_AFIELD(long,4,CS_SA_,ibreaka, XCHAL_NUM_IBREAK)
STRUCT_FIELD (long,4,CS_SA_,ibreakenable)
# endif
#endif
#if XCHAL_NUM_MISC_REGS
STRUCT_AFIELD(long,4,CS_SA_,misc,XCHAL_NUM_MISC_REGS)
#endif
#if XCHAL_HAVE_MEM_ECC_PARITY
STRUCT_FIELD (long,4,CS_SA_,mepc)
STRUCT_FIELD (long,4,CS_SA_,meps)
STRUCT_FIELD (long,4,CS_SA_,mesave)
STRUCT_FIELD (long,4,CS_SA_,mesr)
STRUCT_FIELD (long,4,CS_SA_,mecr)
STRUCT_FIELD (long,4,CS_SA_,mevaddr)
#endif
/* We put this ahead of TLB and other TIE state,
to keep it within S32I/L32I offset range. */
#if XCHAL_HAVE_CP
STRUCT_FIELD (long,4,CS_SA_,cpenable)
#endif
/* TLB state */
#if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR
STRUCT_AFIELD(long,4,CS_SA_,tlbs,8*2)
#endif
#if XCHAL_HAVE_PTP_MMU
/* Compute number of auto-refill (ARF) entries as max of I and D,
to simplify TLB save logic. On the unusual configs with
ITLB ARF != DTLB ARF entries, we'll just end up
saving/restoring some extra entries redundantly. */
# if XCHAL_DTLB_ARF_ENTRIES_LOG2 + XCHAL_ITLB_ARF_ENTRIES_LOG2 > 4
# define ARF_ENTRIES 8
# else
# define ARF_ENTRIES 4
# endif
STRUCT_FIELD (long,4,CS_SA_,ptevaddr)
STRUCT_FIELD (long,4,CS_SA_,rasid)
STRUCT_FIELD (long,4,CS_SA_,dtlbcfg)
STRUCT_FIELD (long,4,CS_SA_,itlbcfg)
/*** WARNING: past this point, field offsets may be larger than S32I/L32I range ***/
STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2)
# if XCHAL_HAVE_SPANNING_WAY /* MMU v3 */
STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
# endif
#endif
/* MPU state */
#if XCHAL_HAVE_MPU
STRUCT_AFIELD(long,4,CS_SA_,mpuentry,8*XCHAL_MPU_ENTRIES)
STRUCT_FIELD (long,4,CS_SA_,cacheadrdis)
#endif
#if XCHAL_HAVE_IDMA
STRUCT_AFIELD(long,4,CS_SA_,idmaregs, IDMA_PSO_SAVE_SIZE)
#endif
/* TIE state */
/* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN,
because the offsets of all subsequent coprocessor save areas are relative
to the NCP save area. */
STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
#if XCHAL_HAVE_CP
#if XCHAL_CP0_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
#endif
#if XCHAL_CP1_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
#endif
#if XCHAL_CP2_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
#endif
#if XCHAL_CP3_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
#endif
#if XCHAL_CP4_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE)
#endif
#if XCHAL_CP5_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
#endif
#if XCHAL_CP6_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
#endif
#if XCHAL_CP7_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE)
#endif
//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP11_SA_ALIGN,CS_SA_,cp11,XCHAL_CP11_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP12_SA_ALIGN,CS_SA_,cp12,XCHAL_CP12_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP13_SA_ALIGN,CS_SA_,cp13,XCHAL_CP13_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP14_SA_ALIGN,CS_SA_,cp14,XCHAL_CP14_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP15_SA_ALIGN,CS_SA_,cp15,XCHAL_CP15_SA_SIZE)
#endif
STRUCT_END(XtosCoreState)
// These are part of non-coprocessor state (ncp):
#if XCHAL_HAVE_MAC16
//STRUCT_FIELD (long,4,CS_SA_,acclo)
//STRUCT_FIELD (long,4,CS_SA_,acchi)
//STRUCT_AFIELD(long,4,CS_SA_,mr, 4)
#endif
#if XCHAL_HAVE_THREADPTR
//STRUCT_FIELD (long,4,CS_SA_,threadptr)
#endif
#if XCHAL_HAVE_S32C1I
//STRUCT_FIELD (long,4,CS_SA_,scompare1)
#endif
#if XCHAL_HAVE_BOOLEANS
//STRUCT_FIELD (long,4,CS_SA_,br)
#endif
// Not saved:
// EXCCAUSE ??
// DEBUGCAUSE ??
// EXCVADDR ??
// DDR
// INTERRUPT
// ... locked cache lines ...
#endif /* _XTOS_CORE_STATE_H_ */

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/* xtruntime-frames.h - exception stack frames for single-threaded run-time */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
/*
* Copyright (c) 2002-2012 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _XTRUNTIME_FRAMES_H_
#define _XTRUNTIME_FRAMES_H_
#include <xtensa/config/core.h>
/* Macros that help define structures for both C and assembler: */
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
#define STRUCT_BEGIN .pushsection .text; .struct 0
#define STRUCT_FIELD(ctype,size,pre,name) pre##name: .space size
#define STRUCT_AFIELD(ctype,size,pre,name,n) pre##name: .if n ; .space (size)*(n) ; .endif
#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) .balign align ; pre##name: .if n ; .space (size)*(n) ; .endif
#define STRUCT_END(sname) sname##Size:; .popsection
#else /*_ASMLANGUAGE||__ASSEMBLER__*/
#define STRUCT_BEGIN typedef struct {
#define STRUCT_FIELD(ctype,size,pre,name) ctype name;
#define STRUCT_AFIELD(ctype,size,pre,name,n) ctype name[n];
#define STRUCT_AFIELD_A(ctype,size,align,pre,name,n) ctype name[n] __attribute__((aligned(align)));
#define STRUCT_END(sname) } sname;
#endif /*_ASMLANGUAGE||__ASSEMBLER__*/
/*
* Kernel vector mode exception stack frame.
*
* NOTE: due to the limited range of addi used in the current
* kernel exception vector, and the fact that historically
* the vector is limited to 12 bytes, the size of this
* stack frame is limited to 128 bytes (currently at 64).
*/
STRUCT_BEGIN
STRUCT_FIELD (long,4,KEXC_,pc) /* "parm" */
STRUCT_FIELD (long,4,KEXC_,ps)
STRUCT_AFIELD(long,4,KEXC_,areg, 4) /* a12 .. a15 */
STRUCT_FIELD (long,4,KEXC_,sar) /* "save" */
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,KEXC_,lcount)
STRUCT_FIELD (long,4,KEXC_,lbeg)
STRUCT_FIELD (long,4,KEXC_,lend)
#endif
#if XCHAL_HAVE_MAC16
STRUCT_FIELD (long,4,KEXC_,acclo)
STRUCT_FIELD (long,4,KEXC_,acchi)
STRUCT_AFIELD(long,4,KEXC_,mr, 4)
#endif
STRUCT_END(KernelFrame)
/*
* User vector mode exception stack frame:
*
* WARNING: if you modify this structure, you MUST modify the
* computation of the pad size (ALIGNPAD) accordingly.
*/
STRUCT_BEGIN
STRUCT_FIELD (long,4,UEXC_,pc)
STRUCT_FIELD (long,4,UEXC_,ps)
STRUCT_FIELD (long,4,UEXC_,sar)
STRUCT_FIELD (long,4,UEXC_,vpri)
#ifdef __XTENSA_CALL0_ABI__
STRUCT_FIELD (long,4,UEXC_,a0)
#endif
STRUCT_FIELD (long,4,UEXC_,a2)
STRUCT_FIELD (long,4,UEXC_,a3)
STRUCT_FIELD (long,4,UEXC_,a4)
STRUCT_FIELD (long,4,UEXC_,a5)
#ifdef __XTENSA_CALL0_ABI__
STRUCT_FIELD (long,4,UEXC_,a6)
STRUCT_FIELD (long,4,UEXC_,a7)
STRUCT_FIELD (long,4,UEXC_,a8)
STRUCT_FIELD (long,4,UEXC_,a9)
STRUCT_FIELD (long,4,UEXC_,a10)
STRUCT_FIELD (long,4,UEXC_,a11)
STRUCT_FIELD (long,4,UEXC_,a12)
STRUCT_FIELD (long,4,UEXC_,a13)
STRUCT_FIELD (long,4,UEXC_,a14)
STRUCT_FIELD (long,4,UEXC_,a15)
#endif
STRUCT_FIELD (long,4,UEXC_,exccause) /* NOTE: can probably rid of this one (pass direct) */
#if XCHAL_HAVE_LOOPS
STRUCT_FIELD (long,4,UEXC_,lcount)
STRUCT_FIELD (long,4,UEXC_,lbeg)
STRUCT_FIELD (long,4,UEXC_,lend)
#endif
#if XCHAL_HAVE_MAC16
STRUCT_FIELD (long,4,UEXC_,acclo)
STRUCT_FIELD (long,4,UEXC_,acchi)
STRUCT_AFIELD(long,4,UEXC_,mr, 4)
#endif
/* ALIGNPAD is the 16-byte alignment padding. */
#ifdef __XTENSA_CALL0_ABI__
# define CALL0_ABI 1
#else
# define CALL0_ABI 0
#endif
#define ALIGNPAD ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3)
#if ALIGNPAD
STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD) /* 16-byte alignment padding */
#endif
/*STRUCT_AFIELD_A(char,1,XCHAL_CPEXTRA_SA_ALIGN,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE+3)&-4)*/ /* not used */
STRUCT_END(UserFrame)
#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
/* Check for UserFrameSize small enough not to require rounding...: */
/* Skip 16-byte save area, then 32-byte space for 8 regs of call12
* (which overlaps with 16-byte GCC nested func chaining area),
* then exception stack frame: */
.set UserFrameTotalSize, 16+32+UserFrameSize
/* Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes): */
.ifgt UserFrameTotalSize-112
/* Round up to 256-byte multiple to accelerate immediate adds: */
.set UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00)
.endif
# define ESF_TOTALSIZE UserFrameTotalSize
#endif /* _ASMLANGUAGE || __ASSEMBLER__ */
#if XCHAL_NUM_CONTEXTS > 1
/* Structure of info stored on new context's stack for setup: */
STRUCT_BEGIN
STRUCT_FIELD (long,4,INFO_,sp)
STRUCT_FIELD (long,4,INFO_,arg1)
STRUCT_FIELD (long,4,INFO_,funcpc)
STRUCT_FIELD (long,4,INFO_,prevps)
STRUCT_END(SetupInfo)
#endif
#define KERNELSTACKSIZE 1024
#endif /* _XTRUNTIME_FRAMES_H_ */

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/*
* xtruntime.h -- general C definitions for single-threaded run-time
*
* Copyright (c) 2002-2013 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef XTRUNTIME_H
#define XTRUNTIME_H
#include <xtensa/config/core.h>
#include <xtensa/config/specreg.h>
#include <xtensa/xtruntime-core-state.h>
#ifndef XTSTR
#define _XTSTR(x) # x
#define XTSTR(x) _XTSTR(x)
#endif
/* _xtos_core_shutoff() flags parameter values: */
#define XTOS_KEEPON_MEM 0x00000100 /* ==PWRCTL_MEM_WAKEUP */
#define XTOS_KEEPON_MEM_SHIFT 8
#define XTOS_KEEPON_DEBUG 0x00001000 /* ==PWRCTL_DEBUG_WAKEUP */
#define XTOS_KEEPON_DEBUG_SHIFT 12
#define XTOS_IDMA_NO_WAIT 0x00010000 /* Do not wait for idma to finish. Disable if necessary */
#define XTOS_IDMA_WAIT_STANDBY 0x00020000 /* Also treat standby state as the end of wait */
#define XTOS_COREF_PSO 0x00000001 /* do power shutoff */
#define XTOS_COREF_PSO_SHIFT 0
#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */
#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */
#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */
#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
#ifdef __cplusplus
extern "C" {
#endif
#if defined(XTOS_MISRA)
typedef void (_xtos_handler_func)(void *);
#elif defined(__cplusplus)
typedef void (_xtos_handler_func)(...);
#else
typedef void (_xtos_handler_func)(void);
#endif
typedef _xtos_handler_func *_xtos_handler;
/*
* unsigned XTOS_SET_INTLEVEL(int intlevel);
* This macro sets the current interrupt level.
* The 'intlevel' parameter must be a constant.
* This macro returns a 32-bit value that must be passed to
* XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
* XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
* it restores only PS.INTLEVEL rather than the entire PS register
* and thus is slower.
*/
#if !XCHAL_HAVE_INTERRUPTS
# define XTOS_SET_INTLEVEL(intlevel) 0
# define XTOS_SET_MIN_INTLEVEL(intlevel) 0
# define XTOS_RESTORE_INTLEVEL(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
#elif XCHAL_HAVE_XEA2
/* In XEA2, we can simply safely set PS.INTLEVEL directly: */
/* NOTE: these asm macros don't modify memory, but they are marked
* as such to act as memory access barriers to the compiler because
* these macros are sometimes used to delineate critical sections;
* function calls are natural barriers (the compiler does not know
* whether a function modifies memory) unless declared to be inlined. */
# define XTOS_SET_INTLEVEL(intlevel) __extension__({ unsigned __tmp; \
__asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
: "=a" (__tmp) : : "memory" ); \
__tmp;})
# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
__asm__ __volatile__( "rsr.ps %0\n" /* get old (current) PS.INTLEVEL */ \
"movi %2, " XTSTR(intlevel) "\n" \
"extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
"blt %2, %1, 1f\n" \
"rsil %0, " XTSTR(intlevel) "\n" \
"1:\n" \
: "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
__tmp;})
# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
__asm__ __volatile__( "wsr.ps %0 ; rsync\n" \
: : "a" (__tmp) : "memory" ); \
}while(0)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
#else
/* In XEA1, we have to rely on INTENABLE register virtualization: */
extern unsigned _xtos_set_vpri( unsigned vpri );
extern unsigned _xtos_vpri_enabled; /* current virtual priority */
# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval)
#endif
/*
* The following macros build upon the above. They are generally used
* instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
* They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
* or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
* the effective interrupt level to what it was before the macro was invoked.
* In XEA2, the DISABLE macros are much faster than the MASK macros
* (in all configs, DISABLE sets the effective interrupt level, whereas MASK
* makes ensures the effective interrupt level is at least the level given
* without lowering it; in XEA2 with INTENABLE virtualization, these macros
* affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
* MASK semantics).
*
* A typical critical section sequence might be:
* unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
* ... critical section ...
* XTOS_RESTORE_INTLEVEL(rval);
*/
/* Enable all interrupts (those activated with _xtos_ints_on()): */
#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0)
/* Disable low priority level interrupts (they can interact with the OS): */
#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
/* Disable interrupts that can interact with the OS: */
#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */
#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
#endif
/* Disable ALL interrupts (not for common use, particularly if one's processor
* configuration has high-level interrupts and one cares about their latency): */
#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
/* These two are deprecated. Use the newer functions below. */
extern unsigned int _xtos_ints_off( unsigned int mask );
extern unsigned int _xtos_ints_on( unsigned int mask );
/* Newer functions to enable/disable the specified interrupt. */
static inline void _xtos_interrupt_enable(unsigned int intnum)
{
_xtos_ints_on(1U << intnum);
}
static inline void _xtos_interrupt_disable(unsigned int intnum)
{
_xtos_ints_off(1U << intnum);
}
extern unsigned _xtos_set_intlevel( int intlevel );
extern unsigned _xtos_set_min_intlevel( int intlevel );
extern unsigned _xtos_restore_intlevel( unsigned restoreval );
extern unsigned _xtos_restore_just_intlevel( unsigned restoreval );
extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f );
extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f );
extern void _xtos_memep_initrams( void );
extern void _xtos_memep_enable( int flags );
/* For use with the tiny LSP (see LSP reference manual). */
#if XCHAL_NUM_INTLEVELS >= 1
extern void _xtos_dispatch_level1_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 2
extern void _xtos_dispatch_level2_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 3
extern void _xtos_dispatch_level3_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 4
extern void _xtos_dispatch_level4_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 5
extern void _xtos_dispatch_level5_interrupts( void );
#endif
#if XCHAL_NUM_INTLEVELS >= 6
extern void _xtos_dispatch_level6_interrupts( void );
#endif
/* Deprecated (but kept because they were documented): */
extern unsigned int _xtos_read_ints( void );
extern void _xtos_clear_ints( unsigned int mask );
/* Power shut-off related routines. */
extern int _xtos_core_shutoff(unsigned flags);
extern int _xtos_core_save(unsigned flags, XtosCoreState *savearea, void *code);
extern void _xtos_core_restore(unsigned retvalue, XtosCoreState *savearea);
#if XCHAL_NUM_CONTEXTS > 1
extern unsigned _xtos_init_context(int context_num, int stack_size,
_xtos_handler_func *start_func, int arg1);
#endif
/* Deprecated: */
#if XCHAL_NUM_TIMERS > 0
extern void _xtos_timer_0_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 1
extern void _xtos_timer_1_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 2
extern void _xtos_timer_2_delta( int cycles );
#endif
#if XCHAL_NUM_TIMERS > 3
extern void _xtos_timer_3_delta( int cycles );
#endif
#ifdef __cplusplus
}
#endif
#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
#endif /* XTRUNTIME_H */