forked from espressif/arduino-esp32
initial import
This commit is contained in:
me-no-dev
committed by
Ivan Grokhotkov
Ivan Grokhotkov
parent
668acc2c08
commit
5f3a205955
168
tools/sdk/ld/esp32.common.ld
Normal file
168
tools/sdk/ld/esp32.common.ld
Normal file
@ -0,0 +1,168 @@
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/* Default entry point: */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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/* Send .iram0 code to iram */
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.iram0.vectors :
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{
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/* Vectors go to IRAM */
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_init_start = ABSOLUTE(.);
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/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
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. = 0x0;
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KEEP(*(.WindowVectors.text));
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. = 0x180;
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KEEP(*(.Level2InterruptVector.text));
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. = 0x1c0;
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KEEP(*(.Level3InterruptVector.text));
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. = 0x200;
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KEEP(*(.Level4InterruptVector.text));
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. = 0x240;
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KEEP(*(.Level5InterruptVector.text));
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. = 0x280;
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KEEP(*(.DebugExceptionVector.text));
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. = 0x2c0;
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KEEP(*(.NMIExceptionVector.text));
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. = 0x300;
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KEEP(*(.KernelExceptionVector.text));
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. = 0x340;
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KEEP(*(.UserExceptionVector.text));
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. = 0x3C0;
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KEEP(*(.DoubleExceptionVector.text));
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. = 0x400;
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*(.*Vector.literal)
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*(.UserEnter.literal);
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*(.UserEnter.text);
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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_init_end = ABSOLUTE(.);
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} > iram0_0_seg
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.iram0.text :
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{
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/* Code marked as runnning out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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*(.iram1 .iram1.*)
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*libfreertos.a:(.literal .text .literal.* .text.*)
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*libphy.a:(.literal .text .literal.* .text.*)
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*librtc.a:(.literal .text .literal.* .text.*)
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*libpp.a:(.literal .text .literal.* .text.*)
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*libhal.a:(.literal .text .literal.* .text.*)
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_iram_text_end = ABSOLUTE(.);
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} > iram0_0_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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KEEP(*(.bss))
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*(.bss.*)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} >dram0_0_seg
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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KEEP(*(.data))
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KEEP(*(.data.*))
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KEEP(*(.gnu.linkonce.d.*))
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KEEP(*(.data1))
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KEEP(*(.sdata))
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KEEP(*(.sdata.*))
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KEEP(*(.gnu.linkonce.s.*))
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KEEP(*(.sdata2))
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KEEP(*(.sdata2.*))
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KEEP(*(.gnu.linkonce.s2.*))
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KEEP(*(.jcr))
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*(.dram1 .dram1.*)
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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_heap_start = ABSOLUTE(.);
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} >dram0_0_seg
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.flash.rodata :
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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*(.eh_frame)
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. = (. + 3) & ~ 3;
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/* C++ constructor and destructor tables, properly ordered: */
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__init_array_start = ABSOLUTE(.);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >drom0_0_seg
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.flash.text :
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >iram0_2_seg
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.rtc.text :
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{
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. = ALIGN(4);
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*(.rtc.literal .rtc.text)
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} >rtc_iram_seg
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.rtc.data :
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{
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*(.rtc.data)
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*(.rtc.rodata)
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} > rtc_slow_seg
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}
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55
tools/sdk/ld/esp32.ld
Normal file
55
tools/sdk/ld/esp32.ld
Normal file
@ -0,0 +1,55 @@
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/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.common.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
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len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
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len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
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}
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
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20
tools/sdk/ld/esp32.peripherals.ld
Normal file
20
tools/sdk/ld/esp32.peripherals.ld
Normal file
@ -0,0 +1,20 @@
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PROVIDE ( UART0 = 0x3ff40000 );
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PROVIDE ( SPI1 = 0x3ff42000 );
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PROVIDE ( SPI0 = 0x3ff43000 );
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PROVIDE ( GPIO = 0x3ff44000 );
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PROVIDE ( SIGMADELTA = 0x3ff44f00 );
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PROVIDE ( UHCI1 = 0x3ff4C000 );
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PROVIDE ( I2S0 = 0x3ff4F000 );
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PROVIDE ( UART1 = 0x3ff50000 );
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PROVIDE ( I2C0 = 0x3ff53000 );
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PROVIDE ( UHCI0 = 0x3ff54000 );
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PROVIDE ( RMT = 0x3ff56000 );
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PROVIDE ( PCNT = 0x3ff57000 );
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PROVIDE ( LEDC = 0x3ff59000 );
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PROVIDE ( TIMERG0 = 0x3ff5F000 );
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PROVIDE ( TIMERG1 = 0x3ff60000 );
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PROVIDE ( SPI2 = 0x3ff64000 );
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PROVIDE ( SPI3 = 0x3ff65000 );
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PROVIDE ( I2C1 = 0x3ff67000 );
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PROVIDE ( I2S1 = 0x3ff6D000 );
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PROVIDE ( UART2 = 0x3ff6E000 );
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1841
tools/sdk/ld/esp32.rom.ld
Normal file
1841
tools/sdk/ld/esp32.rom.ld
Normal file
File diff suppressed because it is too large
Load Diff
52
tools/sdk/ld/esp32_out.ld
Normal file
52
tools/sdk/ld/esp32_out.ld
Normal file
@ -0,0 +1,52 @@
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/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.common.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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/*
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*
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* Automatically generated file; DO NOT EDIT.
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* Espressif IoT Development Framework Configuration
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*
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*/
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + 0x0,
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len = 0x50000 - 0x0 - 0x0
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + 0,
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len = 0x1000 - 0
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}
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000 - 0x0;
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