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Update IDF and Tools

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This commit is contained in:
me-no-dev
2020-10-13 16:52:16 +03:00
parent 8900e8fca9
commit 659e9a51dd
475 changed files with 4511 additions and 1535 deletions
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1
tools/sdk/esp32s2/include/app_update/include/esp_ota_ops.h
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@ -29,6 +29,7 @@ extern "C"
#endif
#define OTA_SIZE_UNKNOWN 0xffffffff /*!< Used for esp_ota_begin() if new image size is unknown */
#define OTA_WITH_SEQUENTIAL_WRITES 0xfffffffe /*!< Used for esp_ota_begin() if new image size is unknown and erase can be done in incremental manner (assuming write operation is in continuous sequence) */
#define ESP_ERR_OTA_BASE 0x1500 /*!< Base error code for ota_ops api */
#define ESP_ERR_OTA_PARTITION_CONFLICT (ESP_ERR_OTA_BASE + 0x01) /*!< Error if request was to write or erase the current running partition */

8
tools/sdk/esp32s2/include/bootloader_support/include/bootloader_flash_config.h
View File

@ -28,6 +28,14 @@ extern "C" {
*/
void bootloader_flash_update_id(void);
/**
* @brief Update the flash size in g_rom_flashchip (global esp_rom_spiflash_chip_t structure).
*
* @param size The size to store, in bytes.
* @return None
*/
void bootloader_flash_update_size(uint32_t size);
/**
* @brief Set the flash CS setup and hold time.
*

8
tools/sdk/esp32s2/include/bootloader_support/include/esp_image_format.h
View File

@ -169,6 +169,14 @@ esp_err_t esp_image_verify_bootloader(uint32_t *length);
*/
esp_err_t esp_image_verify_bootloader_data(esp_image_metadata_t *data);
/**
* @brief Get the flash size of the image
*
* @param app_flash_size The value configured in the image header
* @return Actual size, in bytes.
*/
int esp_image_get_flash_size(esp_image_flash_size_t app_flash_size);
typedef struct {
uint32_t drom_addr;

41
tools/sdk/esp32s2/include/cmock/CMock/src/cmock.h Normal file
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@ -0,0 +1,41 @@
/* ==========================================
CMock Project - Automatic Mock Generation for C
Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
[Released under MIT License. Please refer to license.txt for details]
========================================== */
#ifndef CMOCK_FRAMEWORK_H
#define CMOCK_FRAMEWORK_H
#include "cmock_internals.h"
#define CMOCK_VERSION_MAJOR 2
#define CMOCK_VERSION_MINOR 5
#define CMOCK_VERSION_BUILD 2
#define CMOCK_VERSION ((CMOCK_VERSION_MAJOR << 16) | (CMOCK_VERSION_MINOR << 8) | CMOCK_VERSION_BUILD)
/* should be big enough to index full range of CMOCK_MEM_MAX */
#ifndef CMOCK_MEM_INDEX_TYPE
#include <stddef.h>
#define CMOCK_MEM_INDEX_TYPE size_t
#endif
#define CMOCK_GUTS_NONE (0)
/*-------------------------------------------------------
* Memory API
*-------------------------------------------------------*/
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNew(CMOCK_MEM_INDEX_TYPE size);
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_MEM_INDEX_TYPE obj_index);
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index);
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index);
void* CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index);
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesCapacity(void);
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesFree(void);
CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesUsed(void);
void CMock_Guts_MemFreeAll(void);
void CMock_Guts_MemFreeFinal(void);
#endif /* end of CMOCK_FRAMEWORK_H */

91
tools/sdk/esp32s2/include/cmock/CMock/src/cmock_internals.h Normal file
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@ -0,0 +1,91 @@
/* ==========================================
CMock Project - Automatic Mock Generation for C
Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
[Released under MIT License. Please refer to license.txt for details]
========================================== */
#ifndef CMOCK_FRAMEWORK_INTERNALS_H
#define CMOCK_FRAMEWORK_INTERNALS_H
#include "unity.h"
/* These are constants that the generated mocks have access to */
extern const char* CMockStringOutOfMemory;
extern const char* CMockStringCalledMore;
extern const char* CMockStringCalledLess;
extern const char* CMockStringCalledEarly;
extern const char* CMockStringCalledLate;
extern const char* CMockStringCallOrder;
extern const char* CMockStringIgnPreExp;
extern const char* CMockStringPtrPreExp;
extern const char* CMockStringPtrIsNULL;
extern const char* CMockStringExpNULL;
extern const char* CMockStringMismatch;
/* define CMOCK_MEM_DYNAMIC to grab memory as needed with malloc
* when you do that, CMOCK_MEM_SIZE is used for incremental size instead of total */
#ifdef CMOCK_MEM_STATIC
#undef CMOCK_MEM_DYNAMIC
#endif
#ifdef CMOCK_MEM_DYNAMIC
#include <stdlib.h>
#endif
/* this is used internally during pointer arithmetic. make sure this type is the same size as the target's pointer type */
#ifndef CMOCK_MEM_PTR_AS_INT
#ifdef UNITY_POINTER_WIDTH
#ifdef UNITY_INT_WIDTH
#if UNITY_POINTER_WIDTH == UNITY_INT_WIDTH
#define CMOCK_MEM_PTR_AS_INT unsigned int
#endif
#endif
#endif
#endif
#ifndef CMOCK_MEM_PTR_AS_INT
#ifdef UNITY_POINTER_WIDTH
#ifdef UNITY_LONG_WIDTH
#if UNITY_POINTER_WIDTH == UNITY_LONG_WIDTH
#define CMOCK_MEM_PTR_AS_INT unsigned long
#endif
#if UNITY_POINTER_WIDTH > UNITY_LONG_WIDTH
#define CMOCK_MEM_PTR_AS_INT unsigned long long
#endif
#endif
#endif
#endif
#ifndef CMOCK_MEM_PTR_AS_INT
#define CMOCK_MEM_PTR_AS_INT unsigned long
#endif
/* 0 for no alignment, 1 for 16-bit, 2 for 32-bit, 3 for 64-bit */
#ifndef CMOCK_MEM_ALIGN
#ifdef UNITY_LONG_WIDTH
#if (UNITY_LONG_WIDTH == 16)
#define CMOCK_MEM_ALIGN (1)
#elif (UNITY_LONG_WIDTH == 32)
#define CMOCK_MEM_ALIGN (2)
#elif (UNITY_LONG_WIDTH == 64)
#define CMOCK_MEM_ALIGN (3)
#else
#define CMOCK_MEM_ALIGN (2)
#endif
#else
#define CMOCK_MEM_ALIGN (2)
#endif
#endif
/* amount of memory to allow cmock to use in its internal heap */
#ifndef CMOCK_MEM_SIZE
#define CMOCK_MEM_SIZE (32768)
#endif
/* automatically calculated defs for easier reading */
#define CMOCK_MEM_ALIGN_SIZE (CMOCK_MEM_INDEX_TYPE)(1u << CMOCK_MEM_ALIGN)
#define CMOCK_MEM_ALIGN_MASK (CMOCK_MEM_INDEX_TYPE)(CMOCK_MEM_ALIGN_SIZE - 1)
#define CMOCK_MEM_INDEX_SIZE (CMOCK_MEM_INDEX_TYPE)(CMOCK_MEM_PTR_AS_INT)((sizeof(CMOCK_MEM_INDEX_TYPE) > CMOCK_MEM_ALIGN_SIZE) ? sizeof(CMOCK_MEM_INDEX_TYPE) : CMOCK_MEM_ALIGN_SIZE)
#endif /* end of CMOCK_FRAMEWORK_INTERNALS_H */

3
tools/sdk/esp32s2/include/config/sdkconfig.h
View File

@ -25,6 +25,7 @@
#define CONFIG_BOOTLOADER_RESERVE_RTC_SIZE 0x10
#define CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE 1
#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
#define CONFIG_ESPTOOLPY_WITH_STUB 1
#define CONFIG_ESPTOOLPY_FLASHMODE_QIO 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
@ -487,5 +488,5 @@
#define CONFIG_TOOLPREFIX CONFIG_SDK_TOOLPREFIX
#define CONFIG_UDP_RECVMBOX_SIZE CONFIG_LWIP_UDP_RECVMBOX_SIZE
#define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
#define CONFIG_ARDUINO_IDF_COMMIT "6c17e3a64"
#define CONFIG_ARDUINO_IDF_COMMIT "8bc19ba89"
#define CONFIG_ARDUINO_IDF_BRANCH "master"

23
tools/sdk/esp32s2/include/driver/esp32s2/include/driver/adc.h
View File

@ -44,29 +44,6 @@ esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config);
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* @brief ADC digital controller initialization.
* @return
* - ESP_OK Success
*/
esp_err_t adc_digi_init(void);
/**
* @brief ADC digital controller deinitialization.
* @return
* - ESP_OK Success
*/
esp_err_t adc_digi_deinit(void);
/**
* @brief Setting the digital controller.
*
* @param config Pointer to digital controller paramter. Refer to `adc_digi_config_t`.
*
* @return
* - ESP_OK Success
*/
esp_err_t adc_digi_controller_config(const adc_digi_config_t *config);
/**
* @brief Enable digital controller to trigger the measurement.

80
tools/sdk/esp32s2/include/driver/esp32s2/include/driver/dac.h Normal file
View File

@ -0,0 +1,80 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "driver/dac_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* @brief DAC digital controller initialization.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_init(void);
/**
* @brief DAC digital controller deinitialization.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_deinit(void);
/**
* @brief Setting the DAC digital controller.
*
* @param cfg Pointer to digital controller paramter. See ``dac_digi_config_t``.
*
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg);
/**
* @brief DAC digital controller start output voltage.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_start(void);
/**
* @brief DAC digital controller stop output voltage.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_stop(void);
/**
* @brief Reset DAC digital controller FIFO.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_fifo_reset(void);
/**
* @brief Reset DAC digital controller.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_reset(void);
#ifdef __cplusplus
}
#endif

186
tools/sdk/esp32s2/include/driver/include/driver/adc_common.h
View File

@ -76,7 +76,7 @@ typedef enum {
/**
* @brief ADC digital controller encode option.
*
* @deprecated The ESP32S2 don't use I2S DMA. Call ``adc_digi_output_format_t`` instead.
* @deprecated The ESP32-S2 doesn't use I2S DMA. Call ``adc_digi_output_format_t`` instead.
*/
typedef enum {
ADC_ENCODE_12BIT, /*!< ADC to DMA data format, , [15:12]-channel [11:0]-12 bits ADC data */
@ -84,6 +84,35 @@ typedef enum {
ADC_ENCODE_MAX,
} adc_i2s_encode_t;
/*---------------------------------------------------------------
Common setting
---------------------------------------------------------------*/
/**
* @brief Enable ADC power
*/
void adc_power_on(void);
/**
* @brief Power off SAR ADC
* This function will force power down for ADC
*/
void adc_power_off(void);
/**
* @brief Initialize ADC pad
* @param adc_unit ADC unit index
* @param channel ADC channel index
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel);
/*---------------------------------------------------------------
RTC controller setting
---------------------------------------------------------------*/
/**
* @brief Get the GPIO number of a specific ADC1 channel.
*
@ -97,45 +126,58 @@ typedef enum {
esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num);
/**
* @brief Set the attenuation of a particular channel on ADC1, and configure its associated GPIO pin mux.
*
* The default ADC full-scale voltage is 1.1 V. To read higher voltages (up to the pin maximum voltage,
* usually 3.3 V) requires setting >0 dB signal attenuation for that ADC channel.
*
* When VDD_A is 3.3 V:
*
* - 0 dB attenuation (ADC_ATTEN_DB_0) gives full-scale voltage 1.1 V
* - 2.5 dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5 V
* - 6 dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2 V
* - 11 dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9 V (see note below)
*
* @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured bit width,
* this value in ESP32 is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.
* this value in ESP32S2 is: 8191 for 13-bits.)
*
* @note At 11 dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
*
* @note For ESP32:
* Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
*
* - 0 dB attenuation (ADC_ATTEN_DB_0) between 100 and 950 mV
* - 2.5 dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250 mV
* - 6 dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750 mV
* - 11 dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450 mV
*
* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
*
* @note For any given channel, this function must be called before the first time ``adc1_get_raw()`` is called for that channel.
*
* @note This function can be called multiple times to configure multiple
* ADC channels simultaneously. ``adc1_get_raw()`` can then be called for any configured channel.
*
* @param channel ADC1 channel to configure
* @param atten Attenuation level
*
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG Parameter error
* @brief Set the attenuation of a particular channel on ADC1, and configure its associated GPIO pin mux.
*
* The default ADC full-scale voltage is 1.1 V. To read higher voltages (up to the pin maximum voltage,
* usually 3.3 V) requires setting >0 dB signal attenuation for that ADC channel.
*
* When the analog voltage supply (VDDA) is 3.3 V:
*
* - 0 dB attenuation (ADC_ATTEN_DB_0) gives full-scale voltage 1.1 V
* - 2.5 dB attenuation (ADC_ATTEN_DB_2_5) gives full-scale voltage 1.5 V
* - 6 dB attenuation (ADC_ATTEN_DB_6) gives full-scale voltage 2.2 V
* - 11 dB attenuation (ADC_ATTEN_DB_11) gives full-scale voltage 3.9 V (see note below)
*
* Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
*
* +----------+------------+--------------------------+
* | SoC | attenuation| suggested range (mV) |
* +==========+============+==========================+
* | | 0 | 100 ~ 950 |
* | +------------+--------------------------+
* | | 2.5 | 100 ~ 1250 |
* | ESP32 +------------+--------------------------+
* | | 6 | 150 ~ 1750 |
* | +------------+--------------------------+
* | | 11 | 150 ~ 2450 |
* +----------+------------+--------------------------+
* | | 0 | 100 ~ 800 |
* | +------------+--------------------------+
* | | 2.5 | 100 ~ 1100 |
* | ESP32-S2 +------------+--------------------------+
* | | 6 | 150 ~ 1350 |
* | +------------+--------------------------+
* | | 11 | 150 ~ 2600 |
* +----------+------------+--------------------------+
*
* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
* @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured bit width,
* this value in ESP32 is 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.
* this value in ESP32-S2 is 8191 for 13-bits.)
*
* @note At 11 dB attenuation the maximum voltage is limited by VDDA, not the full scale voltage.
*
* @note For any given channel, this function must be called before the first time ``adc1_get_raw()`` is called for that channel.
*
* @note This function can be called multiple times to configure multiple
* ADC channels simultaneously. You may call ``adc1_get_raw()`` only after configuring a channel.
*
* @param channel ADC1 channel to configure
* @param atten Attenuation level
*
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten);
@ -173,27 +215,6 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit);
*/
int adc1_get_raw(adc1_channel_t channel);
/**
* @brief Enable ADC power
*/
void adc_power_on(void);
/**
* @brief Power off SAR ADC
* This function will force power down for ADC
*/
void adc_power_off(void);
/**
* @brief Initialize ADC pad
* @param adc_unit ADC unit index
* @param channel ADC channel index
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t adc_gpio_init(adc_unit_t adc_unit, adc_channel_t channel);
/**
* @brief Set ADC data invert
* @param adc_unit ADC unit index
@ -215,10 +236,10 @@ esp_err_t adc_set_clk_div(uint8_t clk_div);
/**
* @brief Configure ADC capture width.
*
* @note For ESP32S2, only support ``ADC_WIDTH_BIT_13``.
* @note ESP32-S2 only supports ``ADC_WIDTH_BIT_13``.
*
* @param adc_unit ADC unit index
* @param width_bit Bit capture width for ADC unit. For ESP32S2, only support ``ADC_WIDTH_BIT_13``.
* @param width_bit Bit capture width for ADC unit. ESP32-S2 only supports ``ADC_WIDTH_BIT_13``.
*
* @return
* - ESP_OK success
@ -256,7 +277,7 @@ esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num);
* The default ADC full-scale voltage is 1.1 V. To read higher voltages (up to the pin maximum voltage,
* usually 3.3 V) requires setting >0 dB signal attenuation for that ADC channel.
*
* When VDD_A is 3.3 V:
* When the analog voltage supply (VDDA) is 3.3 V:
*
* - 0 dB attenuation (ADC_ATTEN_0db) gives full-scale voltage 1.1 V
* - 2.5 dB attenuation (ADC_ATTEN_2_5db) gives full-scale voltage 1.5 V
@ -269,10 +290,10 @@ esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num);
*
* @note The full-scale voltage is the voltage corresponding to a maximum reading
* (depending on ADC2 configured bit width,
* this value of ESP32 is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.
* this value of ESP32S2 is: 8191 for 13-bits.)
* this value for ESP32 is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.
* this value for ESP32-S2 is: 8191 for 13-bits.)
*
* @note At 11 dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
* @note At 11 dB attenuation the maximum voltage is limited by VDDA, not the full scale voltage.
*
* @param channel ADC2 channel to configure
* @param atten Attenuation level
@ -297,12 +318,12 @@ esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
* must be called before the first time this function is called. If Wi-Fi is started via ``esp_wifi_start()``, this
* function will always fail with ``ESP_ERR_TIMEOUT``.
*
* @note ESP32S2:
* @note ESP32-S2:
* ADC2 support hardware arbiter. The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
* the low priority controller will read the invalid ADC2 data. Default priority: Wi-Fi > RTC > Digital;
*
* @param channel ADC2 channel to read
* @param width_bit Bit capture width for ADC2. For ESP32S2, only support ``ADC_WIDTH_BIT_13``.
* @param width_bit Bit capture width for ADC2. ESP32-S2 only supports ``ADC_WIDTH_BIT_13``.
* @param raw_out the variable to hold the output data.
*
* @return
@ -345,6 +366,33 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio);
* - ESP_ERR_INVALID_ARG: Unsupported GPIO
*/
esp_err_t adc2_vref_to_gpio(gpio_num_t gpio) __attribute__((deprecated));
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* @brief ADC digital controller initialization.
* @return
* - ESP_OK Success
*/
esp_err_t adc_digi_init(void);
/**
* @brief ADC digital controller deinitialization.
* @return
* - ESP_OK Success
*/
esp_err_t adc_digi_deinit(void);
/**
* @brief Setting the digital controller.
*
* @param config Pointer to digital controller paramter. Refer to `adc_digi_config_t`.
*
* @return
* - ESP_OK Success
*/
esp_err_t adc_digi_controller_config(const adc_digi_config_t *config);
#ifdef __cplusplus
}

17
tools/sdk/esp32s2/include/driver/include/driver/dac.h → tools/sdk/esp32s2/include/driver/include/driver/dac_common.h
View File

@ -67,22 +67,6 @@ esp_err_t dac_output_enable(dac_channel_t channel);
*/
esp_err_t dac_output_disable(dac_channel_t channel);
/**
* @brief Enable DAC output data from I2S
*
* @return
* - ESP_OK success
*/
esp_err_t dac_i2s_enable(void);
/**
* @brief Disable DAC output data from I2S
*
* @return
* - ESP_OK success
*/
esp_err_t dac_i2s_disable(void);
/**
* @brief Enable cosine wave generator output.
*
@ -105,6 +89,7 @@ esp_err_t dac_cw_generator_disable(void);
* @param cw Configuration.
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG The parameter is NULL.
*/
esp_err_t dac_cw_generator_config(dac_cw_config_t *cw);

6
tools/sdk/esp32s2/include/driver/include/driver/twai.h
View File

@ -166,9 +166,9 @@ esp_err_t twai_driver_uninstall(void);
*
* This function starts the TWAI driver, putting the TWAI driver into the running
* state. This allows the TWAI driver to participate in TWAI bus activities such
* as transmitting/receiving messages. The RX queue is reset in this function,
* clearing any unread messages. This function can only be called when the TWAI
* driver is in the stopped state.
* as transmitting/receiving messages. The TX and RX queue are reset in this function,
* clearing any messages that are unread or pending transmission. This function
* can only be called when the TWAI driver is in the stopped state.
*
* @return
* - ESP_OK: TWAI driver is now running

8
tools/sdk/esp32s2/include/esp_eth/include/esp_eth.h
View File

@ -13,14 +13,14 @@
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_eth_com.h"
#include "esp_eth_mac.h"
#include "esp_eth_phy.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Handle of Ethernet driver
*

8
tools/sdk/esp32s2/include/esp_eth/include/esp_eth_com.h
View File

@ -13,13 +13,13 @@
// limitations under the License.
#pragma once
#include "esp_err.h"
#include "esp_event_base.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_err.h"
#include "esp_event_base.h"
/**
* @brief Maximum Ethernet payload size
*
@ -78,6 +78,7 @@ typedef enum {
ETH_STATE_LINK, /*!< Link status changed */
ETH_STATE_SPEED, /*!< Speed updated */
ETH_STATE_DUPLEX, /*!< Duplex updated */
ETH_STATE_PAUSE, /*!< Pause ability updated */
} esp_eth_state_t;
/**
@ -91,6 +92,7 @@ typedef enum {
ETH_CMD_S_PHY_ADDR, /*!< Set PHY address */
ETH_CMD_G_SPEED, /*!< Get Speed */
ETH_CMD_S_PROMISCUOUS, /*!< Set promiscuous mode */
ETH_CMD_S_FLOW_CTRL, /*!< Set flow control */
} esp_eth_io_cmd_t;
/**

33
tools/sdk/esp32s2/include/esp_eth/include/esp_eth_mac.h
View File

@ -13,10 +13,6 @@
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "esp_eth_com.h"
#include "sdkconfig.h"
@ -24,6 +20,10 @@ extern "C" {
#include "driver/spi_master.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Ethernet MAC
*
@ -252,6 +252,31 @@ struct esp_eth_mac_s {
*/
esp_err_t (*set_promiscuous)(esp_eth_mac_t *mac, bool enable);
/**
* @brief Enable flow control on MAC layer or not
*
* @param[in] mac: Ethernet MAC instance
* @param[in] enable: set true to enable flow control; set false to disable flow control
*
* @return
* - ESP_OK: set flow control successfully
* - ESP_FAIL: set flow control failed because some error occurred
*
*/
esp_err_t (*enable_flow_ctrl)(esp_eth_mac_t *mac, bool enable);
/**
* @brief Set the PAUSE ability of peer node
*
* @param[in] mac: Ethernet MAC instance
* @param[in] ability: zero indicates that pause function is supported by link partner; non-zero indicates that pause function is not supported by link partner
*
* @return
* - ESP_OK: set peer pause ability successfully
* - ESP_FAIL: set peer pause ability failed because some error occurred
*/
esp_err_t (*set_peer_pause_ability)(esp_eth_mac_t *mac, uint32_t ability);
/**
* @brief Free memory of Ethernet MAC
*

4
tools/sdk/esp32s2/include/esp_eth/include/esp_eth_netif_glue.h
View File

@ -13,12 +13,12 @@
// limitations under the License.
#pragma once
#include "esp_eth.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "esp_eth.h"
/**
* @brief Create a netif glue for Ethernet driver
* @note netif glue is used to attach io driver to TCP/IP netif

21
tools/sdk/esp32s2/include/esp_eth/include/esp_eth_phy.h
View File

@ -13,14 +13,14 @@
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "esp_eth_com.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_ETH_PHY_ADDR_AUTO (-1)
/**
@ -160,6 +160,19 @@ struct esp_eth_phy_s {
*/
esp_err_t (*get_addr)(esp_eth_phy_t *phy, uint32_t *addr);
/**
* @brief Advertise pause function supported by MAC layer
*
* @param[in] phy: Ethernet PHY instance
* @param[out] addr: Pause ability
*
* @return
* - ESP_OK: Advertise pause ability successfully
* - ESP_ERR_INVALID_ARG: Advertise pause ability failed because of invalid argument
*
*/
esp_err_t (*advertise_pause_ability)(esp_eth_phy_t *phy, uint32_t ability);
/**
* @brief Free memory of Ethernet PHY instance
*

4
tools/sdk/esp32s2/include/esp_eth/include/eth_phy_regs_struct.h
View File

@ -13,12 +13,12 @@
// limitations under the License.
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/******************Basic PHY Registers*******************/
/**

15
tools/sdk/esp32s2/include/esp_http_client/include/esp_http_client.h
View File

@ -524,6 +524,21 @@ bool esp_http_client_is_complete_data_received(esp_http_client_handle_t client);
int esp_http_client_read_response(esp_http_client_handle_t client, char *buffer, int len);
/**
* @brief Process all remaining response data
* This uses an internal buffer to repeatedly receive, parse, and discard response data until complete data is processed.
* As no additional user-supplied buffer is required, this may be preferrable to `esp_http_client_read_response` in situations where the content of the response may be ignored.
*
* @param[in] client The esp_http_client handle
* @param len Length of data discarded
*
* @return
* - ESP_OK If successful, len will have discarded length
* - ESP_FAIL If failed to read response
* - ESP_ERR_INVALID_ARG If the client is NULL
*/
int esp_http_client_flush_response(esp_http_client_handle_t client, int *len);
/**
* @brief Get URL from client
*

42
tools/sdk/esp32s2/include/esp_http_server/include/esp_http_server.h
View File

@ -406,6 +406,12 @@ typedef struct httpd_uri {
* If this flag is true, then method must be HTTP_GET. Otherwise the handshake will not be handled.
*/
bool is_websocket;
/**
* Flag indicating that control frames (PING, PONG, CLOSE) are also passed to the handler
* This is used if a custom processing of the control frames is needed
*/
bool handle_ws_control_frames;
#endif
} httpd_uri_t;
@ -1466,6 +1472,20 @@ esp_err_t httpd_sess_trigger_close(httpd_handle_t handle, int sockfd);
*/
esp_err_t httpd_sess_update_lru_counter(httpd_handle_t handle, int sockfd);
/**
* @brief Returns list of current socket descriptors of active sessions
*
* @param[in] handle Handle to server returned by httpd_start
* @param[in,out] fds In: Number of fds allocated in the supplied structure client_fds
* Out: Number of valid client fds returned in client_fds,
* @param[out] client_fds Array of client fds
*
* @return
* - ESP_OK : Successfully retrieved session list
* - ESP_ERR_INVALID_ARG : Wrong arguments or list is longer than allocated
*/
esp_err_t httpd_get_client_list(httpd_handle_t handle, size_t *fds, int *client_fds);
/** End of Session
* @}
*/
@ -1526,6 +1546,15 @@ typedef enum {
HTTPD_WS_TYPE_PONG = 0xA
} httpd_ws_type_t;
/**
* @brief Enum for client info description
*/
typedef enum {
HTTPD_WS_CLIENT_INVALID = 0x0,
HTTPD_WS_CLIENT_HTTP = 0x1,
HTTPD_WS_CLIENT_WEBSOCKET = 0x2,
} httpd_ws_client_info_t;
/**
* @brief WebSocket frame format
*/
@ -1586,6 +1615,19 @@ esp_err_t httpd_ws_send_frame(httpd_req_t *req, httpd_ws_frame_t *pkt);
*/
esp_err_t httpd_ws_send_frame_async(httpd_handle_t hd, int fd, httpd_ws_frame_t *frame);
/**
* @brief Checks the supplied socket descriptor if it belongs to any active client
* of this server instance and if the websoket protocol is active
*
* @param[in] hd Server instance data
* @param[in] fd Socket descriptor
* @return
* - HTTPD_WS_CLIENT_INVALID : This fd is not a client of this httpd
* - HTTPD_WS_CLIENT_HTTP : This fd is an active client, protocol is not WS
* - HTTPD_WS_CLIENT_WEBSOCKET : This fd is an active client, protocol is WS
*/
httpd_ws_client_info_t httpd_ws_get_fd_info(httpd_handle_t hd, int fd);
#endif /* CONFIG_HTTPD_WS_SUPPORT */
/** End of WebSocket related stuff
* @}

3
tools/sdk/esp32s2/include/esp_https_ota/include/esp_https_ota.h
View File

@ -22,12 +22,15 @@ extern "C" {
#endif
typedef void *esp_https_ota_handle_t;
typedef esp_err_t(*http_client_init_cb_t)(esp_http_client_handle_t);
/**
* @brief ESP HTTPS OTA configuration
*/
typedef struct {
const esp_http_client_config_t *http_config; /*!< ESP HTTP client configuration */
http_client_init_cb_t http_client_init_cb; /*!< Callback after ESP HTTP client is initialised */
bool bulk_flash_erase; /*!< Erase entire flash partition during initialization. By default flash partition is erased during write operation and in chunk of 4K sector size */
} esp_https_ota_config_t;
#define ESP_ERR_HTTPS_OTA_BASE (0x9000)

49
tools/sdk/esp32s2/include/esp_websocket_client/include/esp_websocket_client.h
View File

@ -40,6 +40,7 @@ typedef enum {
WEBSOCKET_EVENT_CONNECTED, /*!< Once the Websocket has been connected to the server, no data exchange has been performed */
WEBSOCKET_EVENT_DISCONNECTED, /*!< The connection has been disconnected */
WEBSOCKET_EVENT_DATA, /*!< When receiving data from the server, possibly multiple portions of the packet */
WEBSOCKET_EVENT_CLOSED, /*!< The connection has been closed cleanly */
WEBSOCKET_EVENT_MAX
} esp_websocket_event_id_t;
@ -125,7 +126,14 @@ esp_err_t esp_websocket_client_set_uri(esp_websocket_client_handle_t client, con
esp_err_t esp_websocket_client_start(esp_websocket_client_handle_t client);
/**
* @brief Close the WebSocket connection
* @brief Stops the WebSocket connection without websocket closing handshake
*
* This API stops ws client and closes TCP connection directly without sending
* close frames. It is a good practice to close the connection in a clean way
* using esp_websocket_client_close().
*
* Notes:
* - Cannot be called from the websocket event handler
*
* @param[in] client The client
*
@ -139,6 +147,9 @@ esp_err_t esp_websocket_client_stop(esp_websocket_client_handle_t client);
* It is the opposite of the esp_websocket_client_init function and must be called with the same handle as input that a esp_websocket_client_init call returned.
* This might close all connections this handle has used.
*
* Notes:
* - Cannot be called from the websocket event handler
*
* @param[in] client The client
*
* @return esp_err_t
@ -187,6 +198,42 @@ int esp_websocket_client_send_bin(esp_websocket_client_handle_t client, const ch
*/
int esp_websocket_client_send_text(esp_websocket_client_handle_t client, const char *data, int len, TickType_t timeout);
/**
* @brief Close the WebSocket connection in a clean way
*
* Sequence of clean close initiated by client:
* * Client sends CLOSE frame
* * Client waits until server echos the CLOSE frame
* * Client waits until server closes the connection
* * Client is stopped the same way as by the `esp_websocket_client_stop()`
*
* Notes:
* - Cannot be called from the websocket event handler
*
* @param[in] client The client
* @param[in] timeout Timeout in RTOS ticks for waiting
*
* @return esp_err_t
*/
esp_err_t esp_websocket_client_close(esp_websocket_client_handle_t client, TickType_t timeout);
/**
* @brief Close the WebSocket connection in a clean way with custom code/data
* Closing sequence is the same as for esp_websocket_client_close()
*
* Notes:
* - Cannot be called from the websocket event handler
*
* @param[in] client The client
* @param[in] code Close status code as defined in RFC6455 section-7.4
* @param[in] data Additional data to closing message
* @param[in] len The length of the additional data
* @param[in] timeout Timeout in RTOS ticks for waiting
*
* @return esp_err_t
*/
esp_err_t esp_websocket_client_close_with_code(esp_websocket_client_handle_t client, int code, const char *data, int len, TickType_t timeout);
/**
* @brief Check the WebSocket client connection state
*

3
tools/sdk/esp32s2/include/esp_wifi/include/esp_private/wifi.h
View File

@ -53,7 +53,8 @@ typedef struct {
*
*/
typedef enum {
WIFI_LOG_ERROR = 0, /*enabled by default*/
WIFI_LOG_NONE = 0,
WIFI_LOG_ERROR , /*enabled by default*/
WIFI_LOG_WARNING, /*enabled by default*/
WIFI_LOG_INFO, /*enabled by default*/
WIFI_LOG_DEBUG, /*can be set in menuconfig*/

4
tools/sdk/esp32s2/include/esp_wifi/include/esp_wifi_crypto_types.h
View File

@ -336,10 +336,12 @@ typedef int (*esp_omac1_aes_128_t)(const uint8_t *key, const uint8_t *data, size
* @data: Pointer to encrypted data buffer
* @data_len: Encrypted data length in bytes
* @decrypted_len: Length of decrypted data
* @espnow_pkt: Indicates if it's an ESPNOW packet
* Returns: Pointer to decrypted data on success, NULL on failure
*/
typedef uint8_t * (*esp_ccmp_decrypt_t)(const uint8_t *tk, const uint8_t *ieee80211_hdr,
const uint8_t *data, size_t data_len, size_t *decrypted_len);
const uint8_t *data, size_t data_len,
size_t *decrypted_len, bool espnow_pkt);
/**
* @brief Encrypt data using CCMP (Counter Mode CBC-MAC Protocol OR

1
tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_master.h
View File

@ -136,7 +136,6 @@ esp_err_t mbc_master_init(mb_port_type_t port_type, void** handler);
* @brief Initialize Modbus Master controller interface handle
*
* @param[in] handler - pointer to master data structure
* @return None
*/
void mbc_master_init_iface(void* handler);

1
tools/sdk/esp32s2/include/freemodbus/common/include/esp_modbus_slave.h
View File

@ -78,7 +78,6 @@ esp_err_t mbc_slave_init(mb_port_type_t port_type, void** handler);
* @brief Initialize Modbus Slave controller interface handle
*
* @param[in] handler - pointer to slave interface data structure
* @return None
*/
void mbc_slave_init_iface(void* handler);

24
tools/sdk/esp32s2/include/freertos/xtensa/include/freertos/portmacro.h
View File

@ -75,7 +75,7 @@ extern "C" {
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <stdarg.h>
#include <xtensa/hal.h>
#include <xtensa/config/core.h>
#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
@ -321,13 +321,27 @@ static inline void __attribute__((always_inline)) uxPortCompareSet(volatile uint
#define portALT_GET_RUN_TIME_COUNTER_VALUE(x) x = (uint32_t)esp_timer_get_time()
#endif
/* Kernel utilities. */
void vPortYield( void );
void vPortEvaluateYieldFromISR(int argc, ...);
void _frxt_setup_switch( void );
#define portYIELD() vPortYield()
#define portYIELD_FROM_ISR() {traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch();}
/**
* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with,
* or without arguments.
*/
#define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER(0, ##__VA_ARGS__,1,0)
#define portGET_ARGUMENT_COUNT_INNER(zero, one, count, ...) count
_Static_assert(portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments");
_Static_assert(portGET_ARGUMENT_COUNT(1) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument");
#define portYIELD() vPortYield()
/**
* @note The macro below could be used when passing a single argument, or without any argument,
* it was developed to support both usages of portYIELD inside of an ISR. Any other usage form
* might result in undesired behaviour
*/
#define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR(portGET_ARGUMENT_COUNT(__VA_ARGS__), ##__VA_ARGS__)
/* Yielding within an API call (when interrupts are off), means the yield should be delayed
until interrupts are re-enabled.

22
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_hal.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/adc_hal.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for ADC (esp32s2 specific part)
@ -34,23 +34,6 @@ extern "C" {
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* Digital controller initialization.
*/
void adc_hal_digi_init(void);
/**
* Digital controller deinitialization.
*/
void adc_hal_digi_deinit(void);
/**
* Setting the digital controller.
*
* @param cfg Pointer to digital controller paramter.
*/
void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
/**
* ADC Digital controller output data invert or not.
*
@ -83,6 +66,9 @@ void adc_hal_digi_disable(void);
* Enable clock and select clock source for ADC digital controller.
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*
* @note ADC and DAC digital controller share the same frequency divider.
* Please set a reasonable frequency division factor to meet the sampling frequency of the ADC and the output frequency of the DAC.
*
* @param clk Refer to ``adc_digi_clk_t``.
*/
void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/adc_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/adc_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/clk_gate_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/clk_gate_ll.h
View File

@ -274,7 +274,7 @@ static inline void periph_ll_reset(periph_module_t periph)
static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
{
return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) != 0 &&
return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
}

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_hal.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cp_dma_hal.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cp_dma_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cp_dma_ll.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/cpu_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/cpu_ll.h
View File

84
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/dac_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/dac_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
@ -23,15 +23,16 @@
#include <stdlib.h>
#include "soc/dac_periph.h"
#include "hal/dac_types.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------
RTC controller setting
DAC common setting
---------------------------------------------------------------*/
/**
* Power on dac module and start output voltage.
*
@ -59,6 +60,9 @@ static inline void dac_ll_power_down(dac_channel_t channel)
}
}
/*---------------------------------------------------------------
RTC controller setting
---------------------------------------------------------------*/
/**
* Output voltage with value (8 bit).
*
@ -204,23 +208,79 @@ static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
/************************************/
/* DAC DMA API's */
/************************************/
/**
* Enable DAC output data from I2S DMA.
* I2S_CLK connect to DAC_CLK, I2S_DATA_OUT connect to DAC_DATA.
* Enable/disable invert the DAC digital controller clock signal.
*
* @param enable true or false.
*/
static inline void dac_ll_dma_enable(void)
static inline void dac_ll_digi_clk_inv(bool enable)
{
SENS.sar_dac_ctrl1.dac_dig_force = 1;
SENS.sar_dac_ctrl1.dac_clk_inv = 1;
SENS.sar_dac_ctrl1.dac_clk_inv = enable;
}
/**
* Disable DAC output data from I2S DMA.
* Enable/disable DAC-DMA mode for dac digital controller.
*/
static inline void dac_ll_dma_disable(void)
static inline void dac_ll_digi_enable_dma(bool enable)
{
SENS.sar_dac_ctrl1.dac_dig_force = 0;
SENS.sar_dac_ctrl1.dac_clk_inv = 0;
SENS.sar_dac_ctrl1.dac_dig_force = enable;
APB_SARADC.apb_dac_ctrl.apb_dac_trans = enable;
}
/**
* Sets the number of interval clock cycles for the digital controller to trigger the DAC output.
* Expression: `dac_output_freq` = `controller_clk` / interval.
*
* @note The clocks of the DAC digital controller use the ADC digital controller clock divider.
*
* @param cycle The number of clock cycles for the trigger output interval. The unit is the divided clock.
*/
static inline void dac_ll_digi_set_trigger_interval(uint32_t cycle)
{
APB_SARADC.apb_dac_ctrl.dac_timer_target = cycle;
}
/**
* Enable/disable DAC digital controller to trigger the DAC output.
*
* @param enable true or false.
*/
static inline void dac_ll_digi_trigger_output(bool enable)
{
APB_SARADC.apb_dac_ctrl.dac_timer_en = enable;
}
/**
* Set DAC conversion mode for digital controller.
*
* @param mode Conversion mode select. See ``dac_digi_convert_mode_t``.
*/
static inline void dac_ll_digi_set_convert_mode(dac_digi_convert_mode_t mode)
{
if (mode == DAC_CONV_NORMAL) {
APB_SARADC.apb_dac_ctrl.apb_dac_alter_mode = 0;
} else {
APB_SARADC.apb_dac_ctrl.apb_dac_alter_mode = 1;
}
}
/**
* Reset FIFO of DAC digital controller.
*/
static inline void dac_ll_digi_fifo_reset(void)
{
APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 1;
APB_SARADC.apb_dac_ctrl.dac_reset_fifo = 0;
}
/**
* Reset DAC digital controller.
*/
static inline void dac_ll_digi_reset(void)
{
APB_SARADC.apb_dac_ctrl.apb_dac_rst = 1;
APB_SARADC.apb_dac_ctrl.apb_dac_rst = 0;
}
#ifdef __cplusplus

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpio_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpio_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-S2 GPIO register operations

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/gpspi_flash_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/gpspi_flash_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The Lowlevel layer for SPI Flash

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/i2c_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/i2c_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/i2s_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/i2s_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-S2 I2S register operations

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/ledc_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/ledc_ll.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/memprot_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/memprot_ll.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/mpu_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/mpu_ll.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/mwdt_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/mwdt_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/pcnt_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/pcnt_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-S2 PCNT register operations

8
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rmt_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/rmt_ll.h
View File

@ -334,8 +334,12 @@ static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
dev->carrier_duty_ch[channel].high = high_ticks;
dev->carrier_duty_ch[channel].low = low_ticks;
// In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register)
// We take care of the "read-modify-write" procedure by ourselves.
typeof(dev->carrier_duty_ch[0]) reg;
reg.high = high_ticks;
reg.low = low_ticks;
dev->carrier_duty_ch[channel].val = reg.val;
}
static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_cntl_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/rtc_cntl_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rtc_io_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/rtc_io_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/rwdt_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/rwdt_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/sigmadelta_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/sigmadelta_ll.h
View File

@ -14,7 +14,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-S2 SIGMADELTA register operations

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/soc_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/soc_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spi_flash_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spi_flash_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The Lowlevel layer for SPI Flash

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spi_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spi_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-S2 SPI register operations

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/spimem_flash_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/spimem_flash_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The Lowlevel layer for SPI Flash

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/systimer_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/systimer_ll.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/timer_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/timer_ll.h
View File

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_hal.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/touch_sensor_hal.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for touch sensor (esp32s2 specific part)

2
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/touch_sensor_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/touch_sensor_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The Lowlevel layer for Touch Sensor

53
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/twai_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/twai_ll.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The Lowlevel layer for TWAI
@ -33,23 +33,22 @@ extern "C" {
/* ------------------------- Defines and Typedefs --------------------------- */
#define TWAI_LL_STATUS_RBS (0x1 << 0)
#define TWAI_LL_STATUS_DOS (0x1 << 1)
#define TWAI_LL_STATUS_TBS (0x1 << 2)
#define TWAI_LL_STATUS_TCS (0x1 << 3)
#define TWAI_LL_STATUS_RS (0x1 << 4)
#define TWAI_LL_STATUS_TS (0x1 << 5)
#define TWAI_LL_STATUS_ES (0x1 << 6)
#define TWAI_LL_STATUS_BS (0x1 << 7)
//Todo: Add Miss status support
#define TWAI_LL_STATUS_RBS (0x1 << 0) //Receive Buffer Status
#define TWAI_LL_STATUS_DOS (0x1 << 1) //Data Overrun Status
#define TWAI_LL_STATUS_TBS (0x1 << 2) //Transmit Buffer Status
#define TWAI_LL_STATUS_TCS (0x1 << 3) //Transmission Complete Status
#define TWAI_LL_STATUS_RS (0x1 << 4) //Receive Status
#define TWAI_LL_STATUS_TS (0x1 << 5) //Transmit Status
#define TWAI_LL_STATUS_ES (0x1 << 6) //Error Status
#define TWAI_LL_STATUS_BS (0x1 << 7) //Bus Status
#define TWAI_LL_INTR_RI (0x1 << 0)
#define TWAI_LL_INTR_TI (0x1 << 1)
#define TWAI_LL_INTR_EI (0x1 << 2)
#define TWAI_LL_INTR_RI (0x1 << 0) //Receive Interrupt
#define TWAI_LL_INTR_TI (0x1 << 1) //Transmit Interrupt
#define TWAI_LL_INTR_EI (0x1 << 2) //Error Interrupt
//Data overrun interrupt not supported in SW due to HW peculiarities
#define TWAI_LL_INTR_EPI (0x1 << 5)
#define TWAI_LL_INTR_ALI (0x1 << 6)
#define TWAI_LL_INTR_BEI (0x1 << 7)
#define TWAI_LL_INTR_EPI (0x1 << 5) //Error Passive Interrupt
#define TWAI_LL_INTR_ALI (0x1 << 6) //Arbitration Lost Interrupt
#define TWAI_LL_INTR_BEI (0x1 << 7) //Bus Error Interrupt
/*
* The following frame structure has an NEARLY identical bit field layout to
@ -95,14 +94,12 @@ _Static_assert(sizeof(twai_ll_frame_buffer_t) == 13, "TX/RX buffer type should b
* in order to write the majority of configuration registers.
*
* @param hw Start address of the TWAI registers
* @return true if reset mode was entered successfully
*
* @note Reset mode is automatically entered on BUS OFF condition
*/
static inline bool twai_ll_enter_reset_mode(twai_dev_t *hw)
static inline void twai_ll_enter_reset_mode(twai_dev_t *hw)
{
hw->mode_reg.rm = 1;
return hw->mode_reg.rm;
}
/**
@ -113,14 +110,12 @@ static inline bool twai_ll_enter_reset_mode(twai_dev_t *hw)
* operating mode.
*
* @param hw Start address of the TWAI registers
* @return true if reset mode was exit successfully
*
* @note Reset mode must be exit to initiate BUS OFF recovery
*/
static inline bool twai_ll_exit_reset_mode(twai_dev_t *hw)
static inline void twai_ll_exit_reset_mode(twai_dev_t *hw)
{
hw->mode_reg.rm = 0;
return !(hw->mode_reg.rm);
}
/**
@ -135,10 +130,10 @@ static inline bool twai_ll_is_in_reset_mode(twai_dev_t *hw)
/**
* @brief Set operating mode of TWAI controller
*
*
* @param hw Start address of the TWAI registers
* @param mode Operating mode
*
*
* @note Must be called in reset mode
*/
static inline void twai_ll_set_mode(twai_dev_t *hw, twai_mode_t mode)
@ -307,8 +302,6 @@ static inline bool twai_ll_is_last_tx_successful(twai_dev_t *hw)
return hw->status_reg.tcs;
}
//Todo: Add stand alone status bit check functions when necessary
/* -------------------------- Interrupt Register ---------------------------- */
/**
@ -376,7 +369,6 @@ static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t
static inline void twai_ll_clear_arb_lost_cap(twai_dev_t *hw)
{
(void)hw->arbitration_lost_captue_reg.val;
//Todo: Decode ALC register
}
/* ----------------------------- ECC Register ------------------------------- */
@ -391,7 +383,6 @@ static inline void twai_ll_clear_arb_lost_cap(twai_dev_t *hw)
static inline void twai_ll_clear_err_code_cap(twai_dev_t *hw)
{
(void)hw->error_code_capture_reg.val;
//Todo: Decode error code capture
}
/* ----------------------------- EWL Register ------------------------------- */
@ -539,7 +530,7 @@ static inline void twai_ll_get_rx_buffer(twai_dev_t *hw, twai_ll_frame_buffer_t
* This function encodes a message into a frame structure. The frame structure
* has an identical layout to the TX buffer, allowing the frame structure to be
* directly copied into TX buffer.
*
*
* @param[in] 11bit or 29bit ID
* @param[in] dlc Data length code
* @param[in] data Pointer to an 8 byte array containing data. NULL if no data
@ -650,8 +641,8 @@ static inline uint32_t twai_ll_get_rx_msg_count(twai_dev_t *hw)
* @brief Set CLKOUT Divider and enable/disable
*
* Configure CLKOUT. CLKOUT is a pre-scaled version of APB CLK. Divider can be
* 1, or any even number from 2 to 490. Set the divider to 0 to disable CLKOUT.
*
* 1, or any even number from 2 to 490. Set the divider to 0 to disable CLKOUT.
*
* @param hw Start address of the TWAI registers
* @param divider Divider for CLKOUT (any even number from 2 to 490). Set to 0 to disable CLKOUT
*/

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/uart_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/uart_ll.h
View File

0
tools/sdk/esp32s2/include/soc/src/esp32s2/include/hal/usb_ll.h → tools/sdk/esp32s2/include/hal/esp32s2/include/hal/usb_ll.h
View File

16
tools/sdk/esp32s2/include/soc/include/hal/adc_hal.h → tools/sdk/esp32s2/include/hal/include/hal/adc_hal.h
View File

@ -185,6 +185,22 @@ int adc_hal_convert(adc_ll_num_t adc_n, int channel, int *value);
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* Digital controller initialization.
*/
void adc_hal_digi_init(void);
/**
* Digital controller deinitialization.
*/
void adc_hal_digi_deinit(void);
/**
* Setting the digital controller.
*
* @param cfg Pointer to digital controller paramter.
*/
void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.

366
tools/sdk/esp32s2/include/soc/include/hal/adc_types.h → tools/sdk/esp32s2/include/hal/include/hal/adc_types.h
View File

@ -19,9 +19,9 @@
#include "soc/adc_caps.h"
/**
* @brief ADC units selected handle.
* @brief ADC unit enumeration.
*
* @note For ADC digital controller(DMA mode), ESP32 don't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`.
* @note For ADC digital controller (DMA mode), ESP32 doesn't support `ADC_UNIT_2`, `ADC_UNIT_BOTH`, `ADC_UNIT_ALTER`.
*/
typedef enum {
ADC_UNIT_1 = 1, /*!< SAR ADC 1. */
@ -34,7 +34,7 @@ typedef enum {
/**
* @brief ADC channels handle. See ``adc1_channel_t``, ``adc2_channel_t``.
*
* @note For ESP32 ADC1, don't support `ADC_CHANNEL_8`, `ADC_CHANNEL_9`. See ``adc1_channel_t``.
* @note For ESP32 ADC1, don't use `ADC_CHANNEL_8`, `ADC_CHANNEL_9`. See ``adc1_channel_t``.
*/
typedef enum {
ADC_CHANNEL_0 = 0, /*!< ADC channel */
@ -54,18 +54,24 @@ typedef enum {
* @brief ADC attenuation parameter. Different parameters determine the range of the ADC. See ``adc1_config_channel_atten``.
*/
typedef enum {
ADC_ATTEN_DB_0 = 0, /*!<The input voltage of ADC will be reduced to about 1/1 */
ADC_ATTEN_DB_2_5 = 1, /*!<The input voltage of ADC will be reduced to about 1/1.34 */
ADC_ATTEN_DB_6 = 2, /*!<The input voltage of ADC will be reduced to about 1/2 */
ADC_ATTEN_DB_11 = 3, /*!<The input voltage of ADC will be reduced to about 1/3.6*/
ADC_ATTEN_DB_0 = 0, /*!<No input attenumation, ADC can measure up to approx. 800 mV. */
ADC_ATTEN_DB_2_5 = 1, /*!<The input voltage of ADC will be attenuated, extending the range of measurement to up to approx. 1100 mV. */
ADC_ATTEN_DB_6 = 2, /*!<The input voltage of ADC will be attenuated, extending the range of measurement to up to approx. 1350 mV. */
ADC_ATTEN_DB_11 = 3, /*!<The input voltage of ADC will be attenuated, extending the range of measurement to up to approx. 2600 mV. */
ADC_ATTEN_MAX,
} adc_atten_t;
#ifdef CONFIG_IDF_TARGET_ESP32
/**
* @brief ESP32 ADC DMA source selection.
*/
#else
/**
* @brief ESP32 ADC DMA source selection.
*
* @note It's be deprecated in ESP32S2. Beacause ESP32S2 don't use I2S DMA.
* @deprecated Not applicable on ESP32-S2 because ESP32-S2 doesn't use I2S DMA.
*/
#endif
typedef enum {
ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */
@ -75,8 +81,8 @@ typedef enum {
/**
* @brief ADC resolution setting option.
*
* @note For ESP32S2. Only support 13 bit resolution.
* For ESP32. Don't support 13 bit resolution.
* @note For ESP32-S2. Only 13 bit resolution is supported.
* For ESP32. 13 bit resolution is not supported.
*/
typedef enum {
ADC_WIDTH_BIT_9 = 0, /*!< ADC capture width is 9Bit. Only ESP32 is supported. */
@ -84,99 +90,11 @@ typedef enum {
ADC_WIDTH_BIT_11 = 2, /*!< ADC capture width is 11Bit. Only ESP32 is supported. */
ADC_WIDTH_BIT_12 = 3, /*!< ADC capture width is 12Bit. Only ESP32 is supported. */
#if !CONFIG_IDF_TARGET_ESP32
ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32S2 is supported. */
ADC_WIDTH_BIT_13 = 4, /*!< ADC capture width is 13Bit. Only ESP32-S2 is supported. */
#endif
ADC_WIDTH_MAX,
} adc_bits_width_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: In single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: In multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note ESP32S2:
* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val; /*!<Raw data value */
};
} adc_digi_output_data_t;
#if !CONFIG_IDF_TARGET_ESP32
/**
* @brief ADC digital controller (DMA mode) clock system setting.
* Expression: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*/
typedef struct {
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
Note: When a higher frequency clock is used (the division factor is less than 9),
the ADC reading value will be slightly offset. */
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
} adc_digi_clk_t;
/**
* @brief ADC arbiter work mode option.
*
* @note ESP32S2: Only ADC2 support arbiter.
*/
typedef enum {
ADC_ARB_MODE_SHIELD,/*!<Force shield arbiter, Select the highest priority controller to work. */
ADC_ARB_MODE_FIX, /*!<Fixed priority switch controller mode. */
ADC_ARB_MODE_LOOP, /*!<Loop priority switch controller mode. Each controller has the same priority,
and the arbiter will switch to the next controller after the measurement is completed. */
} adc_arbiter_mode_t;
/**
* @brief ADC arbiter work mode and priority setting.
*
* @note ESP32S2: Only ADC2 support arbiter.
*/
typedef struct {
adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */
uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
} adc_arbiter_t;
/**
* @brief ADC arbiter default configuration.
*
* @note ESP32S2: Only ADC2 support arbiter.
*/
#define ADC_ARBITER_CONFIG_DEFAULT() { \
.mode = ADC_ARB_MODE_FIX, \
.rtc_pri = 1, \
.dig_pri = 0, \
.pwdet_pri = 2, \
}
/**
* @brief ADC digital controller (DMA mode) work mode.
*
@ -200,18 +118,176 @@ typedef enum {
typedef struct {
union {
struct {
uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration.
0: input voltage * 1;
1: input voltage * 1/1.34;
2: input voltage * 1/2;
3: input voltage * 1/3.6. */
uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements.
0: measurement range 0 - 800mV,
1: measurement range 0 - 1100mV,
2: measurement range 0 - 1350mV,
3: measurement range 0 - 2600mV. */
#ifdef CONFIG_IDF_TARGET_ESP32
uint8_t bit_width: 2; /*!< ADC resolution.
- 0: 9 bit;
- 1: 10 bit;
- 2: 11 bit;
- 3: 12 bit. */
#elif CONFIG_IDF_TARGET_ESP32S2
uint8_t reserved: 2; /*!< reserved0 */
#endif
uint8_t channel: 4; /*!< ADC channel index. */
};
uint8_t val; /*!< Raw entry value */
uint8_t val;
};
} adc_digi_pattern_table_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
Note: For single convert mode. */
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
Note: For multi or alter convert mode. */
ADC_DIGI_FORMAT_MAX,
} adc_digi_output_format_t;
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*
* @note ESP32-S2:
* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit. `ADC_DIGI_FORMAT_11BIT` */
uint16_t val; /*!<Raw data value */
};
} adc_digi_output_data_t;
#if !CONFIG_IDF_TARGET_ESP32
/**
* @brief ADC digital controller (DMA mode) clock system setting.
* Calculation formula: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
*
* @note: The clocks of the DAC digital controller use the ADC digital controller clock divider.
*/
typedef struct {
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
Note: When a higher frequency clock is used (the division factor is less than 9),
the ADC reading value will be slightly offset. */
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
} adc_digi_clk_t;
#endif //!CONFIG_IDF_TARGET_ESP32
/**
* @brief ADC digital controller (DMA mode) configuration parameters.
*
* Example setting: When using ADC1 channel0 to measure voltage, the sampling rate is required to be 1 kHz:
*
* +---------------------+--------+--------+--------+
* | sample rate | 1 kHz | 1 kHz | 1 kHz |
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* | adc1_pattern_len | 1 | 1 | 1 |
* | dig_clk.use_apll | 0 | 0 | 0 |
* | dig_clk.div_num | 99 | 99 | 99 |
* | dig_clk.div_b | 0 | 0 | 0 |
* | dig_clk.div_a | 0 | 0 | 0 |
* | interval | 400 | 400 | 200 |
* +---------------------+--------+--------+--------+
* | `trigger_meas_freq` | 1 kHz | 1 kHz | 2 kHz |
* +---------------------+--------+--------+--------+
*
* Explanation of the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA outputs:
*
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* +---------------------+--------+--------+--------+
* | trigger meas times | 1 | 1 | 1 |
* +---------------------+--------+--------+--------+
* | conv_limit_num | +1 | +1 | +1 |
* | dma_eof_num | +1 | +2 | +1 |
* | dma output (byte) | +2 | +4 | +2 |
* +---------------------+--------+--------+--------+
*/
typedef struct {
bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
#ifdef CONFIG_IDF_TARGET_ESP32S2
uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
The unit is the divided clock. Range: 40 ~ 4095.
Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t``.
Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */
uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
#endif
} adc_digi_config_t;
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
/**
* @brief ADC arbiter work mode option.
*
* @note ESP32-S2: Only ADC2 support arbiter.
*/
typedef enum {
ADC_ARB_MODE_SHIELD,/*!<Force shield arbiter, Select the highest priority controller to work. */
ADC_ARB_MODE_FIX, /*!<Fixed priority switch controller mode. */
ADC_ARB_MODE_LOOP, /*!<Loop priority switch controller mode. Each controller has the same priority,
and the arbiter will switch to the next controller after the measurement is completed. */
} adc_arbiter_mode_t;
/**
* @brief ADC arbiter work mode and priority setting.
*
* @note ESP32-S2: Only ADC2 support arbiter.
*/
typedef struct {
adc_arbiter_mode_t mode; /*!<Refer to ``adc_arbiter_mode_t``. Note: only support ADC2. */
uint8_t rtc_pri; /*!<RTC controller priority. Range: 0 ~ 2. */
uint8_t dig_pri; /*!<Digital controller priority. Range: 0 ~ 2. */
uint8_t pwdet_pri; /*!<Wi-Fi controller priority. Range: 0 ~ 2. */
} adc_arbiter_t;
/**
* @brief ADC arbiter default configuration.
*
* @note ESP32S2: Only ADC2 supports (needs) an arbiter.
*/
#define ADC_ARBITER_CONFIG_DEFAULT() { \
.mode = ADC_ARB_MODE_FIX, \
.rtc_pri = 1, \
.dig_pri = 0, \
.pwdet_pri = 2, \
}
/**
* @brief ADC digital controller (DMA mode) interrupt type options.
*/
@ -221,68 +297,16 @@ typedef enum {
ADC_DIGI_INTR_MASK_ALL = 0x3,
} adc_digi_intr_t;
/**
* @brief ADC digital controller (DMA mode) configuration parameters.
*
* Example setting: Use ADC1 channel0 to measure voltage, the sampling rate is required to be 1KHz:
* +---------------------+--------+--------+--------+
* | sample rate | 1KHz | 1KHz | 1KHz |
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* | adc1_pattern_len | 1 | 1 | 1 |
* | dig_clk.use_apll | 0 | 0 | 0 |
* | dig_clk.div_num | 99 | 99 | 99 |
* | dig_clk.div_b | 0 | 0 | 0 |
* | dig_clk.div_a | 0 | 0 | 0 |
* | interval | 400 | 400 | 200 |
* +---------------------+--------+--------+--------+
* | `trigger_meas_freq` | 1KHz | 1KHz | 2KHz |
* +---------------------+--------+--------+--------+
*
* Explain the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA output:
* +---------------------+--------+--------+--------+
* | conv_mode | single | both | alter |
* +---------------------+--------+--------+--------+
* | trigger meas times | 1 | 1 | 1 |
* +---------------------+--------+--------+--------+
* | conv_limit_num | +1 | +1 | +1 |
* | dma_eof_num | +1 | +2 | +1 |
* | dma output (byte) | +2 | +4 | +2 |
* +---------------------+--------+--------+--------+
*/
typedef struct {
bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to ``adc1_pattern`` */
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
The unit is the divided clock. Range: 40 ~ 4095.
Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t`` */
uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
} adc_digi_config_t;
/**
* @brief ADC digital controller (DMA mode) filter index options.
*
* @note For ESP32S2, The filter object of the ADC is fixed.
* @note For ESP32-S2, The filter object of the ADC is fixed.
*/
typedef enum {
ADC_DIGI_FILTER_IDX0 = 0, /*!<The filter index 0.
For ESP32S2, It can only be used to filter all enabled channels of ADC1 unit at the same time. */
For ESP32-S2, It can only be used to filter all enabled channels of ADC1 unit at the same time. */
ADC_DIGI_FILTER_IDX1, /*!<The filter index 1.
For ESP32S2, It can only be used to filter all enabled channels of ADC2 unit at the same time. */
For ESP32-S2, It can only be used to filter all enabled channels of ADC2 unit at the same time. */
ADC_DIGI_FILTER_IDX_MAX
} adc_digi_filter_idx_t;
@ -302,27 +326,27 @@ typedef enum {
/**
* @brief ADC digital controller (DMA mode) filter configuration.
*
* @note For ESP32S2, The filter object of the ADC is fixed.
* @note For ESP32S2, The filter object is always all enabled channels.
* @note For ESP32-S2, The filter object of the ADC is fixed.
* @note For ESP32-S2, The filter object is always all enabled channels.
*/
typedef struct {
adc_unit_t adc_unit; /*!<Set adc unit number for filter.
For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. */
For ESP32-S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time. */
adc_channel_t channel; /*!<Set adc channel number for filter.
For ESP32S2, it's always `ADC_CHANNEL_MAX` */
For ESP32-S2, it's always `ADC_CHANNEL_MAX` */
adc_digi_filter_mode_t mode;/*!<Set adc filter mode for filter. See ``adc_digi_filter_mode_t``. */
} adc_digi_filter_t;
/**
* @brief ADC digital controller (DMA mode) monitor index options.
*
* @note For ESP32S2, The monitor object of the ADC is fixed.
* @note For ESP32-S2, The monitor object of the ADC is fixed.
*/
typedef enum {
ADC_DIGI_MONITOR_IDX0 = 0, /*!<The monitor index 0.
For ESP32S2, It can only be used to monitor all enabled channels of ADC1 unit at the same time. */
For ESP32-S2, It can only be used to monitor all enabled channels of ADC1 unit at the same time. */
ADC_DIGI_MONITOR_IDX1, /*!<The monitor index 1.
For ESP32S2, It can only be used to monitor all enabled channels of ADC2 unit at the same time. */
For ESP32-S2, It can only be used to monitor all enabled channels of ADC2 unit at the same time. */
ADC_DIGI_MONITOR_IDX_MAX
} adc_digi_monitor_idx_t;
@ -340,14 +364,14 @@ typedef enum {
/**
* @brief ADC digital controller (DMA mode) monitor configuration.
*
* @note For ESP32S2, The monitor object of the ADC is fixed.
* @note For ESP32S2, The monitor object is always all enabled channels.
* @note For ESP32-S2, The monitor object of the ADC is fixed.
* @note For ESP32-S2, The monitor object is always all enabled channels.
*/
typedef struct {
adc_unit_t adc_unit; /*!<Set adc unit number for monitor.
For ESP32S2, monitor IDX0/IDX1 can only be used to monitor all enabled channels of ADC1/ADC2 unit at the same time. */
For ESP32-S2, monitor IDX0/IDX1 can only be used to monitor all enabled channels of ADC1/ADC2 unit at the same time. */
adc_channel_t channel; /*!<Set adc channel number for monitor.
For ESP32S2, it's always `ADC_CHANNEL_MAX` */
For ESP32-S2, it's always `ADC_CHANNEL_MAX` */
adc_digi_monitor_mode_t mode; /*!<Set adc monitor mode. See ``adc_digi_monitor_mode_t``. */
uint32_t threshold; /*!<Set monitor threshold of adc digital controller. */
} adc_digi_monitor_t;

2
tools/sdk/esp32s2/include/soc/include/hal/brownout_hal.h → tools/sdk/esp32s2/include/hal/include/hal/brownout_hal.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once

0
tools/sdk/esp32s2/include/soc/include/hal/cpu_hal.h → tools/sdk/esp32s2/include/hal/include/hal/cpu_hal.h
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0
tools/sdk/esp32s2/include/soc/include/hal/cpu_types.h → tools/sdk/esp32s2/include/hal/include/hal/cpu_types.h
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11
tools/sdk/esp32s2/include/soc/include/hal/dac_hal.h → tools/sdk/esp32s2/include/hal/include/hal/dac_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
@ -75,11 +75,6 @@
void dac_hal_cw_generator_config(dac_cw_config_t *cw);
/**
* Enable DAC output data from DMA.
* Enable/disable DAC output data from DMA.
*/
#define dac_hal_dma_enable() dac_ll_dma_enable()
/**
* Disable DAC output data from DMA.
*/
#define dac_hal_dma_disable() dac_ll_dma_disable()
#define dac_hal_digi_enable_dma(enable) dac_ll_digi_enable_dma(enable)

29
tools/sdk/esp32s2/include/soc/include/hal/dac_types.h → tools/sdk/esp32s2/include/hal/include/hal/dac_types.h
View File

@ -1,6 +1,7 @@
#pragma once
#include "soc/dac_caps.h"
#include "hal/adc_types.h"
#include "sdkconfig.h"
typedef enum {
@ -37,4 +38,30 @@ typedef struct {
uint32_t freq; /*!< Set frequency of cosine wave generator output. Range: 130(130Hz) ~ 55000(100KHz). */
int8_t offset; /*!< Set the voltage value of the DC component of the cosine wave generator output.
Note: Unreasonable settings can cause waveform to be oversaturated. Range: -128 ~ 127. */
} dac_cw_config_t;
} dac_cw_config_t;
#ifdef CONFIG_IDF_TARGET_ESP32S2
/**
* @brief DAC digital controller (DMA mode) work mode.
*/
typedef enum {
DAC_CONV_NORMAL, /*!< The data in the DMA buffer is simultaneously output to the enable channel of the DAC. */
DAC_CONV_ALTER, /*!< The data in the DMA buffer is alternately output to the enable channel of the DAC. */
DAC_CONV_MAX
} dac_digi_convert_mode_t;
/**
* @brief DAC digital controller (DMA mode) configuration parameters.
*/
typedef struct {
dac_digi_convert_mode_t mode; /*!<DAC digital controller (DMA mode) work mode. See ``dac_digi_convert_mode_t``. */
uint32_t interval; /*!<The number of interval clock cycles for the DAC digital controller to output voltage.
The unit is the divided clock. Range: 1 ~ 4095.
Expression: `dac_output_freq` = `controller_clk` / interval. Refer to ``adc_digi_clk_t``.
Note: The sampling rate of each channel is also related to the conversion mode (See ``dac_digi_convert_mode_t``) and pattern table settings. */
adc_digi_clk_t dig_clk; /*!<DAC digital controller clock divider settings. Refer to ``adc_digi_clk_t``.
Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */
} dac_digi_config_t;
#endif //CONFIG_IDF_TARGET_ESP32S2

0
tools/sdk/esp32s2/include/soc/include/hal/esp_flash_err.h → tools/sdk/esp32s2/include/hal/include/hal/esp_flash_err.h
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14
tools/sdk/esp32s2/include/soc/include/hal/gpio_hal.h → tools/sdk/esp32s2/include/hal/include/hal/gpio_hal.h
View File

@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for GPIO
@ -321,17 +321,17 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
#if GPIO_SUPPORTS_FORCE_HOLD
/**
* @brief Force hold digital and rtc gpio pad.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*
* @brief Force hold digital and rtc gpio pad.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*
* @param hal Context of the HAL layer
* */
#define gpio_hal_force_hold_all(hal) gpio_ll_force_hold_all((hal)->dev)
/**
* @brief Force unhold digital and rtc gpio pad.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*
* @brief Force unhold digital and rtc gpio pad.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*
* @param hal Context of the HAL layer
* */
#define gpio_hal_force_unhold_all(hal) gpio_ll_force_unhold_all((hal)->dev)

0
tools/sdk/esp32s2/include/soc/include/hal/gpio_types.h → tools/sdk/esp32s2/include/hal/include/hal/gpio_types.h
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0
tools/sdk/esp32s2/include/soc/include/hal/hal_defs.h → tools/sdk/esp32s2/include/hal/include/hal/hal_defs.h
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20
tools/sdk/esp32s2/include/soc/include/hal/i2c_hal.h → tools/sdk/esp32s2/include/hal/include/hal/i2c_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for I2C
@ -75,7 +75,7 @@ typedef struct {
#define i2c_hal_trans_start(hal) i2c_ll_trans_start((hal)->dev)
/**
* @brief Enable I2C master RX interrupt
* @brief Enable I2C master RX interrupt
*
* @param hal Context of the HAL layer
*
@ -84,7 +84,7 @@ typedef struct {
#define i2c_hal_enable_master_rx_it(hal) i2c_ll_master_enable_rx_it((hal)->dev)
/**
* @brief Enable I2C master TX interrupt
* @brief Enable I2C master TX interrupt
*
* @param hal Context of the HAL layer
*
@ -458,7 +458,7 @@ void i2c_hal_master_fsm_rst(i2c_hal_context_t *hal);
void i2c_hal_master_clr_bus(i2c_hal_context_t *hal);
/**
* @brief Enable I2C slave TX interrupt
* @brief Enable I2C slave TX interrupt
*
* @param hal Context of the HAL layer
*
@ -467,7 +467,7 @@ void i2c_hal_master_clr_bus(i2c_hal_context_t *hal);
void i2c_hal_enable_slave_tx_it(i2c_hal_context_t *hal);
/**
* @brief Disable I2C slave TX interrupt
* @brief Disable I2C slave TX interrupt
*
* @param hal Context of the HAL layer
*
@ -476,7 +476,7 @@ void i2c_hal_enable_slave_tx_it(i2c_hal_context_t *hal);
void i2c_hal_disable_slave_tx_it(i2c_hal_context_t *hal);
/**
* @brief Enable I2C slave RX interrupt
* @brief Enable I2C slave RX interrupt
*
* @param hal Context of the HAL layer
*
@ -485,7 +485,7 @@ void i2c_hal_disable_slave_tx_it(i2c_hal_context_t *hal);
void i2c_hal_enable_slave_rx_it(i2c_hal_context_t *hal);
/**
* @brief Disable I2C slave RX interrupt
* @brief Disable I2C slave RX interrupt
*
* @param hal Context of the HAL layer
*
@ -494,7 +494,7 @@ void i2c_hal_enable_slave_rx_it(i2c_hal_context_t *hal);
void i2c_hal_disable_slave_rx_it(i2c_hal_context_t *hal);
/**
* @brief I2C master handle tx interrupt event
* @brief I2C master handle tx interrupt event
*
* @param hal Context of the HAL layer
* @param event Pointer to accept the interrupt event
@ -504,7 +504,7 @@ void i2c_hal_disable_slave_rx_it(i2c_hal_context_t *hal);
void i2c_hal_master_handle_tx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event);
/**
* @brief I2C master handle rx interrupt event
* @brief I2C master handle rx interrupt event
*
* @param hal Context of the HAL layer
* @param event Pointer to accept the interrupt event
@ -514,7 +514,7 @@ void i2c_hal_master_handle_tx_event(i2c_hal_context_t *hal, i2c_intr_event_t *ev
void i2c_hal_master_handle_rx_event(i2c_hal_context_t *hal, i2c_intr_event_t *event);
/**
* @brief I2C slave handle interrupt event
* @brief I2C slave handle interrupt event
*
* @param hal Context of the HAL layer
* @param event Pointer to accept the interrupt event

0
tools/sdk/esp32s2/include/soc/include/hal/i2c_types.h → tools/sdk/esp32s2/include/hal/include/hal/i2c_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/i2s_hal.h → tools/sdk/esp32s2/include/hal/include/hal/i2s_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for I2S.

0
tools/sdk/esp32s2/include/soc/include/hal/i2s_types.h → tools/sdk/esp32s2/include/hal/include/hal/i2s_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/ledc_hal.h → tools/sdk/esp32s2/include/hal/include/hal/ledc_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for LEDC.

0
tools/sdk/esp32s2/include/soc/include/hal/ledc_types.h → tools/sdk/esp32s2/include/hal/include/hal/ledc_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/mcpwm_hal.h → tools/sdk/esp32s2/include/hal/include/hal/mcpwm_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for MCPWM (common part)

0
tools/sdk/esp32s2/include/soc/include/hal/mcpwm_types.h → tools/sdk/esp32s2/include/hal/include/hal/mcpwm_types.h
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0
tools/sdk/esp32s2/include/soc/include/hal/mpu_hal.h → tools/sdk/esp32s2/include/hal/include/hal/mpu_hal.h
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0
tools/sdk/esp32s2/include/soc/include/hal/mpu_types.h → tools/sdk/esp32s2/include/hal/include/hal/mpu_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/pcnt_hal.h → tools/sdk/esp32s2/include/hal/include/hal/pcnt_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for PCNT.

0
tools/sdk/esp32s2/include/soc/include/hal/pcnt_types.h → tools/sdk/esp32s2/include/hal/include/hal/pcnt_types.h
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0
tools/sdk/esp32s2/include/soc/include/hal/rmt_hal.h → tools/sdk/esp32s2/include/hal/include/hal/rmt_hal.h
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0
tools/sdk/esp32s2/include/soc/include/hal/rmt_types.h → tools/sdk/esp32s2/include/hal/include/hal/rmt_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/rtc_io_hal.h → tools/sdk/esp32s2/include/hal/include/hal/rtc_io_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for RTC IO master (common part)

0
tools/sdk/esp32s2/include/soc/include/hal/rtc_io_types.h → tools/sdk/esp32s2/include/hal/include/hal/rtc_io_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/sdio_slave_hal.h → tools/sdk/esp32s2/include/hal/include/hal/sdio_slave_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for SDIO slave (common part)

2
tools/sdk/esp32s2/include/soc/include/hal/sdio_slave_ll.h → tools/sdk/esp32s2/include/hal/include/hal/sdio_slave_ll.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32 SDIO slave register operations

0
tools/sdk/esp32s2/include/soc/include/hal/sdio_slave_types.h → tools/sdk/esp32s2/include/hal/include/hal/sdio_slave_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/sigmadelta_hal.h → tools/sdk/esp32s2/include/hal/include/hal/sigmadelta_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for SIGMADELTA.

0
tools/sdk/esp32s2/include/soc/include/hal/sigmadelta_types.h → tools/sdk/esp32s2/include/hal/include/hal/sigmadelta_types.h
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0
tools/sdk/esp32s2/include/soc/include/hal/soc_hal.h → tools/sdk/esp32s2/include/hal/include/hal/soc_hal.h
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2
tools/sdk/esp32s2/include/soc/include/hal/spi_flash_hal.h → tools/sdk/esp32s2/include/hal/include/hal/spi_flash_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The HAL is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI Flash (common part)

0
tools/sdk/esp32s2/include/soc/include/hal/spi_flash_types.h → tools/sdk/esp32s2/include/hal/include/hal/spi_flash_types.h
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6
tools/sdk/esp32s2/include/soc/include/hal/spi_hal.h → tools/sdk/esp32s2/include/hal/include/hal/spi_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI master (common part)
@ -169,7 +169,7 @@ void spi_hal_fetch_result(const spi_hal_context_t *hal);
* Utils
* ---------------------------------------------------------*/
/**
* Get the configuration of clock and timing. The configuration will be used when ``spi_hal_setup_device``.
* Calculate the configuration of clock and timing. The configuration will be used when ``spi_hal_setup_device``.
*
* It is highly suggested to do this at initialization, since it takes long time.
*
@ -185,7 +185,7 @@ void spi_hal_fetch_result(const spi_hal_context_t *hal);
*
* @return ESP_OK if desired is available, otherwise fail.
*/
esp_err_t spi_hal_get_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf);
esp_err_t spi_hal_cal_clock_conf(const spi_hal_context_t *hal, int speed_hz, int duty_cycle, bool use_gpio, int input_delay_ns, int *out_freq, spi_hal_timing_conf_t *timing_conf);
/**
* Get the frequency actual used.

2
tools/sdk/esp32s2/include/soc/include/hal/spi_slave_hal.h → tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for SPI slave (common part)

2
tools/sdk/esp32s2/include/soc/include/hal/spi_slave_hd_hal.h → tools/sdk/esp32s2/include/hal/include/hal/spi_slave_hd_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
/*

0
tools/sdk/esp32s2/include/soc/include/hal/spi_types.h → tools/sdk/esp32s2/include/hal/include/hal/spi_types.h
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0
tools/sdk/esp32s2/include/soc/include/hal/systimer_hal.h → tools/sdk/esp32s2/include/hal/include/hal/systimer_hal.h
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0
tools/sdk/esp32s2/include/soc/include/hal/systimer_types.h → tools/sdk/esp32s2/include/hal/include/hal/systimer_types.h
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2
tools/sdk/esp32s2/include/soc/include/hal/timer_hal.h → tools/sdk/esp32s2/include/hal/include/hal/timer_hal.h
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@ -15,7 +15,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in soc/include/hal/readme.md
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for Timer Group.

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