forked from espressif/arduino-esp32
Update IDF to f586f5e (#1296)
* Update BLE lib * Update IDF to f586f5e * Restructure Bluetooth Serial includes * Update esptool and gen_esp32part * Add partition scheme selection for menuconfig * Add partition scheme selection for Arduino IDE * Fix BLE example * Second attempt BLE fix * Add exceptions to PIO
This commit is contained in:
Me No Dev
GitHub
@ -147,11 +147,15 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit);
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esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit);
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/**
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* @brief Configure the ADC1 channel, including setting attenuation.
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* @brief Set the attenuation of a particular channel on ADC1, and configure its
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* associated GPIO pin mux.
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*
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* @note This function also configures the input GPIO pin mux to
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* connect it to the ADC1 channel. It must be called before calling
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* adc1_get_raw() for this channel.
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* @note For any given channel, this function must be called before the first time
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* adc1_get_raw() is called for that channel.
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*
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* @note This function can be called multiple times to configure multiple
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* ADC channels simultaneously. adc1_get_raw() can then be called for any configured
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* channel.
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*
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* The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
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* usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
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@ -168,6 +172,15 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit);
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*
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* @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
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*
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* Due to ADC characteristics, most accurate results are obtained within the following approximate voltage ranges:
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*
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* - 0dB attenuaton (ADC_ATTEN_DB_0) between 100 and 950mV
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* - 2.5dB attenuation (ADC_ATTEN_DB_2_5) between 100 and 1250mV
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* - 6dB attenuation (ADC_ATTEN_DB_6) between 150 to 1750mV
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* - 11dB attenuation (ADC_ATTEN_DB_11) between 150 to 2450mV
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*
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* For maximum accuracy, use the ADC calibration APIs and measure voltages within these recommended ranges.
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*
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* @param channel ADC1 channel to configure
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* @param atten Attenuation level
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*
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@ -178,13 +191,14 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit);
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esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten);
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/**
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* @brief Take an ADC1 reading on a single channel
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* @brief Take an ADC1 reading from a single channel.
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*
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* @note Call adc1_config_width() before the first time this
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* function is called.
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*
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* @note For a given channel, adc1_config_channel_atten(channel)
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* must be called before the first time this function is called.
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* @note For any given channel, adc1_config_channel_atten(channel)
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* must be called before the first time this function is called. Configuring
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* a new channel does not prevent a previously configured channel from being read.
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*
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* @param channel ADC1 channel to read
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*
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@ -204,12 +218,13 @@ int adc1_get_voltage(adc1_channel_t channel) __attribute__((deprecated));
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/** @endcond */
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/**
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* @brief Power on SAR ADC
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* @brief Enable ADC power
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*/
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void adc_power_on();
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/**
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* @brief Power off SAR ADC
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* This function will force power down for ADC
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*/
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void adc_power_off();
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@ -73,41 +73,41 @@ extern "C" {
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#define GPIO_SEL_38 ((uint64_t)(((uint64_t)1)<<38)) /*!< Pin 38 selected */
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#define GPIO_SEL_39 ((uint64_t)(((uint64_t)1)<<39)) /*!< Pin 39 selected */
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#define GPIO_PIN_REG_0 PERIPHS_IO_MUX_GPIO0_U
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#define GPIO_PIN_REG_1 PERIPHS_IO_MUX_U0TXD_U
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#define GPIO_PIN_REG_2 PERIPHS_IO_MUX_GPIO2_U
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#define GPIO_PIN_REG_3 PERIPHS_IO_MUX_U0RXD_U
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#define GPIO_PIN_REG_4 PERIPHS_IO_MUX_GPIO4_U
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#define GPIO_PIN_REG_5 PERIPHS_IO_MUX_GPIO5_U
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#define GPIO_PIN_REG_6 PERIPHS_IO_MUX_SD_CLK_U
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#define GPIO_PIN_REG_7 PERIPHS_IO_MUX_SD_DATA0_U
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#define GPIO_PIN_REG_8 PERIPHS_IO_MUX_SD_DATA1_U
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#define GPIO_PIN_REG_9 PERIPHS_IO_MUX_SD_DATA2_U
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#define GPIO_PIN_REG_10 PERIPHS_IO_MUX_SD_DATA3_U
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#define GPIO_PIN_REG_11 PERIPHS_IO_MUX_SD_CMD_U
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#define GPIO_PIN_REG_12 PERIPHS_IO_MUX_MTDI_U
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#define GPIO_PIN_REG_13 PERIPHS_IO_MUX_MTCK_U
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#define GPIO_PIN_REG_14 PERIPHS_IO_MUX_MTMS_U
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#define GPIO_PIN_REG_15 PERIPHS_IO_MUX_MTDO_U
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#define GPIO_PIN_REG_16 PERIPHS_IO_MUX_GPIO16_U
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#define GPIO_PIN_REG_17 PERIPHS_IO_MUX_GPIO17_U
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#define GPIO_PIN_REG_18 PERIPHS_IO_MUX_GPIO18_U
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#define GPIO_PIN_REG_19 PERIPHS_IO_MUX_GPIO19_U
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#define GPIO_PIN_REG_20 PERIPHS_IO_MUX_GPIO20_U
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#define GPIO_PIN_REG_21 PERIPHS_IO_MUX_GPIO21_U
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#define GPIO_PIN_REG_22 PERIPHS_IO_MUX_GPIO22_U
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#define GPIO_PIN_REG_23 PERIPHS_IO_MUX_GPIO23_U
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#define GPIO_PIN_REG_25 PERIPHS_IO_MUX_GPIO25_U
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#define GPIO_PIN_REG_26 PERIPHS_IO_MUX_GPIO26_U
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#define GPIO_PIN_REG_27 PERIPHS_IO_MUX_GPIO27_U
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#define GPIO_PIN_REG_32 PERIPHS_IO_MUX_GPIO32_U
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#define GPIO_PIN_REG_33 PERIPHS_IO_MUX_GPIO33_U
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#define GPIO_PIN_REG_34 PERIPHS_IO_MUX_GPIO34_U
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#define GPIO_PIN_REG_35 PERIPHS_IO_MUX_GPIO35_U
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#define GPIO_PIN_REG_36 PERIPHS_IO_MUX_GPIO36_U
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#define GPIO_PIN_REG_37 PERIPHS_IO_MUX_GPIO37_U
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#define GPIO_PIN_REG_38 PERIPHS_IO_MUX_GPIO38_U
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#define GPIO_PIN_REG_39 PERIPHS_IO_MUX_GPIO39_U
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#define GPIO_PIN_REG_0 IO_MUX_GPIO0_REG
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#define GPIO_PIN_REG_1 IO_MUX_GPIO1_REG
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#define GPIO_PIN_REG_2 IO_MUX_GPIO2_REG
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#define GPIO_PIN_REG_3 IO_MUX_GPIO3_REG
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#define GPIO_PIN_REG_4 IO_MUX_GPIO4_REG
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#define GPIO_PIN_REG_5 IO_MUX_GPIO5_REG
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#define GPIO_PIN_REG_6 IO_MUX_GPIO6_REG
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#define GPIO_PIN_REG_7 IO_MUX_GPIO7_REG
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#define GPIO_PIN_REG_8 IO_MUX_GPIO8_REG
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#define GPIO_PIN_REG_9 IO_MUX_GPIO9_REG
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#define GPIO_PIN_REG_10 IO_MUX_GPIO10_REG
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#define GPIO_PIN_REG_11 IO_MUX_GPIO11_REG
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#define GPIO_PIN_REG_12 IO_MUX_GPIO12_REG
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#define GPIO_PIN_REG_13 IO_MUX_GPIO13_REG
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#define GPIO_PIN_REG_14 IO_MUX_GPIO14_REG
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#define GPIO_PIN_REG_15 IO_MUX_GPIO15_REG
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#define GPIO_PIN_REG_16 IO_MUX_GPIO16_REG
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#define GPIO_PIN_REG_17 IO_MUX_GPIO17_REG
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#define GPIO_PIN_REG_18 IO_MUX_GPIO18_REG
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#define GPIO_PIN_REG_19 IO_MUX_GPIO19_REG
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#define GPIO_PIN_REG_20 IO_MUX_GPIO20_REG
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#define GPIO_PIN_REG_21 IO_MUX_GPIO21_REG
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#define GPIO_PIN_REG_22 IO_MUX_GPIO22_REG
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#define GPIO_PIN_REG_23 IO_MUX_GPIO23_REG
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#define GPIO_PIN_REG_25 IO_MUX_GPIO25_REG
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#define GPIO_PIN_REG_26 IO_MUX_GPIO26_REG
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#define GPIO_PIN_REG_27 IO_MUX_GPIO27_REG
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#define GPIO_PIN_REG_32 IO_MUX_GPIO32_REG
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#define GPIO_PIN_REG_33 IO_MUX_GPIO33_REG
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#define GPIO_PIN_REG_34 IO_MUX_GPIO34_REG
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#define GPIO_PIN_REG_35 IO_MUX_GPIO35_REG
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#define GPIO_PIN_REG_36 IO_MUX_GPIO36_REG
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#define GPIO_PIN_REG_37 IO_MUX_GPIO37_REG
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#define GPIO_PIN_REG_38 IO_MUX_GPIO38_REG
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#define GPIO_PIN_REG_39 IO_MUX_GPIO39_REG
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#define GPIO_APP_CPU_INTR_ENA (BIT(0))
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#define GPIO_APP_CPU_NMI_INTR_ENA (BIT(1))
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@ -302,6 +302,8 @@ esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level);
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/**
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* @brief GPIO get input level
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*
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* @warning If the pad is not configured for input (or input and output) the returned value is always 0.
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*
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* @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
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*
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* @return
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124
tools/sdk/include/driver/driver/i2s.h
Normal file → Executable file
124
tools/sdk/include/driver/driver/i2s.h
Normal file → Executable file
@ -138,7 +138,8 @@ typedef struct {
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int intr_alloc_flags; /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */
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int dma_buf_count; /*!< I2S DMA Buffer Count */
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int dma_buf_len; /*!< I2S DMA Buffer Length */
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int use_apll; /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
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bool use_apll; /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
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int fixed_mclk; /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value.*/
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} i2s_config_t;
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/**
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@ -207,8 +208,9 @@ typedef intr_handle_t i2s_isr_handle_t;
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* if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead.
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*
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* @return
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* - ESP_OK Success
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* - ESP_FAIL Parameter error
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL IO error
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*/
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esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
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@ -222,7 +224,7 @@ esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
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* be used as RTC DAC function at the same time.
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*
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* @return
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* - ESP_OK Success
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
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@ -241,8 +243,9 @@ esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
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* This function must be called before any I2S driver read/write operations.
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*
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* @return
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* - ESP_OK Success
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* - ESP_FAIL Parameter error
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_ERR_NO_MEM Out of memory
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*/
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esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void* i2s_queue);
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@ -252,8 +255,8 @@ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config,
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
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*
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* @return
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* - ESP_OK Success
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* - ESP_FAIL Parameter error
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
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*/
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esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num);
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@ -276,10 +279,41 @@ esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num);
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* Format of the data in source buffer is determined by the I2S
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* configuration (see i2s_config_t).
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*
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* @return Number of bytes written, or ESP_FAIL (-1) for parameter error. If a timeout occurred, bytes written will be less than total size.
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* @return
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* - Number of bytes written, if timeout occurred, bytes written will be less than the size passed.
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* - ESP_FAIL Parameter error.
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*/
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int i2s_write_bytes(i2s_port_t i2s_num, const char *src, size_t size, TickType_t ticks_to_wait);
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/**
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* @brief Write data to I2S DMA transmit buffer while expanding the number of bits per sample. For example, expanding 16-bit PCM to 32-bit PCM.
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*
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
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*
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* @param src Source address to write from
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*
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* @param size Size of data in bytes
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*
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* @param src_bits Source audio bit
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*
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* @param aim_bits Bit wanted, no more than 32, and must be greater than src_bits
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*
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* @param ticks_to_wait TX buffer wait timeout in RTOS ticks. If this
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* many ticks pass without space becoming available in the DMA
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* transmit buffer, then the function will return (note that if the
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* data is written to the DMA buffer in pieces, the overall operation
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* may still take longer than this timeout.) Pass portMAX_DELAY for no
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* timeout.
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*
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* Format of the data in source buffer is determined by the I2S
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* configuration (see i2s_config_t).
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*
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* @return
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* - Number of bytes written, if timeout occurred, bytes written will be less than the size passed.
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* - ESP_FAIL Parameter error.
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*/
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int i2s_write_expand(i2s_port_t i2s_num, const char *src, int size, int src_bits, int aim_bits, TickType_t ticks_to_wait);
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/**
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* @brief Read data from I2S DMA receive buffer
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*
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@ -293,8 +327,12 @@ int i2s_write_bytes(i2s_port_t i2s_num, const char *src, size_t size, TickType_t
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*
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* Format of the data in source buffer is determined by the I2S
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* configuration (see i2s_config_t).
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* @note If the built-in ADC mode is enabled, we should call i2s_adc_start and i2s_adc_stop around the whole reading process,
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* to prevent the data getting corrupted.
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*
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* @return Number of bytes read, or ESP_FAIL (-1) for parameter error. If a timeout occurred, bytes read will be less than total size.
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* @return
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* - Number of bytes read, if timeout occurred, bytes written will be less than the size passed.
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* - ESP_FAIL Parameter error.
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*/
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int i2s_read_bytes(i2s_port_t i2s_num, char* dest, size_t size, TickType_t ticks_to_wait);
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@ -309,7 +347,9 @@ int i2s_read_bytes(i2s_port_t i2s_num, char* dest, size_t size, TickType_t ticks
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*
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* @param ticks_to_wait Push timeout in RTOS ticks. If space is not available in the DMA TX buffer within this period, no data is written and function returns 0.
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*
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* @return Number of bytes successfully pushed to DMA buffer, or ESP_FAIL (-1) for parameter error. Will be either zero or the size of configured sample buffer.
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* @return
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* - Number of bytes successfully pushed to DMA buffer, will be either zero or the size of configured sample buffer.
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* - ESP_FAIL Parameter error.
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*/
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int i2s_push_sample(i2s_port_t i2s_num, const char *sample, TickType_t ticks_to_wait);
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@ -324,8 +364,9 @@ int i2s_push_sample(i2s_port_t i2s_num, const char *sample, TickType_t ticks_to_
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*
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* @param ticks_to_wait Pop timeout in RTOS ticks. If a sample is not available in the DMA buffer within this period, no data is read and function returns zero.
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*
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* @return Number of bytes successfully read from DMA buffer, or ESP_FAIL (-1) for parameter error. Byte count will be either zero or the size of the configured sample buffer.
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* @return
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* - Number of bytes successfully read from DMA buffer, will be either zero or the size of configured sample buffer.
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* - ESP_FAIL Parameter error.
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*/
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int i2s_pop_sample(i2s_port_t i2s_num, char *sample, TickType_t ticks_to_wait);
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@ -342,8 +383,10 @@ int i2s_pop_sample(i2s_port_t i2s_num, char *sample, TickType_t ticks_to_wait);
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* @param rate I2S sample rate (ex: 8000, 44100...)
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*
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* @return
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* - ESP_OK Success
|
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* - ESP_FAIL Parameter error
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* - ESP_OK Success
|
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* - ESP_ERR_INVALID_ARG Parameter error
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* - ESP_FAIL I2s is not initialized
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* - ESP_ERR_NO_MEM Out of memory
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*/
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esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate);
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@ -355,8 +398,8 @@ esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate);
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
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*
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* @return
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* - ESP_OK Success
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* - ESP_FAIL Parameter error
|
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG Parameter error
|
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*/
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esp_err_t i2s_stop(i2s_port_t i2s_num);
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@ -369,8 +412,8 @@ esp_err_t i2s_stop(i2s_port_t i2s_num);
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
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*
|
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* @return
|
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* - ESP_OK Success
|
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* - ESP_FAIL Parameter error
|
||||
* - ESP_OK Success
|
||||
* - ESP_ERR_INVALID_ARG Parameter error
|
||||
*/
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esp_err_t i2s_start(i2s_port_t i2s_num);
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|
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@ -382,14 +425,14 @@ esp_err_t i2s_start(i2s_port_t i2s_num);
|
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
|
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*
|
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* @return
|
||||
* - ESP_OK Success
|
||||
* - ESP_FAIL Parameter error
|
||||
* - ESP_OK Success
|
||||
* - ESP_ERR_INVALID_ARG Parameter error
|
||||
*/
|
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esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
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|
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/**
|
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* @brief Set clock & bit width used for I2S RX and TX.
|
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*
|
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*
|
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* Similar to i2s_set_sample_rates(), but also sets bit width.
|
||||
*
|
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
|
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@ -399,10 +442,12 @@ esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
|
||||
* @param bits I2S bit width (I2S_BITS_PER_SAMPLE_16BIT, I2S_BITS_PER_SAMPLE_24BIT, I2S_BITS_PER_SAMPLE_32BIT)
|
||||
*
|
||||
* @param ch I2S channel, (I2S_CHANNEL_MONO, I2S_CHANNEL_STEREO)
|
||||
*
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK Success
|
||||
* - ESP_FAIL Parameter error
|
||||
* - ESP_OK Success
|
||||
* - ESP_FAIL Not initialized
|
||||
* - ESP_ERR_INVALID_ARG Parameter error
|
||||
* - ESP_ERR_NO_MEM Out of memory
|
||||
*/
|
||||
esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t bits, i2s_channel_t ch);
|
||||
|
||||
@ -412,11 +457,36 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
|
||||
* @param adc_unit SAR ADC unit index
|
||||
* @param adc_channel ADC channel index
|
||||
* @return
|
||||
* - ESP_OK Success
|
||||
* - ESP_FAIL Parameter error
|
||||
* - ESP_OK Success
|
||||
* - ESP_ERR_INVALID_ARG Parameter error
|
||||
*/
|
||||
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
|
||||
|
||||
/**
|
||||
* @brief Start to use I2S built-in ADC mode
|
||||
* @note This function would acquire the lock of ADC to prevent the data getting corrupted
|
||||
* during the I2S peripheral is being used to do fully continuous ADC sampling.
|
||||
*
|
||||
* @param i2s_num i2s port index
|
||||
* @return
|
||||
* - ESP_OK Success
|
||||
* - ESP_ERR_INVALID_ARG Parameter error
|
||||
* - ESP_ERR_INVALID_STATE driver state error
|
||||
* - ESP_FAIL Internal driver error
|
||||
*/
|
||||
esp_err_t i2s_adc_enable(i2s_port_t i2s_num);
|
||||
|
||||
/**
|
||||
* @brief Stop to use I2S built-in ADC mode
|
||||
* @param i2s_num i2s port index
|
||||
* @note This function would release the lock of ADC so that other tasks can use ADC.
|
||||
* @return
|
||||
* - ESP_OK Success
|
||||
* - ESP_ERR_INVALID_ARG Parameter error
|
||||
* - ESP_ERR_INVALID_STATE driver state error
|
||||
*/
|
||||
esp_err_t i2s_adc_disable(i2s_port_t i2s_num);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -224,6 +224,24 @@ esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num);
|
||||
*/
|
||||
esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Helper function to disconnect internal circuits from an RTC IO
|
||||
* This function disables input, output, pullup, pulldown, and enables
|
||||
* hold feature for an RTC IO.
|
||||
* Use this function if an RTC IO needs to be disconnected from internal
|
||||
* circuits in deep sleep, to minimize leakage current.
|
||||
*
|
||||
* In particular, for ESP32-WROVER module, call
|
||||
* rtc_gpio_isolate(GPIO_NUM_12) before entering deep sleep, to reduce
|
||||
* deep sleep current.
|
||||
*
|
||||
* @param gpio_num GPIO number (e.g. GPIO_NUM_12).
|
||||
* @return
|
||||
* - ESP_OK on success
|
||||
* - ESP_ERR_INVALID_ARG if GPIO is not an RTC IO
|
||||
*/
|
||||
esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Disable force hold signal for all RTC IOs
|
||||
*
|
||||
|
||||
@ -86,7 +86,13 @@
|
||||
|
||||
/* SPI mode R1 response type bits */
|
||||
#define SD_SPI_R1_IDLE_STATE (1<<0)
|
||||
#define SD_SPI_R1_ERASE_RST (1<<1)
|
||||
#define SD_SPI_R1_ILLEGAL_CMD (1<<2)
|
||||
#define SD_SPI_R1_CMD_CRC_ERR (1<<3)
|
||||
#define SD_SPI_R1_ERASE_SEQ_ERR (1<<4)
|
||||
#define SD_SPI_R1_ADDR_ERR (1<<5)
|
||||
#define SD_SPI_R1_PARAM_ERR (1<<6)
|
||||
#define SD_SPI_R1_NO_RESPONSE (1<<7)
|
||||
|
||||
/* 48-bit response decoding (32 bits w/o CRC) */
|
||||
#define MMC_R1(resp) ((resp)[0])
|
||||
|
||||
@ -39,6 +39,7 @@ extern "C" {
|
||||
.io_voltage = 3.3f, \
|
||||
.init = &sdmmc_host_init, \
|
||||
.set_bus_width = &sdmmc_host_set_bus_width, \
|
||||
.get_bus_width = &sdmmc_host_get_slot_width, \
|
||||
.set_card_clk = &sdmmc_host_set_card_clk, \
|
||||
.do_transaction = &sdmmc_host_do_transaction, \
|
||||
.deinit = &sdmmc_host_deinit, \
|
||||
@ -115,6 +116,14 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config)
|
||||
*/
|
||||
esp_err_t sdmmc_host_set_bus_width(int slot, size_t width);
|
||||
|
||||
/**
|
||||
* @brief Get bus width configured in ``sdmmc_host_init_slot`` to be used for data transfer
|
||||
*
|
||||
* @param slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
|
||||
* @return configured bus width of the specified slot.
|
||||
*/
|
||||
size_t sdmmc_host_get_slot_width(int slot);
|
||||
|
||||
/**
|
||||
* @brief Set card clock frequency
|
||||
*
|
||||
|
||||
@ -125,6 +125,7 @@ typedef struct {
|
||||
float io_voltage; /*!< I/O voltage used by the controller (voltage switching is not supported) */
|
||||
esp_err_t (*init)(void); /*!< Host function to initialize the driver */
|
||||
esp_err_t (*set_bus_width)(int slot, size_t width); /*!< host function to set bus width */
|
||||
size_t (*get_bus_width)(int slot); /*!< host function to get bus width */
|
||||
esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */
|
||||
esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo); /*!< host function to do a transaction */
|
||||
esp_err_t (*deinit)(void); /*!< host function to deinitialize the driver */
|
||||
|
||||
@ -30,11 +30,17 @@ extern "C"
|
||||
|
||||
#define SPI_DEVICE_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first
|
||||
#define SPI_DEVICE_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first
|
||||
#define SPI_DEVICE_BIT_LSBFIRST (SPI_DEVICE_TXBIT_LSBFIRST|SPI_DEVICE_RXBIT_LSBFIRST); ///< Transmit and receive LSB first
|
||||
#define SPI_DEVICE_BIT_LSBFIRST (SPI_DEVICE_TXBIT_LSBFIRST|SPI_DEVICE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first
|
||||
#define SPI_DEVICE_3WIRE (1<<2) ///< Use MOSI (=spid) for both sending and receiving data
|
||||
#define SPI_DEVICE_POSITIVE_CS (1<<3) ///< Make CS positive during a transaction instead of negative
|
||||
#define SPI_DEVICE_HALFDUPLEX (1<<4) ///< Transmit data before receiving it, instead of simultaneously
|
||||
#define SPI_DEVICE_CLK_AS_CS (1<<5) ///< Output clock on CS line if CS is active
|
||||
/** There are timing issue when reading at high frequency (the frequency is related to whether native pins are used, valid time after slave sees the clock).
|
||||
* In half-duplex mode, the driver automatically inserts dummy bits before reading phase to fix the timing issue. Set this flag to disable this feature.
|
||||
* However in full-duplex mode, dummy bits are not allowed to use and no way to prevent reading data from being corrupted.
|
||||
* Set this flag to confirm that you're going to work with output only, or read without dummy bits at your own risk.
|
||||
*/
|
||||
#define SPI_DEVICE_NO_DUMMY (1<<6)
|
||||
|
||||
|
||||
typedef struct spi_transaction_t spi_transaction_t;
|
||||
@ -62,11 +68,11 @@ typedef struct {
|
||||
|
||||
#define SPI_TRANS_MODE_DIO (1<<0) ///< Transmit/receive data in 2-bit mode
|
||||
#define SPI_TRANS_MODE_QIO (1<<1) ///< Transmit/receive data in 4-bit mode
|
||||
#define SPI_TRANS_MODE_DIOQIO_ADDR (1<<4) ///< Also transmit address in mode selected by SPI_MODE_DIO/SPI_MODE_QIO
|
||||
#define SPI_TRANS_USE_RXDATA (1<<2) ///< Receive into rx_data member of spi_transaction_t instead into memory at rx_buffer.
|
||||
#define SPI_TRANS_USE_TXDATA (1<<3) ///< Transmit tx_data member of spi_transaction_t instead of data at tx_buffer. Do not set tx_buffer when using this.
|
||||
#define SPI_TRANS_VARIABLE_CMD (1<<4) ///< Use the ``command_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
|
||||
#define SPI_TRANS_VARIABLE_ADDR (1<<5) ///< Use the ``address_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
|
||||
#define SPI_TRANS_MODE_DIOQIO_ADDR (1<<4) ///< Also transmit address in mode selected by SPI_MODE_DIO/SPI_MODE_QIO
|
||||
#define SPI_TRANS_VARIABLE_CMD (1<<5) ///< Use the ``command_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
|
||||
#define SPI_TRANS_VARIABLE_ADDR (1<<6) ///< Use the ``address_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``.
|
||||
|
||||
/**
|
||||
* This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes.
|
||||
@ -160,7 +166,7 @@ esp_err_t spi_bus_free(spi_host_device_t host);
|
||||
* - ESP_ERR_NO_MEM if out of memory
|
||||
* - ESP_OK on success
|
||||
*/
|
||||
esp_err_t spi_bus_add_device(spi_host_device_t host, spi_device_interface_config_t *dev_config, spi_device_handle_t *handle);
|
||||
esp_err_t spi_bus_add_device(spi_host_device_t host, const spi_device_interface_config_t *dev_config, spi_device_handle_t *handle);
|
||||
|
||||
|
||||
/**
|
||||
|
||||
@ -30,7 +30,7 @@ extern "C"
|
||||
|
||||
#define SPI_SLAVE_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first
|
||||
#define SPI_SLAVE_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first
|
||||
#define SPI_SLAVE_BIT_LSBFIRST (SPI_TXBIT_LSBFIRST|SPI_RXBIT_LSBFIRST); ///< Transmit and receive LSB first
|
||||
#define SPI_SLAVE_BIT_LSBFIRST (SPI_SLAVE_TXBIT_LSBFIRST|SPI_SLAVE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first
|
||||
|
||||
|
||||
typedef struct spi_slave_transaction_t spi_slave_transaction_t;
|
||||
@ -163,4 +163,4 @@ esp_err_t spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *tr
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -238,7 +238,7 @@ esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num,
|
||||
esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* alarm_value);
|
||||
|
||||
/**
|
||||
* @brief Get timer alarm value.
|
||||
* @brief Enable or disable generation of timer alarm events.
|
||||
*
|
||||
* @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
|
||||
* @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
|
||||
|
||||
@ -618,8 +618,10 @@ int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t si
|
||||
int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickType_t ticks_to_wait);
|
||||
|
||||
/**
|
||||
* @brief UART ring buffer flush. This will discard all data in the UART RX buffer.
|
||||
*
|
||||
* @brief Alias of uart_flush_input.
|
||||
* UART ring buffer flush. This will discard all data in the UART RX buffer.
|
||||
* @note Instead of waiting the data sent out, this function will clear UART rx buffer.
|
||||
* In order to send all the data in tx FIFO, we can use uart_wait_tx_done function.
|
||||
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
|
||||
*
|
||||
* @return
|
||||
@ -629,8 +631,18 @@ int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, TickTyp
|
||||
esp_err_t uart_flush(uart_port_t uart_num);
|
||||
|
||||
/**
|
||||
* @brief UART get RX ring buffer cached data length
|
||||
* @brief Clear input buffer, discard all the data is in the ring-buffer.
|
||||
* @note In order to send all the data in tx FIFO, we can use uart_wait_tx_done function.
|
||||
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
|
||||
*
|
||||
* @return
|
||||
* - ESP_OK Success
|
||||
* - ESP_FAIL Parameter error
|
||||
*/
|
||||
esp_err_t uart_flush_input(uart_port_t uart_num);
|
||||
|
||||
/**
|
||||
* @brief UART get RX ring buffer cached data length
|
||||
* @param uart_num UART port number.
|
||||
* @param size Pointer of size_t to accept cached data length
|
||||
*
|
||||
@ -671,6 +683,39 @@ esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num);
|
||||
*/
|
||||
esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle);
|
||||
|
||||
/**
|
||||
* @brief Return the nearest detected pattern position in buffer.
|
||||
* The positions of the detected pattern are saved in a queue,
|
||||
* this function will dequeue the first pattern position and move the pointer to next pattern position.
|
||||
* @note If the RX buffer is full and flow control is not enabled,
|
||||
* the detected pattern may not be found in the rx buffer due to overflow.
|
||||
*
|
||||
* The following APIs will modify the pattern position info:
|
||||
* uart_flush_input, uart_read_bytes, uart_driver_delete, uart_pop_pattern_pos
|
||||
* It is the application's responsibility to ensure atomic access to the pattern queue and the rx data buffer
|
||||
* when using pattern detect feature.
|
||||
*
|
||||
* @param uart_num UART port number
|
||||
* @return
|
||||
* - (-1) No pattern found for current index or parameter error
|
||||
* - others the pattern position in rx buffer.
|
||||
*/
|
||||
int uart_pattern_pop_pos(uart_port_t uart_num);
|
||||
|
||||
/**
|
||||
* @brief Allocate a new memory with the given length to save record the detected pattern position in rx buffer.
|
||||
* @param uart_num UART port number
|
||||
* @param queue_length Max queue length for the detected pattern.
|
||||
* If the queue length is not large enough, some pattern positions might be lost.
|
||||
* Set this value to the maximum number of patterns that could be saved in data buffer at the same time.
|
||||
* @return
|
||||
* - ESP_ERR_NO_MEM No enough memory
|
||||
* - ESP_ERR_INVALID_STATE Driver not installed
|
||||
* - ESP_FAIL Parameter error
|
||||
* - ESP_OK Success
|
||||
*/
|
||||
esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user