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Amend "GPIO refactoring (#6259)" (#6527)

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This commit is contained in:
Dirk O. Kaar
2022-04-05 10:28:59 +02:00
committed by GitHub
parent 7dc8ca4e1e
commit 6cfe4613e4
2 changed files with 4 additions and 11 deletions
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7
cores/esp32/esp32-hal-gpio.h
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@ -49,13 +49,6 @@ extern "C" {
#define INPUT_PULLDOWN 0x09 #define INPUT_PULLDOWN 0x09
#define OPEN_DRAIN 0x10 #define OPEN_DRAIN 0x10
#define OUTPUT_OPEN_DRAIN 0x12 #define OUTPUT_OPEN_DRAIN 0x12
#define SPECIAL 0xF0
#define FUNCTION_1 0x00
#define FUNCTION_2 0x20
#define FUNCTION_3 0x40
#define FUNCTION_4 0x60
#define FUNCTION_5 0x80
#define FUNCTION_6 0xA0
#define ANALOG 0xC0 #define ANALOG 0xC0
//Interrupt Modes //Interrupt Modes

8
libraries/Ethernet/src/ETH.cpp
View File

@ -123,7 +123,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
//gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK); //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
//PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]); //PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
pinMode(0, INPUT); pinMode(0, INPUT);
pinMode(0, FUNCTION_6); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[0], 5);
EMAC_EXT.ex_clk_ctrl.ext_en = 1; EMAC_EXT.ex_clk_ctrl.ext_en = 1;
EMAC_EXT.ex_clk_ctrl.int_en = 0; EMAC_EXT.ex_clk_ctrl.int_en = 0;
EMAC_EXT.ex_oscclk_conf.clk_sel = 1; EMAC_EXT.ex_oscclk_conf.clk_sel = 1;
@ -135,7 +135,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
//gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1); //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
//PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]); //PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
pinMode(0, OUTPUT); pinMode(0, OUTPUT);
pinMode(0, FUNCTION_2); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[0], 1);
// Choose the APLL clock to output on GPIO // Choose the APLL clock to output on GPIO
REG_WRITE(PIN_CTRL, 6); REG_WRITE(PIN_CTRL, 6);
#endif #endif
@ -145,7 +145,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
//gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT); //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
//PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]); //PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
pinMode(16, OUTPUT); pinMode(16, OUTPUT);
pinMode(16, FUNCTION_6); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[16], 5);
#endif #endif
} else if(eth_clock_mode == ETH_CLOCK_GPIO17_OUT){ } else if(eth_clock_mode == ETH_CLOCK_GPIO17_OUT){
#if CONFIG_ETH_RMII_CLK_OUT_GPIO != 17 #if CONFIG_ETH_RMII_CLK_OUT_GPIO != 17
@ -153,7 +153,7 @@ static esp_err_t on_lowlevel_init_done(esp_eth_handle_t eth_handle){
//gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180); //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
//PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]); //PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
pinMode(17, OUTPUT); pinMode(17, OUTPUT);
pinMode(17, FUNCTION_6); PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[17], 5);
#endif #endif
} }
#if CONFIG_ETH_RMII_CLK_INPUT #if CONFIG_ETH_RMII_CLK_INPUT