Allow configuration of Ethernet PHY clock source (#916)

* Allow configuration of Ethernet PHY clock source
Refer to https://github.com/espressif/esp-idf/pull/1127
The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY.
The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested).
New example available.

* Allow configuration of Ethernet PHY clock source
Refer to https://github.com/espressif/esp-idf/pull/1127
The internal APLL can be used to generate the 50MHz clock for the internal EMAC and the external Ethernet PHY.
The clock can either be input on GPIO0 (as before) or output on GPIO0, GPIO16 or GPIO17 (only GPIO17 extensively tested).
New example available.
This commit is contained in:
Frank Sautter
2017-12-19 14:06:01 +01:00
committed by Me No Dev
parent 20db2ee421
commit 75bc1e648b
3 changed files with 109 additions and 3 deletions

View File

@ -30,6 +30,7 @@ extern void tcpipInit();
static int _eth_phy_mdc_pin = -1;
static int _eth_phy_mdio_pin = -1;
static int _eth_phy_power_pin = -1;
static eth_clock_mode_t _eth_clk_mode = ETH_CLOCK_GPIO0_IN;
static eth_phy_power_enable_func _eth_phy_power_enable_orig = NULL;
static void _eth_phy_config_gpio(void)
@ -56,7 +57,7 @@ ETHClass::ETHClass():initialized(false),started(false),staticIP(false)
ETHClass::~ETHClass()
{}
bool ETHClass::begin(uint8_t phy_addr, int power, int mdc, int mdio, eth_phy_type_t type)
bool ETHClass::begin(uint8_t phy_addr, int power, int mdc, int mdio, eth_phy_type_t type, eth_clock_mode_t clock_mode)
{
esp_err_t err;
if(initialized){
@ -84,6 +85,7 @@ bool ETHClass::begin(uint8_t phy_addr, int power, int mdc, int mdio, eth_phy_typ
}
eth_config.phy_addr = (eth_phy_base_t)phy_addr;
eth_config.clock_mode = clock_mode;
eth_config.gpio_config = _eth_phy_config_gpio;
eth_config.tcpip_input = tcpip_adapter_eth_input;
if(_eth_phy_power_pin >= 0){