diff --git a/cores/esp32/esp32-hal-dac.c b/cores/esp32/esp32-hal-dac.c
index 91270152..a5ed029b 100644
--- a/cores/esp32/esp32-hal-dac.c
+++ b/cores/esp32/esp32-hal-dac.c
@@ -38,7 +38,11 @@ void IRAM_ATTR __dacWrite(uint8_t pin, uint8_t value)
     }
     pinMode(pin, ANALOG);
     uint8_t channel = pin - DAC1;
+#if CONFIG_IDF_TARGET_ESP32
+    CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN);
+#elif CONFIG_IDF_TARGET_ESP32S2
     SENS.sar_dac_ctrl1.dac_clkgate_en = 1;
+#endif
     RTCIO.pad_dac[channel].dac_xpd_force = 1;
     RTCIO.pad_dac[channel].xpd_dac = 1;
     if (channel == 0) {
diff --git a/cores/esp32/esp32-hal-gpio.c b/cores/esp32/esp32-hal-gpio.c
index a1dc6f61..981593d3 100644
--- a/cores/esp32/esp32-hal-gpio.c
+++ b/cores/esp32/esp32-hal-gpio.c
@@ -169,7 +169,9 @@ extern void IRAM_ATTR __pinMode(uint8_t pin, uint8_t mode)
         if(!rtc_reg) {
             return;//not rtc pin
         }
+#if CONFIG_IDF_TARGET_ESP32S2
         SENS.sar_io_mux_conf.iomux_clk_gate_en = 1;
+#endif
         SET_PERI_REG_MASK(rtc_io_desc[pin].reg, (rtc_io_desc[pin].mux));
         SET_PERI_REG_BITS(rtc_io_desc[pin].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, SOC_PIN_FUNC_RTC_IO, rtc_io_desc[pin].func);