forked from espressif/arduino-esp32
IDF release/v4.4 f3e0c8bc41 (#6075)
esp-dsp: master 6b25cbb esp-face: master 925c72e esp-rainmaker: f1b82c7 esp32-camera: master 221d24d esp_littlefs: master 5a13cd6 fixes: #5948
This commit is contained in:
Me No Dev
GitHub
@ -1,16 +1,8 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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@ -31,35 +23,9 @@
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extern "C" {
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#endif
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* Set I2S DMA data source for digital controller.
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*
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* @param src i2s data source.
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*/
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#define adc_hal_digi_set_data_source(src) adc_ll_digi_set_data_source(src)
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/*---------------------------------------------------------------
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Hall sensor setting
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---------------------------------------------------------------*/
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/**
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* Enable hall sensor.
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*/
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#define adc_hal_hall_enable() adc_ll_hall_enable()
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/**
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* Disable hall sensor.
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*/
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#define adc_hal_hall_disable() adc_ll_hall_disable()
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/**
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* Start hall convert and return the hall value.
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*
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@ -1,3 +1,9 @@
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/adc_periph.h"
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@ -26,22 +32,50 @@ typedef enum {
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ADC_POWER_MAX, /*!< For parameter check. */
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} adc_ll_power_t;
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typedef enum {
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ADC_RTC_DATA_OK = 0,
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} adc_ll_rtc_raw_data_t;
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typedef enum {
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ADC_LL_CTRL_RTC = 0, ///< For ADC1 and ADC2. Select RTC controller.
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ADC_LL_CTRL_ULP = 1, ///< For ADC1 and ADC2. Select ULP controller.
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ADC_LL_CTRL_DIG = 2, ///< For ADC1 and ADC2. Select DIG controller.
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ADC_LL_CTRL_PWDET = 3, ///< For ADC2. Select PWDET controller.
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} adc_ll_controller_t;
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/**
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* @brief ADC digital controller (DMA mode) work mode.
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*
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* @note The conversion mode affects the sampling frequency:
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* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
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* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
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* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
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* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
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*/
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typedef enum {
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ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion
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ADC_LL_DIGI_CONV_ONLY_ADC2 = 1, // Only use ADC2 for conversion
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ADC_LL_DIGI_CONV_BOTH_UNIT = 2, // Use Both ADC1 and ADC2 for conversion simultaneously
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ADC_LL_DIGI_CONV_ALTER_UNIT = 3 // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
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} adc_ll_digi_convert_mode_t;
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//Need a unit test for bit_width
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typedef struct {
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union {
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struct {
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uint8_t atten: 2;
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uint8_t bit_width: 2; //ADC resolution. 0: 9 bit; 1: 10 bit; 2: 11 bit; 3: 12 bit
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uint8_t channel: 4;
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};
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uint8_t val;
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};
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} __attribute__((packed)) adc_ll_digi_pattern_table_t;
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typedef enum {
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ADC_HALL_CTRL_ULP = 0x0,/*!< Hall sensor controlled by ULP */
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ADC_HALL_CTRL_RTC = 0x1 /*!< Hall sensor controlled by RTC */
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} adc_ll_hall_controller_t ;
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typedef enum {
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ADC_CTRL_RTC = 0,
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ADC_CTRL_ULP = 1,
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ADC_CTRL_DIG = 2,
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ADC2_CTRL_PWDET = 3,
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} adc_hal_controller_t ;
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typedef enum {
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ADC_RTC_DATA_OK = 0,
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} adc_ll_rtc_raw_data_t;
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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@ -85,16 +119,6 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
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HAL_FORCE_MODIFY_U32_REG_FIELD(SYSCON.saradc_ctrl, sar_clk_div, div);
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}
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/**
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* Set adc output data format for digital controller.
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*
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* @param format Output data format, see ``adc_digi_output_format_t``.
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*/
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static inline void adc_ll_digi_set_output_format(adc_digi_output_format_t format)
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{
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SYSCON.saradc_ctrl.data_sar_sel = format;
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}
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/**
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* Set adc max conversion number for digital controller.
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* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
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@ -128,21 +152,28 @@ static inline void adc_ll_digi_convert_limit_disable(void)
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* Set adc conversion mode for digital controller.
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*
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* @note ESP32 only support ADC1 single mode.
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* @note For `data_sar_sel` register:
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* 1: [15] unit, [14:11] channel, [10:0] data, 11-bit-width at most. Only work under `ADC_LL_DIGI_CONV_BOTH_UNIT` or `ADC_LL_DIGI_CONV_ALTER_UNIT` mode.
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* 0: [15:12] channel, [11:0] data, 12-bit-width at most. Only work under `ADC_LL_DIGI_CONV_ONLY_ADC1` or `ADC_LL_DIGI_CONV_ONLY_ADC2` mode
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*
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* @param mode Conversion mode select, see ``adc_digi_convert_mode_t``.
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* @param mode Conversion mode select.
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*/
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static inline void adc_ll_digi_set_convert_mode(adc_digi_convert_mode_t mode)
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static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
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{
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if (mode == ADC_CONV_SINGLE_UNIT_1) {
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if (mode == ADC_LL_DIGI_CONV_ONLY_ADC1) {
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SYSCON.saradc_ctrl.work_mode = 0;
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SYSCON.saradc_ctrl.sar_sel = 0;
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} else if (mode == ADC_CONV_SINGLE_UNIT_2) {
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SYSCON.saradc_ctrl.data_sar_sel = 0;
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} else if (mode == ADC_LL_DIGI_CONV_ONLY_ADC2) {
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SYSCON.saradc_ctrl.work_mode = 0;
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SYSCON.saradc_ctrl.sar_sel = 1;
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} else if (mode == ADC_CONV_BOTH_UNIT) {
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SYSCON.saradc_ctrl.data_sar_sel = 0;
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} else if (mode == ADC_LL_DIGI_CONV_BOTH_UNIT) {
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SYSCON.saradc_ctrl.work_mode = 1;
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} else if (mode == ADC_CONV_ALTER_UNIT) {
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SYSCON.saradc_ctrl.data_sar_sel = 1;
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} else if (mode == ADC_LL_DIGI_CONV_ALTER_UNIT) {
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SYSCON.saradc_ctrl.work_mode = 2;
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SYSCON.saradc_ctrl.data_sar_sel = 1;
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}
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}
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@ -163,11 +194,10 @@ static inline void adc_ll_digi_output_invert(adc_ll_num_t adc_n, bool inv_en)
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/**
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* Set I2S DMA data source for digital controller.
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*
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* @param src i2s data source, see ``adc_i2s_source_t``.
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* @param src 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix
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*/
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static inline void adc_ll_digi_set_data_source(adc_i2s_source_t src)
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static inline void adc_ll_digi_set_data_source(bool src)
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{
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/* 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix */
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SYSCON.saradc_ctrl.data_to_i2s = src;
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}
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@ -199,12 +229,33 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
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* @param pattern_index Items index. Range: 0 ~ 15.
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* @param pattern Stored conversion rules, see ``adc_digi_pattern_table_t``.
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*/
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static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t pattern)
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static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
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{
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uint32_t tab;
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uint8_t index = pattern_index / 4;
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uint8_t offset = (pattern_index % 4) * 8;
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if (adc_n == ADC_NUM_1) {
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adc_ll_digi_pattern_table_t pattern = {0};
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uint8_t bit_width;
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switch (table.bit_width) {
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case 9:
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bit_width = 0x0;
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break;
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case 10:
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bit_width = 0x1;
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break;
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case 11:
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bit_width = 0x2;
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break;
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case 12:
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bit_width = 0x3;
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break;
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default:
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bit_width = 0x3;
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}
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pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
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if (table.unit == ADC_NUM_1) {
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tab = SYSCON.saradc_sar1_patt_tab[index]; // Read old register value
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tab &= (~(0xFF000000 >> offset)); // clear old data
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tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
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@ -233,6 +284,15 @@ static inline void adc_ll_digi_clear_pattern_table(adc_ll_num_t adc_n)
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}
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}
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/**
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* Disable clock for ADC digital controller.
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* @note Not used for esp32
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*/
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static inline void adc_ll_digi_controller_clk_disable(void)
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{
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//Leave here for compatibility
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}
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/*---------------------------------------------------------------
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PWDET(Power detect) controller setting
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---------------------------------------------------------------*/
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@ -263,6 +323,20 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
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/*---------------------------------------------------------------
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RTC controller setting
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---------------------------------------------------------------*/
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/**
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* ADC SAR clock division factor setting. ADC SAR clock divided from `RTC_FAST_CLK`.
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*
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* @param div Division factor.
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*/
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static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
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{
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if (adc_n == ADC_NUM_1) {
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HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
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} else { // adc_n == ADC_NUM_2
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HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
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}
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}
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/**
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* Set adc output data format for RTC controller.
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*
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@ -398,62 +472,6 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
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return ADC_RTC_DATA_OK;
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}
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* Set ADC module power management.
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*
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* @param manage Set ADC power status.
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*/
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static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
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{
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/* Bit1 0:Fsm 1: SW mode
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Bit0 0:SW mode power down 1: SW mode power on */
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if (manage == ADC_POWER_SW_ON) {
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SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
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} else if (manage == ADC_POWER_BY_FSM) {
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SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
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} else if (manage == ADC_POWER_SW_OFF) {
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SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
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}
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}
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/**
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* Get ADC module power management.
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*
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* @return
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* - ADC power status.
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*/
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static inline adc_ll_power_t adc_ll_get_power_manage(void)
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{
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/* Bit1 0:Fsm 1: SW mode
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Bit0 0:SW mode power down 1: SW mode power on */
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adc_ll_power_t manage;
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if (SENS.sar_meas_wait2.force_xpd_sar == SENS_FORCE_XPD_SAR_PU) {
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manage = ADC_POWER_SW_ON;
|
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} else if (SENS.sar_meas_wait2.force_xpd_sar == SENS_FORCE_XPD_SAR_PD) {
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manage = ADC_POWER_SW_OFF;
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} else {
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manage = ADC_POWER_BY_FSM;
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}
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return manage;
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}
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|
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/**
|
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* ADC SAR clock division factor setting. ADC SAR clock divided from `RTC_FAST_CLK`.
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*
|
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* @param div Division factor.
|
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*/
|
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static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
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{
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if (adc_n == ADC_NUM_1) {
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HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl, sar1_clk_div, div);
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} else { // adc_n == ADC_NUM_2
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HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_read_ctrl2, sar2_clk_div, div);
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}
|
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}
|
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|
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/**
|
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* Set the attenuation of a particular channel on ADCn.
|
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*/
|
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@ -482,6 +500,27 @@ static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t cha
|
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}
|
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}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Common setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Set ADC module power management.
|
||||
*
|
||||
* @param manage Set ADC power status.
|
||||
*/
|
||||
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
|
||||
{
|
||||
/* Bit1 0:Fsm 1: SW mode
|
||||
Bit0 0:SW mode power down 1: SW mode power on */
|
||||
if (manage == ADC_POWER_SW_ON) {
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
|
||||
} else if (manage == ADC_POWER_BY_FSM) {
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
|
||||
} else if (manage == ADC_POWER_SW_OFF) {
|
||||
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set ADC module controller.
|
||||
* There are five SAR ADC controllers:
|
||||
@ -492,25 +531,25 @@ static inline adc_atten_t adc_ll_get_atten(adc_ll_num_t adc_n, adc_channel_t cha
|
||||
* @param adc_n ADC unit.
|
||||
* @param ctrl ADC controller.
|
||||
*/
|
||||
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_hal_controller_t ctrl)
|
||||
static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t ctrl)
|
||||
{
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
switch ( ctrl ) {
|
||||
case ADC_CTRL_RTC:
|
||||
case ADC_LL_CTRL_RTC:
|
||||
SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
SENS.sar_touch_ctrl1.xpd_hall_force = 1; // 1: SW control HALL power; 0: ULP FSM control HALL power.
|
||||
SENS.sar_touch_ctrl1.hall_phase_force = 1; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
|
||||
break;
|
||||
case ADC_CTRL_ULP:
|
||||
case ADC_LL_CTRL_ULP:
|
||||
SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas_start1.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start1.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
SENS.sar_touch_ctrl1.xpd_hall_force = 0; // 1: SW control HALL power; 0: ULP FSM control HALL power.
|
||||
SENS.sar_touch_ctrl1.hall_phase_force = 0; // 1: SW control HALL phase; 0: ULP FSM control HALL phase.
|
||||
break;
|
||||
case ADC_CTRL_DIG:
|
||||
case ADC_LL_CTRL_DIG:
|
||||
SENS.sar_read_ctrl.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start1.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
@ -522,28 +561,28 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_hal_controller_
|
||||
}
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
switch ( ctrl ) {
|
||||
case ADC_CTRL_RTC:
|
||||
case ADC_LL_CTRL_RTC:
|
||||
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
|
||||
SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
|
||||
break;
|
||||
case ADC_CTRL_ULP:
|
||||
case ADC_LL_CTRL_ULP:
|
||||
SENS.sar_meas_start2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
|
||||
SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
|
||||
break;
|
||||
case ADC_CTRL_DIG:
|
||||
case ADC_LL_CTRL_DIG:
|
||||
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
SENS.sar_read_ctrl2.sar2_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_read_ctrl2.sar2_pwdet_force = 0; // 1: Select power detect control; 0: Select RTC control.
|
||||
SYSCON.saradc_ctrl.sar2_mux = 1; // 1: Select digital control; 0: Select power detect control.
|
||||
break;
|
||||
case ADC2_CTRL_PWDET: // currently only used by Wi-Fi
|
||||
case ADC_LL_CTRL_PWDET: // currently only used by Wi-Fi
|
||||
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
SENS.sar_read_ctrl2.sar2_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
@ -344,6 +336,12 @@ static inline void emac_ll_clear(emac_mac_dev_t *mac_regs)
|
||||
mac_regs->gmacfc.val = 0;
|
||||
}
|
||||
|
||||
/* emacdebug */
|
||||
static inline uint32_t emac_ll_transmit_frame_ctrl_status(emac_mac_dev_t *mac_regs)
|
||||
{
|
||||
return mac_regs->emacdebug.mactfcs;
|
||||
}
|
||||
|
||||
/* emacmiidata */
|
||||
static inline void emac_ll_set_phy_data(emac_mac_dev_t *mac_regs, uint32_t data)
|
||||
{
|
||||
|
||||
@ -1,21 +1,51 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_err.h"
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/dma_types.h"
|
||||
#include "hal/adc_types.h"
|
||||
#include "hal/adc_ll.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#if SOC_GDMA_SUPPORTED
|
||||
#include "soc/gdma_struct.h"
|
||||
#include "hal/gdma_ll.h"
|
||||
#include "hal/dma_types.h"
|
||||
#include "hal/adc_ll.h"
|
||||
#include "hal/dma_types.h"
|
||||
#include "esp_err.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
//ADC utilises SPI3 DMA on ESP32S2
|
||||
#include "hal/spi_ll.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//ADC utilises I2S0 DMA on ESP32
|
||||
#include "hal/i2s_ll.h"
|
||||
#endif
|
||||
|
||||
#if SOC_GDMA_SUPPORTED
|
||||
#define ADC_HAL_DMA_INTR_MASK GDMA_LL_EVENT_RX_SUC_EOF
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#define ADC_HAL_DMA_INTR_MASK SPI_LL_INTR_IN_SUC_EOF
|
||||
#else //CONFIG_IDF_TARGET_ESP32
|
||||
#define ADC_HAL_DMA_INTR_MASK BIT(9)
|
||||
#endif
|
||||
|
||||
//For ADC module, each conversion contains 4 bytes
|
||||
#define ADC_HAL_DATA_LEN_PER_CONV 4
|
||||
|
||||
typedef enum adc_hal_work_mode_t {
|
||||
ADC_HAL_ULP_MODE,
|
||||
ADC_HAL_SINGLE_READ_MODE,
|
||||
ADC_HAL_CONTINUOUS_READ_MODE,
|
||||
ADC_HAL_PWDET_MODE
|
||||
} adc_hal_work_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Enum for DMA descriptor status
|
||||
*/
|
||||
@ -29,6 +59,7 @@ typedef enum adc_hal_dma_desc_status_t {
|
||||
* @brief Configuration of the HAL
|
||||
*/
|
||||
typedef struct adc_hal_config_t {
|
||||
void *dev; ///< DMA peripheral address
|
||||
uint32_t desc_max_num; ///< Number of the descriptors linked once
|
||||
uint32_t dma_chan; ///< DMA channel to be used
|
||||
uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts
|
||||
@ -42,25 +73,30 @@ typedef struct adc_hal_context_t {
|
||||
dma_descriptor_t *rx_desc; ///< DMA descriptors
|
||||
|
||||
/**< these will be assigned by hal layer itself */
|
||||
gdma_dev_t *dev; ///< GDMA address
|
||||
dma_descriptor_t desc_dummy_head; ///< Dummy DMA descriptor for ``cur_desc_ptr`` to start
|
||||
dma_descriptor_t *cur_desc_ptr; ///< Pointer to the current descriptor
|
||||
|
||||
/**< these need to be configured by `adc_hal_config_t` via driver layer*/
|
||||
void *dev; ///< DMA address
|
||||
uint32_t desc_max_num; ///< Number of the descriptors linked once
|
||||
uint32_t dma_chan; ///< DMA channel to be used
|
||||
uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts
|
||||
} adc_hal_context_t;
|
||||
#endif
|
||||
|
||||
typedef struct adc_hal_digi_ctrlr_cfg_t {
|
||||
bool conv_limit_en; //1: adc conversion will stop when `conv_limit_num` reaches. 0: won't stop. NOTE: esp32 should always be set to 1.
|
||||
uint32_t conv_limit_num; //see `conv_limit_en`
|
||||
uint32_t adc_pattern_len; //total pattern item number, including ADC1 and ADC2
|
||||
adc_digi_pattern_config_t *adc_pattern; //pattern item
|
||||
uint32_t sample_freq_hz; //ADC sample frequency
|
||||
adc_digi_convert_mode_t conv_mode; //controller work mode
|
||||
uint32_t bit_width; //output data width
|
||||
} adc_hal_digi_ctrlr_cfg_t;
|
||||
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Common setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* ADC module initialization.
|
||||
*/
|
||||
void adc_hal_init(void);
|
||||
|
||||
/**
|
||||
* Set ADC module power management.
|
||||
*
|
||||
@ -68,51 +104,7 @@ void adc_hal_init(void);
|
||||
*/
|
||||
#define adc_hal_set_power_manage(manage) adc_ll_set_power_manage(manage)
|
||||
|
||||
/**
|
||||
* ADC module clock division factor setting. ADC clock devided from APB clock.
|
||||
*
|
||||
* @prarm div Division factor.
|
||||
*/
|
||||
#define adc_hal_digi_set_clk_div(div) adc_ll_digi_set_clk_div(div)
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
/**
|
||||
* ADC SAR clock division factor setting. ADC SAR clock devided from `RTC_FAST_CLK`.
|
||||
*
|
||||
* @prarm div Division factor.
|
||||
*/
|
||||
#define adc_hal_set_sar_clk_div(adc_n, div) adc_ll_set_sar_clk_div(adc_n, div)
|
||||
|
||||
/**
|
||||
* Set ADC module controller.
|
||||
* There are five SAR ADC controllers:
|
||||
* Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
|
||||
* Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
|
||||
* the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
|
||||
*
|
||||
* @prarm adc_n ADC unit.
|
||||
* @prarm ctrl ADC controller.
|
||||
*/
|
||||
#define adc_hal_set_controller(adc_n, ctrl) adc_ll_set_controller(adc_n, ctrl)
|
||||
#endif //#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
||||
/**
|
||||
* Get the attenuation of a particular channel on ADCn.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param channel ADCn channel number.
|
||||
* @return atten The attenuation option.
|
||||
*/
|
||||
#define adc_hal_get_atten(adc_n, channel) adc_ll_get_atten(adc_n, channel)
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
/**
|
||||
* Close ADC AMP module if don't use it for power save.
|
||||
*/
|
||||
#define adc_hal_amp_disable() adc_ll_amp_disable()
|
||||
#endif
|
||||
void adc_hal_set_controller(adc_ll_num_t unit, adc_hal_work_mode_t work_mode);
|
||||
|
||||
#if SOC_ADC_ARBITER_SUPPORTED
|
||||
//No ADC2 controller arbiter on ESP32
|
||||
@ -133,7 +125,6 @@ void adc_hal_arbiter_config(adc_arbiter_t *config);
|
||||
/*---------------------------------------------------------------
|
||||
PWDET(Power detect) controller setting
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* Set adc cct for PWDET controller.
|
||||
*
|
||||
@ -150,26 +141,6 @@ void adc_hal_arbiter_config(adc_arbiter_t *config);
|
||||
*/
|
||||
#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
RTC controller setting
|
||||
---------------------------------------------------------------*/
|
||||
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
/**
|
||||
* Set adc output data format for RTC controller.
|
||||
*
|
||||
* @prarm adc_n ADC unit.
|
||||
* @prarm bits Output data bits width option.
|
||||
*/
|
||||
#define adc_hal_rtc_set_output_format(adc_n, bits) adc_ll_rtc_set_output_format(adc_n, bits)
|
||||
|
||||
/**
|
||||
* ADC module output data invert or not.
|
||||
*
|
||||
* @prarm adc_n ADC unit.
|
||||
*/
|
||||
#define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en)
|
||||
#endif //#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
|
||||
/**
|
||||
* Enable/disable the output of ADCn's internal reference voltage to one of ADC2's channels.
|
||||
*
|
||||
@ -188,28 +159,108 @@ void adc_hal_arbiter_config(adc_arbiter_t *config);
|
||||
Digital controller setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Digital controller deinitialization.
|
||||
* ADC module initialization.
|
||||
*/
|
||||
void adc_hal_digi_deinit(void);
|
||||
void adc_hal_init(void);
|
||||
|
||||
/**
|
||||
* Digital controller deinitialization.
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_digi_deinit(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Initialize the hal context
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param config Configuration of the HAL
|
||||
*/
|
||||
void adc_hal_context_config(adc_hal_context_t *hal, const adc_hal_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Initialize the HW
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_digi_init(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* Setting the digital controller.
|
||||
*
|
||||
* @param cfg Pointer to digital controller paramter.
|
||||
* @param hal Context of the HAL
|
||||
* @param cfg Pointer to digital controller paramter.
|
||||
*/
|
||||
void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
|
||||
void adc_hal_digi_controller_config(adc_hal_context_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg);
|
||||
|
||||
/**
|
||||
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
|
||||
* @brief Start Conversion
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param hal Context of the HAL
|
||||
* @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_context_t``
|
||||
*/
|
||||
#define adc_hal_digi_clear_pattern_table(adc_n) adc_ll_digi_clear_pattern_table(adc_n)
|
||||
void adc_hal_digi_start(adc_hal_context_t *hal, uint8_t *data_buf);
|
||||
|
||||
#if !SOC_GDMA_SUPPORTED
|
||||
/**
|
||||
* @brief Get the DMA descriptor that Hardware has finished processing.
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*
|
||||
* @return DMA descriptor address
|
||||
*/
|
||||
intptr_t adc_hal_get_desc_addr(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Check the hardware interrupt event
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param mask Event mask
|
||||
*
|
||||
* @return True: the event is triggered. False: the event is not triggered yet.
|
||||
*/
|
||||
bool adc_hal_check_event(adc_hal_context_t *hal, uint32_t mask);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get the ADC reading result
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA
|
||||
* @param[out] cur_desc The descriptor with ADC reading result (from the 1st one to the last one (``eof_desc_addr``))
|
||||
*
|
||||
* @return See ``adc_hal_dma_desc_status_t``
|
||||
*/
|
||||
adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc);
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param mask mask of the interrupt
|
||||
*/
|
||||
void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param mask mask of the interrupt
|
||||
*/
|
||||
void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Stop conversion
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_digi_stop(adc_hal_context_t *hal);
|
||||
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
ADC Single Read
|
||||
---------------------------------------------------------------*/
|
||||
#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
|
||||
#if SOC_ADC_RTC_CTRL_SUPPORTED
|
||||
/**
|
||||
* Set the attenuation of a particular channel on ADCn.
|
||||
*
|
||||
@ -245,7 +296,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
|
||||
*/
|
||||
#define adc_hal_set_atten(adc_n, channel, atten) adc_ll_set_atten(adc_n, channel, atten)
|
||||
|
||||
#else // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#else // #if !SOC_ADC_RTC_CTRL_SUPPORTED
|
||||
/**
|
||||
* Set the attenuation for ADC to single read
|
||||
*
|
||||
@ -256,7 +307,7 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
|
||||
* @param atten ADC attenuation. See ``adc_atten_t``
|
||||
*/
|
||||
#define adc_hal_set_atten(adc_n, channel, atten) adc_ll_onetime_set_atten(atten)
|
||||
#endif
|
||||
#endif //#if SOC_ADC_RTC_CTRL_SUPPORTED
|
||||
|
||||
/**
|
||||
* Start an ADC conversion and get the converted value.
|
||||
@ -277,7 +328,6 @@ esp_err_t adc_hal_convert(adc_ll_num_t adc_n, int channel, int *out_raw);
|
||||
ADC calibration setting
|
||||
---------------------------------------------------------------*/
|
||||
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
||||
// ESP32-S2, C3 and H2 support HW offset calibration.
|
||||
|
||||
/**
|
||||
* @brief Initialize default parameter for the calibration block.
|
||||
@ -314,86 +364,21 @@ uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc
|
||||
|
||||
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
DMA setting
|
||||
RTC controller setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Initialize the hal context
|
||||
* Set adc output data format for RTC controller.
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param config Configuration of the HAL
|
||||
* @prarm adc_n ADC unit.
|
||||
* @prarm bits Output data bits width option.
|
||||
*/
|
||||
void adc_hal_context_config(adc_hal_context_t *hal, const adc_hal_config_t *config);
|
||||
#define adc_hal_rtc_set_output_format(adc_n, bits) adc_ll_rtc_set_output_format(adc_n, bits)
|
||||
|
||||
/**
|
||||
* @brief Initialize the HW
|
||||
* ADC module output data invert or not.
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @prarm adc_n ADC unit.
|
||||
*/
|
||||
void adc_hal_digi_init(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Reset ADC / DMA fifo
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_fifo_reset(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Start DMA
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_context_t``
|
||||
*/
|
||||
void adc_hal_digi_rxdma_start(adc_hal_context_t *hal, uint8_t *data_buf);
|
||||
|
||||
/**
|
||||
* @brief Start ADC
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_digi_start(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Get the ADC reading result
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA
|
||||
* @param[out] cur_desc The descriptor with ADC reading result (from the 1st one to the last one (``eof_desc_addr``))
|
||||
*
|
||||
* @return See ``adc_hal_dma_desc_status_t``
|
||||
*/
|
||||
adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_context_t *hal, const intptr_t eof_desc_addr, dma_descriptor_t **cur_desc);
|
||||
|
||||
/**
|
||||
* @brief Stop DMA
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_digi_rxdma_stop(adc_hal_context_t *hal);
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param mask mask of the interrupt
|
||||
*/
|
||||
void adc_hal_digi_clr_intr(adc_hal_context_t *hal, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
* @param mask mask of the interrupt
|
||||
*/
|
||||
void adc_hal_digi_dis_intr(adc_hal_context_t *hal, uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Stop ADC
|
||||
*
|
||||
* @param hal Context of the HAL
|
||||
*/
|
||||
void adc_hal_digi_stop(adc_hal_context_t *hal);
|
||||
|
||||
#endif //#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
#define adc_hal_rtc_output_invert(adc_n, inv_en) adc_ll_rtc_output_invert(adc_n, inv_en)
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
@ -62,26 +54,9 @@ typedef enum {
|
||||
ADC_ATTEN_MAX,
|
||||
} adc_atten_t;
|
||||
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
/**
|
||||
* @brief ESP32 ADC DMA source selection.
|
||||
*/
|
||||
#else
|
||||
/**
|
||||
* @brief ESP32 ADC DMA source selection.
|
||||
*
|
||||
* @deprecated Not applicable on ESP32-S2 because ESP32-S2 doesn't use I2S DMA.
|
||||
*/
|
||||
#endif
|
||||
typedef enum {
|
||||
ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
|
||||
ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */
|
||||
ADC_I2S_DATA_SRC_MAX,
|
||||
} adc_i2s_source_t;
|
||||
|
||||
/**
|
||||
* @brief ADC resolution setting option.
|
||||
*
|
||||
* @note Only used in single read mode
|
||||
*/
|
||||
typedef enum {
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
@ -97,82 +72,56 @@ typedef enum {
|
||||
ADC_WIDTH_MAX,
|
||||
} adc_bits_width_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) work mode.
|
||||
*
|
||||
* @note The conversion mode affects the sampling frequency:
|
||||
* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
|
||||
* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
|
||||
* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
|
||||
* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_CONV_SINGLE_UNIT_1 = 1, /*!< SAR ADC 1. */
|
||||
ADC_CONV_SINGLE_UNIT_2 = 2, /*!< SAR ADC 2. */
|
||||
ADC_CONV_BOTH_UNIT = 3, /*!< SAR ADC 1 and 2. */
|
||||
ADC_CONV_ALTER_UNIT = 7, /*!< SAR ADC 1 and 2 alternative mode. */
|
||||
ADC_CONV_SINGLE_UNIT_1 = 1, ///< Only use ADC1 for conversion
|
||||
ADC_CONV_SINGLE_UNIT_2 = 2, ///< Only use ADC2 for conversion
|
||||
ADC_CONV_BOTH_UNIT = 3, ///< Use Both ADC1 and ADC2 for conversion simultaneously
|
||||
ADC_CONV_ALTER_UNIT = 7, ///< Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
|
||||
ADC_CONV_UNIT_MAX,
|
||||
} adc_digi_convert_mode_t;
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) conversion rules setting.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
uint8_t atten: 2; /*!< ADC sampling voltage attenuation configuration. Modification of attenuation affects the range of measurements.
|
||||
0: measurement range 0 - 800mV,
|
||||
1: measurement range 0 - 1100mV,
|
||||
2: measurement range 0 - 1350mV,
|
||||
3: measurement range 0 - 2600mV. */
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
uint8_t bit_width: 2; /*!< ADC resolution.
|
||||
- 0: 9 bit;
|
||||
- 1: 10 bit;
|
||||
- 2: 11 bit;
|
||||
- 3: 12 bit. */
|
||||
int8_t channel: 4; /*!< ADC channel index. */
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
uint8_t reserved: 2; /*!< reserved0 */
|
||||
uint8_t channel: 4; /*!< ADC channel index. */
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
uint8_t channel: 3; /*!< ADC channel index. */
|
||||
uint8_t unit: 1; /*!< ADC unit index. */
|
||||
uint8_t reserved: 2; /*!< reserved0 */
|
||||
#endif
|
||||
};
|
||||
uint8_t val; /*!<Raw data value */
|
||||
};
|
||||
} adc_digi_pattern_table_t;
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) output data format option.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_DIGI_FORMAT_12BIT, /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`).
|
||||
Note: For single convert mode. */
|
||||
ADC_DIGI_FORMAT_11BIT, /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`).
|
||||
Note: For multi or alter convert mode. */
|
||||
ADC_DIGI_FORMAT_MAX,
|
||||
ADC_DIGI_FORMAT_12BIT __attribute__((deprecated)), /*!<ADC to DMA data format, [15:12]-channel, [11: 0]-12 bits ADC data (`adc_digi_output_data_t`). Note: For single convert mode. */
|
||||
ADC_DIGI_FORMAT_11BIT __attribute__((deprecated)), /*!<ADC to DMA data format, [15]-adc unit, [14:11]-channel, [10: 0]-11 bits ADC data (`adc_digi_output_data_t`). Note: For multi or alter convert mode. */
|
||||
ADC_DIGI_FORMAT_MAX __attribute__((deprecated)),
|
||||
|
||||
ADC_DIGI_OUTPUT_FORMAT_TYPE1, ///< See `adc_digi_output_data_t.type1`
|
||||
ADC_DIGI_OUTPUT_FORMAT_TYPE2, ///< See `adc_digi_output_data_t.type2`
|
||||
} adc_digi_output_format_t;
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller pattern configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t atten; ///< Attenuation of this ADC channel
|
||||
uint8_t channel; ///< ADC channel
|
||||
uint8_t unit; ///< ADC unit
|
||||
uint8_t bit_width; ///< ADC output bit width
|
||||
} adc_digi_pattern_config_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Output Format
|
||||
---------------------------------------------------------------*/
|
||||
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) output data format.
|
||||
* Used to analyze the acquired ADC (DMA) data.
|
||||
*
|
||||
* @note ESP32-S2:
|
||||
* Member `channel` can be used to judge the validity of the ADC data, because the role of the arbiter may get invalid ADC data.
|
||||
* @note ESP32: Only `type1` is valid. ADC2 does not support DMA mode.
|
||||
* @note ESP32-S2: Member `channel` can be used to judge the validity of the ADC data,
|
||||
* because the role of the arbiter may get invalid ADC data.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
|
||||
uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2:
|
||||
If (channel < ADC_CHANNEL_MAX), The data is valid.
|
||||
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
|
||||
} type1; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_12BIT` */
|
||||
uint16_t channel: 4; /*!<ADC channel index info. */
|
||||
} type1;
|
||||
struct {
|
||||
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
|
||||
uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2:
|
||||
@ -183,8 +132,8 @@ typedef struct {
|
||||
uint16_t val; /*!<Raw data value */
|
||||
};
|
||||
} adc_digi_output_data_t;
|
||||
#endif
|
||||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) output data format.
|
||||
* Used to analyze the acquired ADC (DMA) data.
|
||||
@ -203,112 +152,32 @@ typedef struct {
|
||||
uint32_t val; /*!<Raw data value */
|
||||
};
|
||||
} adc_digi_output_data_t;
|
||||
#endif
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) clock system setting.
|
||||
* Calculation formula: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
|
||||
*
|
||||
* @note: The clocks of the DAC digital controller use the ADC digital controller clock divider.
|
||||
* @brief ADC digital controller (DMA mode) output data format.
|
||||
* Used to analyze the acquired ADC (DMA) data.
|
||||
*/
|
||||
typedef struct {
|
||||
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
|
||||
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
|
||||
Note: When a higher frequency clock is used (the division factor is less than 9),
|
||||
the ADC reading value will be slightly offset. */
|
||||
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
|
||||
uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
|
||||
} adc_digi_clk_t;
|
||||
|
||||
#endif //!CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) configuration parameters.
|
||||
*
|
||||
* Example setting: When using ADC1 channel0 to measure voltage, the sampling rate is required to be 1 kHz:
|
||||
*
|
||||
* +---------------------+--------+--------+--------+
|
||||
* | sample rate | 1 kHz | 1 kHz | 1 kHz |
|
||||
* +---------------------+--------+--------+--------+
|
||||
* | conv_mode | single | both | alter |
|
||||
* | adc1_pattern_len | 1 | 1 | 1 |
|
||||
* | dig_clk.use_apll | 0 | 0 | 0 |
|
||||
* | dig_clk.div_num | 99 | 99 | 99 |
|
||||
* | dig_clk.div_b | 0 | 0 | 0 |
|
||||
* | dig_clk.div_a | 0 | 0 | 0 |
|
||||
* | interval | 400 | 400 | 200 |
|
||||
* +---------------------+--------+--------+--------+
|
||||
* | `trigger_meas_freq` | 1 kHz | 1 kHz | 2 kHz |
|
||||
* +---------------------+--------+--------+--------+
|
||||
*
|
||||
* Explanation of the relationship between `conv_limit_num`, `dma_eof_num` and the number of DMA outputs:
|
||||
*
|
||||
* +---------------------+--------+--------+--------+
|
||||
* | conv_mode | single | both | alter |
|
||||
* +---------------------+--------+--------+--------+
|
||||
* | trigger meas times | 1 | 1 | 1 |
|
||||
* +---------------------+--------+--------+--------+
|
||||
* | conv_limit_num | +1 | +1 | +1 |
|
||||
* | dma_eof_num | +1 | +2 | +1 |
|
||||
* | dma output (byte) | +2 | +4 | +2 |
|
||||
* +---------------------+--------+--------+--------+
|
||||
*/
|
||||
typedef struct {
|
||||
bool conv_limit_en; /*!<Enable the function of limiting ADC conversion times.
|
||||
If the number of ADC conversion trigger count is equal to the `limit_num`, the conversion is stopped. */
|
||||
uint32_t conv_limit_num; /*!<Set the upper limit of the number of ADC conversion triggers. Range: 1 ~ 255. */
|
||||
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
|
||||
uint32_t adc1_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 16 (0: Don't change the pattern table setting).
|
||||
The pattern table that defines the conversion rules for each SAR ADC. Each table has 16 items, in which channel selection,
|
||||
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
|
||||
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
|
||||
uint32_t adc2_pattern_len; /*!<Refer to ``adc1_pattern_len`` */
|
||||
adc_digi_pattern_table_t *adc1_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc1_pattern_len`. */
|
||||
adc_digi_pattern_table_t *adc2_pattern; /*!<Refer to `adc1_pattern` */
|
||||
adc_digi_convert_mode_t conv_mode; /*!<ADC conversion mode for digital controller. See ``adc_digi_convert_mode_t``. */
|
||||
adc_digi_output_format_t format; /*!<ADC output data format for digital controller. See ``adc_digi_output_format_t``. */
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
uint32_t adc_pattern_len; /*!<Pattern table length for digital controller. Range: 0 ~ 7 (0: Don't change the pattern table setting).
|
||||
The pattern table that defines the conversion rules for each SAR ADC. Each table has 7 items, in which channel selection,
|
||||
resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
|
||||
pattern table one by one. For each controller the scan sequence has at most 16 different rules before repeating itself. */
|
||||
adc_digi_pattern_table_t *adc_pattern; /*!<Pointer to pattern table for digital controller. The table size defined by `adc_pattern_len`. */
|
||||
#endif
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
uint32_t interval; /*!<The number of interval clock cycles for the digital controller to trigger the measurement.
|
||||
The unit is the divided clock. Range: 40 ~ 4095.
|
||||
Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval. Refer to ``adc_digi_clk_t``.
|
||||
Note: The sampling rate of each channel is also related to the conversion mode (See ``adc_digi_convert_mode_t``) and pattern table settings. */
|
||||
adc_digi_clk_t dig_clk; /*!<ADC digital controller clock divider settings. Refer to ``adc_digi_clk_t``.
|
||||
Note: The clocks of the DAC digital controller use the ADC digital controller clock divider. */
|
||||
uint32_t dma_eof_num; /*!<DMA eof num of adc digital controller.
|
||||
If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated in DMA.
|
||||
Note: The converted data in the DMA in link buffer will be multiple of two bytes. */
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
uint32_t sample_freq_hz; /*!< The expected ADC sampling frequency in Hz. Range: 611Hz ~ 83333Hz
|
||||
Fs = Fd / interval / 2
|
||||
Fs: sampling frequency;
|
||||
Fd: digital controller frequency, no larger than 5M for better performance
|
||||
interval: interval between 2 measurement trigger signal, the smallest interval should not be smaller than the ADC measurement period, the largest interval should not be larger than 4095 */
|
||||
#endif
|
||||
} adc_digi_config_t;
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) interrupt type options.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_DIGI_INTR_MASK_MONITOR = 0x1,
|
||||
ADC_DIGI_INTR_MASK_MEAS_DONE = 0x2,
|
||||
ADC_DIGI_INTR_MASK_ALL = 0x3,
|
||||
} adc_digi_intr_t;
|
||||
FLAG_ATTR(adc_digi_intr_t)
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 13; /*!<ADC real output data info. Resolution: 13 bit. */
|
||||
uint32_t channel: 4; /*!<ADC channel index info.
|
||||
If (channel < ADC_CHANNEL_MAX), The data is valid.
|
||||
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
|
||||
uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
|
||||
uint32_t reserved17_31: 14; /*!<Reserved17. */
|
||||
} type2; /*!<When the configured output format is 12bit. `ADC_DIGI_FORMAT_11BIT` */
|
||||
uint32_t val; /*!<Raw data value */
|
||||
};
|
||||
} adc_digi_output_data_t;
|
||||
#endif
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
#if SOC_ADC_ARBITER_SUPPORTED
|
||||
/*---------------------------------------------------------------
|
||||
Arbiter
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief ADC arbiter work mode option.
|
||||
*
|
||||
@ -344,7 +213,12 @@ typedef struct {
|
||||
.dig_pri = 0, \
|
||||
.pwdet_pri = 2, \
|
||||
}
|
||||
#endif //#if SOC_ADC_ARBITER_SUPPORTED
|
||||
|
||||
#if SOC_ADC_FILTER_SUPPORTED
|
||||
/*---------------------------------------------------------------
|
||||
Filter
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) filter index options.
|
||||
*
|
||||
@ -387,7 +261,12 @@ typedef struct {
|
||||
For ESP32-S2, it's always `ADC_CHANNEL_MAX` */
|
||||
adc_digi_filter_mode_t mode;/*!<Set adc filter mode for filter. See ``adc_digi_filter_mode_t``. */
|
||||
} adc_digi_filter_t;
|
||||
#endif // #if SOC_ADC_FILTER_SUPPORTED
|
||||
|
||||
#if SOC_ADC_MONITOR_SUPPORTED
|
||||
/*---------------------------------------------------------------
|
||||
Monitor
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) monitor index options.
|
||||
*
|
||||
@ -437,5 +316,41 @@ typedef struct {
|
||||
uint32_t threshold; /*!<Set monitor threshold of adc digital controller. */
|
||||
#endif
|
||||
} adc_digi_monitor_t;
|
||||
#endif //#if SOC_ADC_MONITOR_SUPPORTED
|
||||
|
||||
#endif // CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
||||
/*---------------------------------------------------------------
|
||||
To Be Deprecated TODO: IDF-3610
|
||||
---------------------------------------------------------------*/
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
/**
|
||||
* @brief ESP32 ADC DMA source selection.
|
||||
*/
|
||||
#else
|
||||
/**
|
||||
* @brief ESP32 ADC DMA source selection.
|
||||
*
|
||||
* @deprecated Not applicable on ESP32-S2 because ESP32-S2 doesn't use I2S DMA.
|
||||
*/
|
||||
#endif
|
||||
typedef enum {
|
||||
ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
|
||||
ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */
|
||||
ADC_I2S_DATA_SRC_MAX,
|
||||
} adc_i2s_source_t;
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) clock system setting.
|
||||
* Calculation formula: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
|
||||
*
|
||||
* @note: The clocks of the DAC digital controller use the ADC digital controller clock divider.
|
||||
*/
|
||||
typedef struct {
|
||||
bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
|
||||
uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
|
||||
Note: When a higher frequency clock is used (the division factor is less than 9),
|
||||
the ADC reading value will be slightly offset. */
|
||||
uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
|
||||
uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
|
||||
} adc_digi_clk_t;
|
||||
#endif
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
@ -222,7 +214,7 @@ void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
|
||||
|
||||
void emac_hal_start(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_stop(emac_hal_context_t *hal);
|
||||
esp_err_t emac_hal_stop(emac_hal_context_t *hal);
|
||||
|
||||
uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user