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Implement Tx only Flush (#3433)

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* add option to Flush() to only clear txQueue

Add the option to cause Flush() to just wait for tx data to clear the tx fifo and uart, leave the rx queue and rx fifo as is.

* support tx only flush()

* support tx only Flush()

* support txOnly for Flush()

* compatibility to Stream()

* compatibility for Stream()

* default value error

* default value error

* Update esp32-hal-uart.h

* Update esp32-hal-uart.c

* Update HardwareSerial.cpp

* sp

* correctly implement flushTxOnly()
This commit is contained in:
chuck todd
2019-11-11 07:37:35 -07:00
committed by Me No Dev
parent e59355df71
commit 7d2632c024
4 changed files with 23 additions and 9 deletions
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23
cores/esp32/esp32-hal-uart.c
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@ -327,6 +327,11 @@ void uartWriteBuf(uart_t* uart, const uint8_t * data, size_t len)
}
void uartFlush(uart_t* uart)
{
uartFlushTxOnly(uart,false);
}
void uartFlushTxOnly(uart_t* uart, bool txOnly)
{
if(uart == NULL) {
return;
@ -334,17 +339,19 @@ void uartFlush(uart_t* uart)
UART_MUTEX_LOCK();
while(uart->dev->status.txfifo_cnt || uart->dev->status.st_utx_out);
if( !txOnly ){
//Due to hardware issue, we can not use fifo_rst to reset uart fifo.
//See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
//Due to hardware issue, we can not use fifo_rst to reset uart fifo.
//See description about UART_TXFIFO_RST and UART_RXFIFO_RST in <<esp32_technical_reference_manual>> v2.6 or later.
// we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
READ_PERI_REG(UART_FIFO_REG(uart->num));
}
// we read the data out and make `fifo_len == 0 && rd_addr == wr_addr`.
while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) {
READ_PERI_REG(UART_FIFO_REG(uart->num));
xQueueReset(uart->queue);
}
xQueueReset(uart->queue);
UART_MUTEX_UNLOCK();
}