forked from espressif/arduino-esp32
Esp32 s3 support (#6341)
Co-authored-by: Jason2866 <24528715+Jason2866@users.noreply.github.com> Co-authored-by: Unexpected Maker <seon@unexpectedmaker.com> Co-authored-by: Rodrigo Garcia <rodrigo.garcia@espressif.com> Co-authored-by: Tomáš Pilný <34927466+PilnyTomas@users.noreply.github.com> Co-authored-by: Pedro Minatel <pedro.minatel@espressif.com> Co-authored-by: Ivan Grokhotkov <ivan@espressif.com> Co-authored-by: Jan Procházka <90197375+P-R-O-C-H-Y@users.noreply.github.com> Co-authored-by: Limor "Ladyada" Fried <limor@ladyada.net>
This commit is contained in:
@ -186,6 +186,11 @@
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#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP 0 // Feedback - 0 or 1
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#endif
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// Enable/disable conversion from 16.16 to 10.14 format on full-speed devices. See tud_audio_n_fb_set().
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#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
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#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION 0 // 0 or 1
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#endif
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// Audio interrupt control EP size - disabled if 0
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#ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
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#define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN 0 // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
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@ -454,10 +459,15 @@ TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_byte
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#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
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TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
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// User code should call this function with feedback value in 16.16 format for FS and HS.
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// Value will be corrected for FS to 10.14 format automatically.
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// (see Universal Serial Bus Specification Revision 2.0 5.12.4.2).
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// Feedback value will be sent at FB endpoint interval till it's changed.
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// This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
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//
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// The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
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// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
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// expects 16.16 format and handles the conversion to 10.14 on FS.
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//
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// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the
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// driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
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bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
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static inline bool tud_audio_fb_set(uint32_t feedback);
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#endif
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@ -42,14 +42,14 @@
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* \defgroup CDC_Serial_Host Host
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* @{ */
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bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb);
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bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_xfer_cb_t complete_cb);
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static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
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static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_xfer_cb_t complete_cb)
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{
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return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
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}
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static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
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static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_xfer_cb_t complete_cb)
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{
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return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
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}
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@ -50,7 +50,7 @@ typedef struct {
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}rndish_data_t;
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void rndish_init(void);
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tusb_error_t rndish_open_subtask(uint8_t dev_addr, cdch_data_t *p_cdc);
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bool rndish_open_subtask(uint8_t dev_addr, cdch_data_t *p_cdc);
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void rndish_xfer_isr(cdch_data_t *p_cdc, pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
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void rndish_close(uint8_t dev_addr);
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@ -645,7 +645,7 @@ enum {
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#define HID_REPORT_SIZE_N(x, n) HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_SIZE, RI_TYPE_GLOBAL, n)
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#define HID_REPORT_ID(x) HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_ID, RI_TYPE_GLOBAL, 1),
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#define HID_REPORT_ID_N(x) HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_ID, RI_TYPE_GLOBAL, n),
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#define HID_REPORT_ID_N(x, n) HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_ID, RI_TYPE_GLOBAL, n),
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#define HID_REPORT_COUNT(x) HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_COUNT, RI_TYPE_GLOBAL, 1)
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#define HID_REPORT_COUNT_N(x, n) HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_COUNT, RI_TYPE_GLOBAL, n)
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@ -1106,7 +1106,10 @@ enum
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{'8' , 0 }, /* 0x60 */ \
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{'9' , 0 }, /* 0x61 */ \
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{'0' , 0 }, /* 0x62 */ \
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{'0' , 0 }, /* 0x63 */ \
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{'.' , 0 }, /* 0x63 */ \
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{0 , 0 }, /* 0x64 */ \
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{0 , 0 }, /* 0x65 */ \
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{0 , 0 }, /* 0x66 */ \
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{'=' , '=' }, /* 0x67 */ \
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@ -131,6 +131,9 @@ TU_ATTR_WEAK uint8_t tud_msc_get_maxlun_cb(void);
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// - Start = 1 : active mode, if load_eject = 1 : load disk storage
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TU_ATTR_WEAK bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject);
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// Invoked when received REQUEST_SENSE
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TU_ATTR_WEAK int32_t tud_msc_request_sense_cb(uint8_t lun, void* buffer, uint16_t bufsize);
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// Invoked when Read10 command is complete
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TU_ATTR_WEAK void tud_msc_read10_complete_cb(uint8_t lun);
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@ -52,6 +52,7 @@ uint32_t tud_vendor_n_write_available (uint8_t itf);
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static inline
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uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
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uint32_t tud_vendor_n_flush (uint8_t itf);
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//--------------------------------------------------------------------+
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// Application API (Single Port)
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@ -64,6 +65,7 @@ static inline void tud_vendor_read_flush (void);
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static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize);
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static inline uint32_t tud_vendor_write_str (char const* str);
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static inline uint32_t tud_vendor_write_available (void);
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static inline uint32_t tud_vendor_flush (void);
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//--------------------------------------------------------------------+
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// Application Callback API (weak is optional)
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@ -71,6 +73,8 @@ static inline uint32_t tud_vendor_write_available (void);
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// Invoked when received new data
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TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t itf);
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// Invoked when last rx transfer finished
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TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t itf, uint32_t sent_bytes);
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//--------------------------------------------------------------------+
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// Inline Functions
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@ -121,6 +125,11 @@ static inline uint32_t tud_vendor_write_available (void)
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return tud_vendor_n_write_available(0);
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}
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static inline uint32_t tud_vendor_flush (void)
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{
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return tud_vendor_n_flush(0);
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}
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//--------------------------------------------------------------------+
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// Internal Class Driver API
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//--------------------------------------------------------------------+
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@ -49,16 +49,16 @@ static inline bool tusbh_custom_is_mounted(uint8_t dev_addr, uint16_t vendor_id,
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return false;
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}
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tusb_error_t tusbh_custom_read(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void * p_buffer, uint16_t length);
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tusb_error_t tusbh_custom_write(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void const * p_data, uint16_t length);
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bool tusbh_custom_read(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void * p_buffer, uint16_t length);
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bool tusbh_custom_write(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void const * p_data, uint16_t length);
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//--------------------------------------------------------------------+
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// Internal Class Driver API
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//--------------------------------------------------------------------+
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void cush_init(void);
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tusb_error_t cush_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length);
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void cush_isr(pipe_handle_t pipe_hdl, xfer_result_t event);
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void cush_close(uint8_t dev_addr);
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void cush_init(void);
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bool cush_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length);
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void cush_isr(pipe_handle_t pipe_hdl, xfer_result_t event);
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void cush_close(uint8_t dev_addr);
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#ifdef __cplusplus
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}
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@ -38,6 +38,7 @@
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#define TU_MIN(_x, _y) ( ( (_x) < (_y) ) ? (_x) : (_y) )
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#define TU_MAX(_x, _y) ( ( (_x) > (_y) ) ? (_x) : (_y) )
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#define TU_U16(_high, _low) ((uint16_t) (((_high) << 8) | (_low)))
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#define TU_U16_HIGH(_u16) ((uint8_t) (((_u16) >> 8) & 0x00ff))
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#define TU_U16_LOW(_u16) ((uint8_t) ((_u16) & 0x00ff))
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#define U16_TO_U8S_BE(_u16) TU_U16_HIGH(_u16), TU_U16_LOW(_u16)
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@ -70,23 +71,10 @@
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#include "tusb_compiler.h"
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#include "tusb_verify.h"
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#include "tusb_types.h"
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#include "tusb_debug.h"
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#include "tusb_error.h" // TODO remove
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#include "tusb_timeout.h" // TODO remove
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//--------------------------------------------------------------------+
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// Internal Helper used by Host and Device Stack
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//--------------------------------------------------------------------+
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// Check if endpoint descriptor is valid per USB specs
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bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
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// Bind all endpoint of a interface descriptor to class driver
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void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
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// Calculate total length of n interfaces (depending on IAD)
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uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
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//--------------------------------------------------------------------+
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// Internal Inline Functions
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//--------------------------------------------------------------------+
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@ -267,138 +255,6 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, ui
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+ TU_BIN8(dlsb))
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#endif
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//--------------------------------------------------------------------+
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// Debug Function
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//--------------------------------------------------------------------+
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// CFG_TUSB_DEBUG for debugging
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// 0 : no debug
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// 1 : print error
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// 2 : print warning
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// 3 : print info
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#if CFG_TUSB_DEBUG
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void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
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#ifdef CFG_TUSB_DEBUG_PRINTF
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extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...);
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#define tu_printf CFG_TUSB_DEBUG_PRINTF
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#else
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#define tu_printf printf
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#endif
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static inline
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void tu_print_var(uint8_t const* buf, uint32_t bufsize)
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{
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for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
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}
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// Log with Level
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#define TU_LOG(n, ...) TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
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#define TU_LOG_MEM(n, ...) TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
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#define TU_LOG_VAR(n, ...) TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
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#define TU_LOG_INT(n, ...) TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
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#define TU_LOG_HEX(n, ...) TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
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#define TU_LOG_LOCATION() tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
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#define TU_LOG_FAILED() tu_printf("%s: %d: Failed\r\n", __PRETTY_FUNCTION__, __LINE__)
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// Log Level 1: Error
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#define TU_LOG1 tu_printf
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#define TU_LOG1_MEM tu_print_mem
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#define TU_LOG1_VAR(_x) tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
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#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
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#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
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// Log Level 2: Warn
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#if CFG_TUSB_DEBUG >= 2
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#define TU_LOG2 TU_LOG1
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#define TU_LOG2_MEM TU_LOG1_MEM
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#define TU_LOG2_VAR TU_LOG1_VAR
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#define TU_LOG2_INT TU_LOG1_INT
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#define TU_LOG2_HEX TU_LOG1_HEX
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#endif
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// Log Level 3: Info
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#if CFG_TUSB_DEBUG >= 3
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#define TU_LOG3 TU_LOG1
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#define TU_LOG3_MEM TU_LOG1_MEM
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#define TU_LOG3_VAR TU_LOG1_VAR
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#define TU_LOG3_INT TU_LOG1_INT
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#define TU_LOG3_HEX TU_LOG1_HEX
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#endif
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typedef struct
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{
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uint32_t key;
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const char* data;
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} tu_lookup_entry_t;
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typedef struct
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{
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uint16_t count;
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tu_lookup_entry_t const* items;
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} tu_lookup_table_t;
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static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
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{
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static char not_found[11];
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for(uint16_t i=0; i<p_table->count; i++)
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{
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if (p_table->items[i].key == key) return p_table->items[i].data;
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}
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// not found return the key value in hex
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sprintf(not_found, "0x%08lX", (unsigned long) key);
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return not_found;
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}
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#endif // CFG_TUSB_DEBUG
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#ifndef TU_LOG
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#define TU_LOG(n, ...)
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#define TU_LOG_MEM(n, ...)
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#define TU_LOG_VAR(n, ...)
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#define TU_LOG_INT(n, ...)
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#define TU_LOG_HEX(n, ...)
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#define TU_LOG_LOCATION()
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#define TU_LOG_FAILED()
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#endif
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// TODO replace all TU_LOGn with TU_LOG(n)
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|
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#define TU_LOG0(...)
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#define TU_LOG0_MEM(...)
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#define TU_LOG0_VAR(...)
|
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#define TU_LOG0_INT(...)
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#define TU_LOG0_HEX(...)
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#ifndef TU_LOG1
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#define TU_LOG1(...)
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#define TU_LOG1_MEM(...)
|
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#define TU_LOG1_VAR(...)
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#define TU_LOG1_INT(...)
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#define TU_LOG1_HEX(...)
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#endif
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#ifndef TU_LOG2
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#define TU_LOG2(...)
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#define TU_LOG2_MEM(...)
|
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#define TU_LOG2_VAR(...)
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#define TU_LOG2_INT(...)
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#define TU_LOG2_HEX(...)
|
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#endif
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#ifndef TU_LOG3
|
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#define TU_LOG3(...)
|
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#define TU_LOG3_MEM(...)
|
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#define TU_LOG3_VAR(...)
|
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#define TU_LOG3_INT(...)
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#define TU_LOG3_HEX(...)
|
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#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
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||||
|
@ -51,10 +51,10 @@
|
||||
#endif
|
||||
|
||||
// Compile-time Assert
|
||||
#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
|
||||
#define TU_VERIFY_STATIC _Static_assert
|
||||
#elif defined (__cplusplus) && __cplusplus >= 201103L
|
||||
#if defined (__cplusplus) && __cplusplus >= 201103L
|
||||
#define TU_VERIFY_STATIC static_assert
|
||||
#elif defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
|
||||
#define TU_VERIFY_STATIC _Static_assert
|
||||
#elif defined(__CCRX__)
|
||||
#define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0];
|
||||
#else
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||||
@ -75,7 +75,11 @@
|
||||
* Nth position is the same as the number of arguments
|
||||
* - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
|
||||
*------------------------------------------------------------------*/
|
||||
#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
|
||||
#if !defined(__CCRX__)
|
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#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
|
||||
#else
|
||||
#define TU_ARGS_NUM(...) _TU_NARG(_0, __VA_ARGS__,_RSEQ_N())
|
||||
#endif
|
||||
|
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#define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__)
|
||||
#define _GET_NTH_ARG( \
|
||||
@ -137,9 +141,11 @@
|
||||
#define TU_BSWAP16(u16) (__builtin_bswap16(u16))
|
||||
#define TU_BSWAP32(u32) (__builtin_bswap32(u32))
|
||||
|
||||
#ifndef __ARMCC_VERSION
|
||||
// List of obsolete callback function that is renamed and should not be defined.
|
||||
// Put it here since only gcc support this pragma
|
||||
#pragma GCC poison tud_vendor_control_request_cb
|
||||
#pragma GCC poison tud_vendor_control_request_cb
|
||||
#endif
|
||||
|
||||
#elif defined(__TI_COMPILER_VERSION__)
|
||||
#define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
|
||||
|
@ -0,0 +1,174 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_DEBUG_H_
|
||||
#define _TUSB_DEBUG_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Debug
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// CFG_TUSB_DEBUG for debugging
|
||||
// 0 : no debug
|
||||
// 1 : print error
|
||||
// 2 : print warning
|
||||
// 3 : print info
|
||||
#if CFG_TUSB_DEBUG
|
||||
|
||||
// Enum to String for debugging purposes
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
extern char const* const tu_str_speed[];
|
||||
extern char const* const tu_str_std_request[];
|
||||
#endif
|
||||
|
||||
void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
|
||||
|
||||
#ifdef CFG_TUSB_DEBUG_PRINTF
|
||||
extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...);
|
||||
#define tu_printf CFG_TUSB_DEBUG_PRINTF
|
||||
#else
|
||||
#define tu_printf printf
|
||||
#endif
|
||||
|
||||
static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
|
||||
{
|
||||
for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
|
||||
}
|
||||
|
||||
// Log with Level
|
||||
#define TU_LOG(n, ...) TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
|
||||
#define TU_LOG_MEM(n, ...) TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
|
||||
#define TU_LOG_VAR(n, ...) TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
|
||||
#define TU_LOG_INT(n, ...) TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
|
||||
#define TU_LOG_HEX(n, ...) TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
|
||||
#define TU_LOG_LOCATION() tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
|
||||
#define TU_LOG_FAILED() tu_printf("%s: %d: Failed\r\n", __PRETTY_FUNCTION__, __LINE__)
|
||||
|
||||
// Log Level 1: Error
|
||||
#define TU_LOG1 tu_printf
|
||||
#define TU_LOG1_MEM tu_print_mem
|
||||
#define TU_LOG1_VAR(_x) tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
|
||||
#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
|
||||
#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
|
||||
|
||||
// Log Level 2: Warn
|
||||
#if CFG_TUSB_DEBUG >= 2
|
||||
#define TU_LOG2 TU_LOG1
|
||||
#define TU_LOG2_MEM TU_LOG1_MEM
|
||||
#define TU_LOG2_VAR TU_LOG1_VAR
|
||||
#define TU_LOG2_INT TU_LOG1_INT
|
||||
#define TU_LOG2_HEX TU_LOG1_HEX
|
||||
#endif
|
||||
|
||||
// Log Level 3: Info
|
||||
#if CFG_TUSB_DEBUG >= 3
|
||||
#define TU_LOG3 TU_LOG1
|
||||
#define TU_LOG3_MEM TU_LOG1_MEM
|
||||
#define TU_LOG3_VAR TU_LOG1_VAR
|
||||
#define TU_LOG3_INT TU_LOG1_INT
|
||||
#define TU_LOG3_HEX TU_LOG1_HEX
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t key;
|
||||
const char* data;
|
||||
} tu_lookup_entry_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t count;
|
||||
tu_lookup_entry_t const* items;
|
||||
} tu_lookup_table_t;
|
||||
|
||||
static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
|
||||
{
|
||||
static char not_found[11];
|
||||
|
||||
for(uint16_t i=0; i<p_table->count; i++)
|
||||
{
|
||||
if (p_table->items[i].key == key) return p_table->items[i].data;
|
||||
}
|
||||
|
||||
// not found return the key value in hex
|
||||
snprintf(not_found, sizeof(not_found), "0x%08lX", (unsigned long) key);
|
||||
|
||||
return not_found;
|
||||
}
|
||||
|
||||
#endif // CFG_TUSB_DEBUG
|
||||
|
||||
#ifndef TU_LOG
|
||||
#define TU_LOG(n, ...)
|
||||
#define TU_LOG_MEM(n, ...)
|
||||
#define TU_LOG_VAR(n, ...)
|
||||
#define TU_LOG_INT(n, ...)
|
||||
#define TU_LOG_HEX(n, ...)
|
||||
#define TU_LOG_LOCATION()
|
||||
#define TU_LOG_FAILED()
|
||||
#endif
|
||||
|
||||
// TODO replace all TU_LOGn with TU_LOG(n)
|
||||
|
||||
#define TU_LOG0(...)
|
||||
#define TU_LOG0_MEM(...)
|
||||
#define TU_LOG0_VAR(...)
|
||||
#define TU_LOG0_INT(...)
|
||||
#define TU_LOG0_HEX(...)
|
||||
|
||||
#ifndef TU_LOG1
|
||||
#define TU_LOG1(...)
|
||||
#define TU_LOG1_MEM(...)
|
||||
#define TU_LOG1_VAR(...)
|
||||
#define TU_LOG1_INT(...)
|
||||
#define TU_LOG1_HEX(...)
|
||||
#endif
|
||||
|
||||
#ifndef TU_LOG2
|
||||
#define TU_LOG2(...)
|
||||
#define TU_LOG2_MEM(...)
|
||||
#define TU_LOG2_VAR(...)
|
||||
#define TU_LOG2_INT(...)
|
||||
#define TU_LOG2_HEX(...)
|
||||
#endif
|
||||
|
||||
#ifndef TU_LOG3
|
||||
#define TU_LOG3(...)
|
||||
#define TU_LOG3_MEM(...)
|
||||
#define TU_LOG3_VAR(...)
|
||||
#define TU_LOG3_INT(...)
|
||||
#define TU_LOG3_HEX(...)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_DEBUG_H_ */
|
@ -1,75 +0,0 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/** \ingroup Group_Common
|
||||
* \defgroup Group_Error Error Codes
|
||||
* @{ */
|
||||
|
||||
#ifndef _TUSB_ERRORS_H_
|
||||
#define _TUSB_ERRORS_H_
|
||||
|
||||
#include "tusb_option.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ERROR_ENUM(x) x,
|
||||
#define ERROR_STRING(x) #x,
|
||||
|
||||
#define ERROR_TABLE(ENTRY) \
|
||||
ENTRY(TUSB_ERROR_NONE )\
|
||||
ENTRY(TUSB_ERROR_INVALID_PARA )\
|
||||
ENTRY(TUSB_ERROR_DEVICE_NOT_READY )\
|
||||
ENTRY(TUSB_ERROR_INTERFACE_IS_BUSY )\
|
||||
ENTRY(TUSB_ERROR_HCD_OPEN_PIPE_FAILED )\
|
||||
ENTRY(TUSB_ERROR_OSAL_TIMEOUT )\
|
||||
ENTRY(TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED )\
|
||||
ENTRY(TUSB_ERROR_MSCH_DEVICE_NOT_MOUNTED )\
|
||||
ENTRY(TUSB_ERROR_NOT_SUPPORTED )\
|
||||
ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY )\
|
||||
ENTRY(TUSB_ERROR_FAILED )\
|
||||
|
||||
/// \brief Error Code returned
|
||||
/// TODO obsolete and to be remove
|
||||
typedef enum
|
||||
{
|
||||
ERROR_TABLE(ERROR_ENUM)
|
||||
TUSB_ERROR_COUNT
|
||||
}tusb_error_t;
|
||||
|
||||
#if CFG_TUSB_DEBUG
|
||||
/// Enum to String for debugging purposes. Only available if \ref CFG_TUSB_DEBUG > 0
|
||||
extern char const* const tusb_strerr[TUSB_ERROR_COUNT];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_ERRORS_H_ */
|
||||
|
||||
/** @} */
|
@ -24,108 +24,151 @@
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef TUSB_DCD_ATTR_H_
|
||||
#define TUSB_DCD_ATTR_H_
|
||||
#ifndef TUSB_MCU_H_
|
||||
#define TUSB_MCU_H_
|
||||
|
||||
#include "tusb_option.h"
|
||||
//--------------------------------------------------------------------+
|
||||
// Port Specific
|
||||
// TUP stand for TinyUSB Port (can be renamed)
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Attribute includes
|
||||
// - ENDPOINT_MAX: max (logical) number of endpoint
|
||||
// - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
|
||||
// e.g EP1 OUT & EP1 IN cannot exist together
|
||||
// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
|
||||
//------------- Unaligned Memory Access -------------//
|
||||
|
||||
// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
|
||||
#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
|
||||
#define TUP_ARCH_STRICT_ALIGN 0
|
||||
#else
|
||||
#define TUP_ARCH_STRICT_ALIGN 1
|
||||
#endif
|
||||
|
||||
/* USB Controller Attributes for Device, Host or MCU (both)
|
||||
* - ENDPOINT_MAX: max (logical) number of endpoint
|
||||
* - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
|
||||
* e.g EP1 OUT & EP1 IN cannot exist together
|
||||
* - RHPORT_HIGHSPEED: mask to indicate which port support highspeed mode (without external PHY)
|
||||
* bit0 for port0 and so on.
|
||||
*/
|
||||
|
||||
//------------- NXP -------------//
|
||||
#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 5
|
||||
#define TUP_DCD_ENDPOINT_MAX 5
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 16
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
#define TUP_USBIP_OHCI
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
|
||||
// TODO USB0 has 6, USB1 has 4
|
||||
#define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define TUP_USBIP_CHIPIDEA_HS
|
||||
#define TUP_USBIP_EHCI
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
|
||||
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 5
|
||||
#define TUP_DCD_ENDPOINT_MAX 5
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
|
||||
// TODO USB0 has 5, USB1 has 6
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
|
||||
// TODO USB0 has 5, USB1 has 6
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
|
||||
#define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_USBIP_CHIPIDEA_HS
|
||||
#define TUP_USBIP_EHCI
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#define TUP_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
|
||||
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 16
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 16
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
|
||||
//------------- Nordic -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
|
||||
// 8 CBI + 1 ISO
|
||||
#define DCD_ATTR_ENDPOINT_MAX 9
|
||||
#define TUP_DCD_ENDPOINT_MAX 9
|
||||
|
||||
//------------- Microchip -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
|
||||
TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_SAMG)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
#define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 10
|
||||
#define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
#define TUP_DCD_ENDPOINT_MAX 10
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01
|
||||
#define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
|
||||
//------------- ST -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F0)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F1)
|
||||
#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
|
||||
defined (STM32F107xB) || defined (STM32F107xC)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 4
|
||||
#define DCD_ATTR_DWC2_STM32
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 4
|
||||
#else
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#endif
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F2)
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
// FS has 4 ep, HS has 5 ep
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define DCD_ATTR_DWC2_STM32
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F3)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
// For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define DCD_ATTR_DWC2_STM32
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
// FS has 6, HS has 9
|
||||
#define DCD_ATTR_ENDPOINT_MAX 9
|
||||
#define DCD_ATTR_DWC2_STM32
|
||||
#define TUP_DCD_ENDPOINT_MAX 9
|
||||
|
||||
// MCU with on-chip HS Phy
|
||||
#if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
|
||||
#define TUP_RHPORT_HIGHSPEED 0x02 // Port 0: FS, Port 1: HS
|
||||
#endif
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 9
|
||||
#define DCD_ATTR_DWC2_STM32
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 9
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32L4)
|
||||
#if defined (STM32L475xx) || defined (STM32L476xx) || \
|
||||
@ -133,78 +176,110 @@
|
||||
defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
|
||||
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
|
||||
defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define DCD_ATTR_DWC2_STM32
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_USBIP_DWC2_STM32
|
||||
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
#else
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#endif
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
//------------- Sony -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_CXD56)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 7
|
||||
#define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
#define TUP_DCD_ENDPOINT_MAX 7
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01
|
||||
#define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
|
||||
|
||||
//------------- TI -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
//------------- ValentyUSB -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 16
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
|
||||
//------------- Nuvoton -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_NUC120)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_NUC505)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 12
|
||||
#define TUP_DCD_ENDPOINT_MAX 12
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01
|
||||
|
||||
//------------- Espressif -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 6
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_DCD_ENDPOINT_MAX 6
|
||||
|
||||
//------------- Dialog -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_DA1469X)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 4
|
||||
#define TUP_DCD_ENDPOINT_MAX 4
|
||||
|
||||
//------------- Raspberry Pi -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RP2040)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 16
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
|
||||
//------------- Silabs -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 7
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_DCD_ENDPOINT_MAX 7
|
||||
|
||||
//------------- Renesas -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 10
|
||||
#define TUP_DCD_ENDPOINT_MAX 10
|
||||
|
||||
//------------- GigaDevice -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 4
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_DCD_ENDPOINT_MAX 4
|
||||
|
||||
//------------- Broadcom -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01
|
||||
|
||||
//------------- Broadcom -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
#define TUP_USBIP_DWC2
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
|
||||
#else
|
||||
#warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
|
||||
#define DCD_ATTR_ENDPOINT_MAX 8
|
||||
//------------- BridgeTek -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_FT90X)
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_FT93X)
|
||||
#define TUP_DCD_ENDPOINT_MAX 16
|
||||
#define TUP_RHPORT_HIGHSPEED 0x01
|
||||
|
||||
//------------ Allwinner -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_F1C100S)
|
||||
#define TUP_DCD_ENDPOINT_MAX 4
|
||||
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Default Values
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#ifndef TUP_DCD_ENDPOINT_MAX
|
||||
#warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
|
||||
#define TUP_DCD_ENDPOINT_MAX 8
|
||||
#endif
|
||||
|
||||
// Default to fullspeed if not defined
|
||||
//#ifndef PORT_HIGHSPEED
|
||||
// #define DCD_ATTR_PORT_HIGHSPEED 0x00
|
||||
//#endif
|
||||
#ifndef TUP_RHPORT_HIGHSPEED
|
||||
#define TUP_RHPORT_HIGHSPEED 0x00
|
||||
#endif
|
||||
|
||||
#endif
|
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2022, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TUSB_PRIVATE_H_
|
||||
#define _TUSB_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct TU_ATTR_PACKED
|
||||
{
|
||||
volatile uint8_t busy : 1;
|
||||
volatile uint8_t stalled : 1;
|
||||
volatile uint8_t claimed : 1;
|
||||
}tu_edpt_state_t;
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Internal Helper used by Host and Device Stack
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Check if endpoint descriptor is valid per USB specs
|
||||
bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
|
||||
|
||||
// Bind all endpoint of a interface descriptor to class driver
|
||||
void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
|
||||
|
||||
// Calculate total length of n interfaces (depending on IAD)
|
||||
uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
|
||||
|
||||
// Claim an endpoint with provided mutex
|
||||
bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
|
||||
|
||||
// Release an endpoint with provided mutex
|
||||
bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_PRIVATE_H_ */
|
@ -223,19 +223,13 @@ enum {
|
||||
|
||||
#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2)
|
||||
|
||||
/// Device State TODO remove
|
||||
typedef enum
|
||||
{
|
||||
TUSB_DEVICE_STATE_UNPLUG = 0 ,
|
||||
TUSB_DEVICE_STATE_CONFIGURED ,
|
||||
TUSB_DEVICE_STATE_SUSPENDED ,
|
||||
}tusb_device_state_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
XFER_RESULT_SUCCESS,
|
||||
XFER_RESULT_FAILED,
|
||||
XFER_RESULT_STALLED,
|
||||
XFER_RESULT_TIMEOUT,
|
||||
XFER_RESULT_INVALID
|
||||
}xfer_result_t;
|
||||
|
||||
enum // TODO remove
|
||||
@ -265,6 +259,7 @@ typedef enum
|
||||
|
||||
enum
|
||||
{
|
||||
CONTROL_STAGE_IDLE,
|
||||
CONTROL_STAGE_SETUP,
|
||||
CONTROL_STAGE_DATA,
|
||||
CONTROL_STAGE_ACK
|
||||
|
@ -74,10 +74,8 @@
|
||||
|
||||
#if CFG_TUSB_DEBUG
|
||||
#include <stdio.h>
|
||||
#define _MESS_ERR(_err) tu_printf("%s %d: failed, error = %s\r\n", __func__, __LINE__, tusb_strerr[_err])
|
||||
#define _MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
|
||||
#else
|
||||
#define _MESS_ERR(_err) do {} while (0)
|
||||
#define _MESS_FAILED() do {} while (0)
|
||||
#endif
|
||||
|
||||
@ -144,32 +142,6 @@
|
||||
#define TU_ASSERT(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
|
||||
#endif
|
||||
|
||||
// TODO remove TU_ASSERT_ERR() later
|
||||
|
||||
/*------------- Generator for TU_VERIFY_ERR and TU_VERIFY_ERR_HDLR -------------*/
|
||||
#define TU_VERIFY_ERR_DEF2(_error, _handler) do \
|
||||
{ \
|
||||
uint32_t _err = (uint32_t)(_error); \
|
||||
if ( 0 != _err ) { _MESS_ERR(_err); _handler; return _err; } \
|
||||
} while(0)
|
||||
|
||||
#define TU_VERIFY_ERR_DEF3(_error, _handler, _ret) do \
|
||||
{ \
|
||||
uint32_t _err = (uint32_t)(_error); \
|
||||
if ( 0 != _err ) { _MESS_ERR(_err); _handler; return _ret; } \
|
||||
} while(0)
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* ASSERT Error
|
||||
* basically TU_VERIFY Error with TU_BREAKPOINT() as handler
|
||||
*------------------------------------------------------------------*/
|
||||
#define ASSERT_ERR_1ARGS(_error) TU_VERIFY_ERR_DEF2(_error, TU_BREAKPOINT())
|
||||
#define ASSERT_ERR_2ARGS(_error, _ret) TU_VERIFY_ERR_DEF3(_error, TU_BREAKPOINT(), _ret)
|
||||
|
||||
#ifndef TU_ASSERT_ERR
|
||||
#define TU_ASSERT_ERR(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_ERR_2ARGS, ASSERT_ERR_1ARGS,UNUSED)(__VA_ARGS__)
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* ASSERT HDLR
|
||||
*------------------------------------------------------------------*/
|
||||
|
@ -30,7 +30,6 @@
|
||||
#include "common/tusb_common.h"
|
||||
#include "osal/osal.h"
|
||||
#include "common/tusb_fifo.h"
|
||||
#include "dcd_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -41,7 +40,7 @@
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#ifndef CFG_TUD_ENDPPOINT_MAX
|
||||
#define CFG_TUD_ENDPPOINT_MAX DCD_ATTR_ENDPOINT_MAX
|
||||
#define CFG_TUD_ENDPPOINT_MAX TUP_DCD_ENDPOINT_MAX
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
@ -106,12 +105,12 @@ typedef struct TU_ATTR_ALIGNED(4)
|
||||
void dcd_init (uint8_t rhport);
|
||||
|
||||
// Interrupt Handler
|
||||
#if __GNUC__
|
||||
#if __GNUC__ && !defined(__ARMCC_VERSION)
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wredundant-decls"
|
||||
#endif
|
||||
void dcd_int_handler(uint8_t rhport);
|
||||
#if __GNUC__
|
||||
#if __GNUC__ && !defined(__ARMCC_VERSION)
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
|
@ -453,7 +453,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
|
||||
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
|
||||
TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
|
||||
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
|
||||
TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
|
||||
TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
|
||||
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
|
||||
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
|
||||
|
||||
@ -502,7 +502,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
|
||||
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
|
||||
TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
|
||||
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
|
||||
TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
|
||||
TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
|
||||
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
|
||||
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
|
||||
|
||||
@ -550,7 +550,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
|
||||
/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
|
||||
TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
|
||||
/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
|
||||
TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
|
||||
TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
|
||||
/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
|
||||
TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
|
||||
/* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
|
||||
@ -558,7 +558,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
|
||||
|
||||
// Calculate wMaxPacketSize of Endpoints
|
||||
#define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
|
||||
((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
|
||||
((((_maxFrequency + (TUD_OPT_HIGH_SPEED ? 7999 : 999)) / (TUD_OPT_HIGH_SPEED ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
|
||||
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
|
@ -58,6 +58,8 @@ usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR
|
||||
|
||||
typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
|
||||
|
||||
void usbd_int_set(bool enabled);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBD Endpoint API
|
||||
//--------------------------------------------------------------------+
|
||||
@ -78,7 +80,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
|
||||
// If caller does not make any transfer, it must release endpoint for others.
|
||||
bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr);
|
||||
|
||||
// Release an endpoint without submitting a transfer
|
||||
// Release claimed endpoint without submitting a transfer
|
||||
bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr);
|
||||
|
||||
// Check if endpoint is busy transferring
|
||||
|
@ -30,12 +30,24 @@
|
||||
#include "common/tusb_common.h"
|
||||
#include "osal/osal.h"
|
||||
#include "common/tusb_fifo.h"
|
||||
#include "hcd_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Configuration
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#ifndef CFG_TUH_ENDPOINT_MAX
|
||||
#define CFG_TUH_ENDPOINT_MAX (CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3)
|
||||
// #ifdef TUP_HCD_ENDPOINT_MAX
|
||||
// #define CFG_TUH_ENDPPOINT_MAX TUP_HCD_ENDPOINT_MAX
|
||||
// #else
|
||||
// #define
|
||||
// #endif
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
@ -82,26 +94,14 @@ typedef struct
|
||||
|
||||
} hcd_event_t;
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
// Max number of endpoints per device
|
||||
enum {
|
||||
// TODO better computation
|
||||
HCD_MAX_ENDPOINT = CFG_TUH_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3),
|
||||
HCD_MAX_XFER = HCD_MAX_ENDPOINT*2,
|
||||
};
|
||||
|
||||
//#define HCD_MAX_ENDPOINT 16
|
||||
//#define HCD_MAX_XFER 16
|
||||
|
||||
typedef struct {
|
||||
typedef struct
|
||||
{
|
||||
uint8_t rhport;
|
||||
uint8_t hub_addr;
|
||||
uint8_t hub_port;
|
||||
uint8_t speed;
|
||||
} hcd_devtree_info_t;
|
||||
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Controller API
|
||||
//--------------------------------------------------------------------+
|
||||
|
@ -1,105 +0,0 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef TUSB_HCD_ATTR_H_
|
||||
#define TUSB_HCD_ATTR_H_
|
||||
|
||||
#include "tusb_option.h"
|
||||
|
||||
// Attribute includes
|
||||
// - ENDPOINT_MAX: max (logical) number of endpoint
|
||||
// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
|
||||
|
||||
//------------- NXP -------------//
|
||||
#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
|
||||
#define HCD_ATTR_OHCI
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
|
||||
#define HCD_ATTR_EHCI_TRANSDIMENSION
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
|
||||
// #define HCD_ATTR_EHCI_NXP_PTD
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
|
||||
// #define HCD_ATTR_EHCI_NXP_PTD
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
|
||||
#define HCD_ATTR_EHCI_TRANSDIMENSION
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX)
|
||||
|
||||
//------------- Microchip -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
|
||||
TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_SAMG)
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
|
||||
|
||||
//------------- ST -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1, OPT_MCU_STM32F3) || \
|
||||
TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32L4)
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F2, OPT_MCU_STM32F3, OPT_MCU_STM32F4)
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
|
||||
|
||||
#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
|
||||
|
||||
//------------- Sony -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_CXD56)
|
||||
|
||||
//------------- Nuvoton -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_NUC505)
|
||||
|
||||
//------------- Espressif -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
|
||||
|
||||
//------------- Raspberry Pi -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RP2040)
|
||||
|
||||
//------------- Silabs -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
|
||||
|
||||
//------------- Renesas -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
|
||||
|
||||
//#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
|
||||
// #define DCD_ATTR_ENDPOINT_MAX not known yet
|
||||
|
||||
//------------- GigaDevice -------------//
|
||||
#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
|
||||
|
||||
#else
|
||||
// #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
|
||||
#endif
|
||||
|
||||
// Default to fullspeed if not defined
|
||||
//#ifndef PORT_HIGHSPEED
|
||||
// #define DCD_ATTR_PORT_HIGHSPEED 0x00
|
||||
//#endif
|
||||
|
||||
#endif
|
@ -171,12 +171,35 @@ typedef struct {
|
||||
|
||||
TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
|
||||
|
||||
bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
|
||||
bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
|
||||
// Clear feature
|
||||
bool hub_port_clear_feature (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Set feature
|
||||
bool hub_port_set_feature (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get port status
|
||||
bool hub_port_get_status (uint8_t hub_addr, uint8_t hub_port, void* resp,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get status from Interrupt endpoint
|
||||
bool hub_edpt_status_xfer(uint8_t dev_addr);
|
||||
|
||||
// Reset a port
|
||||
static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
|
||||
{
|
||||
return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_arg);
|
||||
}
|
||||
|
||||
// Clear Reset Change
|
||||
static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
|
||||
{
|
||||
return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_arg);
|
||||
}
|
||||
|
||||
bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb);
|
||||
bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb);
|
||||
bool hub_status_pipe_queue(uint8_t dev_addr);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Internal Class Driver API
|
||||
|
@ -38,7 +38,31 @@
|
||||
// MACRO CONSTANT TYPEDEF
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
typedef bool (*tuh_control_complete_cb_t)(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
|
||||
// forward declaration
|
||||
struct tuh_control_xfer_s;
|
||||
typedef struct tuh_control_xfer_s tuh_control_xfer_t;
|
||||
|
||||
typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result);
|
||||
|
||||
struct tuh_control_xfer_s
|
||||
{
|
||||
tusb_control_request_t request TU_ATTR_ALIGNED(4);
|
||||
uint8_t* buffer;
|
||||
tuh_control_xfer_cb_t complete_cb;
|
||||
uintptr_t user_arg;
|
||||
};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION CALLBACK
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
|
||||
|
||||
// Invoked when device is mounted (configured)
|
||||
TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
|
||||
|
||||
/// Invoked when device is unmounted (bus reset/unplugged)
|
||||
TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION API
|
||||
@ -57,40 +81,125 @@ void tuh_task(void);
|
||||
extern void hcd_int_handler(uint8_t rhport);
|
||||
#define tuh_int_handler hcd_int_handler
|
||||
|
||||
bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid);
|
||||
tusb_speed_t tuh_speed_get(uint8_t dev_addr);
|
||||
bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
|
||||
|
||||
tusb_speed_t tuh_speed_get(uint8_t daddr);
|
||||
|
||||
// Check if device is connected and configured
|
||||
bool tuh_mounted(uint8_t dev_addr);
|
||||
bool tuh_mounted(uint8_t daddr);
|
||||
|
||||
// Check if device is suspended
|
||||
static inline bool tuh_suspended(uint8_t dev_addr)
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline bool tuh_suspended(uint8_t daddr)
|
||||
{
|
||||
// TODO implement suspend & resume on host
|
||||
(void) dev_addr;
|
||||
(void) daddr;
|
||||
return false;
|
||||
}
|
||||
|
||||
// Check if device is ready to communicate with
|
||||
TU_ATTR_ALWAYS_INLINE
|
||||
static inline bool tuh_ready(uint8_t dev_addr)
|
||||
static inline bool tuh_ready(uint8_t daddr)
|
||||
{
|
||||
return tuh_mounted(dev_addr) && !tuh_suspended(dev_addr);
|
||||
return tuh_mounted(daddr) && !tuh_suspended(daddr);
|
||||
}
|
||||
|
||||
// Carry out control transfer
|
||||
bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
|
||||
// Carry out a control transfer
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
|
||||
bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer);
|
||||
|
||||
// Sync (blocking) version of tuh_control_xfer()
|
||||
// return transfer result
|
||||
uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms);
|
||||
|
||||
// Set Configuration (control transfer)
|
||||
// config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
|
||||
bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION CALLBACK
|
||||
// Descriptors Asynchronous (non-blocking)
|
||||
//--------------------------------------------------------------------+
|
||||
//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
|
||||
|
||||
// Invoked when device is mounted (configured)
|
||||
TU_ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr);
|
||||
// Get an descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
/// Invoked when device is unmounted (bus reset/unplugged)
|
||||
TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr);
|
||||
// Get device descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get configuration descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get HID report descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get string descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
|
||||
bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get manufacturer string descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get product string descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
// Get serial string descriptor (control transfer)
|
||||
// true on success, false if there is on-going control transfer or incorrect parameters
|
||||
bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
|
||||
tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Descriptors Synchronous (blocking)
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_device()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_configuration()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_hid_report()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_string()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_manufacturer_string()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_product_string()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
// Sync (blocking) version of tuh_descriptor_get_serial_string()
|
||||
// return transfer result
|
||||
uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
@ -57,6 +57,8 @@ uint8_t usbh_get_rhport(uint8_t dev_addr);
|
||||
|
||||
uint8_t* usbh_get_enum_buf(void);
|
||||
|
||||
void usbh_int_set(bool enabled);
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USBH Endpoint API
|
||||
//--------------------------------------------------------------------+
|
||||
@ -71,6 +73,7 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
|
||||
// If caller does not make any transfer, it must release endpoint for others.
|
||||
bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
|
||||
|
||||
// Release claimed endpoint without submitting a transfer
|
||||
bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
|
||||
|
||||
// Check if endpoint transferring is complete
|
||||
|
@ -31,9 +31,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \addtogroup group_osal
|
||||
* @{ */
|
||||
|
||||
#include "common/tusb_common.h"
|
||||
|
||||
// Return immediately
|
||||
@ -57,6 +54,8 @@ typedef void (*osal_task_func_t)( void * );
|
||||
#include "osal_pico.h"
|
||||
#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
|
||||
#include "osal_rtthread.h"
|
||||
#elif CFG_TUSB_OS == OPT_OS_RTX4
|
||||
#include "osal_rtx4.h"
|
||||
#elif CFG_TUSB_OS == OPT_OS_CUSTOM
|
||||
#include "tusb_os_custom.h" // implemented by application
|
||||
#else
|
||||
@ -65,47 +64,26 @@ typedef void (*osal_task_func_t)( void * );
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OSAL Porting API
|
||||
// Should be implemented as static inline function in osal_port.h header
|
||||
/*
|
||||
static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
|
||||
static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
|
||||
static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
|
||||
static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
|
||||
|
||||
static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
|
||||
static inline bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
|
||||
static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
|
||||
|
||||
static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl);
|
||||
*/
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#if __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wredundant-decls"
|
||||
#endif
|
||||
//------------- Semaphore -------------//
|
||||
static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
|
||||
static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
|
||||
static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
|
||||
|
||||
static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
|
||||
|
||||
//------------- Mutex -------------//
|
||||
static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
|
||||
static inline bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
|
||||
static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
|
||||
|
||||
//------------- Queue -------------//
|
||||
static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl);
|
||||
#if __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#if 0 // TODO remove subtask related macros later
|
||||
// Sub Task
|
||||
#define OSAL_SUBTASK_BEGIN
|
||||
#define OSAL_SUBTASK_END return TUSB_ERROR_NONE;
|
||||
|
||||
#define STASK_RETURN(_error) return _error;
|
||||
#define STASK_INVOKE(_subtask, _status) (_status) = _subtask
|
||||
#define STASK_ASSERT(_cond) TU_VERIFY(_cond, TUSB_ERROR_OSAL_TASK_FAILED)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* _TUSB_OSAL_H_ */
|
||||
|
@ -68,6 +68,7 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
|
||||
BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
|
||||
// not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
|
||||
if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
|
||||
#else
|
||||
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
||||
@ -114,7 +115,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
|
||||
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
|
||||
static _type _name##_##buf[_depth];\
|
||||
osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
|
||||
|
||||
@ -151,6 +152,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
|
||||
BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
|
||||
// not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
|
||||
if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
|
||||
#else
|
||||
portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
|
||||
@ -169,4 +171,4 @@ static inline bool osal_queue_empty(osal_queue_t qhdl)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TUSB_OSAL_FREERTOS_H_ */
|
||||
#endif
|
||||
|
@ -96,7 +96,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
|
||||
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
|
||||
static _type _name##_##buf[_depth];\
|
||||
static struct os_event _name##_##evbuf[_depth];\
|
||||
osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf = _name##_##evbuf};\
|
||||
|
@ -103,59 +103,34 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
|
||||
//--------------------------------------------------------------------+
|
||||
#include "common/tusb_fifo.h"
|
||||
|
||||
// extern to avoid including dcd.h and hcd.h
|
||||
#if TUSB_OPT_DEVICE_ENABLED
|
||||
extern void dcd_int_disable(uint8_t rhport);
|
||||
extern void dcd_int_enable(uint8_t rhport);
|
||||
#endif
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
extern void hcd_int_disable(uint8_t rhport);
|
||||
extern void hcd_int_enable(uint8_t rhport);
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t role; // device or host
|
||||
tu_fifo_t ff;
|
||||
void (*interrupt_set)(bool);
|
||||
tu_fifo_t ff;
|
||||
}osal_queue_def_t;
|
||||
|
||||
typedef osal_queue_def_t* osal_queue_t;
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
|
||||
// _int_set is used as mutex in OS NONE (disable/enable USB ISR)
|
||||
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
|
||||
uint8_t _name##_buf[_depth*sizeof(_type)]; \
|
||||
osal_queue_def_t _name = { \
|
||||
.role = _role, \
|
||||
.interrupt_set = _int_set, \
|
||||
.ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
|
||||
}
|
||||
|
||||
// lock queue by disable USB interrupt
|
||||
static inline void _osal_q_lock(osal_queue_t qhdl)
|
||||
{
|
||||
(void) qhdl;
|
||||
|
||||
#if TUSB_OPT_DEVICE_ENABLED
|
||||
if (qhdl->role == OPT_MODE_DEVICE) dcd_int_disable(TUD_OPT_RHPORT);
|
||||
#endif
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
if (qhdl->role == OPT_MODE_HOST) hcd_int_disable(TUH_OPT_RHPORT);
|
||||
#endif
|
||||
// disable dcd/hcd interrupt
|
||||
qhdl->interrupt_set(false);
|
||||
}
|
||||
|
||||
// unlock queue
|
||||
static inline void _osal_q_unlock(osal_queue_t qhdl)
|
||||
{
|
||||
(void) qhdl;
|
||||
|
||||
#if TUSB_OPT_DEVICE_ENABLED
|
||||
if (qhdl->role == OPT_MODE_DEVICE) dcd_int_enable(TUD_OPT_RHPORT);
|
||||
#endif
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
if (qhdl->role == OPT_MODE_HOST) hcd_int_enable(TUH_OPT_RHPORT);
|
||||
#endif
|
||||
// enable dcd/hcd interrupt
|
||||
qhdl->interrupt_set(true);
|
||||
}
|
||||
|
||||
static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
|
||||
|
@ -100,7 +100,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
|
||||
//--------------------------------------------------------------------+
|
||||
#include "common/tusb_fifo.h"
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
#if CFG_TUH_ENABLED
|
||||
extern void hcd_int_disable(uint8_t rhport);
|
||||
extern void hcd_int_enable(uint8_t rhport);
|
||||
#endif
|
||||
@ -114,7 +114,7 @@ typedef struct
|
||||
typedef osal_queue_def_t* osal_queue_t;
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
|
||||
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
|
||||
uint8_t _name##_buf[_depth*sizeof(_type)]; \
|
||||
osal_queue_def_t _name = { \
|
||||
.ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
|
||||
|
@ -90,7 +90,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
|
||||
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
|
||||
static _type _name##_##buf[_depth]; \
|
||||
osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
|
||||
|
||||
|
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021 Tian Yunhao (t123yh)
|
||||
* Copyright (c) 2019 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_OSAL_RTX4_H_
|
||||
#define _TUSB_OSAL_RTX4_H_
|
||||
|
||||
#include <rtl.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// TASK API
|
||||
//--------------------------------------------------------------------+
|
||||
static inline void osal_task_delay(uint32_t msec)
|
||||
{
|
||||
uint16_t hi = msec >> 16;
|
||||
uint16_t lo = msec;
|
||||
while (hi--) {
|
||||
os_dly_wait(0xFFFE);
|
||||
}
|
||||
os_dly_wait(lo);
|
||||
}
|
||||
|
||||
static inline uint16_t msec2wait(uint32_t msec) {
|
||||
if (msec == OSAL_TIMEOUT_WAIT_FOREVER)
|
||||
return 0xFFFF;
|
||||
else if (msec >= 0xFFFE)
|
||||
return 0xFFFE;
|
||||
else
|
||||
return msec;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Semaphore API
|
||||
//--------------------------------------------------------------------+
|
||||
typedef OS_SEM osal_semaphore_def_t;
|
||||
typedef OS_ID osal_semaphore_t;
|
||||
|
||||
static inline OS_ID osal_semaphore_create(osal_semaphore_def_t* semdef) {
|
||||
os_sem_init(semdef, 0);
|
||||
return semdef;
|
||||
}
|
||||
|
||||
static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
|
||||
if ( !in_isr ) {
|
||||
os_sem_send(sem_hdl);
|
||||
} else {
|
||||
isr_sem_send(sem_hdl);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) {
|
||||
return os_sem_wait(sem_hdl, msec2wait(msec)) != OS_R_TMO;
|
||||
}
|
||||
|
||||
static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
|
||||
// TODO: implement
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MUTEX API (priority inheritance)
|
||||
//--------------------------------------------------------------------+
|
||||
typedef OS_MUT osal_mutex_def_t;
|
||||
typedef OS_ID osal_mutex_t;
|
||||
|
||||
static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
|
||||
{
|
||||
os_mut_init(mdef);
|
||||
return mdef;
|
||||
}
|
||||
|
||||
static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
|
||||
{
|
||||
return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO;
|
||||
}
|
||||
|
||||
static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
|
||||
{
|
||||
return os_mut_release(mutex_hdl) == OS_R_OK;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// QUEUE API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// role device/host is used by OS NONE for mutex (disable usb isr) only
|
||||
#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
|
||||
os_mbx_declare(_name##__mbox, _depth); \
|
||||
_declare_box(_name##__pool, sizeof(_type), _depth); \
|
||||
osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t depth;
|
||||
uint16_t item_sz;
|
||||
U32* pool;
|
||||
U32* mbox;
|
||||
}osal_queue_def_t;
|
||||
|
||||
typedef osal_queue_def_t* osal_queue_t;
|
||||
|
||||
static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
|
||||
{
|
||||
os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4);
|
||||
_init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz);
|
||||
return qdef;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
|
||||
{
|
||||
void* buf;
|
||||
os_mbx_wait(qhdl->mbox, &buf, 0xFFFF);
|
||||
memcpy(data, buf, qhdl->item_sz);
|
||||
_free_box(qhdl->pool, buf);
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
|
||||
{
|
||||
void* buf = _alloc_box(qhdl->pool);
|
||||
memcpy(buf, data, qhdl->item_sz);
|
||||
if ( !in_isr )
|
||||
{
|
||||
os_mbx_send(qhdl->mbox, buf, 0xFFFF);
|
||||
}
|
||||
else
|
||||
{
|
||||
isr_mbx_send(qhdl->mbox, buf);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool osal_queue_empty(osal_queue_t qhdl)
|
||||
{
|
||||
return os_mbx_check(qhdl->mbox) == qhdl->depth;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
@ -101,8 +101,8 @@ typedef struct
|
||||
|
||||
// Word 2: qTQ Token
|
||||
volatile uint32_t ping_err : 1 ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator
|
||||
volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of slipt transaction
|
||||
volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete slip transaction
|
||||
volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of split transaction
|
||||
volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete split transaction
|
||||
volatile uint32_t xact_err : 1 ; ///< Error (Timeout, CRC, Bad PID ... )
|
||||
volatile uint32_t babble_err : 1 ; ///< Babble detected, also set Halted bit to 1
|
||||
volatile uint32_t buffer_err : 1 ; ///< Data overrun/underrun error
|
||||
|
@ -0,0 +1,931 @@
|
||||
/*******************************************************************************
|
||||
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software
|
||||
* and any derivatives exclusively with Microchip products. It is your
|
||||
* responsibility to comply with third party license terms applicable to your
|
||||
* use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
|
||||
* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
|
||||
* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
|
||||
* PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
|
||||
* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
|
||||
* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
|
||||
* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
|
||||
* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
|
||||
* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
|
||||
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
USBHS Peripheral Library Register Defintions
|
||||
|
||||
File Name:
|
||||
usbhs_registers.h
|
||||
|
||||
Summary:
|
||||
USBHS PLIB Register Defintions
|
||||
|
||||
Description:
|
||||
This file contains the constants and defintions which are required by the
|
||||
the USBHS library.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __USBHS_REGISTERS_H__
|
||||
#define __USBHS_REGISTERS_H__
|
||||
|
||||
#include <p32xxxx.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*****************************************
|
||||
* Module Register Offsets.
|
||||
*****************************************/
|
||||
|
||||
#define USBHS_REG_FADDR 0x000
|
||||
#define USBHS_REG_POWER 0x001
|
||||
#define USBHS_REG_INTRTX 0x002
|
||||
#define USBHS_REG_INTRRX 0x004
|
||||
#define USBHS_REG_INTRTXE 0x006
|
||||
#define USBHS_REG_INTRRXE 0x008
|
||||
#define USBHS_REG_INTRUSB 0x00A
|
||||
#define USBHS_REG_INTRUSBE 0x00B
|
||||
#define USBHS_REG_FRAME 0x00C
|
||||
#define USBHS_REG_INDEX 0x00E
|
||||
#define USBHS_REG_TESTMODE 0x00F
|
||||
|
||||
/*******************************************************
|
||||
* Endpoint Control Status Registers (CSR). These values
|
||||
* should be added to either the 0x10 to access the
|
||||
* register through Indexed CSR. To access the actual
|
||||
* CSR, see ahead in this header file.
|
||||
******************************************************/
|
||||
|
||||
#define USBHS_REG_EP_TXMAXP 0x000
|
||||
#define USBHS_REG_EP_CSR0L 0x002
|
||||
#define USBHS_REG_EP_CSR0H 0x003
|
||||
#define USBHS_REG_EP_TXCSRL 0x002
|
||||
#define USBHS_REG_EP_TXCSRH 0x003
|
||||
#define USBHS_REG_EP_RXMAXP 0x004
|
||||
#define USBHS_REG_EP_RXCSRL 0x006
|
||||
#define USBHS_REG_EP_RXCSRH 0x007
|
||||
#define USBHS_REG_EP_COUNT0 0x008
|
||||
#define USBHS_REG_EP_RXCOUNT 0x008
|
||||
#define USBHS_REG_EP_TYPE0 0x01A
|
||||
#define USBHS_REG_EP_TXTYPE 0x01A
|
||||
#define USBHS_REG_EP_NAKLIMIT0 0x01B
|
||||
#define USBHS_REG_EP_TXINTERVAL 0x01B
|
||||
#define USBHS_REG_EP_RXTYPE 0x01C
|
||||
#define USBHS_REG_EP_RXINTERVAL 0x01D
|
||||
#define USBHS_REG_EP_CONFIGDATA 0x01F
|
||||
#define USBHS_REG_EP_FIFOSIZE 0x01F
|
||||
|
||||
#define USBHS_HOST_EP0_SETUPKT_SET 0x8
|
||||
#define USBHS_HOST_EP0_TXPKTRDY_SET 0x2
|
||||
#define USBHS_SOFT_RST_NRST_SET 0x1
|
||||
#define USBHS_SOFT_RST_NRSTX_SET 0x2
|
||||
#define USBHS_EP0_DEVICE_SERVICED_RXPKTRDY 0x40
|
||||
#define USBHS_EP0_DEVICE_DATAEND 0x08
|
||||
#define USBHS_EP0_DEVICE_TXPKTRDY 0x02
|
||||
#define USBHS_EP0_HOST_STATUS_STAGE_START 0x40
|
||||
#define USBHS_EP0_HOST_REQPKT 0x20
|
||||
#define USBHS_EP0_HOST_TXPKTRDY 0x02
|
||||
#define USBHS_EP0_HOST_RXPKTRDY 0x01
|
||||
#define USBHS_EP_DEVICE_TX_SENT_STALL 0x20
|
||||
#define USBHS_EP_DEVICE_TX_SEND_STALL 0x10
|
||||
#define USBHS_EP_DEVICE_RX_SENT_STALL 0x40
|
||||
#define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
|
||||
|
||||
/* FADDR - Device Function Address */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned FUNC:7;
|
||||
unsigned :1;
|
||||
};
|
||||
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_FADDR_t;
|
||||
|
||||
/* POWER - Control Resume and Suspend signalling */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned SUSPEN:1;
|
||||
unsigned SUSPMODE:1;
|
||||
unsigned RESUME:1;
|
||||
unsigned RESET:1;
|
||||
unsigned HSMODE:1;
|
||||
unsigned HSEN:1;
|
||||
unsigned SOFTCONN:1;
|
||||
unsigned ISOUPD:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_POWER_t;
|
||||
|
||||
/* INTRTXE - Transmit endpoint interrupt enable */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned EP0IE:1;
|
||||
unsigned EP1TXIE:1;
|
||||
unsigned EP2TXIE:1;
|
||||
unsigned EP3TXIE:1;
|
||||
unsigned EP4TXIE:1;
|
||||
unsigned EP5TXIE:1;
|
||||
unsigned EP6TXIE:1;
|
||||
unsigned EP7TXIE:1;
|
||||
unsigned :8;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint16_t w;
|
||||
};
|
||||
|
||||
} __USBHS_INTRTXE_t;
|
||||
|
||||
/* INTRRXE - Receive endpoint interrupt enable */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned :1;
|
||||
unsigned EP1RXIE:1;
|
||||
unsigned EP2RXIE:1;
|
||||
unsigned EP3RXIE:1;
|
||||
unsigned EP4RXIE:1;
|
||||
unsigned EP5RXIE:1;
|
||||
unsigned EP6RXIE:1;
|
||||
unsigned EP7RXIE:1;
|
||||
unsigned :8;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint16_t w;
|
||||
};
|
||||
|
||||
} __USBHS_INTRRXE_t;
|
||||
|
||||
/* INTRUSBE - General USB Interrupt enable */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned SUSPIE:1;
|
||||
unsigned RESUMEIE:1;
|
||||
unsigned RESETIE:1;
|
||||
unsigned SOFIE:1;
|
||||
unsigned CONNIE:1;
|
||||
unsigned DISCONIE:1;
|
||||
unsigned SESSRQIE:1;
|
||||
unsigned VBUSERRIE:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_INTRUSBE_t;
|
||||
|
||||
/* FRAME - Frame number */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RFRMNUM:11;
|
||||
unsigned :5;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint16_t w;
|
||||
};
|
||||
|
||||
} __USBHS_FRAME_t;
|
||||
|
||||
/* INDEX - Endpoint index */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned ENDPOINT:4;
|
||||
unsigned :4;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_INDEX_t;
|
||||
|
||||
/* TESTMODE - Test mode register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned NAK:1;
|
||||
unsigned TESTJ:1;
|
||||
unsigned TESTK:1;
|
||||
unsigned PACKET:1;
|
||||
unsigned FORCEHS:1;
|
||||
unsigned FORCEFS:1;
|
||||
unsigned FIFOACC:1;
|
||||
unsigned FORCEHST:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TESTMODE_t;
|
||||
|
||||
/* COUNT0 - Indicates the amount of data received in endpoint 0 */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXCNT:7;
|
||||
unsigned :1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_COUNT0_t;
|
||||
|
||||
/* TYPE0 - Operating speed of target device */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned :6;
|
||||
unsigned SPEED:2;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TYPE0_t;
|
||||
|
||||
/* DEVCTL - Module control register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned SESSION:1;
|
||||
unsigned HOSTREQ:1;
|
||||
unsigned HOSTMODE:1;
|
||||
unsigned VBUS:2;
|
||||
unsigned LSDEV:1;
|
||||
unsigned FSDEV:1;
|
||||
unsigned BDEV:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_DEVCTL_t;
|
||||
|
||||
/* CSR0L Device - Endpoint Device Mode Control Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXPKTRDY:1;
|
||||
unsigned TXPKTRDY:1;
|
||||
unsigned SENTSTALL:1;
|
||||
unsigned DATAEND:1;
|
||||
unsigned SETUPEND:1;
|
||||
unsigned SENDSTALL:1;
|
||||
unsigned SVCRPR:1;
|
||||
unsigned SVSSETEND:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_CSR0L_DEVICE_t;
|
||||
|
||||
/* CSR0L Host - Endpoint Host Mode Control Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXPKTRDY:1;
|
||||
unsigned TXPKTRDY:1;
|
||||
unsigned RXSTALL:1;
|
||||
unsigned SETUPPKT:1;
|
||||
unsigned ERROR:1;
|
||||
unsigned REQPKT:1;
|
||||
unsigned STATPKT:1;
|
||||
unsigned NAKTMOUT:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_CSR0L_HOST_t;
|
||||
|
||||
/* TXCSRL Device - Endpoint Transmit Control Status Register Low */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXPKTRDY:1;
|
||||
unsigned FIFOONE:1;
|
||||
unsigned UNDERRUN:1;
|
||||
unsigned FLUSH:1;
|
||||
unsigned SENDSTALL:1;
|
||||
unsigned SENTSTALL:1;
|
||||
unsigned CLRDT:1;
|
||||
unsigned INCOMPTX:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TXCSRL_DEVICE_t;
|
||||
|
||||
/* TXCSRL Host - Endpoint Transmit Control Status Register Low */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXPKTRDY:1;
|
||||
unsigned FIFONE:1;
|
||||
unsigned ERROR:1;
|
||||
unsigned FLUSH:1;
|
||||
unsigned SETUPPKT:1;
|
||||
unsigned RXSTALL:1;
|
||||
unsigned CLRDT:1;
|
||||
unsigned INCOMPTX:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TXCSRL_HOST_t;
|
||||
|
||||
/* TXCSRH Device - Endpoint Transmit Control Status Register High */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned :2;
|
||||
unsigned DMAREQMD:1;
|
||||
unsigned FRCDATTG:1;
|
||||
unsigned DMAREQENL:1;
|
||||
unsigned MODE:1;
|
||||
unsigned ISO:1;
|
||||
unsigned AUTOSET:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TXCSRH_DEVICE_t;
|
||||
|
||||
/* TXCSRH Host - Endpoint Transmit Control Status Register High */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned DATATGGL:1;
|
||||
unsigned DTWREN:1;
|
||||
unsigned DMAREQMD:1;
|
||||
unsigned FRCDATTG:1;
|
||||
unsigned DMAREQEN:1;
|
||||
unsigned MODE:1;
|
||||
unsigned :1;
|
||||
unsigned AUOTSET:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TXCSRH_HOST_t;
|
||||
|
||||
/* CSR0H Device - Endpoint 0 Control Status Register High */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned FLSHFIFO:1;
|
||||
unsigned :7;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_CSR0H_DEVICE_t;
|
||||
|
||||
/* CSR0H Host - Endpoint 0 Control Status Register High */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned FLSHFIFO:1;
|
||||
unsigned DATATGGL:1;
|
||||
unsigned DTWREN:1;
|
||||
unsigned DISPING:1;
|
||||
unsigned :4;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_CSR0H_HOST_t;
|
||||
|
||||
/* RXMAXP - Receive Endpoint Max packet size. */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXMAXP:11;
|
||||
unsigned MULT:5;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint16_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXMAXP_t;
|
||||
|
||||
/* RXCSRL Device - Receive endpoint Control Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXPKTRDY:1;
|
||||
unsigned FIFOFULL:1;
|
||||
unsigned OVERRUN:1;
|
||||
unsigned DATAERR:1;
|
||||
unsigned FLUSH:1;
|
||||
unsigned SENDSTALL:1;
|
||||
unsigned SENTSTALL:1;
|
||||
unsigned CLRDT:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXCSRL_DEVICE_t;
|
||||
|
||||
/* RXCSRL Host - Receive endpoint Control Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXPKTRDY:1;
|
||||
unsigned FIFOFULL:1;
|
||||
unsigned ERROR:1;
|
||||
unsigned DERRNAKT:1;
|
||||
unsigned FLUSH:1;
|
||||
unsigned REQPKT:1;
|
||||
unsigned RXSTALL:1;
|
||||
unsigned CLRDT:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXCSRL_HOST_t;
|
||||
|
||||
/* RXCSRH Device - Receive endpoint Control Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned INCOMPRX:1;
|
||||
unsigned :2;
|
||||
unsigned DMAREQMODE:1;
|
||||
unsigned DISNYET:1;
|
||||
unsigned DMAREQEN:1;
|
||||
unsigned ISO:1;
|
||||
unsigned AUTOCLR:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXCSRH_DEVICE_t;
|
||||
|
||||
/* RXCSRH Host - Receive endpoint Control Status Register */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned INCOMPRX:1;
|
||||
unsigned DATATGGL:1;
|
||||
unsigned DATATWEN:1;
|
||||
unsigned DMAREQMD:1;
|
||||
unsigned PIDERR:1;
|
||||
unsigned DMAREQEN:1;
|
||||
unsigned AUTORQ:1;
|
||||
unsigned AUOTCLR:1;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXCSRH_HOST_t;
|
||||
|
||||
/* RXCOUNT - Amount of data pending in RX FIFO */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXCNT:14;
|
||||
unsigned :2;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint16_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXCOUNT_t;
|
||||
|
||||
/* TXTYPE - Specifies the target transmit endpoint */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TEP:4;
|
||||
unsigned PROTOCOL:2;
|
||||
unsigned SPEED:2;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_TXTYPE_t;
|
||||
|
||||
/* RXTYPE - Specifies the target receive endpoint */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TEP:4;
|
||||
unsigned PROTOCOL:2;
|
||||
unsigned SPEED:2;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint8_t w;
|
||||
};
|
||||
|
||||
} __USBHS_RXTYPE_t;
|
||||
|
||||
/* TXINTERVAL - Defines the polling interval */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t TXINTERV;
|
||||
|
||||
} __USBHS_TXINTERVAL_t;
|
||||
|
||||
/* RXINTERVAL - Defines the polling interval */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RXINTERV;
|
||||
|
||||
} __USBHS_RXINTERVAL_t;
|
||||
|
||||
/* TXMAXP - Maximum amount of data that can be transferred through a TX endpoint
|
||||
* */
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXMAXP:11;
|
||||
unsigned MULT:5;
|
||||
};
|
||||
uint16_t w;
|
||||
|
||||
} __USBHS_TXMAXP_t;
|
||||
|
||||
/* TXFIFOSZ - Size of the transmit endpoint FIFO */
|
||||
typedef struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXFIFOSZ:4;
|
||||
unsigned TXDPB:1;
|
||||
unsigned :3;
|
||||
|
||||
} __USBHS_TXFIFOSZ_t;
|
||||
|
||||
/* RXFIFOSZ - Size of the receive endpoint FIFO */
|
||||
typedef struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXFIFOSZ:4;
|
||||
unsigned RXDPB:1;
|
||||
unsigned :3;
|
||||
|
||||
} __USBHS_RXFIFOSZ_t;
|
||||
|
||||
/* TXFIFOADD - Start address of the transmit endpoint FIFO */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXFIFOAD:13;
|
||||
unsigned :3;
|
||||
};
|
||||
uint16_t w;
|
||||
|
||||
} __USBHS_TXFIFOADD_t;
|
||||
|
||||
/* RXFIFOADD - Start address of the receive endpoint FIFO */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXFIFOAD:13;
|
||||
unsigned :3;
|
||||
};
|
||||
uint16_t w;
|
||||
|
||||
} __USBHS_RXFIFOADD_t;
|
||||
|
||||
/* SOFTRST - Asserts NRSTO and NRSTOX */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned NRST:1;
|
||||
unsigned NRSTX:1;
|
||||
unsigned :6;
|
||||
};
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_SOFTRST_t;
|
||||
|
||||
/* TXFUNCADDR - Target address of transmit endpoint */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXFADDR:7;
|
||||
unsigned :1;
|
||||
};
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_TXFUNCADDR_t;
|
||||
|
||||
/* RXFUNCADDR - Target address of receive endpoint */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXFADDR:7;
|
||||
unsigned :1;
|
||||
};
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_RXFUNCADDR_t;
|
||||
|
||||
/* TXHUBADDR - Address of the hub to which the target transmit device endpoint
|
||||
* is connected */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXHUBADDR:7;
|
||||
unsigned MULTTRAN:1;
|
||||
};
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_TXHUBADDR_t;
|
||||
|
||||
/* RXHUBADDR - Address of the hub to which the target receive device endpoint is
|
||||
* connected */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXHUBADDR:7;
|
||||
unsigned MULTTRAN:1;
|
||||
};
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_RXHUBADDR_t;
|
||||
|
||||
/* TXHUBPORT - Address of the hub to which the target transmit device endpoint
|
||||
* is connected. */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned TXHUBPRT:7;
|
||||
unsigned :1;
|
||||
};
|
||||
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_TXHUBPORT_t;
|
||||
|
||||
/* RXHUBPORT - Address of the hub to which the target receive device endpoint
|
||||
* is connected. */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned RXHUBPRT:7;
|
||||
unsigned :1;
|
||||
};
|
||||
|
||||
uint8_t w;
|
||||
|
||||
} __USBHS_RXHUBPORT_t;
|
||||
|
||||
/* DMACONTROL - Configures a DMA channel */
|
||||
typedef union
|
||||
{
|
||||
struct __attribute__((packed))
|
||||
{
|
||||
unsigned DMAEN:1;
|
||||
unsigned DMADIR:1;
|
||||
unsigned DMAMODE:1;
|
||||
unsigned DMAIE:1;
|
||||
unsigned DMAEP:4;
|
||||
unsigned DMAERR:1;
|
||||
unsigned DMABRSTM:2;
|
||||
unsigned:21;
|
||||
};
|
||||
|
||||
uint32_t w;
|
||||
|
||||
} __USBHS_DMACNTL_t;
|
||||
|
||||
/* Endpoint Control and Status Register Set */
|
||||
typedef struct __attribute__((packed))
|
||||
{
|
||||
volatile __USBHS_TXMAXP_t TXMAXPbits;
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
union
|
||||
{
|
||||
volatile __USBHS_CSR0L_DEVICE_t CSR0L_DEVICEbits;
|
||||
volatile __USBHS_CSR0L_HOST_t CSR0L_HOSTbits;
|
||||
};
|
||||
union
|
||||
{
|
||||
volatile __USBHS_CSR0H_DEVICE_t CSR0H_DEVICEbits;
|
||||
volatile __USBHS_CSR0H_HOST_t CSR0H_HOSTbits;
|
||||
};
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
union
|
||||
{
|
||||
volatile __USBHS_TXCSRL_DEVICE_t TXCSRL_DEVICEbits;
|
||||
volatile __USBHS_TXCSRL_HOST_t TXCSRL_HOSTbits;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile __USBHS_TXCSRH_DEVICE_t TXCSRH_DEVICEbits;
|
||||
volatile __USBHS_TXCSRH_HOST_t TXCSRH_HOSTbits;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
volatile __USBHS_RXMAXP_t RXMAXPbits;
|
||||
|
||||
union
|
||||
{
|
||||
volatile __USBHS_RXCSRL_DEVICE_t RXCSRL_DEVICEbits;
|
||||
volatile __USBHS_RXCSRL_HOST_t RXCSRL_HOSTbits;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile __USBHS_RXCSRH_DEVICE_t RXCSRH_DEVICEbits;
|
||||
volatile __USBHS_RXCSRH_HOST_t RXCSRH_HOSTbits;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile __USBHS_COUNT0_t COUNT0bits;
|
||||
volatile __USBHS_RXCOUNT_t RXCOUNTbits;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile __USBHS_TYPE0_t TYPE0bits;
|
||||
volatile __USBHS_TXTYPE_t TXTYPEbits;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile uint8_t NAKLIMIT0;
|
||||
volatile __USBHS_TXINTERVAL_t TXINTERVALbits;
|
||||
};
|
||||
|
||||
volatile __USBHS_RXTYPE_t RXTYPEbits;
|
||||
volatile __USBHS_RXINTERVAL_t RXINTERVALbits;
|
||||
unsigned :8;
|
||||
union
|
||||
{
|
||||
volatile uint8_t CONFIGDATA;
|
||||
volatile uint8_t FIFOSIZE;
|
||||
};
|
||||
|
||||
} __USBHS_EPCSR_t;
|
||||
|
||||
/* Set of registers that configure the multi-point option */
|
||||
typedef struct __attribute__((packed))
|
||||
{
|
||||
volatile __USBHS_TXFUNCADDR_t TXFUNCADDRbits;
|
||||
unsigned :8;
|
||||
volatile __USBHS_TXHUBADDR_t TXHUBADDRbits;
|
||||
volatile __USBHS_TXHUBPORT_t TXHUBPORTbits;
|
||||
volatile __USBHS_RXFUNCADDR_t RXFUNCADDRbits;
|
||||
unsigned :8;
|
||||
volatile __USBHS_RXHUBADDR_t RXHUBADDRbits;
|
||||
volatile __USBHS_RXHUBPORT_t RXHUBPORTbits;
|
||||
|
||||
} __USBHS_TARGET_ADDR_t;
|
||||
|
||||
/* Set of registers that configure the DMA channel */
|
||||
typedef struct __attribute__((packed))
|
||||
{
|
||||
volatile __USBHS_DMACNTL_t DMACNTLbits;
|
||||
volatile uint32_t DMAADDR;
|
||||
volatile uint32_t DMACOUNT;
|
||||
volatile uint32_t pad;
|
||||
} __USBHS_DMA_CHANNEL_t;
|
||||
|
||||
/* USBHS module register set */
|
||||
typedef struct __attribute__((aligned(4),packed))
|
||||
{
|
||||
volatile __USBHS_FADDR_t FADDRbits;
|
||||
volatile __USBHS_POWER_t POWERbits;
|
||||
volatile uint16_t INTRTX;
|
||||
volatile uint16_t INTRRX;
|
||||
volatile __USBHS_INTRTXE_t INTRTXEbits;
|
||||
volatile __USBHS_INTRRXE_t INTRRXEbits;
|
||||
volatile uint8_t INTRUSB;
|
||||
volatile __USBHS_INTRUSBE_t INTRUSBEbits;
|
||||
volatile __USBHS_FRAME_t FRAMEbits;
|
||||
volatile __USBHS_INDEX_t INDEXbits;
|
||||
volatile __USBHS_TESTMODE_t TESTMODEbits;
|
||||
volatile __USBHS_EPCSR_t INDEXED_EPCSR;
|
||||
volatile uint32_t FIFO[16];
|
||||
volatile __USBHS_DEVCTL_t DEVCTLbits;
|
||||
volatile uint8_t MISC;
|
||||
volatile __USBHS_TXFIFOSZ_t TXFIFOSZbits;
|
||||
volatile __USBHS_RXFIFOSZ_t RXFIFOSZbits;
|
||||
|
||||
volatile __USBHS_TXFIFOADD_t TXFIFOADDbits;
|
||||
volatile __USBHS_RXFIFOADD_t RXFIFOADDbits;
|
||||
|
||||
volatile uint32_t VCONTROL;
|
||||
volatile uint16_t HWVERS;
|
||||
volatile uint8_t padding1[10];
|
||||
volatile uint8_t EPINFO;
|
||||
volatile uint8_t RAMINFO;
|
||||
volatile uint8_t LINKINFO;
|
||||
volatile uint8_t VPLEN;
|
||||
volatile uint8_t HS_EOF1;
|
||||
volatile uint8_t FS_EOF1;
|
||||
volatile uint8_t LS_EOF1;
|
||||
|
||||
volatile __USBHS_SOFTRST_t SOFTRSTbits;
|
||||
|
||||
volatile __USBHS_TARGET_ADDR_t TADDR[16];
|
||||
volatile __USBHS_EPCSR_t EPCSR[16];
|
||||
volatile uint32_t DMA_INTR;
|
||||
volatile __USBHS_DMA_CHANNEL_t DMA_CHANNEL[8];
|
||||
volatile uint32_t RQPKTXOUNT[16];
|
||||
|
||||
} usbhs_registers_t;
|
||||
|
||||
#endif
|
@ -42,6 +42,9 @@ enum {
|
||||
OHCI_MAX_ITD = 4
|
||||
};
|
||||
|
||||
#define ED_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
|
||||
#define GTD_MAX ED_MAX
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// OHCI Data Structure
|
||||
//--------------------------------------------------------------------+
|
||||
@ -159,11 +162,11 @@ typedef struct TU_ATTR_ALIGNED(256)
|
||||
struct {
|
||||
ohci_ed_t ed;
|
||||
ohci_gtd_t gtd;
|
||||
}control[CFG_TUH_DEVICE_MAX+1];
|
||||
}control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
|
||||
|
||||
// ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
|
||||
ohci_ed_t ed_pool[HCD_MAX_ENDPOINT];
|
||||
ohci_gtd_t gtd_pool[HCD_MAX_XFER];
|
||||
ohci_ed_t ed_pool[ED_MAX];
|
||||
ohci_gtd_t gtd_pool[GTD_MAX];
|
||||
|
||||
volatile uint16_t frame_number_hi;
|
||||
|
||||
|
@ -56,7 +56,7 @@ typedef struct hw_endpoint
|
||||
// Interrupt, bulk, etc
|
||||
uint8_t transfer_type;
|
||||
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
#if CFG_TUH_ENABLED
|
||||
// Only needed for host
|
||||
uint8_t dev_addr;
|
||||
|
||||
|
@ -91,6 +91,13 @@
|
||||
#include "stm32g4xx.h"
|
||||
#define PMA_LENGTH (1024u)
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
|
||||
#include "stm32wbxx.h"
|
||||
#define PMA_LENGTH (1024u)
|
||||
/* ST provided header has incorrect value */
|
||||
#undef USB_PMAADDR
|
||||
#define USB_PMAADDR USB1_PMAADDR
|
||||
|
||||
#else
|
||||
#error You are using an untested or unimplemented STM32 variant. Please update the driver.
|
||||
// This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
|
||||
|
@ -0,0 +1,643 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021 Koji KITAYAMA
|
||||
* Copyright (c) 2021 Tian Yunhao (t123yh)
|
||||
* Copyright (c) 2021 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_MUSB_DEF
|
||||
#define _TUSB_MUSB_DEF
|
||||
|
||||
|
||||
#define USBC_Readb(reg) (*(volatile unsigned char *)(reg))
|
||||
#define USBC_Readw(reg) (*(volatile unsigned short *)(reg))
|
||||
#define USBC_Readl(reg) (*(volatile unsigned long *)(reg))
|
||||
|
||||
#define USBC_Writeb(value, reg) (*(volatile unsigned char *)(reg) = (value))
|
||||
#define USBC_Writew(value, reg) (*(volatile unsigned short *)(reg) = (value))
|
||||
#define USBC_Writel(value, reg) (*(volatile unsigned long *)(reg) = (value))
|
||||
|
||||
|
||||
#define USBC_SetBit_Mask_b(reg,mask) do { \
|
||||
unsigned char _r = USBC_Readb(reg); \
|
||||
_r |= (unsigned char)(mask); \
|
||||
USBC_Writeb(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_SetBit_Mask_w(reg,mask) do { \
|
||||
unsigned short _r = USBC_Readw(reg); \
|
||||
_r |= (unsigned short)(mask); \
|
||||
USBC_Writew(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_SetBit_Mask_l(reg,mask) do { \
|
||||
unsigned int _r = USBC_Readl(reg); \
|
||||
_r |= (unsigned int)(mask); \
|
||||
USBC_Writel(_r,reg); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#define USBC_ClrBit_Mask_b(reg,mask) do { \
|
||||
unsigned char _r = USBC_Readb(reg); \
|
||||
_r &= (~(unsigned char)(mask)); \
|
||||
USBC_Writeb(_r,reg); \
|
||||
}while(0);
|
||||
#define USBC_ClrBit_Mask_w(reg,mask) do { \
|
||||
unsigned short _r = USBC_Readw(reg); \
|
||||
_r &= (~(unsigned short)(mask)); \
|
||||
USBC_Writew(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_ClrBit_Mask_l(reg,mask) do { \
|
||||
unsigned int _r = USBC_Readl(reg); \
|
||||
_r &= (~(unsigned int)(mask)); \
|
||||
USBC_Writel(_r,reg); \
|
||||
}while(0)
|
||||
#define USBC_REG_test_bit_b(bp, reg) (USBC_Readb(reg) & (1 << (bp)))
|
||||
#define USBC_REG_test_bit_w(bp, reg) (USBC_Readw(reg) & (1 << (bp)))
|
||||
#define USBC_REG_test_bit_l(bp, reg) (USBC_Readl(reg) & (1 << (bp)))
|
||||
|
||||
#define USBC_REG_set_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) | (1 << (bp))) , (reg)))
|
||||
#define USBC_REG_set_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) | (1 << (bp))) , (reg)))
|
||||
#define USBC_REG_set_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) | (1 << (bp))) , (reg)))
|
||||
|
||||
#define USBC_REG_clear_bit_b(bp, reg) (USBC_Writeb((USBC_Readb(reg) & (~ (1 << (bp)))) , (reg)))
|
||||
#define USBC_REG_clear_bit_w(bp, reg) (USBC_Writew((USBC_Readw(reg) & (~ (1 << (bp)))) , (reg)))
|
||||
#define USBC_REG_clear_bit_l(bp, reg) (USBC_Writel((USBC_Readl(reg) & (~ (1 << (bp)))) , (reg)))
|
||||
|
||||
#define SW_UDC_EPNUMS 3
|
||||
|
||||
#define SUNXI_SRAMC_BASE 0x01c00000
|
||||
//---------------------------------------------------------------
|
||||
// reg base
|
||||
//---------------------------------------------------------------
|
||||
#define USBC0_BASE 0x01c13000
|
||||
#define USBC1_BASE 0x01c14000
|
||||
#define USBC2_BASE 0x01c1E000
|
||||
|
||||
//Some reg whithin musb
|
||||
#define USBPHY_CLK_REG 0x01c200CC
|
||||
#define USBPHY_CLK_RST_BIT 0
|
||||
#define USBPHY_CLK_GAT_BIT 1
|
||||
|
||||
#define BUS_CLK_RST_REG 0x01c202c0 //Bus Clock Reset Register Bit24 : USB CLK RST
|
||||
#define BUS_RST_USB_BIT 24
|
||||
|
||||
#define BUS_CLK_GATE0_REG 0x01c20060 //Bus Clock Gating Register Bit24 : USB CLK GATE 0: Mask 1 : Pass
|
||||
#define BUS_CLK_USB_BIT 24
|
||||
|
||||
//#define USB_INTR
|
||||
|
||||
#define NDMA_CFG_REG
|
||||
//-----------------------------------------------------------------------
|
||||
// musb reg offset
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define USBC_REG_o_FADDR 0x0098
|
||||
#define USBC_REG_o_PCTL 0x0040
|
||||
#define USBC_REG_o_INTTx 0x0044
|
||||
#define USBC_REG_o_INTRx 0x0046
|
||||
#define USBC_REG_o_INTTxE 0x0048
|
||||
#define USBC_REG_o_INTRxE 0x004A
|
||||
#define USBC_REG_o_INTUSB 0x004C
|
||||
#define USBC_REG_o_INTUSBE 0x0050
|
||||
#define USBC_REG_o_FRNUM 0x0054
|
||||
#define USBC_REG_o_EPIND 0x0042
|
||||
#define USBC_REG_o_TMCTL 0x007C
|
||||
|
||||
#define USBC_REG_o_TXMAXP 0x0080
|
||||
#define USBC_REG_o_CSR0 0x0082
|
||||
#define USBC_REG_o_TXCSR 0x0082
|
||||
#define USBC_REG_o_RXMAXP 0x0084
|
||||
#define USBC_REG_o_RXCSR 0x0086
|
||||
#define USBC_REG_o_COUNT0 0x0088
|
||||
#define USBC_REG_o_RXCOUNT 0x0088
|
||||
#define USBC_REG_o_EP0TYPE 0x008C
|
||||
#define USBC_REG_o_TXTYPE 0x008C
|
||||
#define USBC_REG_o_NAKLIMIT0 0x008D
|
||||
#define USBC_REG_o_TXINTERVAL 0x008D
|
||||
#define USBC_REG_o_RXTYPE 0x008E
|
||||
#define USBC_REG_o_RXINTERVAL 0x008F
|
||||
|
||||
//#define USBC_REG_o_CONFIGDATA 0x001F //
|
||||
|
||||
#define USBC_REG_o_EPFIFO0 0x0000
|
||||
#define USBC_REG_o_EPFIFO1 0x0004
|
||||
#define USBC_REG_o_EPFIFO2 0x0008
|
||||
#define USBC_REG_o_EPFIFO3 0x000C
|
||||
#define USBC_REG_o_EPFIFO4 0x0010
|
||||
#define USBC_REG_o_EPFIFO5 0x0014
|
||||
#define USBC_REG_o_EPFIFOx(n) (0x0000 + (n<<2))
|
||||
|
||||
#define USBC_REG_o_DEVCTL 0x0041
|
||||
|
||||
#define USBC_REG_o_TXFIFOSZ 0x0090
|
||||
#define USBC_REG_o_RXFIFOSZ 0x0094
|
||||
#define USBC_REG_o_TXFIFOAD 0x0092
|
||||
#define USBC_REG_o_RXFIFOAD 0x0096
|
||||
|
||||
#define USBC_REG_o_VEND0 0x0043
|
||||
#define USBC_REG_o_VEND1 0x007D
|
||||
#define USBC_REG_o_VEND3 0x007E
|
||||
|
||||
//#define USBC_REG_o_PHYCTL 0x006C
|
||||
#define USBC_REG_o_EPINFO 0x0078
|
||||
#define USBC_REG_o_RAMINFO 0x0079
|
||||
#define USBC_REG_o_LINKINFO 0x007A
|
||||
#define USBC_REG_o_VPLEN 0x007B
|
||||
#define USBC_REG_o_HSEOF 0x007C
|
||||
#define USBC_REG_o_FSEOF 0x007D
|
||||
#define USBC_REG_o_LSEOF 0x007E
|
||||
|
||||
//new
|
||||
#define USBC_REG_o_FADDR0 0x0098
|
||||
#define USBC_REG_o_HADDR0 0x009A
|
||||
#define USBC_REG_o_HPORT0 0x009B
|
||||
#define USBC_REG_o_TXFADDRx 0x0098
|
||||
#define USBC_REG_o_TXHADDRx 0x009A
|
||||
#define USBC_REG_o_TXHPORTx 0x009B
|
||||
#define USBC_REG_o_RXFADDRx 0x009C
|
||||
#define USBC_REG_o_RXHADDRx 0x009E
|
||||
#define USBC_REG_o_RXHPORTx 0x009F
|
||||
|
||||
|
||||
#define USBC_REG_o_RPCOUNT 0x008A
|
||||
|
||||
//new
|
||||
#define USBC_REG_o_ISCR 0x0400
|
||||
#define USBC_REG_o_PHYCTL 0x0404
|
||||
#define USBC_REG_o_PHYBIST 0x0408
|
||||
#define USBC_REG_o_PHYTUNE 0x040c
|
||||
|
||||
#define USBC_REG_o_CSR 0x0410
|
||||
|
||||
#define USBC_REG_o_PMU_IRQ 0x0800
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// registers
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define USBC_REG_FADDR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FADDR )
|
||||
#define USBC_REG_PCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PCTL )
|
||||
#define USBC_REG_INTTx(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTTx )
|
||||
#define USBC_REG_INTRx(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTRx )
|
||||
#define USBC_REG_INTTxE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTTxE )
|
||||
#define USBC_REG_INTRxE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTRxE )
|
||||
#define USBC_REG_INTUSB(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTUSB )
|
||||
#define USBC_REG_INTUSBE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_INTUSBE )
|
||||
#define USBC_REG_FRNUM(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FRNUM )
|
||||
#define USBC_REG_EPIND(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPIND )
|
||||
#define USBC_REG_TMCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TMCTL )
|
||||
#define USBC_REG_TXMAXP(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXMAXP )
|
||||
|
||||
#define USBC_REG_CSR0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_CSR0 )
|
||||
#define USBC_REG_TXCSR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXCSR )
|
||||
|
||||
#define USBC_REG_RXMAXP(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXMAXP )
|
||||
#define USBC_REG_RXCSR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXCSR )
|
||||
|
||||
#define USBC_REG_COUNT0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_COUNT0 )
|
||||
#define USBC_REG_RXCOUNT(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXCOUNT )
|
||||
|
||||
#define USBC_REG_EP0TYPE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EP0TYPE )
|
||||
#define USBC_REG_TXTYPE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXTYPE )
|
||||
|
||||
#define USBC_REG_NAKLIMIT0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_NAKLIMIT0 )
|
||||
#define USBC_REG_TXINTERVAL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXINTERVAL )
|
||||
|
||||
#define USBC_REG_RXTYPE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXTYPE )
|
||||
#define USBC_REG_RXINTERVAL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXINTERVAL )
|
||||
//#define USBC_REG_CONFIGDATA(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_CONFIGDATA )
|
||||
#define USBC_REG_EPFIFO0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO0 )
|
||||
#define USBC_REG_EPFIFO1(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO1 )
|
||||
#define USBC_REG_EPFIFO2(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO2 )
|
||||
#define USBC_REG_EPFIFO3(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO3 )
|
||||
#define USBC_REG_EPFIFO4(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO4 )
|
||||
#define USBC_REG_EPFIFO5(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPFIFO5 )
|
||||
#define USBC_REG_EPFIFOx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_EPFIFOx(n) )
|
||||
#define USBC_REG_DEVCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_DEVCTL )
|
||||
#define USBC_REG_TXFIFOSZ(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXFIFOSZ )
|
||||
#define USBC_REG_RXFIFOSZ(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXFIFOSZ )
|
||||
#define USBC_REG_TXFIFOAD(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_TXFIFOAD )
|
||||
#define USBC_REG_RXFIFOAD(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RXFIFOAD )
|
||||
#define USBC_REG_VEND0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_VEND0 )
|
||||
#define USBC_REG_VEND1(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_VEND1 )
|
||||
#define USBC_REG_EPINFO(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_EPINFO )
|
||||
#define USBC_REG_RAMINFO(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_RAMINFO )
|
||||
#define USBC_REG_LINKINFO(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_LINKINFO )
|
||||
#define USBC_REG_VPLEN(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_VPLEN )
|
||||
#define USBC_REG_HSEOF(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_HSEOF )
|
||||
#define USBC_REG_FSEOF(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FSEOF )
|
||||
#define USBC_REG_LSEOF(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_LSEOF )
|
||||
|
||||
#define USBC_REG_FADDR0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_FADDR0 )
|
||||
#define USBC_REG_HADDR0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_HADDR0 )
|
||||
#define USBC_REG_HPORT0(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_HPORT0 )
|
||||
|
||||
#define USBC_REG_TXFADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_TXFADDRx )
|
||||
#define USBC_REG_TXHADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_TXHADDRx )
|
||||
#define USBC_REG_TXHPORTx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_TXHPORTx )
|
||||
#define USBC_REG_RXFADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RXFADDRx )
|
||||
#define USBC_REG_RXHADDRx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RXHADDRx )
|
||||
#define USBC_REG_RXHPORTx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RXHPORTx )
|
||||
|
||||
#define USBC_REG_RPCOUNTx(usbc_base_addr, n) ((usbc_base_addr) + USBC_REG_o_RPCOUNT )
|
||||
|
||||
#define USBC_REG_ISCR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_ISCR )
|
||||
#define USBC_REG_PHYCTL(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PHYCTL )
|
||||
#define USBC_REG_PHYBIST(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PHYBIST )
|
||||
#define USBC_REG_PHYTUNE(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PHYTUNE )
|
||||
#define USBC_REG_PMU_IRQ(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_PMU_IRQ )
|
||||
#define USBC_REG_CSR(usbc_base_addr) ((usbc_base_addr) + USBC_REG_o_CSR)
|
||||
//-----------------------------------------------------------------------
|
||||
// bit position
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
/* USB Power Control for Host only */
|
||||
#define USBC_BP_POWER_H_HIGH_SPEED_EN 5
|
||||
#define USBC_BP_POWER_H_HIGH_SPEED_FLAG 4
|
||||
#define USBC_BP_POWER_H_RESET 3
|
||||
#define USBC_BP_POWER_H_RESUME 2
|
||||
#define USBC_BP_POWER_H_SUSPEND 1
|
||||
#define USBC_BP_POWER_H_SUEPEND_EN 0
|
||||
|
||||
/* USB Power Control for device only */
|
||||
#define USBC_BP_POWER_D_ISO_UPDATE_EN 7
|
||||
#define USBC_BP_POWER_D_SOFT_CONNECT 6
|
||||
#define USBC_BP_POWER_D_HIGH_SPEED_EN 5
|
||||
#define USBC_BP_POWER_D_HIGH_SPEED_FLAG 4
|
||||
#define USBC_BP_POWER_D_RESET_FLAG 3
|
||||
#define USBC_BP_POWER_D_RESUME 2
|
||||
#define USBC_BP_POWER_D_SUSPEND 1
|
||||
#define USBC_BP_POWER_D_ENABLE_SUSPENDM 0
|
||||
|
||||
/* interrupt flags for ep0 and the Tx ep1~4 */
|
||||
#define USBC_BP_INTTx_FLAG_EP5 5
|
||||
#define USBC_BP_INTTx_FLAG_EP4 4
|
||||
#define USBC_BP_INTTx_FLAG_EP3 3
|
||||
#define USBC_BP_INTTx_FLAG_EP2 2
|
||||
#define USBC_BP_INTTx_FLAG_EP1 1
|
||||
#define USBC_BP_INTTx_FLAG_EP0 0
|
||||
|
||||
/* interrupt flags for Rx ep1~4 */
|
||||
#define USBC_BP_INTRx_FLAG_EP5 5
|
||||
#define USBC_BP_INTRx_FLAG_EP4 4
|
||||
#define USBC_BP_INTRx_FLAG_EP3 3
|
||||
#define USBC_BP_INTRx_FLAG_EP2 2
|
||||
#define USBC_BP_INTRx_FLAG_EP1 1
|
||||
|
||||
/* interrupt enable for Tx ep0~4 */
|
||||
#define USBC_BP_INTTxE_EN_EP5 5
|
||||
#define USBC_BP_INTTxE_EN_EP4 4
|
||||
#define USBC_BP_INTTxE_EN_EP3 3
|
||||
#define USBC_BP_INTTxE_EN_EP2 2
|
||||
#define USBC_BP_INTTxE_EN_EP1 1
|
||||
#define USBC_BP_INTTxE_EN_EP0 0
|
||||
|
||||
/* interrupt enable for Rx ep1~4 */
|
||||
#define USBC_BP_INTRxE_EN_EP5 5
|
||||
#define USBC_BP_INTRxE_EN_EP4 4
|
||||
#define USBC_BP_INTRxE_EN_EP3 3
|
||||
#define USBC_BP_INTRxE_EN_EP2 2
|
||||
#define USBC_BP_INTRxE_EN_EP1 1
|
||||
|
||||
/* USB interrupt */
|
||||
#define USBC_BP_INTUSB_VBUS_ERROR 7
|
||||
#define USBC_BP_INTUSB_SESSION_REQ 6
|
||||
#define USBC_BP_INTUSB_DISCONNECT 5
|
||||
#define USBC_BP_INTUSB_CONNECT 4
|
||||
#define USBC_BP_INTUSB_SOF 3
|
||||
#define USBC_BP_INTUSB_RESET 2
|
||||
#define USBC_BP_INTUSB_RESUME 1
|
||||
#define USBC_BP_INTUSB_SUSPEND 0
|
||||
|
||||
/* USB interrupt enable */
|
||||
#define USBC_BP_INTUSBE_EN_VBUS_ERROR 7
|
||||
#define USBC_BP_INTUSBE_EN_SESSION_REQ 6
|
||||
#define USBC_BP_INTUSBE_EN_DISCONNECT 5
|
||||
#define USBC_BP_INTUSBE_EN_CONNECT 4
|
||||
#define USBC_BP_INTUSBE_EN_SOF 3
|
||||
#define USBC_BP_INTUSBE_EN_RESET 2
|
||||
#define USBC_BP_INTUSBE_EN_RESUME 1
|
||||
#define USBC_BP_INTUSBE_EN_SUSPEND 0
|
||||
|
||||
/* Test Mode Control */
|
||||
#define USBC_BP_TMCTL_FORCE_HOST 7
|
||||
#define USBC_BP_TMCTL_FIFO_ACCESS 6
|
||||
#define USBC_BP_TMCTL_FORCE_FS 5
|
||||
#define USBC_BP_TMCTL_FORCE_HS 4
|
||||
#define USBC_BP_TMCTL_TEST_PACKET 3
|
||||
#define USBC_BP_TMCTL_TEST_K 2
|
||||
#define USBC_BP_TMCTL_TEST_J 1
|
||||
#define USBC_BP_TMCTL_TEST_SE0_NAK 0
|
||||
|
||||
/* Tx Max packet */
|
||||
#define USBC_BP_TXMAXP_PACKET_COUNT 11
|
||||
#define USBC_BP_TXMAXP_MAXIMUM_PAYLOAD 0
|
||||
|
||||
/* Control and Status Register for ep0 for Host only */
|
||||
#define USBC_BP_CSR0_H_DisPing 11
|
||||
#define USBC_BP_CSR0_H_FlushFIFO 8
|
||||
#define USBC_BP_CSR0_H_NAK_Timeout 7
|
||||
#define USBC_BP_CSR0_H_StatusPkt 6
|
||||
#define USBC_BP_CSR0_H_ReqPkt 5
|
||||
#define USBC_BP_CSR0_H_Error 4
|
||||
#define USBC_BP_CSR0_H_SetupPkt 3
|
||||
#define USBC_BP_CSR0_H_RxStall 2
|
||||
#define USBC_BP_CSR0_H_TxPkRdy 1
|
||||
#define USBC_BP_CSR0_H_RxPkRdy 0
|
||||
|
||||
/* Control and Status Register for ep0 for device only */
|
||||
#define USBC_BP_CSR0_D_FLUSH_FIFO 8
|
||||
#define USBC_BP_CSR0_D_SERVICED_SETUP_END 7
|
||||
#define USBC_BP_CSR0_D_SERVICED_RX_PKT_READY 6
|
||||
#define USBC_BP_CSR0_D_SEND_STALL 5
|
||||
#define USBC_BP_CSR0_D_SETUP_END 4
|
||||
#define USBC_BP_CSR0_D_DATA_END 3
|
||||
#define USBC_BP_CSR0_D_SENT_STALL 2
|
||||
#define USBC_BP_CSR0_D_TX_PKT_READY 1
|
||||
#define USBC_BP_CSR0_D_RX_PKT_READY 0
|
||||
|
||||
/* Tx ep Control and Status Register for Host only */
|
||||
#define USBC_BP_TXCSR_H_AUTOSET 15
|
||||
#define USBC_BP_TXCSR_H_RESERVED 14
|
||||
#define USBC_BP_TXCSR_H_MODE 13
|
||||
#define USBC_BP_TXCSR_H_DMA_REQ_EN 12
|
||||
#define USBC_BP_TXCSR_H_FORCE_DATA_TOGGLE 11
|
||||
#define USBC_BP_TXCSR_H_DMA_REQ_MODE 10
|
||||
#define USBC_BP_TXCSR_H_NAK_TIMEOUT 7
|
||||
#define USBC_BP_TXCSR_H_CLEAR_DATA_TOGGLE 6
|
||||
#define USBC_BP_TXCSR_H_TX_STALL 5
|
||||
#define USBC_BP_TXCSR_H_FLUSH_FIFO 3
|
||||
#define USBC_BP_TXCSR_H_ERROR 2
|
||||
#define USBC_BP_TXCSR_H_FIFO_NOT_EMPTY 1
|
||||
#define USBC_BP_TXCSR_H_TX_READY 0
|
||||
|
||||
/* Tx ep Control and Status Register for Device only */
|
||||
#define USBC_BP_TXCSR_D_AUTOSET 15
|
||||
#define USBC_BP_TXCSR_D_ISO 14
|
||||
#define USBC_BP_TXCSR_D_MODE 13
|
||||
#define USBC_BP_TXCSR_D_DMA_REQ_EN 12
|
||||
#define USBC_BP_TXCSR_D_FORCE_DATA_TOGGLE 11
|
||||
#define USBC_BP_TXCSR_D_DMA_REQ_MODE 10
|
||||
#define USBC_BP_TXCSR_D_INCOMPLETE 7
|
||||
#define USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE 6
|
||||
#define USBC_BP_TXCSR_D_SENT_STALL 5
|
||||
#define USBC_BP_TXCSR_D_SEND_STALL 4
|
||||
#define USBC_BP_TXCSR_D_FLUSH_FIFO 3
|
||||
#define USBC_BP_TXCSR_D_UNDER_RUN 2
|
||||
#define USBC_BP_TXCSR_D_FIFO_NOT_EMPTY 1
|
||||
#define USBC_BP_TXCSR_D_TX_READY 0
|
||||
|
||||
/* Rx Max Packet */
|
||||
#define USBC_BP_RXMAXP_PACKET_COUNT 11
|
||||
#define USBC_BP_RXMAXP_MAXIMUM_PAYLOAD 0
|
||||
|
||||
/* Rx ep Control and Status Register for Host only */
|
||||
#define USBC_BP_RXCSR_H_AUTO_CLEAR 15
|
||||
#define USBC_BP_RXCSR_H_AUTO_REQ 14
|
||||
#define USBC_BP_RXCSR_H_DMA_REQ_EN 13
|
||||
#define USBC_BP_RXCSR_H_PID_ERROR 12
|
||||
#define USBC_BP_RXCSR_H_DMA_REQ_MODE 11
|
||||
|
||||
#define USBC_BP_RXCSR_H_INCOMPLETE 8
|
||||
#define USBC_BP_RXCSR_H_CLEAR_DATA_TOGGLE 7
|
||||
#define USBC_BP_RXCSR_H_RX_STALL 6
|
||||
#define USBC_BP_RXCSR_H_REQ_PACKET 5
|
||||
#define USBC_BP_RXCSR_H_FLUSH_FIFO 4
|
||||
#define USBC_BP_RXCSR_H_NAK_TIMEOUT 3
|
||||
#define USBC_BP_RXCSR_H_ERROR 2
|
||||
#define USBC_BP_RXCSR_H_FIFO_FULL 1
|
||||
#define USBC_BP_RXCSR_H_RX_PKT_READY 0
|
||||
|
||||
/* Rx ep Control and Status Register for Device only */
|
||||
#define USBC_BP_RXCSR_D_AUTO_CLEAR 15
|
||||
#define USBC_BP_RXCSR_D_ISO 14
|
||||
#define USBC_BP_RXCSR_D_DMA_REQ_EN 13
|
||||
#define USBC_BP_RXCSR_D_DISABLE_NYET 12
|
||||
#define USBC_BP_RXCSR_D_DMA_REQ_MODE 11
|
||||
|
||||
#define USBC_BP_RXCSR_D_INCOMPLETE 8
|
||||
#define USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE 7
|
||||
#define USBC_BP_RXCSR_D_SENT_STALL 6
|
||||
#define USBC_BP_RXCSR_D_SEND_STALL 5
|
||||
#define USBC_BP_RXCSR_D_FLUSH_FIFO 4
|
||||
#define USBC_BP_RXCSR_D_DATA_ERROR 3
|
||||
#define USBC_BP_RXCSR_D_OVERRUN 2
|
||||
#define USBC_BP_RXCSR_D_FIFO_FULL 1
|
||||
#define USBC_BP_RXCSR_D_RX_PKT_READY 0
|
||||
|
||||
/* Tx Type Register for host only */
|
||||
#define USBC_BP_TXTYPE_SPEED 6 //new
|
||||
#define USBC_BP_TXTYPE_PROROCOL 4
|
||||
#define USBC_BP_TXTYPE_TARGET_EP_NUM 0
|
||||
|
||||
/* Rx Type Register for host only */
|
||||
#define USBC_BP_RXTYPE_SPEED 6 //new
|
||||
#define USBC_BP_RXTYPE_PROROCOL 4
|
||||
#define USBC_BP_RXTYPE_TARGET_EP_NUM 0
|
||||
|
||||
/* Core Configueation */
|
||||
#define USBC_BP_CONFIGDATA_MPRXE 7
|
||||
#define USBC_BP_CONFIGDATA_MPTXE 6
|
||||
#define USBC_BP_CONFIGDATA_BIGENDIAN 5
|
||||
#define USBC_BP_CONFIGDATA_HBRXE 4
|
||||
#define USBC_BP_CONFIGDATA_HBTXE 3
|
||||
#define USBC_BP_CONFIGDATA_DYNFIFO_SIZING 2
|
||||
#define USBC_BP_CONFIGDATA_SOFTCONE 1
|
||||
#define USBC_BP_CONFIGDATA_UTMI_DATAWIDTH 0
|
||||
|
||||
/* OTG Device Control */
|
||||
#define USBC_BP_DEVCTL_B_DEVICE 7
|
||||
#define USBC_BP_DEVCTL_FS_DEV 6
|
||||
#define USBC_BP_DEVCTL_LS_DEV 5
|
||||
|
||||
#define USBC_BP_DEVCTL_VBUS 3
|
||||
#define USBC_BP_DEVCTL_HOST_MODE 2
|
||||
#define USBC_BP_DEVCTL_HOST_REQ 1
|
||||
#define USBC_BP_DEVCTL_SESSION 0
|
||||
|
||||
/* Tx EP FIFO size control */
|
||||
#define USBC_BP_TXFIFOSZ_DPB 4
|
||||
#define USBC_BP_TXFIFOSZ_SZ 0
|
||||
|
||||
/* Rx EP FIFO size control */
|
||||
#define USBC_BP_RXFIFOSZ_DPB 4
|
||||
#define USBC_BP_RXFIFOSZ_SZ 0
|
||||
|
||||
/* vendor0 */
|
||||
#define USBC_BP_VEND0_DRQ_SEL 1
|
||||
#define USBC_BP_VEND0_BUS_SEL 0
|
||||
|
||||
/* hub address */
|
||||
#define USBC_BP_HADDR_MULTI_TT 7
|
||||
|
||||
/* Interface Status and Control */
|
||||
#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
|
||||
#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
|
||||
#define USBC_BP_ISCR_EXT_ID_STATUS 28
|
||||
#define USBC_BP_ISCR_EXT_DM_STATUS 27
|
||||
#define USBC_BP_ISCR_EXT_DP_STATUS 26
|
||||
#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
|
||||
#define USBC_BP_ISCR_MERGED_ID_STATUS 24
|
||||
|
||||
#define USBC_BP_ISCR_ID_PULLUP_EN 17
|
||||
#define USBC_BP_ISCR_DPDM_PULLUP_EN 16
|
||||
#define USBC_BP_ISCR_FORCE_ID 14
|
||||
#define USBC_BP_ISCR_FORCE_VBUS_VALID 12
|
||||
#define USBC_BP_ISCR_VBUS_VALID_SRC 10
|
||||
|
||||
#define USBC_BP_ISCR_HOSC_EN 7
|
||||
#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
|
||||
#define USBC_BP_ISCR_ID_CHANGE_DETECT 5
|
||||
#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
|
||||
#define USBC_BP_ISCR_IRQ_ENABLE 3
|
||||
#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
|
||||
#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
|
||||
#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
|
||||
|
||||
|
||||
#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
|
||||
#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
|
||||
#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
|
||||
#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
|
||||
//-----------------------------------------------------------------------
|
||||
// <20>Զ<EFBFBD><D4B6><EFBFBD>
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
/* usb<73><62>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD> */
|
||||
#define USBC_MAX_CTL_NUM 1
|
||||
#define USBC_MAX_EP_NUM 3 //ep0~2, ep<65>ĸ<EFBFBD><C4B8><EFBFBD>
|
||||
#define USBC_MAX_FIFO_SIZE (2 * 1024)
|
||||
|
||||
/* usb OTG mode */
|
||||
#define USBC_OTG_HOST 0
|
||||
#define USBC_OTG_DEVICE 1
|
||||
|
||||
/* usb device type */
|
||||
#define USBC_DEVICE_HSDEV 0
|
||||
#define USBC_DEVICE_FSDEV 1
|
||||
#define USBC_DEVICE_LSDEV 2
|
||||
|
||||
/* usb transfer type */
|
||||
#define USBC_TS_TYPE_IDLE 0
|
||||
#define USBC_TS_TYPE_CTRL 1
|
||||
#define USBC_TS_TYPE_ISO 2
|
||||
#define USBC_TS_TYPE_INT 3
|
||||
#define USBC_TS_TYPE_BULK 4
|
||||
|
||||
/* usb transfer mode */
|
||||
#define USBC_TS_MODE_UNKOWN 0
|
||||
#define USBC_TS_MODE_LS 1
|
||||
#define USBC_TS_MODE_FS 2
|
||||
#define USBC_TS_MODE_HS 3
|
||||
|
||||
/* usb Vbus status */
|
||||
#define USBC_VBUS_STATUS_BELOW_SESSIONEND 0
|
||||
#define USBC_VBUS_STATUS_ABOVE_SESSIONEND_BELOW_AVALID 1
|
||||
#define USBC_VBUS_STATUS_ABOVE_AVALID_BELOW_VBUSVALID 2
|
||||
#define USBC_VBUS_STATUS_ABOVE_VBUSVALID 3
|
||||
|
||||
/* usb io type */
|
||||
#define USBC_IO_TYPE_PIO 0
|
||||
#define USBC_IO_TYPE_DMA 1
|
||||
|
||||
/* usb ep type */
|
||||
#define USBC_EP_TYPE_IDLE 0
|
||||
#define USBC_EP_TYPE_EP0 1
|
||||
#define USBC_EP_TYPE_TX 2
|
||||
#define USBC_EP_TYPE_RX 3
|
||||
|
||||
/* usb id type */
|
||||
#define USBC_ID_TYPE_DISABLE 0
|
||||
#define USBC_ID_TYPE_HOST 1
|
||||
#define USBC_ID_TYPE_DEVICE 2
|
||||
|
||||
/* usb vbus valid type */
|
||||
#define USBC_VBUS_TYPE_DISABLE 0
|
||||
#define USBC_VBUS_TYPE_LOW 1
|
||||
#define USBC_VBUS_TYPE_HIGH 2
|
||||
|
||||
/* usb a valid source */
|
||||
#define USBC_A_VALID_SOURCE_UTMI_AVALID 0
|
||||
#define USBC_A_VALID_SOURCE_UTMI_VBUS 1
|
||||
|
||||
/* usb device switch */
|
||||
#define USBC_DEVICE_SWITCH_OFF 0
|
||||
#define USBC_DEVICE_SWITCH_ON 1
|
||||
|
||||
/* usb fifo config mode */
|
||||
#define USBC_FIFO_MODE_4K 0
|
||||
#define USBC_FIFO_MODE_8K 1
|
||||
|
||||
/*
|
||||
**************************************************
|
||||
* usb interrupt mask
|
||||
*
|
||||
**************************************************
|
||||
*/
|
||||
|
||||
/* interrupt flags for ep0 and the Tx ep1~4 */
|
||||
#define USBC_INTTx_FLAG_EP5 (1 << USBC_BP_INTTx_FLAG_EP5)
|
||||
#define USBC_INTTx_FLAG_EP4 (1 << USBC_BP_INTTx_FLAG_EP4)
|
||||
#define USBC_INTTx_FLAG_EP3 (1 << USBC_BP_INTTx_FLAG_EP3)
|
||||
#define USBC_INTTx_FLAG_EP2 (1 << USBC_BP_INTTx_FLAG_EP2)
|
||||
#define USBC_INTTx_FLAG_EP1 (1 << USBC_BP_INTTx_FLAG_EP1)
|
||||
#define USBC_INTTx_FLAG_EP0 (1 << USBC_BP_INTTx_FLAG_EP0)
|
||||
|
||||
/* interrupt flags for Rx ep1~4 */
|
||||
#define USBC_INTRx_FLAG_EP5 (1 << USBC_BP_INTRx_FLAG_EP5)
|
||||
#define USBC_INTRx_FLAG_EP4 (1 << USBC_BP_INTRx_FLAG_EP4)
|
||||
#define USBC_INTRx_FLAG_EP3 (1 << USBC_BP_INTRx_FLAG_EP3)
|
||||
#define USBC_INTRx_FLAG_EP2 (1 << USBC_BP_INTRx_FLAG_EP2)
|
||||
#define USBC_INTRx_FLAG_EP1 (1 << USBC_BP_INTRx_FLAG_EP1)
|
||||
|
||||
/* USB interrupt */
|
||||
#define USBC_INTUSB_VBUS_ERROR (1 << USBC_BP_INTUSB_VBUS_ERROR)
|
||||
#define USBC_INTUSB_SESSION_REQ (1 << USBC_BP_INTUSB_SESSION_REQ)
|
||||
#define USBC_INTUSB_DISCONNECT (1 << USBC_BP_INTUSB_DISCONNECT)
|
||||
#define USBC_INTUSB_CONNECT (1 << USBC_BP_INTUSB_CONNECT)
|
||||
#define USBC_INTUSB_SOF (1 << USBC_BP_INTUSB_SOF)
|
||||
#define USBC_INTUSB_RESET (1 << USBC_BP_INTUSB_RESET)
|
||||
#define USBC_INTUSB_RESUME (1 << USBC_BP_INTUSB_RESUME)
|
||||
#define USBC_INTUSB_SUSPEND (1 << USBC_BP_INTUSB_SUSPEND)
|
||||
|
||||
#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
|
||||
#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
|
||||
#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
|
||||
#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
|
||||
#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
|
||||
#define USB_CSRL0_STALL 0x00000020 // Send Stall
|
||||
#define USB_CSRL0_SETEND 0x00000010 // Setup End
|
||||
#define USB_CSRL0_ERROR 0x00000010 // Error
|
||||
#define USB_CSRL0_DATAEND 0x00000008 // Data End
|
||||
#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
|
||||
#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
|
||||
#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
|
||||
#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
|
||||
|
||||
#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
|
||||
#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
|
||||
|
||||
#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
|
||||
#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
|
||||
|
||||
#endif
|
@ -986,16 +986,16 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size");
|
||||
|
||||
/******************** Bit definition for OTG register ********************/
|
||||
#define GNPTXFSIZ_NPTXFSA_Pos (0U)
|
||||
#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << NPTXFSA_Pos) // 0x0000FFFF */
|
||||
#define GNPTXFSIZ_NPTXFSA_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos) // 0x0000FFFF */
|
||||
#define GNPTXFSIZ_NPTXFSA GNPTXFSIZ_NPTXFSA_Msk // Nonperiodic transmit RAM start address */
|
||||
#define GNPTXFSIZ_NPTXFD_Pos (16U)
|
||||
#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << NPTXFD_Pos) // 0xFFFF0000 */
|
||||
#define GNPTXFSIZ_NPTXFD_Msk (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos) // 0xFFFF0000 */
|
||||
#define GNPTXFSIZ_NPTXFD GNPTXFSIZ_NPTXFD_Msk // Nonperiodic TxFIFO depth */
|
||||
#define DIEPTXF0_TX0FSA_Pos (0U)
|
||||
#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << TX0FSA_Pos) // 0x0000FFFF */
|
||||
#define DIEPTXF0_TX0FSA_Msk (0xFFFFUL << DIEPTXF0_TX0FSA_Pos) // 0x0000FFFF */
|
||||
#define DIEPTXF0_TX0FSA DIEPTXF0_TX0FSA_Msk // Endpoint 0 transmit RAM start address */
|
||||
#define DIEPTXF0_TX0FD_Pos (16U)
|
||||
#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << TX0FD_Pos) // 0xFFFF0000 */
|
||||
#define DIEPTXF0_TX0FD_Msk (0xFFFFUL << DIEPTXF0_TX0FD_Pos) // 0xFFFF0000 */
|
||||
#define DIEPTXF0_TX0FD DIEPTXF0_TX0FD_Msk // Endpoint 0 TxFIFO depth */
|
||||
|
||||
/******************** Bit definition for DVBUSPULSE register ********************/
|
||||
|
@ -39,7 +39,7 @@
|
||||
#include "common/tusb_fifo.h"
|
||||
|
||||
//------------- HOST -------------//
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
#if CFG_TUH_ENABLED
|
||||
#include "host/usbh.h"
|
||||
|
||||
#if CFG_TUH_HID
|
||||
@ -61,7 +61,7 @@
|
||||
#endif
|
||||
|
||||
//------------- DEVICE -------------//
|
||||
#if TUSB_OPT_DEVICE_ENABLED
|
||||
#if CFG_TUD_ENABLED
|
||||
#include "device/usbd.h"
|
||||
|
||||
#if CFG_TUD_HID
|
||||
@ -117,8 +117,6 @@
|
||||
//--------------------------------------------------------------------+
|
||||
// APPLICATION API
|
||||
//--------------------------------------------------------------------+
|
||||
/** \ingroup group_application_api
|
||||
* @{ */
|
||||
|
||||
// Initialize device/host stack
|
||||
// Note: when using with RTOS, this should be called after scheduler/kernel is started.
|
||||
@ -131,8 +129,6 @@ bool tusb_inited(void);
|
||||
// TODO
|
||||
// bool tusb_teardown(void);
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
@ -30,7 +30,7 @@
|
||||
#include "common/tusb_compiler.h"
|
||||
|
||||
#define TUSB_VERSION_MAJOR 0
|
||||
#define TUSB_VERSION_MINOR 12
|
||||
#define TUSB_VERSION_MINOR 13
|
||||
#define TUSB_VERSION_REVISION 0
|
||||
#define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
|
||||
|
||||
@ -80,6 +80,7 @@
|
||||
#define OPT_MCU_STM32L4 309 ///< ST L4
|
||||
#define OPT_MCU_STM32G0 310 ///< ST G0
|
||||
#define OPT_MCU_STM32G4 311 ///< ST G4
|
||||
#define OPT_MCU_STM32WB 312 ///< ST WB
|
||||
|
||||
// Sony
|
||||
#define OPT_MCU_CXD56 400 ///< SONY CXD56
|
||||
@ -138,6 +139,16 @@
|
||||
// Infineon
|
||||
#define OPT_MCU_XMC4000 1800 ///< Infineon XMC4000
|
||||
|
||||
// PIC
|
||||
#define OPT_MCU_PIC32MZ 1900 ///< MicroChip PIC32MZ family
|
||||
|
||||
// BridgeTek
|
||||
#define OPT_MCU_FT90X 2000 ///< BridgeTek FT90x
|
||||
#define OPT_MCU_FT93X 2001 ///< BridgeTek FT93x
|
||||
|
||||
// Allwinner
|
||||
#define OPT_MCU_F1C100S 2100 ///< Allwinner F1C100s family
|
||||
|
||||
// Helper to check if configured MCU is one of listed
|
||||
// Apply _TU_CHECK_MCU with || as separator to list of input
|
||||
#define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m)
|
||||
@ -153,6 +164,7 @@
|
||||
#define OPT_OS_CUSTOM 4 ///< Custom OS is implemented by application
|
||||
#define OPT_OS_PICO 5 ///< Raspberry Pi Pico SDK
|
||||
#define OPT_OS_RTTHREAD 6 ///< RT-Thread
|
||||
#define OPT_OS_RTX4 7 ///< Keil RTX 4
|
||||
|
||||
// Allow to use command line to change the config name/location
|
||||
#ifdef CFG_TUSB_CONFIG_FILE
|
||||
@ -161,27 +173,29 @@
|
||||
#include "tusb_config.h"
|
||||
#endif
|
||||
|
||||
#include "common/tusb_mcu.h"
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
// RootHub Mode Configuration
|
||||
// CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port
|
||||
//--------------------------------------------------------------------
|
||||
|
||||
// Lower 4-bit is operational mode
|
||||
#define OPT_MODE_NONE 0x00 ///< Disabled
|
||||
#define OPT_MODE_DEVICE 0x01 ///< Device Mode
|
||||
#define OPT_MODE_HOST 0x02 ///< Host Mode
|
||||
|
||||
// Higher 4-bit is max operational speed (corresponding to tusb_speed_t)
|
||||
#define OPT_MODE_FULL_SPEED 0x00 ///< Max Full Speed
|
||||
#define OPT_MODE_LOW_SPEED 0x10 ///< Max Low Speed
|
||||
#define OPT_MODE_HIGH_SPEED 0x20 ///< Max High Speed
|
||||
// Low byte is operational mode
|
||||
#define OPT_MODE_NONE 0x0000 ///< Disabled
|
||||
#define OPT_MODE_DEVICE 0x0001 ///< Device Mode
|
||||
#define OPT_MODE_HOST 0x0002 ///< Host Mode
|
||||
|
||||
// High byte is max operational speed (corresponding to tusb_speed_t)
|
||||
#define OPT_MODE_DEFAULT_SPEED 0x0000 ///< Default (max) speed supported by MCU
|
||||
#define OPT_MODE_LOW_SPEED 0x0100 ///< Low Speed
|
||||
#define OPT_MODE_FULL_SPEED 0x0200 ///< Full Speed
|
||||
#define OPT_MODE_HIGH_SPEED 0x0400 ///< High Speed
|
||||
#define OPT_MODE_SPEED_MASK 0xff00
|
||||
|
||||
#ifndef CFG_TUSB_RHPORT0_MODE
|
||||
#define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef CFG_TUSB_RHPORT1_MODE
|
||||
#define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
|
||||
#endif
|
||||
@ -191,20 +205,57 @@
|
||||
#error "TinyUSB currently does not support same modes on more than 1 roothub port"
|
||||
#endif
|
||||
|
||||
// Which roothub port is configured as host
|
||||
#define TUH_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
|
||||
#define TUSB_OPT_HOST_ENABLED ( TUH_OPT_RHPORT >= 0 )
|
||||
//------------- Roothub as Device -------------//
|
||||
|
||||
// Which roothub port is configured as device
|
||||
#define TUD_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
|
||||
|
||||
#if TUD_OPT_RHPORT == 0
|
||||
#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
|
||||
#if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE
|
||||
#define TUD_RHPORT_MODE (CFG_TUSB_RHPORT0_MODE)
|
||||
#define TUD_OPT_RHPORT 0
|
||||
#elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE
|
||||
#define TUD_RHPORT_MODE (CFG_TUSB_RHPORT1_MODE)
|
||||
#define TUD_OPT_RHPORT 1
|
||||
#else
|
||||
#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
|
||||
#define TUD_RHPORT_MODE OPT_MODE_NONE
|
||||
#define TUD_OPT_RHPORT -1
|
||||
#endif
|
||||
|
||||
#define CFG_TUD_ENABLED (TUD_RHPORT_MODE & OPT_MODE_DEVICE)
|
||||
|
||||
#if CFG_TUD_ENABLED
|
||||
#define TUD_OPT_HIGH_SPEED ((TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (TUP_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)))
|
||||
#else
|
||||
#define TUD_OPT_HIGH_SPEED 0
|
||||
#endif
|
||||
|
||||
//------------- Roothub as Host -------------//
|
||||
|
||||
#if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST
|
||||
#define TUH_RHPORT_MODE (CFG_TUSB_RHPORT0_MODE)
|
||||
#define TUH_OPT_RHPORT 0
|
||||
#elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST
|
||||
#define TUH_RHPORT_MODE (CFG_TUSB_RHPORT1_MODE)
|
||||
#define TUH_OPT_RHPORT 1
|
||||
#else
|
||||
#define TUH_RHPORT_MODE OPT_MODE_NONE
|
||||
#define TUH_OPT_RHPORT -1
|
||||
#endif
|
||||
|
||||
#define CFG_TUH_ENABLED ( TUH_RHPORT_MODE & OPT_MODE_HOST )
|
||||
|
||||
// For backward compatible
|
||||
#define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
|
||||
#define TUSB_OPT_HOST_ENABLED CFG_TUH_ENABLED
|
||||
|
||||
// TODO move later
|
||||
// TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
|
||||
// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
|
||||
// to generate unaligned access code.
|
||||
// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
|
||||
#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
|
||||
#define TUP_MCU_STRICT_ALIGN 1
|
||||
#else
|
||||
#define TUP_MCU_STRICT_ALIGN 0
|
||||
#endif
|
||||
|
||||
#define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 )
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// COMMON OPTIONS
|
||||
@ -234,6 +285,9 @@
|
||||
#define CFG_TUSB_OS_INC_PATH
|
||||
#endif
|
||||
|
||||
// mutex is only needed for RTOS TODO also required with multiple core MCUs
|
||||
#define TUSB_OPT_MUTEX (CFG_TUSB_OS != OPT_OS_NONE)
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
// DEVICE OPTIONS
|
||||
//--------------------------------------------------------------------
|
||||
@ -302,7 +356,7 @@
|
||||
//--------------------------------------------------------------------
|
||||
// HOST OPTIONS
|
||||
//--------------------------------------------------------------------
|
||||
#if TUSB_OPT_HOST_ENABLED
|
||||
#if CFG_TUH_ENABLED
|
||||
#ifndef CFG_TUH_DEVICE_MAX
|
||||
#define CFG_TUH_DEVICE_MAX 1
|
||||
#endif
|
||||
@ -310,7 +364,7 @@
|
||||
#ifndef CFG_TUH_ENUMERATION_BUFSIZE
|
||||
#define CFG_TUH_ENUMERATION_BUFSIZE 256
|
||||
#endif
|
||||
#endif // TUSB_OPT_HOST_ENABLED
|
||||
#endif // CFG_TUH_ENABLED
|
||||
|
||||
//------------- CLASS -------------//
|
||||
|
||||
@ -338,31 +392,6 @@
|
||||
#define CFG_TUH_VENDOR 0
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Port Specific
|
||||
// TUP stand for TinyUSB Port (can be renamed)
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
//------------- Unaligned Memory -------------//
|
||||
|
||||
// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
|
||||
#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
|
||||
#define TUP_ARCH_STRICT_ALIGN 0
|
||||
#else
|
||||
#define TUP_ARCH_STRICT_ALIGN 1
|
||||
#endif
|
||||
|
||||
// TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
|
||||
// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
|
||||
// to generate unaligned access code.
|
||||
// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
|
||||
#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
|
||||
#define TUP_MCU_STRICT_ALIGN 1
|
||||
#else
|
||||
#define TUP_MCU_STRICT_ALIGN 0
|
||||
#endif
|
||||
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Configuration Validation
|
||||
//------------------------------------------------------------------
|
||||
|
Reference in New Issue
Block a user