Esp32 s3 support (#6341)

Co-authored-by: Jason2866 <24528715+Jason2866@users.noreply.github.com>
Co-authored-by: Unexpected Maker <seon@unexpectedmaker.com>
Co-authored-by: Rodrigo Garcia <rodrigo.garcia@espressif.com>
Co-authored-by: Tomáš Pilný <34927466+PilnyTomas@users.noreply.github.com>
Co-authored-by: Pedro Minatel <pedro.minatel@espressif.com>
Co-authored-by: Ivan Grokhotkov <ivan@espressif.com>
Co-authored-by: Jan Procházka <90197375+P-R-O-C-H-Y@users.noreply.github.com>
Co-authored-by: Limor "Ladyada" Fried <limor@ladyada.net>

tools/sdk/esp32s3/ld/esp32s3.peripherals.ld

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+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+PROVIDE ( UART0 = 0x60000000 );
+PROVIDE ( SPIMEM1 = 0x60002000 );
+PROVIDE ( SPIMEM0 = 0x60003000 );
+PROVIDE ( GPIO = 0x60004000 );
+PROVIDE ( SIGMADELTA = 0x60004f00 );
+PROVIDE ( RTCCNTL = 0x60008000 );
+PROVIDE ( RTCIO = 0x60008400 );
+PROVIDE ( SENS = 0x60008800 );
+PROVIDE ( HINF = 0x6000B000 );
+PROVIDE ( I2S0 = 0x6000F000 );
+PROVIDE ( I2S1 = 0x6002D000 );
+PROVIDE ( UART1 = 0x60010000 );
+PROVIDE ( I2C0 = 0x60013000 );
+PROVIDE ( UHCI0 = 0x60014000 );
+PROVIDE ( UHCI1 = 0x60014000 );
+PROVIDE ( HOST = 0x60015000 );
+PROVIDE ( RMT = 0x60016000 );
+PROVIDE ( RMTMEM = 0x60016800 );
+PROVIDE ( PCNT = 0x60017000 );
+PROVIDE ( SLC = 0x60018000 );
+PROVIDE ( LEDC = 0x60019000 );
+PROVIDE ( MCPWM0 = 0x6001E000 );
+PROVIDE ( MCPWM1 = 0x6002C000 );
+PROVIDE ( MCP = 0x600c3000 );
+PROVIDE ( TIMERG0 = 0x6001F000 );
+PROVIDE ( TIMERG1 = 0x60020000 );
+PROVIDE ( SYSTIMER = 0x60023000 );
+PROVIDE ( GPSPI2  = 0x60024000 );
+PROVIDE ( GPSPI3  = 0x60025000 );
+PROVIDE ( SYSCON = 0x60026000 );
+PROVIDE ( I2C1 = 0x60027000 );
+PROVIDE ( SDMMC = 0x60028000 );
+PROVIDE ( TWAI = 0x6002B000 );
+PROVIDE ( GPSPI4 = 0x60037000 );
+PROVIDE ( GDMA = 0x6003F000 );
+PROVIDE ( UART2  = 0x6002E000 );
+PROVIDE ( DMA = 0x6003F000 );
+PROVIDE ( APB_SARADC = 0x60040000 );
+PROVIDE ( LCD_CAM    = 0x60041000 );
+PROVIDE ( USB_SERIAL_JTAG  = 0x60038000 );
+PROVIDE ( USB0     = 0x60080000 );
+PROVIDE ( USBH     = 0x60080000 );
+PROVIDE ( USB_WRAP = 0x60039000 );

tools/sdk/esp32s3/ld/esp32s3.rom.api.ld

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+/**
+ * ROM APIs
+ */
+
+/* user may provide newer version of tjpgd */
+/* so here directly assign the symbols with the ROM API address to make sure one from rom is correctly linked */
+PROVIDE ( esp_rom_tjpgd_decomp = 0x40000864 );
+PROVIDE ( esp_rom_tjpgd_prepare = 0x40000858 );
+
+PROVIDE ( esp_rom_crc32_le = crc32_le );
+PROVIDE ( esp_rom_crc16_le = crc16_le );
+PROVIDE ( esp_rom_crc8_le  = crc8_le );
+PROVIDE ( esp_rom_crc32_be = crc32_be );
+PROVIDE ( esp_rom_crc16_be = crc16_be );
+PROVIDE ( esp_rom_crc8_be  = crc8_be );
+
+PROVIDE ( esp_rom_gpio_pad_select_gpio    = gpio_pad_select_gpio );
+PROVIDE ( esp_rom_gpio_pad_pullup_only    = gpio_pad_pullup );
+PROVIDE ( esp_rom_gpio_pad_set_drv        = gpio_pad_set_drv );
+PROVIDE ( esp_rom_gpio_pad_unhold         = gpio_pad_unhold );
+PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
+
+PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
+PROVIDE ( esp_rom_efuse_get_flash_gpio_info    = ets_efuse_get_spiconfig );
+PROVIDE ( esp_rom_efuse_get_flash_wp_gpio      = ets_efuse_get_wp_pad );
+PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
+
+PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_uart_usb_acm_init   = Uart_Init_USB );
+PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
+
+PROVIDE ( esp_rom_md5_init   = MD5Init );
+PROVIDE ( esp_rom_md5_update = MD5Update );
+PROVIDE ( esp_rom_md5_final  = MD5Final );
+
+PROVIDE ( esp_rom_printf   = ets_printf );
+PROVIDE ( esp_rom_delay_us = ets_delay_us );
+PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
+PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
+
+PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );

tools/sdk/esp32s3/ld/esp32s3.rom.libgcc.ld

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+/* ROM function interface esp32s3.rom.libgcc.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libgcc
+ ***************************************/
+
+/* Functions */
+__absvdi2 = 0x4000216c;
+__absvsi2 = 0x40002178;
+__adddf3 = 0x40002184;
+__addsf3 = 0x40002190;
+__addvdi3 = 0x4000219c;
+__addvsi3 = 0x400021a8;
+__ashldi3 = 0x400021b4;
+__ashrdi3 = 0x400021c0;
+__bswapdi2 = 0x400021cc;
+__bswapsi2 = 0x400021d8;
+__clear_cache = 0x400021e4;
+__clrsbdi2 = 0x400021f0;
+__clrsbsi2 = 0x400021fc;
+__clzdi2 = 0x40002208;
+__clzsi2 = 0x40002214;
+__cmpdi2 = 0x40002220;
+__ctzdi2 = 0x4000222c;
+__ctzsi2 = 0x40002238;
+__divdc3 = 0x40002244;
+__divdf3 = 0x40002250;
+__divdi3 = 0x4000225c;
+__divsc3 = 0x40002268;
+__divsf3 = 0x40002274;
+__divsi3 = 0x40002280;
+__eqdf2 = 0x4000228c;
+__eqsf2 = 0x40002298;
+__extendsfdf2 = 0x400022a4;
+__ffsdi2 = 0x400022b0;
+__ffssi2 = 0x400022bc;
+__fixdfdi = 0x400022c8;
+__fixdfsi = 0x400022d4;
+__fixsfdi = 0x400022e0;
+__fixsfsi = 0x400022ec;
+__fixunsdfsi = 0x400022f8;
+__fixunssfdi = 0x40002304;
+__fixunssfsi = 0x40002310;
+__floatdidf = 0x4000231c;
+__floatdisf = 0x40002328;
+__floatsidf = 0x40002334;
+__floatsisf = 0x40002340;
+__floatundidf = 0x4000234c;
+__floatundisf = 0x40002358;
+__floatunsidf = 0x40002364;
+__floatunsisf = 0x40002370;
+__gcc_bcmp = 0x4000237c;
+__gedf2 = 0x40002388;
+__gesf2 = 0x40002394;
+__gtdf2 = 0x400023a0;
+__gtsf2 = 0x400023ac;
+__ledf2 = 0x400023b8;
+__lesf2 = 0x400023c4;
+__lshrdi3 = 0x400023d0;
+__ltdf2 = 0x400023dc;
+__ltsf2 = 0x400023e8;
+__moddi3 = 0x400023f4;
+__modsi3 = 0x40002400;
+__muldc3 = 0x4000240c;
+__muldf3 = 0x40002418;
+__muldi3 = 0x40002424;
+__mulsc3 = 0x40002430;
+__mulsf3 = 0x4000243c;
+__mulsi3 = 0x40002448;
+__mulvdi3 = 0x40002454;
+__mulvsi3 = 0x40002460;
+__nedf2 = 0x4000246c;
+__negdf2 = 0x40002478;
+__negdi2 = 0x40002484;
+__negsf2 = 0x40002490;
+__negvdi2 = 0x4000249c;
+__negvsi2 = 0x400024a8;
+__nesf2 = 0x400024b4;
+__paritysi2 = 0x400024c0;
+__popcountdi2 = 0x400024cc;
+__popcountsi2 = 0x400024d8;
+__powidf2 = 0x400024e4;
+__powisf2 = 0x400024f0;
+__subdf3 = 0x400024fc;
+__subsf3 = 0x40002508;
+__subvdi3 = 0x40002514;
+__subvsi3 = 0x40002520;
+__truncdfsf2 = 0x4000252c;
+__ucmpdi2 = 0x40002538;
+__udivdi3 = 0x40002544;
+__udivmoddi4 = 0x40002550;
+__udivsi3 = 0x4000255c;
+__udiv_w_sdiv = 0x40002568;
+__umoddi3 = 0x40002574;
+__umodsi3 = 0x40002580;
+__unorddf2 = 0x4000258c;
+__unordsf2 = 0x40002598;

tools/sdk/esp32s3/ld/esp32s3.rom.newlib-nano.ld

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+/* ROM function interface esp32s3.rom.newlib-nano.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib_nano_format
+ ***************************************/
+
+/* Functions */
+__sprint_r = 0x4000156c;
+_fiprintf_r = 0x40001578;
+_fprintf_r = 0x40001584;
+_printf_common = 0x40001590;
+_printf_i = 0x4000159c;
+_vfiprintf_r = 0x400015a8;
+_vfprintf_r = 0x400015b4;
+fiprintf = 0x400015c0;
+fprintf = 0x400015cc;
+printf = 0x400015d8;
+vfiprintf = 0x400015e4;
+vfprintf = 0x400015f0;

tools/sdk/esp32s3/ld/esp32s3.rom.newlib-time.ld

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+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* These are the newlib functions and the .bss/.data symbols which are related to 'time_t'
+   or other structures which include 'time_t' (like 'struct stat').
+   These ROM functions were compiled with sizeof(time_t) == 4.
+   When compiling with sizeof(time_t) == 8, these functions should be excluded from the build.
+ */
+
+_isatty_r = 0x4000126c;
+PROVIDE( __smakebuf_r = 0x40001530 );
+PROVIDE( __swsetup_r = 0x40001560 );
+PROVIDE( __swhatbuf_r = 0x4000153c );

tools/sdk/esp32s3/ld/esp32s3.rom.newlib.ld

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+/* ROM function interface esp32s3.rom.newlib.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib
+ ***************************************/
+
+/* Functions */
+esp_rom_newlib_init_common_mutexes = 0x400011dc;
+memset = 0x400011e8;
+memcpy = 0x400011f4;
+memmove = 0x40001200;
+memcmp = 0x4000120c;
+strcpy = 0x40001218;
+strncpy = 0x40001224;
+strcmp = 0x40001230;
+strncmp = 0x4000123c;
+strlen = 0x40001248;
+strstr = 0x40001254;
+bzero = 0x40001260;
+sbrk = 0x40001278;
+isalnum = 0x40001284;
+isalpha = 0x40001290;
+isascii = 0x4000129c;
+isblank = 0x400012a8;
+iscntrl = 0x400012b4;
+isdigit = 0x400012c0;
+islower = 0x400012cc;
+isgraph = 0x400012d8;
+isprint = 0x400012e4;
+ispunct = 0x400012f0;
+isspace = 0x400012fc;
+isupper = 0x40001308;
+toupper = 0x40001314;
+tolower = 0x40001320;
+toascii = 0x4000132c;
+memccpy = 0x40001338;
+memchr = 0x40001344;
+memrchr = 0x40001350;
+strcasecmp = 0x4000135c;
+strcasestr = 0x40001368;
+strcat = 0x40001374;
+strdup = 0x40001380;
+strchr = 0x4000138c;
+strcspn = 0x40001398;
+strcoll = 0x400013a4;
+strlcat = 0x400013b0;
+strlcpy = 0x400013bc;
+strlwr = 0x400013c8;
+strncasecmp = 0x400013d4;
+strncat = 0x400013e0;
+strndup = 0x400013ec;
+strnlen = 0x400013f8;
+strrchr = 0x40001404;
+strsep = 0x40001410;
+strspn = 0x4000141c;
+strtok_r = 0x40001428;
+strupr = 0x40001434;
+longjmp = 0x40001440;
+setjmp = 0x4000144c;
+abs = 0x40001458;
+div = 0x40001464;
+labs = 0x40001470;
+ldiv = 0x4000147c;
+qsort = 0x40001488;
+rand_r = 0x40001494;
+rand = 0x400014a0;
+srand = 0x400014ac;
+utoa = 0x400014b8;
+itoa = 0x400014c4;
+atoi = 0x400014d0;
+atol = 0x400014dc;
+strtol = 0x400014e8;
+strtoul = 0x400014f4;
+PROVIDE( fflush = 0x40001500 );
+PROVIDE( _fflush_r = 0x4000150c );
+PROVIDE( _fwalk = 0x40001518 );
+PROVIDE( _fwalk_reent = 0x40001524 );
+PROVIDE( __swbuf_r = 0x40001548 );
+__swbuf = 0x40001554;
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x3fceffd4;
+_global_impure_ptr = 0x3fceffd0;

tools/sdk/esp32s3/ld/esp32s3.rom.version.ld

@@ -0,0 +1,8 @@
+/* ROM version variables for esp32s3
+ *
+ * These addresses should be compatible with any ROM version for this chip.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+_rom_chip_id = 0x40000570;
+_rom_eco_version = 0x40000574;

tools/sdk/esp32s3/ld/memory.ld

@@ -0,0 +1,94 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/**
+ *                    ESP32-S3 Linker Script Memory Layout
+ * This file describes the memory layout (memory blocks) by virtual memory addresses.
+ * This linker script is passed through the C preprocessor to include configuration options.
+ * Please use preprocessor features sparingly!
+ * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
+ */
+/*
+ * Automatically generated file. DO NOT EDIT.
+ * Espressif IoT Development Framework (ESP-IDF) Configuration Header
+ */
+       
+/* List of deprecated options */
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* CPU instruction prefetch padding size for flash mmap scenario */
+_esp_flash_mmap_prefetch_pad_size = 16;
+/* CPU instruction prefetch padding size for memory protection scenario */
+_esp_memprot_prefetch_pad_size = 0;
+/* Memory alignment size for PMS */
+_esp_memprot_align_size = 0;
+/*
+ * 40370000 <- IRAM/Icache -> 40378000 <- D/IRAM (I) -> 403E0000
+ *                            3FC88000 <- D/IRAM (D) -> 3FCF0000 <- DRAM/DCache -> 3FD00000
+ *
+ * Startup code uses the IRAM from 0x403BA000 to 0x403E0000, which is not available for static
+ * memory, but can only be used after app starts.
+ *
+ * D cache use the memory from high address, so when it's configured to 16K/32K, the region
+ * 0x3FCF000 ~ (3FD00000 - DATA_CACHE_SIZE) should be available. This region is not used as
+ * static memory, leaving to the heap.
+ */
+MEMORY
+{
+  /**
+   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+   *  are connected to the data port of the CPU and eg allow byte-wise access.
+   */
+  /* IRAM for PRO CPU. */
+  iram0_0_seg (RX) : org = (0x40370000 + 0x4000), len = (((0x403BA000 - (0x40378000 - 0x3FC88000)) - 0x3FC88000) + 0x8000 - 0x4000)
+  /* Flash mapped instruction data */
+  iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20
+  /**
+   * (0x20 offset above is a convenience for the app binary image generation.
+   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+   * header. Setting this offset makes it simple to meet the flash cache MMU's
+   * constraint that (paddr % 64KB == vaddr % 64KB).)
+   */
+  /**
+   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
+   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
+   */
+  dram0_0_seg (RW) : org = (0x3FC88000), len = ((0x403BA000 - (0x40378000 - 0x3FC88000)) - 0x3FC88000)
+  /* Flash mapped constant data */
+  drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
+  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
+  /**
+   * RTC fast memory (executable). Persists over deep sleep.
+   */
+  rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - (0x10)
+  /**
+   * RTC fast memory (same block as above), viewed from data bus
+   */
+  rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - (0x10)
+  /**
+   * RTC slow memory (data accessible). Persists over deep sleep.
+   * Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
+   */
+  rtc_slow_seg(RW) : org = 0x50000000 + 0,
+                                     len = 0x2000 - 0
+}
+_static_data_end = _bss_end;
+/* Heap ends at top of dram0_0_seg */
+_heap_end = 0x40000000;
+_data_seg_org = ORIGIN(rtc_data_seg);
+REGION_ALIAS("rtc_data_location", rtc_slow_seg );
+REGION_ALIAS("default_code_seg", iram0_2_seg);
+REGION_ALIAS("default_rodata_seg", drom0_0_seg);
+/**
+ *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
+ *  also be first in the segment.
+ */
+  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
+         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")