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Update IDF to 3.2-3276a13 and esptool.py to 2.5.0 (#1878)

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* TX Flow Control and Code cleanup

* Use semaphore instead of delay

TX functionality is done.

* Use single buffer and empty queue on exit

* Fix compile issues because of LwIP code relocation

* Add temporary header to fix Azure not compiling

* Fix AsyncUDP early init

* AsyncUDP Multicast fixes

* Add source mac address and rework multicast

* Allow redefinition of default pins for Serials 1 and 2

* Update IDF to 3276a13

* Update esptool.py to 2.5.0

* Fix sketches

* Fix log level in BluetoothSetial
This commit is contained in:
Me No Dev
2018-09-21 08:39:36 +02:00
committed by GitHub
parent 4e96bffe0e
commit 96822d783f
447 changed files with 37993 additions and 10849 deletions
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2
tools/sdk/include/esp32/rom/libc_stubs.h
View File

@ -51,7 +51,7 @@ struct syscall_stub_table
int (*_rename_r)(struct _reent *r, const char*, const char*);
clock_t (*_times_r)(struct _reent *r, struct tms *);
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
void (*_raise_r)(struct _reent *r);
void (*_raise_r)(struct _reent *r); /* function signature is incorrect in ROM */
int (*_unlink_r)(struct _reent *r, const char*);
int (*_link_r)(struct _reent *r, const char*, const char*);
int (*_stat_r)(struct _reent *r, const char*, struct stat *);

6
tools/sdk/include/esp32/rom/rtc.h
View File

@ -55,7 +55,7 @@ extern "C" {
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
@ -68,8 +68,10 @@ extern "C" {
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON
@ -192,7 +194,7 @@ void set_rtc_memory_crc(void);
*
* @return None
*/
void software_reset(void);
void __attribute__((noreturn)) software_reset(void);
/**
* @brief Software Reset digital core.