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IDF master c13afea63 (#5214)

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esp-dsp: master 7cc5073
esp-face: master 420fc7e
esp-rainmaker: f1b82c7
esp32-camera: master 6f8489e
esp_littlefs: master b58f00c
This commit is contained in:
Me No Dev
2021-05-31 16:32:51 +03:00
committed by GitHub
parent 0db9e2f45b
commit a618fc1361
616 changed files with 11842 additions and 4932 deletions
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5
tools/sdk/esp32/include/ulp/include/esp32/ulp.h
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@ -464,10 +464,11 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
* reg_addr register and offset_ field (this offset is expressed in 32-bit words).
* 32 bits written to RTC memory are built as follows:
* - bits [31:21] hold the PC of current instruction, expressed in 32-bit words
* - bits [20:16] = 5'b1
* - bits [20:18] = 3'b0
* - bits [17:16] reg_addr (0..3)
* - bits [15:0] are assigned the contents of reg_val
*
* RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] }
* RTC_SLOW_MEM[addr + offset_] = { insn_PC[10:0], 3'b0, reg_addr, reg_val[15:0] }
*/
#define I_ST(reg_val, reg_addr, offset_) { .st = { \
.dreg = reg_val, \

5
tools/sdk/esp32/include/ulp/include/esp32s2/ulp.h
View File

@ -430,10 +430,11 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
* reg_addr register and offset_ field (this offset is expressed in 32-bit words).
* 32 bits written to RTC memory are built as follows:
* - bits [31:21] hold the PC of current instruction, expressed in 32-bit words
* - bits [20:16] = 5'b1
* - bits [20:18] = 3'b0
* - bits [17:16] reg_addr (0..3)
* - bits [15:0] are assigned the contents of reg_val
*
* RTC_SLOW_MEM[addr + offset_] = { 5'b0, insn_PC[10:0], val[15:0] }
* RTC_SLOW_MEM[addr + offset_] = { insn_PC[10:0], 3'b0, reg_addr, reg_val[15:0] }
*/
#define I_ST(reg_val, reg_addr, offset_) { .st = { \
.dreg = reg_val, \