From a761281d8c9f0c285f01bfd1e77b30ed190c1ee8 Mon Sep 17 00:00:00 2001
From: me-no-dev <hristo@espressif.com>
Date: Thu, 14 May 2020 19:02:35 +0300
Subject: [PATCH] Fix PSRAM support

---
 cores/esp32/Esp.cpp           | 24 ++++++++++++++++++------
 cores/esp32/esp32-hal-misc.c  |  2 +-
 cores/esp32/esp32-hal-psram.c | 14 +++++++++++++-
 3 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/cores/esp32/Esp.cpp b/cores/esp32/Esp.cpp
index ea1cc3c8..11e9018f 100644
--- a/cores/esp32/Esp.cpp
+++ b/cores/esp32/Esp.cpp
@@ -133,24 +133,36 @@ uint32_t EspClass::getMaxAllocHeap(void)
 
 uint32_t EspClass::getPsramSize(void)
 {
-    multi_heap_info_t info;
-    heap_caps_get_info(&info, MALLOC_CAP_SPIRAM);
-    return info.total_free_bytes + info.total_allocated_bytes;
+	if(psramFound()){
+	    multi_heap_info_t info;
+	    heap_caps_get_info(&info, MALLOC_CAP_SPIRAM);
+	    return info.total_free_bytes + info.total_allocated_bytes;
+	}
+	return 0;
 }
 
 uint32_t EspClass::getFreePsram(void)
 {
-    return heap_caps_get_free_size(MALLOC_CAP_SPIRAM);
+	if(psramFound()){
+	    return heap_caps_get_free_size(MALLOC_CAP_SPIRAM);
+	}
+	return 0;
 }
 
 uint32_t EspClass::getMinFreePsram(void)
 {
-    return heap_caps_get_minimum_free_size(MALLOC_CAP_SPIRAM);
+	if(psramFound()){
+	    return heap_caps_get_minimum_free_size(MALLOC_CAP_SPIRAM);
+	}
+	return 0;
 }
 
 uint32_t EspClass::getMaxAllocPsram(void)
 {
-    return heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM);
+	if(psramFound()){
+	    return heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM);
+	}
+	return 0;
 }
 
 static uint32_t sketchSize(sketchSize_t response) {
diff --git a/cores/esp32/esp32-hal-misc.c b/cores/esp32/esp32-hal-misc.c
index ae3d2c88..06c64e83 100644
--- a/cores/esp32/esp32-hal-misc.c
+++ b/cores/esp32/esp32-hal-misc.c
@@ -210,7 +210,7 @@ void initArduino()
 #ifdef F_CPU
     setCpuFrequencyMhz(F_CPU/1000000);
 #endif
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
     psramInit();
 #endif
     esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL);
diff --git a/cores/esp32/esp32-hal-psram.c b/cores/esp32/esp32-hal-psram.c
index 51fadfba..b9935a79 100644
--- a/cores/esp32/esp32-hal-psram.c
+++ b/cores/esp32/esp32-hal-psram.c
@@ -14,7 +14,7 @@
 
 #include "esp32-hal.h"
 
-#if CONFIG_SPIRAM_SUPPORT
+#if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
 #include "soc/efuse_reg.h"
 #include "esp_heap_caps.h"
 
@@ -22,6 +22,9 @@
 #ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
 #if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
 #include "esp32/spiram.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/spiram.h"
+#include "esp32s2/rom/cache.h"
 #else 
 #error Target CONFIG_IDF_TARGET is not supported
 #endif
@@ -40,6 +43,7 @@ bool psramInit(){
     if (spiramFailed) {
         return false;
     }
+#if CONFIG_IDF_TARGET_ESP32
     uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
     uint32_t pkg_ver = chip_ver & 0x7;
     if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
@@ -48,13 +52,21 @@ bool psramInit(){
         return false;
     }
     esp_spiram_init_cache();
+#elif CONFIG_IDF_TARGET_ESP32S2
+    extern void esp_config_data_cache_mode(void);
+    esp_config_data_cache_mode();
+    Cache_Enable_DCache(0);
+#endif
     if (esp_spiram_init() != ESP_OK) {
         spiramFailed = true;
         log_w("PSRAM init failed!");
+#if CONFIG_IDF_TARGET_ESP32
         pinMatrixOutDetach(16, false, false);
         pinMatrixOutDetach(17, false, false);
+#endif
         return false;
     }
+    esp_spiram_init_cache();
     if (!esp_spiram_test()) {
         spiramFailed = true;
         log_e("PSRAM test failed!");