forked from espressif/arduino-esp32
Update IDF libs to 9314bf0
This commit is contained in:
me-no-dev
@ -83,9 +83,11 @@ SECTIONS
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_iram_text_start = ABSOLUTE(.);
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*(.iram1 .iram1.*)
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*libfreertos.a:(.literal .text .literal.* .text.*)
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*libheap.a:multi_heap.o(.literal .text .literal.* .text.*)
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*libesp32.a:panic.o(.literal .text .literal.* .text.*)
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*libesp32.a:core_dump.o(.literal .text .literal.* .text.*)
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*libesp32.a:heap_alloc_caps.o(.literal .text .literal.* .text.*)
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*libapp_trace.a:(.literal .text .literal.* .text.*)
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*libxtensa-debug-module.a:eri.o(.literal .text .literal.* .text.*)
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*libesp32.a:app_trace.o(.literal .text .literal.* .text.*)
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*libphy.a:(.literal .text .literal.* .text.*)
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*librtc.a:(.literal .text .literal.* .text.*)
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@ -98,21 +100,22 @@ SECTIONS
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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KEEP(*(.data))
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KEEP(*(.data.*))
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KEEP(*(.gnu.linkonce.d.*))
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KEEP(*(.data1))
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KEEP(*(.sdata))
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KEEP(*(.sdata.*))
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KEEP(*(.gnu.linkonce.s.*))
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KEEP(*(.sdata2))
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KEEP(*(.sdata2.*))
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KEEP(*(.gnu.linkonce.s2.*))
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KEEP(*(.jcr))
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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*(.dram1 .dram1.*)
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*libesp32.a:panic.o(.rodata .rodata.*)
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*libesp32.a:app_trace.o(.rodata .rodata.*)
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*libphy.a:(.rodata .rodata.*)
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*libapp_trace.a:(.rodata .rodata.*)
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*libheap.a:multi_heap.o(.rodata .rodata.*)
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >dram0_0_seg
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@ -25,8 +25,16 @@ MEMORY
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
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/*
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(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
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which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
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cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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@ -37,7 +45,9 @@ MEMORY
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len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
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/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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@ -830,6 +830,7 @@ PROVIDE ( lmp_io_cap_req_handler = 0x4002c7a4 );
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PROVIDE ( ld_acl_tx_packet_type_select = 0x4002fb40 );
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PROVIDE ( ld_acl_sched = 0x40033268 );
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PROVIDE ( ld_acl_sniff_sched = 0x4003340c );
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PROVIDE ( lm_cmd_cmp_send = 0x40051838 );
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PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 );
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PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 );
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PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 );
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@ -1249,6 +1250,13 @@ PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 );
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PROVIDE ( r_lm_oob_f1 = 0x40012e54 );
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PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 );
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PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 );
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PROVIDE ( nvds_null_read = 0x400542a0 );
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PROVIDE ( nvds_null_write = 0x400542a8 );
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PROVIDE ( nvds_null_erase = 0x400542b0 );
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PROVIDE ( nvds_read = 0x400542c4 );
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PROVIDE ( nvds_write = 0x400542fc );
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PROVIDE ( nvds_erase = 0x40054334 );
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PROVIDE ( nvds_init_memory = 0x40054358 );
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PROVIDE ( r_lmp_pack = 0x4001135c );
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PROVIDE ( r_lmp_unpack = 0x4001149c );
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PROVIDE ( r_lm_read_features = 0x4004f0d8 );
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@ -1625,6 +1633,8 @@ PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );
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PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );
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PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );
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PROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );
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PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c );
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PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
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PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
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/*
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@ -1803,6 +1813,7 @@ PROVIDE ( ets_set_user_start = 0x4000687c );
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PROVIDE ( ets_unpack_flash_code = 0x40007018 );
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PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c );
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PROVIDE ( rom_main = 0x400076c4 );
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PROVIDE ( ets_write_char_uart = 0x40007cf8 );
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PROVIDE ( ets_install_putc1 = 0x40007d18 );
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PROVIDE ( ets_install_putc2 = 0x40007d38 );
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PROVIDE ( ets_install_uart_printf = 0x40007d28 );
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@ -1842,6 +1853,7 @@ PROVIDE ( ets_timer_setfn = 0x40008350 );
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PROVIDE ( ets_update_cpu_frequency_rom = 0x40008550 ); /* Updates g_ticks_per_us on the current CPU only; not on the other core */
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/* Following are static data, but can be used, not generated by script <<<<< btdm data */
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PROVIDE ( hci_tl_env = 0x3ffb8154 );
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PROVIDE ( ld_acl_env = 0x3ffb8258 );
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PROVIDE ( ld_active_ch_map = 0x3ffb8334 );
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PROVIDE ( ld_bcst_acl_env = 0x3ffb8274 );
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@ -1862,5 +1874,7 @@ PROVIDE ( ld_strain_env = 0x3ffb8330 );
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PROVIDE ( LM_Sniff = 0x3ffb8230 );
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PROVIDE ( LM_SniffSubRate = 0x3ffb8214 );
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PROVIDE ( prbs_64bytes = 0x3ff98992 );
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PROVIDE ( nvds_env = 0x3ffb8364 );
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PROVIDE ( nvds_magic_number = 0x3ff9912a );
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/* Above are static data, but can be used, not generated by script >>>>> btdm data */
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@ -27,8 +27,14 @@ MEMORY
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
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/*
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(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
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which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
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cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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@ -37,7 +43,8 @@ MEMORY
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dram0_0_seg (RW) : org = 0x3FFB0000 + 0x10000,
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len = 0x50000 - 0x0 - 0x10000
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
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/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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