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Fix PSRAM support

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This commit is contained in:
me-no-dev
2020-05-14 19:02:35 +03:00
parent 176e5b0e79
commit cebaf93dd8
3 changed files with 32 additions and 8 deletions
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24
cores/esp32/Esp.cpp
View File

@ -133,24 +133,36 @@ uint32_t EspClass::getMaxAllocHeap(void)
uint32_t EspClass::getPsramSize(void) uint32_t EspClass::getPsramSize(void)
{ {
multi_heap_info_t info; if(psramFound()){
heap_caps_get_info(&info, MALLOC_CAP_SPIRAM); multi_heap_info_t info;
return info.total_free_bytes + info.total_allocated_bytes; heap_caps_get_info(&info, MALLOC_CAP_SPIRAM);
return info.total_free_bytes + info.total_allocated_bytes;
}
return 0;
} }
uint32_t EspClass::getFreePsram(void) uint32_t EspClass::getFreePsram(void)
{ {
return heap_caps_get_free_size(MALLOC_CAP_SPIRAM); if(psramFound()){
return heap_caps_get_free_size(MALLOC_CAP_SPIRAM);
}
return 0;
} }
uint32_t EspClass::getMinFreePsram(void) uint32_t EspClass::getMinFreePsram(void)
{ {
return heap_caps_get_minimum_free_size(MALLOC_CAP_SPIRAM); if(psramFound()){
return heap_caps_get_minimum_free_size(MALLOC_CAP_SPIRAM);
}
return 0;
} }
uint32_t EspClass::getMaxAllocPsram(void) uint32_t EspClass::getMaxAllocPsram(void)
{ {
return heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM); if(psramFound()){
return heap_caps_get_largest_free_block(MALLOC_CAP_SPIRAM);
}
return 0;
} }
static uint32_t sketchSize(sketchSize_t response) { static uint32_t sketchSize(sketchSize_t response) {

2
cores/esp32/esp32-hal-misc.c
View File

@ -210,7 +210,7 @@ void initArduino()
#ifdef F_CPU #ifdef F_CPU
setCpuFrequencyMhz(F_CPU/1000000); setCpuFrequencyMhz(F_CPU/1000000);
#endif #endif
#if CONFIG_SPIRAM_SUPPORT #if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
psramInit(); psramInit();
#endif #endif
esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL); esp_log_level_set("*", CONFIG_LOG_DEFAULT_LEVEL);

14
cores/esp32/esp32-hal-psram.c
View File

@ -14,7 +14,7 @@
#include "esp32-hal.h" #include "esp32-hal.h"
#if CONFIG_SPIRAM_SUPPORT #if CONFIG_SPIRAM_SUPPORT || CONFIG_SPIRAM
#include "soc/efuse_reg.h" #include "soc/efuse_reg.h"
#include "esp_heap_caps.h" #include "esp_heap_caps.h"
@ -22,6 +22,9 @@
#ifdef ESP_IDF_VERSION_MAJOR // IDF 4+ #ifdef ESP_IDF_VERSION_MAJOR // IDF 4+
#if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4 #if CONFIG_IDF_TARGET_ESP32 // ESP32/PICO-D4
#include "esp32/spiram.h" #include "esp32/spiram.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/spiram.h"
#include "esp32s2/rom/cache.h"
#else #else
#error Target CONFIG_IDF_TARGET is not supported #error Target CONFIG_IDF_TARGET is not supported
#endif #endif
@ -40,6 +43,7 @@ bool psramInit(){
if (spiramFailed) { if (spiramFailed) {
return false; return false;
} }
#if CONFIG_IDF_TARGET_ESP32
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG); uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
uint32_t pkg_ver = chip_ver & 0x7; uint32_t pkg_ver = chip_ver & 0x7;
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) { if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
@ -48,13 +52,21 @@ bool psramInit(){
return false; return false;
} }
esp_spiram_init_cache(); esp_spiram_init_cache();
#elif CONFIG_IDF_TARGET_ESP32S2
extern void esp_config_data_cache_mode(void);
esp_config_data_cache_mode();
Cache_Enable_DCache(0);
#endif
if (esp_spiram_init() != ESP_OK) { if (esp_spiram_init() != ESP_OK) {
spiramFailed = true; spiramFailed = true;
log_w("PSRAM init failed!"); log_w("PSRAM init failed!");
#if CONFIG_IDF_TARGET_ESP32
pinMatrixOutDetach(16, false, false); pinMatrixOutDetach(16, false, false);
pinMatrixOutDetach(17, false, false); pinMatrixOutDetach(17, false, false);
#endif
return false; return false;
} }
esp_spiram_init_cache();
if (!esp_spiram_test()) { if (!esp_spiram_test()) {
spiramFailed = true; spiramFailed = true;
log_e("PSRAM test failed!"); log_e("PSRAM test failed!");