From e38d0daaab2d0326d2733b34f13bb7cec41c879e Mon Sep 17 00:00:00 2001
From: Peter Dimov <pdimov@pdimov.com>
Date: Wed, 22 Mar 2006 22:46:53 +0000
Subject: [PATCH] Fix issues on HP-UX (ILP32 model)

[SVN r33449]
---
 .../boost/detail/sp_counted_base_gcc_ia64.hpp | 36 +++++++++----------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/include/boost/detail/sp_counted_base_gcc_ia64.hpp b/include/boost/detail/sp_counted_base_gcc_ia64.hpp
index efcfd11..7f4bd25 100644
--- a/include/boost/detail/sp_counted_base_gcc_ia64.hpp
+++ b/include/boost/detail/sp_counted_base_gcc_ia64.hpp
@@ -5,7 +5,7 @@
 //  detail/sp_counted_base_gcc_ia64.hpp - g++ on IA64
 //
 //  Copyright (c) 2001, 2002, 2003 Peter Dimov and Multi Media Ltd.
-//  Copyright 2004-2005 Peter Dimov
+//  Copyright 2004-2006 Peter Dimov
 //  Copyright 2005 Ben Hutchings
 //
 //  Distributed under the Boost Software License, Version 1.0. (See
@@ -24,55 +24,55 @@ namespace boost
 namespace detail
 {
 
-inline void atomic_increment( long * pw )
+inline void atomic_increment( int * pw )
 {
     // ++*pw;
 
-    long tmp;
+    int tmp;
 
     // No barrier is required here but fetchadd always has an acquire or
     // release barrier associated with it.  We choose release as it should be
     // cheaper.
-    __asm__ ("fetchadd8.rel %0=[%2],1" :
+    __asm__ ("fetchadd4.rel %0=%1,1" :
          "=r"(tmp), "=m"(*pw) :
-         "r"(pw), "m"( *pw ));
+         "m"( *pw ));
 }
 
-inline long atomic_decrement( long * pw )
+inline int atomic_decrement( int * pw )
 {
     // return --*pw;
 
-    long rv;
+    int rv;
 
-    __asm__ ("     fetchadd8.rel %0=[%2],-1 ;; \n"
+    __asm__ ("     fetchadd4.rel %0=%1,-1 ;; \n"
              "     cmp.eq        p7,p0=1,%0 ;; \n"
-             "(p7) ld8.acq       %0=[%2]    " :
+             "(p7) ld4.acq       %0=%1    " :
              "=&r"(rv), "=m"(*pw) :
-             "r"(pw), "m"( *pw ) :
+             "m"( *pw ) :
              "p7");
 
     return rv;
 }
 
-inline long atomic_conditional_increment( long * pw )
+inline int atomic_conditional_increment( int * pw )
 {
     // if( *pw != 0 ) ++*pw;
     // return *pw;
 
-    long rv, tmp, tmp2;
+    int rv, tmp, tmp2;
 
-    __asm__ ("0:   ld8          %0=[%4]           ;; \n"
+    __asm__ ("0:   ld4          %0=%3           ;; \n"
          "     cmp.eq       p7,p0=0,%0        ;; \n"
          "(p7) br.cond.spnt 1f                \n"
          "     mov          ar.ccv=%0         \n"
          "     add          %1=1,%0           ;; \n"
-         "     cmpxchg8.acq %2=[%4],%1,ar.ccv ;; \n"
+         "     cmpxchg4.acq %2=%3,%1,ar.ccv ;; \n"
          "     cmp.ne       p7,p0=%0,%2       ;; \n"
          "(p7) br.cond.spnt 0b                \n"
          "     mov          %0=%1             ;; \n"
          "1:" : 
          "=&r"(rv), "=&r"(tmp), "=&r"(tmp2), "=m"(*pw) :
-         "r"(pw), "m"( *pw ) :
+         "m"( *pw ) :
          "ar.ccv", "p7");
 
     return rv;
@@ -85,8 +85,8 @@ private:
     sp_counted_base( sp_counted_base const & );
     sp_counted_base & operator= ( sp_counted_base const & );
 
-    long use_count_;        // #shared
-    long weak_count_;       // #weak + (#shared != 0)
+    int use_count_;        // #shared
+    int weak_count_;       // #weak + (#shared != 0)
 
 public:
 
@@ -146,7 +146,7 @@ public:
 
     long use_count() const // nothrow
     {
-        return static_cast<long const volatile &>( use_count_ );
+        return static_cast<int const volatile &>( use_count_ ); // TODO use ld.acq here
     }
 };