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										 |  |  | // Copyright 2010 Dolphin Emulator Project
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											2015-05-18 01:08:10 +02:00
										 |  |  | // Licensed under GPLv2+
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											2014-02-10 13:54:46 -05:00
										 |  |  | // Refer to the license.txt file included.
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											2010-08-14 08:53:05 +00:00
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											2014-02-10 13:54:46 -05:00
										 |  |  | #pragma once
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										 |  |  | #define DSP_REG_AR0 0x00  // address registers
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							|  |  |  | #define DSP_REG_AR1 0x01
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							|  |  |  | #define DSP_REG_AR2 0x02
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							|  |  |  | #define DSP_REG_AR3 0x03
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							|  |  |  | #define DSP_REG_IX0 0x04  // indexing registers (actually, mostly used as increments)
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							|  |  |  | #define DSP_REG_IX1 0x05
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							|  |  |  | #define DSP_REG_IX2 0x06
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							|  |  |  | #define DSP_REG_IX3 0x07
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							|  |  |  | #define DSP_REG_WR0                                                                                \
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							|  |  |  |   0x08  // address wrapping registers. should be initialized to 0xFFFF if not used.
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							|  |  |  | #define DSP_REG_WR1 0x09
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							|  |  |  | #define DSP_REG_WR2 0x0a
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							|  |  |  | #define DSP_REG_WR3 0x0b
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							|  |  |  | #define DSP_REG_ST0 0x0c  // stacks.
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							|  |  |  | #define DSP_REG_ST1 0x0d
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							|  |  |  | #define DSP_REG_ST2 0x0e
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							|  |  |  | #define DSP_REG_ST3 0x0f
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							|  |  |  | #define DSP_REG_CR 0x12  // Seems to be the top 8 bits of LRS/SRS.
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							|  |  |  | #define DSP_REG_SR 0x13
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							|  |  |  | #define DSP_REG_PRODL 0x14  // product.
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							|  |  |  | #define DSP_REG_PRODM 0x15
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							|  |  |  | #define DSP_REG_PRODH 0x16
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							|  |  |  | #define DSP_REG_PRODM2 0x17
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							|  |  |  | #define DSP_REG_AXL0 0x18
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							|  |  |  | #define DSP_REG_AXL1 0x19
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							|  |  |  | #define DSP_REG_AXH0 0x1a
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							|  |  |  | #define DSP_REG_AXH1 0x1b
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							|  |  |  | #define DSP_REG_ACC0 0x1c  // accumulator (global)
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							|  |  |  | #define DSP_REG_ACC1 0x1d
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							|  |  |  | #define DSP_REG_ACL0 0x1c  // Low accumulator
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							|  |  |  | #define DSP_REG_ACL1 0x1d
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							|  |  |  | #define DSP_REG_ACM0 0x1e  // Mid accumulator
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							|  |  |  | #define DSP_REG_ACM1 0x1f
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							|  |  |  | #define DSP_REG_ACH0 0x10  // Sign extended 8 bit register 0
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							|  |  |  | #define DSP_REG_ACH1 0x11  // Sign extended 8 bit register 1
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