Now that the accuracy of ScheduleEvent has changed, 0 cycles will
schedule an event as soon as possible. But this breaks ATV 2.
So we schedule it 100 cycles out (unless it's a really short copy)
This was a struct with exactly one element, and
an overloaded constructor which matches the construtor
of this element. So there is no need for this stacked
structur.
Detects a situation where the game is writing to the dcache at the address being DMA'd. As we do not have dcache emulation, invalid data is being DMA'd causing audio glitches. The following code detects this and enables the DMA to complete instantly before the invalid data is written.
Added accurate ARAM DMA transfer timing.
Removed the addition of DSP exception checking.
Updated ARAM DMA and FIFO write exception checking to uses these types.
Conflicts:
Source/Core/Core/PowerPC/Interpreter/Interpreter_Tables.cpp
Source/Core/Core/PowerPC/PPCTables.h
When AIDMA begins, the first thing it does is load the source address
and length into internal registers. It then triggers the AID interrupt.
Some begin the AIDMA process without all the data necessary for the
interrupt callback being set up already - they require a few more cycles
to set it up (the delay between the DMA being set to begin and the
interrupt firing). The value of this delay was approximated by tests on real
hardware.
This is good for a couple of reasons: one, it gets rid of duplicated code,
and two, DSP emulation shouldn't need to interact with audio in the first
place.
- remove unused variables
- reduce the scope where it makes sense
- correct limits (did you know that strcat()'s last parameter does not
include the \0 that is always added?)
- set some free()'d pointers to NULL
