forked from dolphin-emu/dolphin
1067 lines
31 KiB
C++
1067 lines
31 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "Common.h"
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#include "ArmEmitter.h"
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#include "CPUDetect.h"
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#include <assert.h>
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#include <stdarg.h>
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// For cache flushing on Symbian/iOS/Blackberry
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#ifdef __SYMBIAN32__
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#include <e32std.h>
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#endif
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#ifdef IOS
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#include <libkern/OSCacheControl.h>
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#include <sys/mman.h>
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#endif
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#ifdef BLACKBERRY
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#include <sys/mman.h>
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#endif
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namespace ArmGen
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{
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inline u32 RotR(u32 a, int amount) {
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if (!amount) return a;
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return (a >> amount) | (a << (32 - amount));
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}
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inline u32 RotL(u32 a, int amount) {
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if (!amount) return a;
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return (a << amount) | (a >> (32 - amount));
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}
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bool TryMakeOperand2(u32 imm, Operand2 &op2) {
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// Just brute force it.
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for (int i = 0; i < 16; i++) {
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int mask = RotR(0xFF, i * 2);
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if ((imm & mask) == imm) {
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op2 = Operand2((u8)(RotL(imm, i * 2)), (u8)i);
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return true;
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}
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}
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return false;
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}
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bool TryMakeOperand2_AllowInverse(u32 imm, Operand2 &op2, bool *inverse)
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{
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if (!TryMakeOperand2(imm, op2)) {
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*inverse = true;
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return TryMakeOperand2(~imm, op2);
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} else {
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*inverse = false;
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return true;
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}
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}
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bool TryMakeOperand2_AllowNegation(s32 imm, Operand2 &op2, bool *negated)
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{
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if (!TryMakeOperand2(imm, op2)) {
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*negated = true;
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return TryMakeOperand2(-imm, op2);
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} else {
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*negated = false;
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return true;
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}
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}
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void ARMXEmitter::MOVI2R(ARMReg reg, u32 val, bool optimize)
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{
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Operand2 op2;
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bool inverse;
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if (!optimize)
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{
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// Only used in backpatch atm
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// Only support ARMv7 right now
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if (cpu_info.bArmV7) {
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MOVW(reg, val & 0xFFFF);
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MOVT(reg, val, true);
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}
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else
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{
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// ARMv6 version won't use backpatch for now
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// Run again with optimizations
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MOVI2R(reg, val);
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}
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} else if (TryMakeOperand2_AllowInverse(val, op2, &inverse)) {
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if (!inverse)
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MOV(reg, op2);
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else
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MVN(reg, op2);
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} else {
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if (cpu_info.bArmV7) {
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// ARMv7 - can use MOVT/MOVW, best choice
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MOVW(reg, val & 0xFFFF);
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if(val & 0xFFFF0000)
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MOVT(reg, val, true);
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} else {
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// ARMv6 - fallback sequence.
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// TODO: Optimize further. Can for example choose negation etc.
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// Literal pools is another way to do this but much more complicated
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// so I can't really be bothered for an outdated CPU architecture like ARMv6.
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bool first = true;
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int shift = 16;
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for (int i = 0; i < 4; i++) {
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if (val & 0xFF) {
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if (first) {
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MOV(reg, Operand2((u8)val, (u8)(shift & 0xF)));
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first = false;
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} else {
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ORR(reg, reg, Operand2((u8)val, (u8)(shift & 0xF)));
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}
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}
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shift -= 4;
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val >>= 8;
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}
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}
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}
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}
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// Moves IMM to memory location
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void ARMXEmitter::ARMABI_MOVI2M(Operand2 op, Operand2 val)
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{
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// This moves imm to a memory location
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MOVW(R14, val); MOVT(R14, val, true);
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MOVW(R12, op); MOVT(R12, op, true);
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STR(R12, R14); // R10 is what we want to store
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}
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void ARMXEmitter::QuickCallFunction(ARMReg reg, void *func) {
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MOVI2R(reg, (u32)(func));
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BL(reg);
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}
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void ARMXEmitter::SetCodePtr(u8 *ptr)
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{
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code = ptr;
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startcode = code;
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}
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const u8 *ARMXEmitter::GetCodePtr() const
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{
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return code;
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}
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u8 *ARMXEmitter::GetWritableCodePtr()
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{
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return code;
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}
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void ARMXEmitter::ReserveCodeSpace(u32 bytes)
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{
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for (u32 i = 0; i < bytes/4; i++)
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Write32(0xE1200070); //bkpt 0
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}
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const u8 *ARMXEmitter::AlignCode16()
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{
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ReserveCodeSpace((-(s32)code) & 15);
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return code;
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}
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const u8 *ARMXEmitter::AlignCodePage()
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{
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ReserveCodeSpace((-(s32)code) & 4095);
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return code;
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}
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void ARMXEmitter::FlushIcache()
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{
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FlushIcacheSection(lastCacheFlushEnd, code);
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lastCacheFlushEnd = code;
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}
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void ARMXEmitter::FlushIcacheSection(u8 *start, u8 *end)
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{
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#ifdef __SYMBIAN32__
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User::IMB_Range(start, end);
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#elif defined(BLACKBERRY)
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msync(start, end - start, MS_SYNC | MS_INVALIDATE_ICACHE);
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#elif defined(IOS)
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sys_cache_control(kCacheFunctionPrepareForExecution, start, end - start);
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#elif !defined(_WIN32)
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#ifndef ANDROID
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start = startcode;
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#endif
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__builtin___clear_cache(start, end);
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#endif
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}
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void ARMXEmitter::SetCC(CCFlags cond)
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{
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condition = cond << 28;
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}
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void ARMXEmitter::NOP(int count)
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{
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for (int i = 0; i < count; i++) {
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Write32(condition | 0x01A00000);
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}
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}
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void ARMXEmitter::SETEND(bool BE)
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{
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//SETEND is non-conditional
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Write32( 0xF1010000 | (BE << 9));
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}
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void ARMXEmitter::BKPT(u16 arg)
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{
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Write32(condition | 0x01200070 | (arg << 4 & 0x000FFF00) | (arg & 0x0000000F));
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}
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void ARMXEmitter::YIELD()
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{
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Write32(condition | 0x0320F001);
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}
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FixupBranch ARMXEmitter::B()
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{
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FixupBranch branch;
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branch.type = 0; // Zero for B
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branch.ptr = code;
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branch.condition = condition;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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FixupBranch ARMXEmitter::BL()
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{
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FixupBranch branch;
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branch.type = 1; // Zero for B
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branch.ptr = code;
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branch.condition = condition;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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FixupBranch ARMXEmitter::B_CC(CCFlags Cond)
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{
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FixupBranch branch;
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branch.type = 0; // Zero for B
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branch.ptr = code;
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branch.condition = Cond << 28;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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void ARMXEmitter::B_CC(CCFlags Cond, const void *fnptr)
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{
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s32 distance = (s32)fnptr - (s32(code) + 8);
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"B_CC out of range (%p calls %p)", code, fnptr);
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Write32((Cond << 28) | 0x0A000000 | ((distance >> 2) & 0x00FFFFFF));
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}
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FixupBranch ARMXEmitter::BL_CC(CCFlags Cond)
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{
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FixupBranch branch;
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branch.type = 1; // Zero for B
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branch.ptr = code;
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branch.condition = Cond << 28;
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//We'll write NOP here for now.
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Write32(condition | 0x01A00000);
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return branch;
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}
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void ARMXEmitter::SetJumpTarget(FixupBranch const &branch)
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{
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s32 distance = (s32(code) - 8) - (s32)branch.ptr;
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"SetJumpTarget out of range (%p calls %p)", code,
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branch.ptr);
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if(branch.type == 0) // B
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*(u32*)branch.ptr = (u32)(branch.condition | (10 << 24) | ((distance >> 2) &
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0x00FFFFFF));
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else // BL
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*(u32*)branch.ptr = (u32)(branch.condition | 0x0B000000 | ((distance >> 2)
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& 0x00FFFFFF));
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}
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void ARMXEmitter::B (const void *fnptr)
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{
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s32 distance = (s32)fnptr - (s32(code) + 8);
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"B out of range (%p calls %p)", code, fnptr);
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Write32(condition | 0x0A000000 | ((distance >> 2) & 0x00FFFFFF));
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}
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void ARMXEmitter::B(ARMReg src)
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{
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Write32(condition | 0x12FFF10 | src);
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}
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void ARMXEmitter::BL(const void *fnptr)
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{
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s32 distance = (s32)fnptr - (s32(code) + 8);
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_assert_msg_(DYNA_REC, distance > -33554432
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&& distance <= 33554432,
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"BL out of range (%p calls %p)", code, fnptr);
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Write32(condition | 0x0B000000 | ((distance >> 2) & 0x00FFFFFF));
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}
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void ARMXEmitter::BL(ARMReg src)
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{
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Write32(condition | 0x12FFF30 | src);
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}
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void ARMXEmitter::PUSH(const int num, ...)
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{
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u16 RegList = 0;
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u8 Reg;
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int i;
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va_list vl;
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va_start(vl, num);
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for (i=0;i<num;i++)
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{
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Reg = va_arg(vl, u32);
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RegList |= (1 << Reg);
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}
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va_end(vl);
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Write32(condition | (2349 << 16) | RegList);
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}
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void ARMXEmitter::POP(const int num, ...)
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{
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u16 RegList = 0;
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u8 Reg;
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int i;
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va_list vl;
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va_start(vl, num);
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for (i=0;i<num;i++)
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{
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Reg = va_arg(vl, u32);
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RegList |= (1 << Reg);
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}
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va_end(vl);
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Write32(condition | (2237 << 16) | RegList);
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}
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void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, Operand2 op2)
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{
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Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | op2.Imm5() | (op << 4) | src);
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}
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void ARMXEmitter::WriteShiftedDataOp(u32 op, bool SetFlags, ARMReg dest, ARMReg src, ARMReg op2)
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{
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Write32(condition | (13 << 21) | (SetFlags << 20) | (dest << 12) | (op2 << 8) | (op << 4) | src);
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}
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// IMM, REG, IMMSREG, RSR
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// -1 for invalid if the instruction doesn't support that
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const s32 InstOps[][4] = {{16, 0, 0, 0}, // AND(s)
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{17, 1, 1, 1}, // EOR(s)
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{18, 2, 2, 2}, // SUB(s)
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{19, 3, 3, 3}, // RSB(s)
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{20, 4, 4, 4}, // ADD(s)
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{21, 5, 5, 5}, // ADC(s)
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{22, 6, 6, 6}, // SBC(s)
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{23, 7, 7, 7}, // RSC(s)
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{24, 8, 8, 8}, // TST
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{25, 9, 9, 9}, // TEQ
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{26, 10, 10, 10}, // CMP
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{27, 11, 11, 11}, // CMN
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{28, 12, 12, 12}, // ORR(s)
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{29, 13, 13, 13}, // MOV(s)
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{30, 14, 14, 14}, // BIC(s)
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{31, 15, 15, 15}, // MVN(s)
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{24, -1, -1, -1}, // MOVW
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{26, -1, -1, -1}, // MOVT
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};
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const char *InstNames[] = { "AND",
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"EOR",
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"SUB",
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"RSB",
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"ADD",
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"ADC",
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"SBC",
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"RSC",
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"TST",
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"TEQ",
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"CMP",
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"CMN",
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"ORR",
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"MOV",
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"BIC",
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"MVN"
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};
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void ARMXEmitter::AND (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm); }
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void ARMXEmitter::ANDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(0, Rd, Rn, Rm, true); }
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void ARMXEmitter::EOR (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(1, Rd, Rn, Rm); }
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void ARMXEmitter::EORS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(1, Rd, Rn, Rm, true); }
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void ARMXEmitter::SUB (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(2, Rd, Rn, Rm); }
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void ARMXEmitter::SUBS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(2, Rd, Rn, Rm, true); }
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void ARMXEmitter::RSB (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(3, Rd, Rn, Rm); }
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void ARMXEmitter::RSBS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(3, Rd, Rn, Rm, true); }
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void ARMXEmitter::ADD (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(4, Rd, Rn, Rm); }
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void ARMXEmitter::ADDS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(4, Rd, Rn, Rm, true); }
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void ARMXEmitter::ADC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(5, Rd, Rn, Rm); }
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void ARMXEmitter::ADCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(5, Rd, Rn, Rm, true); }
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void ARMXEmitter::SBC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(6, Rd, Rn, Rm); }
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void ARMXEmitter::SBCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(6, Rd, Rn, Rm, true); }
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void ARMXEmitter::RSC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(7, Rd, Rn, Rm); }
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void ARMXEmitter::RSCS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(7, Rd, Rn, Rm, true); }
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void ARMXEmitter::TST ( ARMReg Rn, Operand2 Rm) { WriteInstruction(8, R0, Rn, Rm, true); }
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void ARMXEmitter::TEQ ( ARMReg Rn, Operand2 Rm) { WriteInstruction(9, R0, Rn, Rm, true); }
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void ARMXEmitter::CMP ( ARMReg Rn, Operand2 Rm) { WriteInstruction(10, R0, Rn, Rm, true); }
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void ARMXEmitter::CMN ( ARMReg Rn, Operand2 Rm) { WriteInstruction(11, R0, Rn, Rm, true); }
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void ARMXEmitter::ORR (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(12, Rd, Rn, Rm); }
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void ARMXEmitter::ORRS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(12, Rd, Rn, Rm, true); }
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void ARMXEmitter::MOV (ARMReg Rd, Operand2 Rm) { WriteInstruction(13, Rd, R0, Rm); }
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void ARMXEmitter::MOVS(ARMReg Rd, Operand2 Rm) { WriteInstruction(13, Rd, R0, Rm, true); }
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void ARMXEmitter::BIC (ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(14, Rd, Rn, Rm); }
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void ARMXEmitter::BICS(ARMReg Rd, ARMReg Rn, Operand2 Rm) { WriteInstruction(14, Rd, Rn, Rm, true); }
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void ARMXEmitter::MVN (ARMReg Rd, Operand2 Rm) { WriteInstruction(15, Rd, R0, Rm); }
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void ARMXEmitter::MVNS(ARMReg Rd, Operand2 Rm) { WriteInstruction(15, Rd, R0, Rm, true); }
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void ARMXEmitter::MOVW(ARMReg Rd, Operand2 Rm) { WriteInstruction(16, Rd, R0, Rm); }
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void ARMXEmitter::MOVT(ARMReg Rd, Operand2 Rm, bool TopBits) { WriteInstruction(17, Rd, R0, TopBits ? Rm.Value >> 16 : Rm); }
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void ARMXEmitter::WriteInstruction (u32 Op, ARMReg Rd, ARMReg Rn, Operand2 Rm, bool SetFlags) // This can get renamed later
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{
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s32 op = InstOps[Op][Rm.GetType()]; // Type always decided by last operand
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u32 Data = Rm.GetData();
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if (Rm.GetType() == TYPE_IMM)
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{
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switch (Op)
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{
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// MOV cases that support IMM16
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case 16:
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case 17:
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Data = Rm.Imm16();
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break;
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default:
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break;
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}
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}
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if (op == -1)
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_assert_msg_(DYNA_REC, false, "%s not yet support %d", InstNames[Op], Rm.GetType());
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Write32(condition | (op << 21) | (SetFlags ? (1 << 20) : 0) | Rn << 16 | Rd << 12 | Data);
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}
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// Data Operations
|
|
void ARMXEmitter::WriteSignedMultiply(u32 Op, u32 Op2, u32 Op3, ARMReg dest, ARMReg r1, ARMReg r2)
|
|
{
|
|
Write32(condition | (0x7 << 24) | (Op << 20) | (dest << 16) | (Op2 << 12) | (r1 << 8) | (Op3 << 5) | (1 << 4) | r2);
|
|
}
|
|
void ARMXEmitter::UDIV(ARMReg dest, ARMReg dividend, ARMReg divisor)
|
|
{
|
|
if (!cpu_info.bIDIVa)
|
|
PanicAlert("Trying to use integer divide on hardware that doesn't support it. Bad programmer.");
|
|
WriteSignedMultiply(3, 0xF, 0, dest, divisor, dividend);
|
|
}
|
|
void ARMXEmitter::SDIV(ARMReg dest, ARMReg dividend, ARMReg divisor)
|
|
{
|
|
if (!cpu_info.bIDIVa)
|
|
PanicAlert("Trying to use integer divide on hardware that doesn't support it. Bad programmer.");
|
|
WriteSignedMultiply(1, 0xF, 0, dest, divisor, dividend);
|
|
}
|
|
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, false, dest, src, op2);}
|
|
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, Operand2 op2) { WriteShiftedDataOp(0, true, dest, src, op2);}
|
|
void ARMXEmitter::LSL (ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, false, dest, src, op2);}
|
|
void ARMXEmitter::LSLS(ARMReg dest, ARMReg src, ARMReg op2) { WriteShiftedDataOp(1, true, dest, src, op2);}
|
|
void ARMXEmitter::MUL (ARMReg dest, ARMReg src, ARMReg op2)
|
|
{
|
|
Write32(condition | (dest << 16) | (src << 8) | (9 << 4) | op2);
|
|
}
|
|
void ARMXEmitter::MULS(ARMReg dest, ARMReg src, ARMReg op2)
|
|
{
|
|
Write32(condition | (1 << 20) | (dest << 16) | (src << 8) | (9 << 4) | op2);
|
|
}
|
|
|
|
void ARMXEmitter::Write4OpMultiply(u32 op, ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn) {
|
|
Write32(condition | (op << 20) | (destHi << 16) | (destLo << 12) | (rm << 8) | (9 << 4) | rn);
|
|
}
|
|
|
|
void ARMXEmitter::UMULL(ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn)
|
|
{
|
|
Write4OpMultiply(0x8, destLo, destHi, rn, rm);
|
|
}
|
|
|
|
void ARMXEmitter::SMULL(ARMReg destLo, ARMReg destHi, ARMReg rm, ARMReg rn)
|
|
{
|
|
Write4OpMultiply(0xC, destLo, destHi, rn, rm);
|
|
}
|
|
|
|
void ARMXEmitter::SXTB (ARMReg dest, ARMReg op2)
|
|
{
|
|
Write32(condition | (0x6AF << 16) | (dest << 12) | (7 << 4) | op2);
|
|
}
|
|
void ARMXEmitter::SXTH (ARMReg dest, ARMReg op2, u8 rotation)
|
|
{
|
|
SXTAH(dest, (ARMReg)15, op2, rotation);
|
|
}
|
|
void ARMXEmitter::SXTAH(ARMReg dest, ARMReg src, ARMReg op2, u8 rotation)
|
|
{
|
|
// bits ten and 11 are the rotation amount, see 8.8.232 for more
|
|
// information
|
|
Write32(condition | (0x6B << 20) | (src << 16) | (dest << 12) | (rotation << 10) | (7 << 4) | op2);
|
|
}
|
|
void ARMXEmitter::REV (ARMReg dest, ARMReg src )
|
|
{
|
|
Write32(condition | (107 << 20) | (15 << 16) | (dest << 12) | (243 << 4) | src);
|
|
}
|
|
void ARMXEmitter::REV16(ARMReg dest, ARMReg src)
|
|
{
|
|
Write32(condition | (0x3DF << 16) | (dest << 12) | (0xFD << 4) | src);
|
|
}
|
|
|
|
void ARMXEmitter::_MSR (bool write_nzcvq, bool write_g, Operand2 op2)
|
|
{
|
|
Write32(condition | (0x320F << 12) | (write_nzcvq << 19) | (write_g << 18) | op2.Imm12Mod());
|
|
}
|
|
void ARMXEmitter::_MSR (bool write_nzcvq, bool write_g, ARMReg src)
|
|
{
|
|
Write32(condition | (0x120F << 12) | (write_nzcvq << 19) | (write_g << 18) | src);
|
|
}
|
|
void ARMXEmitter::MRS (ARMReg dest)
|
|
{
|
|
Write32(condition | (16 << 20) | (15 << 16) | (dest << 12));
|
|
}
|
|
|
|
void ARMXEmitter::WriteStoreOp(u32 op, ARMReg dest, ARMReg src, s16 op2)
|
|
{
|
|
bool Index = op2 != 0 ? true : false;
|
|
bool Add = op2 >= 0 ? true : false;
|
|
u32 imm = abs(op2);
|
|
Write32(condition | (op << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (src << 12) | imm);
|
|
}
|
|
void ARMXEmitter::STR (ARMReg dest, ARMReg src, s16 op) { WriteStoreOp(0x40, dest, src, op);}
|
|
void ARMXEmitter::STRB(ARMReg dest, ARMReg src, s16 op) { WriteStoreOp(0x44, dest, src, op);}
|
|
void ARMXEmitter::STR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
|
|
{
|
|
Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | offset);
|
|
}
|
|
void ARMXEmitter::LDREX(ARMReg dest, ARMReg base)
|
|
{
|
|
Write32(condition | (25 << 20) | (base << 16) | (dest << 12) | 0xF9F);
|
|
}
|
|
void ARMXEmitter::STREX(ARMReg dest, ARMReg base, ARMReg op)
|
|
{
|
|
_assert_msg_(DYNA_REC, (dest != base && dest != op), "STREX dest can't be other two registers");
|
|
Write32(condition | (24 << 20) | (base << 16) | (dest << 12) | (0xF9 << 4) | op);
|
|
}
|
|
void ARMXEmitter::DMB ()
|
|
{
|
|
Write32(0xF57FF05E);
|
|
}
|
|
void ARMXEmitter::SVC(Operand2 op)
|
|
{
|
|
Write32(condition | (0x0F << 24) | op.Imm24());
|
|
}
|
|
|
|
void ARMXEmitter::LDR (ARMReg dest, ARMReg src, s16 op) { WriteStoreOp(0x41, src, dest, op);}
|
|
void ARMXEmitter::LDRH(ARMReg dest, ARMReg src, Operand2 op)
|
|
{
|
|
u8 Imm = op.Imm8();
|
|
Write32(condition | (0x05 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
|
|
}
|
|
void ARMXEmitter::LDRB(ARMReg dest, ARMReg src, s16 op) { WriteStoreOp(0x45, src, dest, op);}
|
|
|
|
void ARMXEmitter::LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
|
|
{
|
|
Write32(condition | (0x61 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (dest << 12) | offset);
|
|
}
|
|
void ARMXEmitter::WriteRegStoreOp(u32 op, ARMReg dest, bool WriteBack, u16 RegList)
|
|
{
|
|
Write32(condition | (op << 20) | (WriteBack << 21) | (dest << 16) | RegList);
|
|
}
|
|
void ARMXEmitter::STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...)
|
|
{
|
|
u16 RegList = 0;
|
|
u8 Reg;
|
|
int i;
|
|
va_list vl;
|
|
va_start(vl, Regnum);
|
|
for (i=0;i<Regnum;i++)
|
|
{
|
|
Reg = va_arg(vl, u32);
|
|
RegList |= (1 << Reg);
|
|
}
|
|
va_end(vl);
|
|
WriteRegStoreOp(0x90, dest, WriteBack, RegList);
|
|
}
|
|
void ARMXEmitter::LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...)
|
|
{
|
|
u16 RegList = 0;
|
|
u8 Reg;
|
|
int i;
|
|
va_list vl;
|
|
va_start(vl, Regnum);
|
|
for (i=0;i<Regnum;i++)
|
|
{
|
|
Reg = va_arg(vl, u32);
|
|
RegList |= (1 << Reg);
|
|
}
|
|
va_end(vl);
|
|
WriteRegStoreOp(0x89, dest, WriteBack, RegList);
|
|
}
|
|
|
|
ARMReg ARMXEmitter::SubBase(ARMReg Reg)
|
|
{
|
|
if (Reg >= S0)
|
|
{
|
|
if (Reg >= D0)
|
|
{
|
|
if (Reg >= Q0)
|
|
return (ARMReg)((Reg - Q0) * 2); // Always gets encoded as a double register
|
|
return (ARMReg)(Reg - D0);
|
|
}
|
|
return (ARMReg)(Reg - S0);
|
|
}
|
|
return Reg;
|
|
}
|
|
|
|
// NEON Specific
|
|
void ARMXEmitter::VADD(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd >= D0, "Pass invalid register to VADD(integer)");
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Can't use VADD(integer) when CPU doesn't support it");
|
|
|
|
bool register_quad = Vd >= Q0;
|
|
|
|
// Gets encoded as a double register
|
|
Vd = SubBase(Vd);
|
|
Vn = SubBase(Vn);
|
|
Vm = SubBase(Vm);
|
|
|
|
Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | (Size << 20) | ((Vn & 0xF) << 16) \
|
|
| ((Vd & 0xF) << 12) | (0x8 << 8) | ((Vn & 0x10) << 3) | (register_quad << 6) \
|
|
| ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
|
|
}
|
|
void ARMXEmitter::VSUB(IntegerSize Size, ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd >= Q0, "Pass invalid register to VSUB(integer)");
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Can't use VSUB(integer) when CPU doesn't support it");
|
|
|
|
// Gets encoded as a double register
|
|
Vd = SubBase(Vd);
|
|
Vn = SubBase(Vn);
|
|
Vm = SubBase(Vm);
|
|
|
|
Write32((0xF3 << 24) | ((Vd & 0x10) << 18) | (Size << 20) | ((Vn & 0xF) << 16) \
|
|
| ((Vd & 0xF) << 12) | (0x8 << 8) | ((Vn & 0x10) << 3) | (1 << 6) \
|
|
| ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
|
|
// VFP Specific
|
|
|
|
void ARMXEmitter::VLDR(ARMReg Dest, ARMReg Base, s16 offset)
|
|
{
|
|
_assert_msg_(DYNA_REC, Dest >= S0 && Dest <= D31, "Passed Invalid dest register to VLDR");
|
|
_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid Base register to VLDR");
|
|
|
|
bool Add = offset >= 0 ? true : false;
|
|
u32 imm = abs(offset);
|
|
|
|
_assert_msg_(DYNA_REC, (imm & 0xC03) == 0, "VLDR: Offset needs to be word aligned and small enough");
|
|
|
|
if (imm & 0xC03) {
|
|
ERROR_LOG(DYNA_REC, "VLDR: Bad offset %08x", imm);
|
|
}
|
|
|
|
bool single_reg = Dest < D0;
|
|
|
|
Dest = SubBase(Dest);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0xD << 24) | (Add << 23) | ((Dest & 0x1) << 22) | (1 << 20) | (Base << 16) \
|
|
| ((Dest & 0x1E) << 11) | (10 << 8) | (imm >> 2));
|
|
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0xD << 24) | (Add << 23) | ((Dest & 0x10) << 18) | (1 << 20) | (Base << 16) \
|
|
| ((Dest & 0xF) << 12) | (11 << 8) | (imm >> 2));
|
|
}
|
|
}
|
|
void ARMXEmitter::VSTR(ARMReg Src, ARMReg Base, s16 offset)
|
|
{
|
|
_assert_msg_(DYNA_REC, Src >= S0 && Src <= D31, "Passed invalid src register to VSTR");
|
|
_assert_msg_(DYNA_REC, Base <= R15, "Passed invalid base register to VSTR");
|
|
|
|
bool Add = offset >= 0 ? true : false;
|
|
u32 imm = abs(offset);
|
|
|
|
_assert_msg_(DYNA_REC, (imm & 0xC03) == 0, "VSTR: Offset needs to be word aligned and small enough");
|
|
|
|
if (imm & 0xC03) {
|
|
ERROR_LOG(DYNA_REC, "VSTR: Bad offset %08x", imm);
|
|
}
|
|
|
|
bool single_reg = Src < D0;
|
|
|
|
Src = SubBase(Src);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0xD << 24) | (Add << 23) | ((Src & 0x1) << 22) | (Base << 16) \
|
|
| ((Src & 0x1E) << 11) | (10 << 8) | (imm >> 2));
|
|
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0xD << 24) | (Add << 23) | ((Src & 0x10) << 18) | (Base << 16) \
|
|
| ((Src & 0xF) << 12) | (11 << 8) | (imm >> 2));
|
|
}
|
|
}
|
|
void ARMXEmitter::VCMP(ARMReg Vd, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
|
|
bool single_reg = Vd < D0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x34 << 16) | ((Vd & 0x1E) << 11) \
|
|
| (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x34 << 16) | ((Vd & 0xF) << 12) \
|
|
| (0x2F << 6) | ((Vm & 0x10) << 1) | (Vm & 0xF));
|
|
}
|
|
}
|
|
void ARMXEmitter::VCMP(ARMReg Vd)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd < Q0, "Passed invalid Vd to VCMP");
|
|
bool single_reg = Vd < D0;
|
|
|
|
Vd = SubBase(Vd);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x35 << 16) | ((Vd & 0x1E) << 11) \
|
|
| (0x2B << 6));
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x35 << 16) | ((Vd & 0xF) << 12) \
|
|
| (0x2F << 6));
|
|
}
|
|
}
|
|
void ARMXEmitter::VDIV(ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd < Q0, "Pased invalid dest register to VSQRT");
|
|
_assert_msg_(DYNA_REC, Vn < Q0, "Passed invalid Vn to VSQRT");
|
|
_assert_msg_(DYNA_REC, Vm < Q0, "Passed invalid Vm to VSQRT");
|
|
bool single_reg = Vd < D0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vn = SubBase(Vn);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | ((Vn & 0x1E) << 15) \
|
|
| ((Vd & 0x1E) << 11) | (0xA << 8) | ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) \
|
|
| (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
|
|
| ((Vd & 0xF) << 12) | (0xB << 8) | ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) \
|
|
| (Vm & 0xF));
|
|
}
|
|
}
|
|
void ARMXEmitter::VSQRT(ARMReg Vd, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd < Q0, "Pased invalid dest register to VSQRT");
|
|
_assert_msg_(DYNA_REC, Vm < Q0, "Passed invalid Vm to VSQRT");
|
|
bool single_reg = Vd < D0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
|
|
| ((Vd & 0x1E) << 11) | (0x2B << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
|
|
| ((Vd & 0xF) << 12) | (0x2F << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
}
|
|
|
|
// VFP and ASIMD
|
|
void ARMXEmitter::VABS(ARMReg Vd, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd < Q0, "VABS doesn't currently support Quad reg");
|
|
_assert_msg_(DYNA_REC, Vd >= S0, "VABS doesn't support ARM Regs");
|
|
bool single_reg = Vd < D0;
|
|
bool double_reg = Vd < Q0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0xEB << 20) | ((Vd & 0x1) << 22) | ((Vd & 0x1E) << 11) \
|
|
| (0xAC << 4) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
if (double_reg)
|
|
{
|
|
Write32(NO_COND | (0xEB << 20) | ((Vd & 0x10) << 18) | ((Vd & 0xF) << 12) \
|
|
| (0xBC << 4) | ((Vm & 0x10) << 1) | (Vm & 0xF));
|
|
}
|
|
else
|
|
{
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
|
|
// XXX: TODO
|
|
}
|
|
}
|
|
}
|
|
|
|
void ARMXEmitter::VADD(ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VADD");
|
|
_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VADD");
|
|
_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VADD");
|
|
bool single_reg = Vd < D0;
|
|
bool double_reg = Vd < Q0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vn = SubBase(Vn);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
|
|
| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
|
|
| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
if (double_reg)
|
|
{
|
|
Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
|
|
| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
|
|
| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
else
|
|
{
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
|
|
Write32((0xF2 << 24) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
|
|
| ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3) \
|
|
| (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
}
|
|
}
|
|
void ARMXEmitter::VSUB(ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VSUB");
|
|
_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VSUB");
|
|
_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VSUB");
|
|
bool single_reg = Vd < D0;
|
|
bool double_reg = Vd < Q0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vn = SubBase(Vn);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x3 << 20) \
|
|
| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
|
|
| ((Vn & 0x1) << 7) | (1 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
if (double_reg)
|
|
{
|
|
Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x3 << 20) \
|
|
| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
|
|
| ((Vn & 0x10) << 3) | (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
else
|
|
{
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VADD with Quad Reg without support!");
|
|
Write32((0xF2 << 24) | (1 << 21) | ((Vd & 0x10) << 18) | ((Vn & 0xF) << 16) \
|
|
| ((Vd & 0xF) << 12) | (0xD << 8) | ((Vn & 0x10) << 3) \
|
|
| (1 << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
}
|
|
}
|
|
void ARMXEmitter::VMUL(ARMReg Vd, ARMReg Vn, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd >= S0, "Passed invalid dest register to VADD");
|
|
_assert_msg_(DYNA_REC, Vn >= S0, "Passed invalid Vn to VADD");
|
|
_assert_msg_(DYNA_REC, Vm >= S0, "Passed invalid Vm to VADD");
|
|
bool single_reg = Vd < D0;
|
|
bool double_reg = Vd < Q0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vn = SubBase(Vn);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1C << 23) | ((Vd & 0x1) << 22) | (0x2 << 20) \
|
|
| ((Vn & 0x1E) << 15) | ((Vd & 0x1E) << 11) | (0x5 << 9) \
|
|
| ((Vn & 0x1) << 7) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
if (double_reg)
|
|
{
|
|
Write32(NO_COND | (0x1C << 23) | ((Vd & 0x10) << 18) | (0x2 << 20) \
|
|
| ((Vn & 0xF) << 16) | ((Vd & 0xF) << 12) | (0xB << 8) \
|
|
| ((Vn & 0x10) << 3) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
else
|
|
{
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VMUL with Quad Reg without support!");
|
|
// XXX: TODO
|
|
}
|
|
}
|
|
}
|
|
|
|
void ARMXEmitter::VNEG(ARMReg Vd, ARMReg Vm)
|
|
{
|
|
_assert_msg_(DYNA_REC, Vd < Q0, "VNEG doesn't currently support Quad reg");
|
|
_assert_msg_(DYNA_REC, Vd >= S0, "VNEG doesn't support ARM Regs");
|
|
bool single_reg = Vd < D0;
|
|
bool double_reg = Vd < Q0;
|
|
|
|
Vd = SubBase(Vd);
|
|
Vm = SubBase(Vm);
|
|
|
|
if (single_reg)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x1) << 22) | (0x31 << 16) \
|
|
| ((Vd & 0x1E) << 11) | (0x29 << 6) | ((Vm & 0x1) << 5) | (Vm >> 1));
|
|
}
|
|
else
|
|
{
|
|
if (double_reg)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Vd & 0x10) << 18) | (0x31 << 16) \
|
|
| ((Vd & 0xF) << 12) | (0x2D << 6) | ((Vm & 0x10) << 2) | (Vm & 0xF));
|
|
}
|
|
else
|
|
{
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use VNEG with Quad Reg without support!");
|
|
// XXX: TODO
|
|
|
|
}
|
|
}
|
|
}
|
|
|
|
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src, bool high)
|
|
{
|
|
_assert_msg_(DYNA_REC, Src < S0, "This VMOV doesn't support SRC other than ARM Reg");
|
|
_assert_msg_(DYNA_REC, Dest >= D0, "This VMOV doesn't support DEST other than VFP");
|
|
|
|
Dest = SubBase(Dest);
|
|
|
|
Write32(NO_COND | (0xE << 24) | (high << 21) | ((Dest & 0xF) << 16) | (Src << 12) \
|
|
| (11 << 8) | ((Dest & 0x10) << 3) | (1 << 4));
|
|
}
|
|
|
|
void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
|
|
{
|
|
if (Dest > R15)
|
|
{
|
|
if (Src < S0)
|
|
{
|
|
if (Dest < D0)
|
|
{
|
|
// Moving to a Neon register FROM ARM Reg
|
|
Dest = (ARMReg)(Dest - S0);
|
|
Write32(NO_COND | (0xE0 << 20) | ((Dest & 0x1E) << 15) | (Src << 12) \
|
|
| (0xA << 8) | ((Dest & 0x1) << 7) | (1 << 4));
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
// Move 64bit from Arm reg
|
|
_assert_msg_(DYNA_REC, false, "This VMOV doesn't support moving 64bit ARM to NEON");
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (Src > R15)
|
|
{
|
|
if (Src < D0)
|
|
{
|
|
// Moving to ARM Reg from Neon Register
|
|
Src = (ARMReg)(Src - S0);
|
|
Write32(NO_COND | (0xE1 << 20) | ((Src & 0x1E) << 15) | (Dest << 12) \
|
|
| (0xA << 8) | ((Src & 0x1) << 7) | (1 << 4));
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
// Move 64bit To Arm reg
|
|
_assert_msg_(DYNA_REC, false, "This VMOV doesn't support moving 64bit ARM From NEON");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// Move Arm reg to Arm reg
|
|
_assert_msg_(DYNA_REC, false, "VMOV doesn't support moving ARM registers");
|
|
}
|
|
}
|
|
// Moving NEON registers
|
|
int SrcSize = Src < D0 ? 1 : Src < Q0 ? 2 : 4;
|
|
int DestSize = Dest < D0 ? 1 : Dest < Q0 ? 2 : 4;
|
|
bool Single = DestSize == 1;
|
|
bool Quad = DestSize == 4;
|
|
|
|
_assert_msg_(DYNA_REC, SrcSize == DestSize, "VMOV doesn't support moving different register sizes");
|
|
|
|
Dest = SubBase(Dest);
|
|
Src = SubBase(Src);
|
|
|
|
if (Single)
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Dest & 0x1) << 22) | (0x3 << 20) | ((Dest & 0x1E) << 11) \
|
|
| (0x5 << 9) | (1 << 6) | ((Src & 0x1) << 5) | ((Src & 0x1E) >> 1));
|
|
}
|
|
else
|
|
{
|
|
// Double and quad
|
|
if (Quad)
|
|
{
|
|
_assert_msg_(DYNA_REC, cpu_info.bNEON, "Trying to use quad registers when you don't support ASIMD.");
|
|
// Gets encoded as a Double register
|
|
Write32((0xF2 << 24) | ((Dest & 0x10) << 18) | (2 << 20) | ((Src & 0xF) << 16) \
|
|
| ((Dest & 0xF) << 12) | (1 << 8) | ((Src & 0x10) << 3) | (1 << 6) \
|
|
| ((Src & 0x10) << 1) | (1 << 4) | (Src & 0xF));
|
|
|
|
}
|
|
else
|
|
{
|
|
Write32(NO_COND | (0x1D << 23) | ((Dest & 0x10) << 18) | (0x3 << 20) | ((Dest & 0xF) << 12) \
|
|
| (0x2D << 6) | ((Src & 0x10) << 1) | (Src & 0xF));
|
|
}
|
|
}
|
|
}
|
|
|
|
}
|