forked from dolphin-emu/dolphin
04105baf4e
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3573 8ced0084-cf51-0410-be5f-012b33b47a6e
314 lines
7.5 KiB
C++
314 lines
7.5 KiB
C++
/*====================================================================
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filename: gdsp_interface.h
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project: GCemu
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created: 2004-6-18
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mail: duddie@walla.com
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Copyright (c) 2005 Duddie & Tratax
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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====================================================================*/
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#include <stdlib.h>
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#include "Thread.h"
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#include "MemoryUtil.h"
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#include "DSPCore.h"
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#include "DSPHost.h"
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#include "DSPTables.h"
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#include "DSPAnalyzer.h"
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#include "DSPAccelerator.h"
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#include "DSPInterpreter.h"
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#include "DSPHWInterface.h"
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void gdsp_do_dma();
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Common::CriticalSection g_CriticalSection;
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static volatile u16 gdsp_mbox[2][2];
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u16 gdsp_ifx_regs[256];
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void gdsp_ifx_init()
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{
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for (int i = 0; i < 256; i++)
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{
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gdsp_ifx_regs[i] = 0;
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}
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gdsp_mbox[0][0] = 0;
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gdsp_mbox[0][1] = 0;
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gdsp_mbox[1][0] = 0;
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gdsp_mbox[1][1] = 0;
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}
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u32 gdsp_mbox_peek(u8 mbx)
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{
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if (DSPHost_OnThread())
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g_CriticalSection.Enter();
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u32 value = ((gdsp_mbox[mbx][0] << 16) | gdsp_mbox[mbx][1]);
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if (DSPHost_OnThread())
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g_CriticalSection.Leave();
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return value;
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}
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void gdsp_mbox_write_h(u8 mbx, u16 val)
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{
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if (DSPHost_OnThread())
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g_CriticalSection.Enter();
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gdsp_mbox[mbx][0] = val & 0x7fff;
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if (DSPHost_OnThread())
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g_CriticalSection.Leave();
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}
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void gdsp_mbox_write_l(u8 mbx, u16 val)
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{
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if (DSPHost_OnThread())
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g_CriticalSection.Enter();
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gdsp_mbox[mbx][1] = val;
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gdsp_mbox[mbx][0] |= 0x8000;
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if (DSPHost_OnThread())
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g_CriticalSection.Leave();
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if (mbx == GDSP_MBOX_DSP)
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{
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DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
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} else {
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// Trigger exception?
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}
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}
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u16 gdsp_mbox_read_h(u8 mbx)
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{
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return gdsp_mbox[mbx][0]; // TODO: mask away the top bit?
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}
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u16 gdsp_mbox_read_l(u8 mbx)
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{
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if (DSPHost_OnThread())
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g_CriticalSection.Enter();
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u16 val = gdsp_mbox[mbx][1];
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gdsp_mbox[mbx][0] &= ~0x8000;
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DEBUG_LOG(DSPLLE, "- DSP reads mail from mbx %i: %08x (pc=0x%04x)", mbx, gdsp_mbox_peek(mbx), g_dsp.pc);
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if (DSPHost_OnThread())
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g_CriticalSection.Leave();
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return val;
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}
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void gdsp_ifx_write(u16 addr, u16 val)
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{
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switch (addr & 0xff)
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{
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case 0xfb: // DIRQ
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if (val & 0x1)
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DSPHost_InterruptRequest();
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break;
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case 0xfc: // DMBH
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gdsp_mbox_write_h(GDSP_MBOX_DSP, val);
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break;
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case 0xfd: // DMBL
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gdsp_mbox_write_l(GDSP_MBOX_DSP, val);
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break;
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case 0xcb: // DSBL
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gdsp_ifx_regs[addr & 0xFF] = val;
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gdsp_do_dma();
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gdsp_ifx_regs[DSP_DSCR] &= ~0x0004;
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break;
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case 0xd3: // ZeldaUnk (accelerator WRITE)
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ERROR_LOG(DSPLLE, "Write To ZeldaUnk pc=%04x (%04x)\n", g_dsp.pc, val);
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dsp_write_aram_d3(val);
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break;
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case 0xde:
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//if (val)
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// PanicAlert("Gain written: %04x", val); // BMX XXX does, and sounds HORRIBLE.
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case 0xcd:
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case 0xce:
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case 0xcf:
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case 0xc9:
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gdsp_ifx_regs[addr & 0xFF] = val;
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break;
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default:
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if ((addr & 0xff) >= 0xa0) {
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if (pdlabels[(addr & 0xFF) - 0xa0].name) {
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INFO_LOG(DSPLLE, "%04x MW %s (%04x)\n", g_dsp.pc, pdlabels[(addr & 0xFF) - 0xa0].name, val);
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}
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else {
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ERROR_LOG(DSPLLE, "%04x MW %04x (%04x)\n", g_dsp.pc, addr, val);
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}
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}
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else {
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ERROR_LOG(DSPLLE, "%04x MW %04x (%04x)\n", g_dsp.pc, addr, val);
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}
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gdsp_ifx_regs[addr & 0xFF] = val;
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break;
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}
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}
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u16 gdsp_ifx_read(u16 addr)
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{
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switch (addr & 0xff)
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{
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case 0xfc: // DMBH
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return gdsp_mbox_read_h(GDSP_MBOX_DSP);
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case 0xfe: // CMBH
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return gdsp_mbox_read_h(GDSP_MBOX_CPU);
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case 0xff: // CMBL
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return gdsp_mbox_read_l(GDSP_MBOX_CPU);
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case 0xc9:
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return gdsp_ifx_regs[addr & 0xFF];
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case 0xdd: // ADPCM Accelerator reads
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return dsp_read_accelerator();
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case 0xd3:
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ERROR_LOG(DSPLLE, "DSP read aram D3");
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return dsp_read_aram_d3();
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default:
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if ((addr & 0xff) >= 0xa0) {
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if (pdlabels[(addr & 0xFF) - 0xa0].name) {
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INFO_LOG(DSPLLE, "%04x MR %s (%04x)\n", g_dsp.pc, pdlabels[(addr & 0xFF) - 0xa0].name, gdsp_ifx_regs[addr & 0xFF]);
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}
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else {
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ERROR_LOG(DSPLLE, "%04x MR %04x (%04x)\n", g_dsp.pc, addr, gdsp_ifx_regs[addr & 0xFF]);
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}
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}
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else {
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ERROR_LOG(DSPLLE, "%04x MR %04x (%04x)\n", g_dsp.pc, addr, gdsp_ifx_regs[addr & 0xFF]);
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}
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return gdsp_ifx_regs[addr & 0xFF];
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}
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}
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void gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
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{
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UnWriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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u8* dst = ((u8*)g_dsp.iram);
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for (u32 i = 0; i < size; i += 2)
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{
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// TODO : this may be different on Wii.
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*(u16*)&dst[dsp_addr + i] = Common::swap16(*(const u16*)&g_dsp.cpu_ram[(addr + i) & 0x0fffffff]);
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}
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WriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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INFO_LOG(DSPLLE, "*** Copy new UCode from 0x%08x to 0x%04x (crc: %8x)\n", addr, dsp_addr, g_dsp.iram_crc);
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g_dsp.iram_crc = DSPHost_CodeLoaded(g_dsp.cpu_ram + (addr & 0x0fffffff), size);
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DSPAnalyzer::Analyze();
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}
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void gdsp_idma_out(u16 dsp_addr, u32 addr, u32 size)
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{
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ERROR_LOG(DSPLLE, "*** idma_out IRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
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}
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// TODO: These should eat clock cycles.
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void gdsp_ddma_in(u16 dsp_addr, u32 addr, u32 size)
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{
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if ((addr & 0x7FFFFFFF) > 0x01FFFFFF)
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{
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ERROR_LOG(DSPLLE, "*** ddma_in read from invalid addr (0x%08x)\n", addr);
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return;
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}
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u8* dst = ((u8*)g_dsp.dram);
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for (u32 i = 0; i < size; i += 2)
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{
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*(u16*)&dst[dsp_addr + i] = Common::swap16(*(const u16*)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF]);
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}
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INFO_LOG(DSPLLE, "*** ddma_in RAM (0x%08x) -> DRAM_DSP (0x%04x) : size (0x%08x)\n", addr, dsp_addr / 2, size);
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}
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void gdsp_ddma_out(u16 dsp_addr, u32 addr, u32 size)
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{
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if ((addr & 0x7FFFFFFF) > 0x01FFFFFF)
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{
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ERROR_LOG(DSPLLE, "*** gdsp_ddma_out to invalid addr (0x%08x)\n", addr);
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return;
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}
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const u8* src = ((const u8*)g_dsp.dram);
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for (u32 i = 0; i < size; i += 2)
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{
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*(u16*)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF] = Common::swap16(*(const u16*)&src[dsp_addr + i]);
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}
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INFO_LOG(DSPLLE, "*** ddma_out DRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
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}
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void gdsp_do_dma()
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{
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u16 ctl;
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u32 addr;
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u16 dsp_addr;
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u16 len;
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addr = (gdsp_ifx_regs[DSP_DSMAH] << 16) | gdsp_ifx_regs[DSP_DSMAL];
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ctl = gdsp_ifx_regs[DSP_DSCR];
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dsp_addr = gdsp_ifx_regs[DSP_DSPA] * 2;
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len = gdsp_ifx_regs[DSP_DSBL];
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if ((ctl > 3) || (len > 0x4000))
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{
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ERROR_LOG(DSPLLE, "DMA ERROR pc: %04x ctl: %04x addr: %08x da: %04x size: %04x\n", g_dsp.pc, ctl, addr, dsp_addr, len);
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exit(0);
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}
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switch (ctl & 0x3)
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{
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case (DSP_CR_DMEM | DSP_CR_TO_CPU):
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gdsp_ddma_out(dsp_addr, addr, len);
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break;
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case (DSP_CR_DMEM | DSP_CR_FROM_CPU):
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gdsp_ddma_in(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_TO_CPU):
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gdsp_idma_out(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_FROM_CPU):
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gdsp_idma_in(dsp_addr, addr, len);
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break;
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}
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}
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